if_dwc.c (f0a7dd7703124af42da3705bb11e785c0eb9f0c4) if_dwc.c (363b7c39fbad7c03f46e24bb4e435fad5cb56aa7)
1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 *
4 * This software was developed by SRI International and the University of
5 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
6 * ("CTSRD"), as part of the DARPA CRASH research programme.
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 64 unchanged lines hidden (view full) ---

73#include <dev/dwc/dwc1000_reg.h>
74#include <dev/dwc/dwc1000_core.h>
75#include <dev/dwc/dwc1000_dma.h>
76
77#include "if_dwc_if.h"
78#include "gpio_if.h"
79#include "miibus_if.h"
80
1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 *
4 * This software was developed by SRI International and the University of
5 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
6 * ("CTSRD"), as part of the DARPA CRASH research programme.
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 64 unchanged lines hidden (view full) ---

73#include <dev/dwc/dwc1000_reg.h>
74#include <dev/dwc/dwc1000_core.h>
75#include <dev/dwc/dwc1000_dma.h>
76
77#include "if_dwc_if.h"
78#include "gpio_if.h"
79#include "miibus_if.h"
80
81#define MAC_RESET_TIMEOUT 100
82
83static struct resource_spec dwc_spec[] = {
84 { SYS_RES_MEMORY, 0, RF_ACTIVE },
85 { SYS_RES_IRQ, 0, RF_ACTIVE },
86 { -1, 0 }
87};
88
89static void dwc_stop_locked(struct dwc_softc *sc);
90

--- 403 unchanged lines hidden (view full) ---

494}
495
496static int
497dwc_attach(device_t dev)
498{
499 uint8_t macaddr[ETHER_ADDR_LEN];
500 struct dwc_softc *sc;
501 if_t ifp;
81static struct resource_spec dwc_spec[] = {
82 { SYS_RES_MEMORY, 0, RF_ACTIVE },
83 { SYS_RES_IRQ, 0, RF_ACTIVE },
84 { -1, 0 }
85};
86
87static void dwc_stop_locked(struct dwc_softc *sc);
88

--- 403 unchanged lines hidden (view full) ---

492}
493
494static int
495dwc_attach(device_t dev)
496{
497 uint8_t macaddr[ETHER_ADDR_LEN];
498 struct dwc_softc *sc;
499 if_t ifp;
502 int error, i;
500 int error;
503 uint32_t reg;
504 uint32_t txpbl, rxpbl, pbl;
505 bool nopblx8 = false;
506 bool fixed_burst = false;
507 bool mixed_burst = false;
508 bool aal = false;
509
510 sc = device_get_softc(dev);

--- 65 unchanged lines hidden (view full) ---

576 /* Reset the PHY if needed */
577 if (dwc_reset_phy(sc) != 0) {
578 device_printf(dev, "Can't reset the PHY\n");
579 bus_release_resources(dev, dwc_spec, sc->res);
580 return (ENXIO);
581 }
582
583 /* Reset */
501 uint32_t reg;
502 uint32_t txpbl, rxpbl, pbl;
503 bool nopblx8 = false;
504 bool fixed_burst = false;
505 bool mixed_burst = false;
506 bool aal = false;
507
508 sc = device_get_softc(dev);

--- 65 unchanged lines hidden (view full) ---

574 /* Reset the PHY if needed */
575 if (dwc_reset_phy(sc) != 0) {
576 device_printf(dev, "Can't reset the PHY\n");
577 bus_release_resources(dev, dwc_spec, sc->res);
578 return (ENXIO);
579 }
580
581 /* Reset */
584 reg = READ4(sc, BUS_MODE);
585 reg |= (BUS_MODE_SWR);
586 WRITE4(sc, BUS_MODE, reg);
587
588 for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
589 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
590 break;
591 DELAY(10);
582 if ((error = dma1000_reset(sc)) != 0) {
583 device_printf(sc->dev, "Can't reset DMA controller.\n");
584 bus_release_resources(sc->dev, dwc_spec, sc->res);
585 return (error);
592 }
586 }
593 if (i >= MAC_RESET_TIMEOUT) {
594 device_printf(sc->dev, "Can't reset DWC.\n");
595 bus_release_resources(dev, dwc_spec, sc->res);
596 return (ENXIO);
597 }
598
599 reg = BUS_MODE_USP;
600 if (!nopblx8)
601 reg |= BUS_MODE_EIGHTXPBL;
602 reg |= (txpbl << BUS_MODE_PBL_SHIFT);
603 reg |= (rxpbl << BUS_MODE_RPBL_SHIFT);
604 if (fixed_burst)
605 reg |= BUS_MODE_FIXEDBURST;

--- 130 unchanged lines hidden --- 		587
588 reg = BUS_MODE_USP;
589 if (!nopblx8)
590 reg |= BUS_MODE_EIGHTXPBL;
591 reg |= (txpbl << BUS_MODE_PBL_SHIFT);
592 reg |= (rxpbl << BUS_MODE_RPBL_SHIFT);
593 if (fixed_burst)
594 reg |= BUS_MODE_FIXEDBURST;

--- 130 unchanged lines hidden ---