if_ath.c (3e4f384ed293f2f1d7a099d6fa652f414ee45a97) if_ath.c (f50e4ebf6a779dfa0b4d5aaeaabde41bb19296f3)
1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 1902 unchanged lines hidden (view full) ---

1911 ATH_LOCK(sc);
1912 ath_power_setselfgen(sc, HAL_PM_AWAKE);
1913 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1914 ath_power_setpower(sc, HAL_PM_AWAKE);
1915 ATH_UNLOCK(sc);
1916
1917 ath_hal_reset(ah, sc->sc_opmode,
1918 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 1902 unchanged lines hidden (view full) ---

1911 ATH_LOCK(sc);
1912 ath_power_setselfgen(sc, HAL_PM_AWAKE);
1913 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1914 ath_power_setpower(sc, HAL_PM_AWAKE);
1915 ATH_UNLOCK(sc);
1916
1917 ath_hal_reset(ah, sc->sc_opmode,
1918 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1919 AH_FALSE, &status);
1919 AH_FALSE, HAL_RESET_NORMAL, &status);
1920 ath_reset_keycache(sc);
1921
1922 ATH_RX_LOCK(sc);
1923 sc->sc_rx_stopped = 1;
1924 sc->sc_rx_resetted = 1;
1925 ATH_RX_UNLOCK(sc);
1926
1927 /* Let DFS at it in case it's a DFS channel */

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2444 * and then setup of the interrupt mask.
2445 */
2446 ath_settkipmic(sc);
2447 ath_update_chainmasks(sc, ic->ic_curchan);
2448 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2449 sc->sc_cur_rxchainmask);
2450
2451 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE,
1920 ath_reset_keycache(sc);
1921
1922 ATH_RX_LOCK(sc);
1923 sc->sc_rx_stopped = 1;
1924 sc->sc_rx_resetted = 1;
1925 ATH_RX_UNLOCK(sc);
1926
1927 /* Let DFS at it in case it's a DFS channel */

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2444 * and then setup of the interrupt mask.
2445 */
2446 ath_settkipmic(sc);
2447 ath_update_chainmasks(sc, ic->ic_curchan);
2448 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2449 sc->sc_cur_rxchainmask);
2450
2451 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE,
2452 &status)) {
2452 HAL_RESET_NORMAL, &status)) {
2453 device_printf(sc->sc_dev,
2454 "unable to reset hardware; hal status %u\n", status);
2455 return (ENODEV);
2456 }
2457
2458 ATH_RX_LOCK(sc);
2459 sc->sc_rx_stopped = 1;
2460 sc->sc_rx_resetted = 1;

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2818 */
2819 ath_draintxq(sc, reset_type); /* stop xmit side */
2820
2821 ath_settkipmic(sc); /* configure TKIP MIC handling */
2822 /* NB: indicate channel change so we do a full reset */
2823 ath_update_chainmasks(sc, ic->ic_curchan);
2824 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2825 sc->sc_cur_rxchainmask);
2453 device_printf(sc->sc_dev,
2454 "unable to reset hardware; hal status %u\n", status);
2455 return (ENODEV);
2456 }
2457
2458 ATH_RX_LOCK(sc);
2459 sc->sc_rx_stopped = 1;
2460 sc->sc_rx_resetted = 1;

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2818 */
2819 ath_draintxq(sc, reset_type); /* stop xmit side */
2820
2821 ath_settkipmic(sc); /* configure TKIP MIC handling */
2822 /* NB: indicate channel change so we do a full reset */
2823 ath_update_chainmasks(sc, ic->ic_curchan);
2824 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2825 sc->sc_cur_rxchainmask);
2826 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
2826 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE,
2827 HAL_RESET_NORMAL, &status))
2827 device_printf(sc->sc_dev,
2828 "%s: unable to reset hardware; hal status %u\n",
2829 __func__, status);
2830 sc->sc_diversity = ath_hal_getdiversity(ah);
2831
2832 ATH_RX_LOCK(sc);
2833 sc->sc_rx_stopped = 1;
2834 sc->sc_rx_resetted = 1;

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5418 /*
5419 * Next, flush the non-scheduled frames.
5420 */
5421 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
5422
5423 ath_update_chainmasks(sc, chan);
5424 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
5425 sc->sc_cur_rxchainmask);
2828 device_printf(sc->sc_dev,
2829 "%s: unable to reset hardware; hal status %u\n",
2830 __func__, status);
2831 sc->sc_diversity = ath_hal_getdiversity(ah);
2832
2833 ATH_RX_LOCK(sc);
2834 sc->sc_rx_stopped = 1;
2835 sc->sc_rx_resetted = 1;

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5419 /*
5420 * Next, flush the non-scheduled frames.
5421 */
5422 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
5423
5424 ath_update_chainmasks(sc, chan);
5425 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
5426 sc->sc_cur_rxchainmask);
5426 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
5427 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE,
5428 HAL_RESET_NORMAL, &status)) {
5427 device_printf(sc->sc_dev, "%s: unable to reset "
5428 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5429 __func__, ieee80211_chan2ieee(ic, chan),
5430 chan->ic_freq, chan->ic_flags, status);
5431 ret = EIO;
5432 goto finish;
5433 }
5434 sc->sc_diversity = ath_hal_getdiversity(ah);

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5429 device_printf(sc->sc_dev, "%s: unable to reset "
5430 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5431 __func__, ieee80211_chan2ieee(ic, chan),
5432 chan->ic_freq, chan->ic_flags, status);
5433 ret = EIO;
5434 goto finish;
5435 }
5436 sc->sc_diversity = ath_hal_getdiversity(ah);

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