ata-siliconimage.c (0cde70967fabb99fd95b5dea8af3861344691529) ata-siliconimage.c (066f913a94b134b6d5e32b6af88f297c7da9c031)
1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 40 unchanged lines hidden (view full) ---

49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_cmd_ch_attach(device_t dev);
56static int ata_cmd_status(device_t dev);
1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 40 unchanged lines hidden (view full) ---

49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_cmd_ch_attach(device_t dev);
56static int ata_cmd_status(device_t dev);
57static void ata_cmd_setmode(device_t dev, int mode);
57static int ata_cmd_setmode(device_t dev, int target, int mode);
58static int ata_sii_ch_attach(device_t dev);
59static int ata_sii_ch_detach(device_t dev);
60static int ata_sii_status(device_t dev);
61static void ata_sii_reset(device_t dev);
58static int ata_sii_ch_attach(device_t dev);
59static int ata_sii_ch_detach(device_t dev);
60static int ata_sii_status(device_t dev);
61static void ata_sii_reset(device_t dev);
62static void ata_sii_setmode(device_t dev, int mode);
62static int ata_sii_setmode(device_t dev, int target, int mode);
63static int ata_siiprb_ch_attach(device_t dev);
64static int ata_siiprb_ch_detach(device_t dev);
65static int ata_siiprb_status(device_t dev);
66static int ata_siiprb_begin_transaction(struct ata_request *request);
67static int ata_siiprb_end_transaction(struct ata_request *request);
68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
70static u_int32_t ata_siiprb_softreset(device_t dev, int port);

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140 &ctlr->r_rid2, RF_ACTIVE))){
141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
142 return ENXIO;
143 }
144 ctlr->ch_attach = ata_siiprb_ch_attach;
145 ctlr->ch_detach = ata_siiprb_ch_detach;
146 ctlr->reset = ata_siiprb_reset;
147 ctlr->setmode = ata_sata_setmode;
63static int ata_siiprb_ch_attach(device_t dev);
64static int ata_siiprb_ch_detach(device_t dev);
65static int ata_siiprb_status(device_t dev);
66static int ata_siiprb_begin_transaction(struct ata_request *request);
67static int ata_siiprb_end_transaction(struct ata_request *request);
68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
70static u_int32_t ata_siiprb_softreset(device_t dev, int port);

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140 &ctlr->r_rid2, RF_ACTIVE))){
141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
142 return ENXIO;
143 }
144 ctlr->ch_attach = ata_siiprb_ch_attach;
145 ctlr->ch_detach = ata_siiprb_ch_detach;
146 ctlr->reset = ata_siiprb_reset;
147 ctlr->setmode = ata_sata_setmode;
148 ctlr->getrev = ata_sata_getrev;
148 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
149
150 /* reset controller */
151 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
152 DELAY(10000);
153 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
154 break;
155

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188 if (ctlr->r_res2) {
189 ctlr->ch_attach = ata_sii_ch_attach;
190 ctlr->ch_detach = ata_sii_ch_detach;
191 }
192
193 if (ctlr->chip->max_dma >= ATA_SA150) {
194 ctlr->reset = ata_sii_reset;
195 ctlr->setmode = ata_sata_setmode;
149 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
150
151 /* reset controller */
152 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
153 DELAY(10000);
154 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
155 break;
156

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189 if (ctlr->r_res2) {
190 ctlr->ch_attach = ata_sii_ch_attach;
191 ctlr->ch_detach = ata_sii_ch_detach;
192 }
193
194 if (ctlr->chip->max_dma >= ATA_SA150) {
195 ctlr->reset = ata_sii_reset;
196 ctlr->setmode = ata_sata_setmode;
197 ctlr->getrev = ata_sata_getrev;
196 }
197 else
198 ctlr->setmode = ata_sii_setmode;
199 break;
200
201 default:
202 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
203 device_printf(dev, "HW has secondary channel disabled\n");

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241 (ch->unit ? 0x08 : 0x04))) {
242 pci_write_config(device_get_parent(dev), 0x71,
243 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
244 return ata_pci_status(dev);
245 }
246 return 0;
247}
248
198 }
199 else
200 ctlr->setmode = ata_sii_setmode;
201 break;
202
203 default:
204 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
205 device_printf(dev, "HW has secondary channel disabled\n");

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243 (ch->unit ? 0x08 : 0x04))) {
244 pci_write_config(device_get_parent(dev), 0x71,
245 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
246 return ata_pci_status(dev);
247 }
248 return 0;
249}
250
249static void
250ata_cmd_setmode(device_t dev, int mode)
251static int
252ata_cmd_setmode(device_t dev, int target, int mode)
251{
253{
252 device_t gparent = GRANDPARENT(dev);
253 struct ata_pci_controller *ctlr = device_get_softc(gparent);
254 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
255 struct ata_device *atadev = device_get_softc(dev);
256 int devno = (ch->unit << 1) + atadev->unit;
257 int error;
258
259 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
260
261 mode = ata_check_80pin(dev, mode);
262
263 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
264
265 if (bootverbose)
266 device_printf(dev, "%ssetting %s on %s chip\n",
267 (error) ? "FAILURE " : "",
268 ata_mode2str(mode), ctlr->chip->text);
269 if (!error) {
254 device_t parent = device_get_parent(dev);
255 struct ata_pci_controller *ctlr = device_get_softc(parent);
256 struct ata_channel *ch = device_get_softc(dev);
257 int devno = (ch->unit << 1) + target;
270 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
271 int ureg = ch->unit ? 0x7b : 0x73;
258 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
259 int ureg = ch->unit ? 0x7b : 0x73;
272
273 if (mode >= ATA_UDMA0) {
274 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
260 int piomode;
261 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
262 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
275 { 0x11, 0x42 }, { 0x25, 0x8a },
276 { 0x15, 0x4a }, { 0x05, 0x0a } };
277
263 { 0x11, 0x42 }, { 0x25, 0x8a },
264 { 0x15, 0x4a }, { 0x05, 0x0a } };
265
278 u_int8_t umode = pci_read_config(gparent, ureg, 1);
266 mode = min(mode, ctlr->chip->max_dma);
267 if (mode >= ATA_UDMA0) {
268 u_int8_t umode = pci_read_config(parent, ureg, 1);
279
269
280 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
281 umode |= udmatimings[mode & ATA_MODE_MASK][atadev->unit];
282 pci_write_config(gparent, ureg, umode, 1);
270 umode &= ~(target == 0 ? 0x35 : 0xca);
271 umode |= udmatimings[mode & ATA_MODE_MASK][target];
272 pci_write_config(parent, ureg, umode, 1);
273 piomode = ATA_PIO4;
274 } else {
275 pci_write_config(parent, ureg,
276 pci_read_config(parent, ureg, 1) &
277 ~(target == 0 ? 0x35 : 0xca), 1);
278 piomode = mode;
283 }
279 }
284 else if (mode >= ATA_WDMA0) {
285 int dmatimings[] = { 0x87, 0x32, 0x3f };
286
287 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
288 pci_write_config(gparent, ureg,
289 pci_read_config(gparent, ureg, 1) &
290 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
291 }
292 else {
293 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
294 pci_write_config(gparent, treg,
295 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
296 pci_write_config(gparent, ureg,
297 pci_read_config(gparent, ureg, 1) &
298 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
299 }
300 atadev->mode = mode;
301 }
280 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
281 return (mode);
302}
303
304static int
305ata_sii_ch_attach(device_t dev)
306{
307 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
308 struct ata_channel *ch = device_get_softc(dev);
309 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);

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330 if (ctlr->chip->max_dma >= ATA_SA150) {
331 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
332 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
333 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
334 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
335 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
336 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
337 ch->flags |= ATA_NO_SLAVE;
282}
283
284static int
285ata_sii_ch_attach(device_t dev)
286{
287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
288 struct ata_channel *ch = device_get_softc(dev);
289 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);

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310 if (ctlr->chip->max_dma >= ATA_SA150) {
311 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
312 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
313 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
314 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
315 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
316 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
317 ch->flags |= ATA_NO_SLAVE;
318 ch->flags |= ATA_SATA;
338
339 /* enable PHY state change interrupt */
340 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
341 }
342
319
320 /* enable PHY state change interrupt */
321 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
322 }
323
343 ch->dma.max_iosize = (ATA_DMA_ENTRIES - 1) * PAGE_SIZE;
344 if (ctlr->chip->cfg2 & SII_BUG) {
345 /* work around errata in early chips */
346 ch->dma.boundary = 8192;
347 ch->dma.segsize = 15 * DEV_BSIZE;
348 }
349
350 ata_pci_hw(dev);
351 ch->hw.status = ata_sii_status;
324 if (ctlr->chip->cfg2 & SII_BUG) {
325 /* work around errata in early chips */
326 ch->dma.boundary = 8192;
327 ch->dma.segsize = 15 * DEV_BSIZE;
328 }
329
330 ata_pci_hw(dev);
331 ch->hw.status = ata_sii_status;
332 if (ctlr->chip->cfg2 & SII_SETCLK)
333 ch->flags |= ATA_CHECKS_CABLE;
352 return 0;
353}
354
355static int
356ata_sii_ch_detach(device_t dev)
357{
358
359 ata_pci_dmafini(dev);

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381
382static void
383ata_sii_reset(device_t dev)
384{
385 if (ata_sata_phy_reset(dev, -1, 1))
386 ata_generic_reset(dev);
387}
388
334 return 0;
335}
336
337static int
338ata_sii_ch_detach(device_t dev)
339{
340
341 ata_pci_dmafini(dev);

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363
364static void
365ata_sii_reset(device_t dev)
366{
367 if (ata_sata_phy_reset(dev, -1, 1))
368 ata_generic_reset(dev);
369}
370
389static void
390ata_sii_setmode(device_t dev, int mode)
371static int
372ata_sii_setmode(device_t dev, int target, int mode)
391{
373{
392 device_t gparent = GRANDPARENT(dev);
393 struct ata_pci_controller *ctlr = device_get_softc(gparent);
394 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
395 struct ata_device *atadev = device_get_softc(dev);
396 int rego = (ch->unit << 4) + (atadev->unit << 1);
397 int mreg = ch->unit ? 0x84 : 0x80;
398 int mask = 0x03 << (atadev->unit << 2);
399 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
400 int error;
374 device_t parent = device_get_parent(dev);
375 struct ata_pci_controller *ctlr = device_get_softc(parent);
376 struct ata_channel *ch = device_get_softc(dev);
377 int rego = (ch->unit << 4) + (target << 1);
378 int mreg = ch->unit ? 0x84 : 0x80;
379 int mask = 0x03 << (target << 2);
380 int mval = pci_read_config(parent, mreg, 1) & ~mask;
381 int piomode;
382 u_int8_t preg = 0xa4 + rego;
383 u_int8_t dreg = 0xa8 + rego;
384 u_int8_t ureg = 0xac + rego;
385 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
386 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
387 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
401
388
402 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
389 mode = min(mode, ctlr->chip->max_dma);
403
390
404 if (ctlr->chip->cfg2 & SII_SETCLK) {
405 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
391 if (ctlr->chip->cfg2 & SII_SETCLK) {
392 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) &
406 (ch->unit ? 0x02 : 0x01))) {
393 (ch->unit ? 0x02 : 0x01))) {
407 ata_print_cable(dev, "controller");
408 mode = ATA_UDMA2;
394 ata_print_cable(dev, "controller");
395 mode = ATA_UDMA2;
396 }
409 }
397 }
410 }
411 else
412 mode = ata_check_80pin(dev, mode);
413
414 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
415
416 if (bootverbose)
417 device_printf(dev, "%ssetting %s on %s chip\n",
418 (error) ? "FAILURE " : "",
419 ata_mode2str(mode), ctlr->chip->text);
420 if (error)
421 return;
422
423 if (mode >= ATA_UDMA0) {
424 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
425 u_int8_t ureg = 0xac + rego;
426
427 pci_write_config(gparent, mreg,
428 mval | (0x03 << (atadev->unit << 2)), 1);
429 pci_write_config(gparent, ureg,
430 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
398 if (mode >= ATA_UDMA0) {
399 pci_write_config(parent, mreg,
400 mval | (0x03 << (target << 2)), 1);
401 pci_write_config(parent, ureg,
402 (pci_read_config(parent, ureg, 1) & ~0x3f) |
431 udmatimings[mode & ATA_MODE_MASK], 1);
403 udmatimings[mode & ATA_MODE_MASK], 1);
432
433 }
434 else if (mode >= ATA_WDMA0) {
435 u_int8_t dreg = 0xa8 + rego;
436 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
437
438 pci_write_config(gparent, mreg,
439 mval | (0x02 << (atadev->unit << 2)), 1);
440 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
441
442 }
443 else {
444 u_int8_t preg = 0xa4 + rego;
445 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
446
447 pci_write_config(gparent, mreg,
448 mval | (0x01 << (atadev->unit << 2)), 1);
449 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
450 }
451 atadev->mode = mode;
404 piomode = ATA_PIO4;
405 } else if (mode >= ATA_WDMA0) {
406 pci_write_config(parent, mreg,
407 mval | (0x02 << (target << 2)), 1);
408 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
409 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
410 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
411 } else {
412 pci_write_config(parent, mreg,
413 mval | (0x01 << (target << 2)), 1);
414 piomode = mode;
415 }
416 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
417 return (mode);
452}
453
454
455struct ata_siiprb_dma_prdentry {
456 u_int64_t addr;
457 u_int32_t count;
458 u_int32_t control;
459} __packed;

--- 447 unchanged lines hidden --- 		418}
419
420
421struct ata_siiprb_dma_prdentry {
422 u_int64_t addr;
423 u_int32_t count;
424 u_int32_t control;
425} __packed;

--- 447 unchanged lines hidden ---