ata-intel.c (301f81f0fbdbfb17ba5394898821af4f0b60b1b5) ata-intel.c (066f913a94b134b6d5e32b6af88f297c7da9c031)
1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 41 unchanged lines hidden (view full) ---

50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_intel_chipinit(device_t dev);
56static int ata_intel_ch_attach(device_t dev);
57static void ata_intel_reset(device_t dev);
1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 41 unchanged lines hidden (view full) ---

50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_intel_chipinit(device_t dev);
56static int ata_intel_ch_attach(device_t dev);
57static void ata_intel_reset(device_t dev);
58static void ata_intel_old_setmode(device_t dev, int mode);
59static void ata_intel_new_setmode(device_t dev, int mode);
60static void ata_intel_sata_setmode(device_t dev, int mode);
58static int ata_intel_old_setmode(device_t dev, int target, int mode);
59static int ata_intel_new_setmode(device_t dev, int target, int mode);
60static int ata_intel_sata_getrev(device_t dev, int target);
61static int ata_intel_31244_ch_attach(device_t dev);
62static int ata_intel_31244_ch_detach(device_t dev);
63static int ata_intel_31244_status(device_t dev);
64static void ata_intel_31244_tf_write(struct ata_request *request);
65static void ata_intel_31244_reset(device_t dev);
66
67/* misc defines */
68#define INTEL_AHCI 1

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176 RF_ACTIVE)))
177 return ENXIO;
178 ctlr->channels = 4;
179 ctlr->ch_attach = ata_intel_31244_ch_attach;
180 ctlr->ch_detach = ata_intel_31244_ch_detach;
181 ctlr->reset = ata_intel_31244_reset;
182 }
183 ctlr->setmode = ata_sata_setmode;
61static int ata_intel_31244_ch_attach(device_t dev);
62static int ata_intel_31244_ch_detach(device_t dev);
63static int ata_intel_31244_status(device_t dev);
64static void ata_intel_31244_tf_write(struct ata_request *request);
65static void ata_intel_31244_reset(device_t dev);
66
67/* misc defines */
68#define INTEL_AHCI 1

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176 RF_ACTIVE)))
177 return ENXIO;
178 ctlr->channels = 4;
179 ctlr->ch_attach = ata_intel_31244_ch_attach;
180 ctlr->ch_detach = ata_intel_31244_ch_detach;
181 ctlr->reset = ata_intel_31244_reset;
182 }
183 ctlr->setmode = ata_sata_setmode;
184 ctlr->getrev = ata_sata_getrev;
184 }
185
186 /* non SATA intel chips goes here */
187 else if (ctlr->chip->max_dma < ATA_SA150) {
188 ctlr->channels = ctlr->chip->cfg2;
189 ctlr->ch_attach = ata_intel_ch_attach;
190 ctlr->ch_detach = ata_pci_ch_detach;
191 ctlr->setmode = ata_intel_new_setmode;

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209 (ata_ahci_chipinit(dev) != ENXIO))
210 return 0;
211
212 /* if BAR(5) is IO it should point to SATA interface registers */
213 ctlr->r_type2 = SYS_RES_IOPORT;
214 ctlr->r_rid2 = PCIR_BAR(5);
215 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
216 &ctlr->r_rid2, RF_ACTIVE)))
185 }
186
187 /* non SATA intel chips goes here */
188 else if (ctlr->chip->max_dma < ATA_SA150) {
189 ctlr->channels = ctlr->chip->cfg2;
190 ctlr->ch_attach = ata_intel_ch_attach;
191 ctlr->ch_detach = ata_pci_ch_detach;
192 ctlr->setmode = ata_intel_new_setmode;

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210 (ata_ahci_chipinit(dev) != ENXIO))
211 return 0;
212
213 /* if BAR(5) is IO it should point to SATA interface registers */
214 ctlr->r_type2 = SYS_RES_IOPORT;
215 ctlr->r_rid2 = PCIR_BAR(5);
216 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
217 &ctlr->r_rid2, RF_ACTIVE)))
217 ctlr->setmode = ata_intel_sata_setmode;
218 else
219 ctlr->setmode = ata_sata_setmode;
218 ctlr->getrev = ata_intel_sata_getrev;
219 ctlr->setmode = ata_sata_setmode;
220 }
221 return 0;
222}
223
224static int
225ata_intel_ch_attach(device_t dev)
226{
227 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));

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235 if (ctlr->r_res2) {
236 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
237 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
238 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
239 ch->r_io[ATA_IDX_DATA].offset = 0x04;
240 }
241
242 ch->flags |= ATA_ALWAYS_DMASTAT;
220 }
221 return 0;
222}
223
224static int
225ata_intel_ch_attach(device_t dev)
226{
227 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));

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235 if (ctlr->r_res2) {
236 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
237 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
238 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
239 ch->r_io[ATA_IDX_DATA].offset = 0x04;
240 }
241
242 ch->flags |= ATA_ALWAYS_DMASTAT;
243 if (ctlr->chip->max_dma >= ATA_SA150) {
244 if (ctlr->chip->cfg1 == 0 &&
245 (pci_read_config(device_get_parent(dev), 0x90, 1) & 0x04) == 0)
246 ch->flags |= ATA_NO_SLAVE;
247 ch->flags |= ATA_SATA;
248 } else
249 ch->flags |= ATA_CHECKS_CABLE;
243 return 0;
244}
245
246static void
247ata_intel_reset(device_t dev)
248{
249 device_t parent = device_get_parent(dev);
250 struct ata_pci_controller *ctlr = device_get_softc(parent);
251 struct ata_channel *ch = device_get_softc(dev);
252 int mask, timeout;
253
254 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
255 if (ctlr->chip->cfg1) {
256 mask = (0x0005 << ch->unit);
257 }
258 else {
259 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
260 if (pci_read_config(parent, 0x90, 1) & 0x04)
261 mask = 0x0003;
250 return 0;
251}
252
253static void
254ata_intel_reset(device_t dev)
255{
256 device_t parent = device_get_parent(dev);
257 struct ata_pci_controller *ctlr = device_get_softc(parent);
258 struct ata_channel *ch = device_get_softc(dev);
259 int mask, timeout;
260
261 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
262 if (ctlr->chip->cfg1) {
263 mask = (0x0005 << ch->unit);
264 }
265 else {
266 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
267 if (pci_read_config(parent, 0x90, 1) & 0x04)
268 mask = 0x0003;
262 else {
269 else
263 mask = (0x0001 << ch->unit);
270 mask = (0x0001 << ch->unit);
264 /* XXX SOS should be in intel_ch_attach if we grow it */
265 ch->flags |= ATA_NO_SLAVE;
266 }
267 }
268 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
269 DELAY(10);
270 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
271
272 /* wait up to 1 sec for "connect well" */
273 for (timeout = 0; timeout < 100 ; timeout++) {
274 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
275 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
276 break;
277 ata_udelay(10000);
278 }
279 ata_generic_reset(dev);
280}
281
271 }
272 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
273 DELAY(10);
274 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
275
276 /* wait up to 1 sec for "connect well" */
277 for (timeout = 0; timeout < 100 ; timeout++) {
278 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
279 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
280 break;
281 ata_udelay(10000);
282 }
283 ata_generic_reset(dev);
284}
285
282static void
283ata_intel_old_setmode(device_t dev, int mode)
286static int
287ata_intel_old_setmode(device_t dev, int target, int mode)
284{
288{
285 /* NOT YET */
289 device_t parent = device_get_parent(dev);
290 struct ata_pci_controller *ctlr = device_get_softc(parent);
291
292 mode = min(mode, ctlr->chip->max_dma);
293 return (mode);
286}
287
294}
295
288static void
289ata_intel_new_setmode(device_t dev, int mode)
296static int
297ata_intel_new_setmode(device_t dev, int target, int mode)
290{
298{
291 device_t gparent = GRANDPARENT(dev);
292 struct ata_pci_controller *ctlr = device_get_softc(gparent);
293 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
294 struct ata_device *atadev = device_get_softc(dev);
295 int devno = (ch->unit << 1) + atadev->unit;
296 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
297 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
298 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
299 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
300 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
301 u_int32_t mask40 = 0, new40 = 0;
302 u_int8_t mask44 = 0, new44 = 0;
303 int error;
304 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23,
305 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
299 device_t parent = device_get_parent(dev);
300 struct ata_pci_controller *ctlr = device_get_softc(parent);
301 struct ata_channel *ch = device_get_softc(dev);
302 int devno = (ch->unit << 1) + target;
303 int piomode;
304 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
305 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
306 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
307 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
308 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
309 u_int32_t mask40 = 0, new40 = 0;
310 u_int8_t mask44 = 0, new44 = 0;
311 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 };
312 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
306
313
307 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
308
309 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
310 ata_print_cable(dev, "controller");
311 mode = ATA_UDMA2;
312 }
313
314 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
315
316 if (bootverbose)
317 device_printf(dev, "%ssetting %s on %s chip\n",
318 (error) ? "FAILURE " : "",
319 ata_mode2str(mode), ctlr->chip->text);
320 if (!error) {
314 mode = min(mode, ctlr->chip->max_dma);
315 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
316 ata_print_cable(dev, "controller");
317 mode = ATA_UDMA2;
318 }
319 /* Enable/disable UDMA and set timings. */
321 if (mode >= ATA_UDMA0) {
320 if (mode >= ATA_UDMA0) {
322 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
323
324 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
325 pci_write_config(gparent, 0x4a,
326 (reg4a & ~(0x3 << (devno << 2))) |
327 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
321 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
322 pci_write_config(parent, 0x4a,
323 (reg4a & ~(0x3 << (devno << 2))) |
324 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
325 piomode = ATA_PIO4;
326 } else {
327 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
328 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
329 piomode = mode;
328 }
330 }
329 else {
330 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
331 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
332 }
333 reg54 |= 0x0400;
331 reg54 |= 0x0400;
334 if (mode >= ATA_UDMA3)
335 reg54 |= (0x1 << devno);
336 else
337 reg54 &= ~(0x1 << devno);
332 /* Set UDMA reference clock (33/66/133MHz). */
333 reg54 &= ~(0x1001 << devno);
338 if (mode >= ATA_UDMA5)
339 reg54 |= (0x1000 << devno);
334 if (mode >= ATA_UDMA5)
335 reg54 |= (0x1000 << devno);
340 else
341 reg54 &= ~(0x1000 << devno);
342
343 pci_write_config(gparent, 0x54, reg54, 2);
344
336 else if (mode >= ATA_UDMA3)
337 reg54 |= (0x1 << devno);
338 pci_write_config(parent, 0x54, reg54, 2);
339 /* Allow PIO/WDMA timing controls. */
345 reg40 &= ~0x00ff00ff;
346 reg40 |= 0x40774077;
340 reg40 &= ~0x00ff00ff;
341 reg40 |= 0x40774077;
347
348 if (atadev->unit == ATA_MASTER) {
342 /* Set PIO/WDMA timings. */
343 if (target == 0) {
349 mask40 = 0x3300;
344 mask40 = 0x3300;
350 new40 = timings[ata_mode2idx(mode)] << 8;
351 }
352 else {
345 new40 = timings[ata_mode2idx(piomode)] << 8;
346 } else {
353 mask44 = 0x0f;
347 mask44 = 0x0f;
354 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
355 (timings[ata_mode2idx(mode)] & 0x03);
348 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) |
349 (timings[ata_mode2idx(piomode)] & 0x03);
356 }
357 if (ch->unit) {
358 mask40 <<= 16;
359 new40 <<= 16;
360 mask44 <<= 4;
361 new44 <<= 4;
362 }
350 }
351 if (ch->unit) {
352 mask40 <<= 16;
353 new40 <<= 16;
354 mask44 <<= 4;
355 new44 <<= 4;
356 }
363 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
364 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
365
366 atadev->mode = mode;
367 }
357 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
358 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
359 return (mode);
368}
369
360}
361
370static void
371ata_intel_sata_setmode(device_t dev, int mode)
362static int
363ata_intel_sata_getrev(device_t dev, int target)
372{
364{
373 struct ata_device *atadev = device_get_softc(dev);
365 struct ata_channel *ch = device_get_softc(dev);
366 int devno = (ch->unit << 1) + target;
374
367
375 if (atadev->param.satacapabilities != 0x0000 &&
376 atadev->param.satacapabilities != 0xffff) {
377
378 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
379 int devno = (ch->unit << 1) + atadev->unit;
380
381 /* on some drives we need to set the transfer mode */
382 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
383 ata_limit_mode(dev, mode, ATA_UDMA6));
384
385 /* set ATA_SSTATUS register offset */
386 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
368 /* set ATA_SSTATUS register offset */
369 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
387
388 /* query SATA STATUS for the speed */
370 /* query SATA STATUS for the speed */
389 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) ==
390 ATA_SS_CONWELL_GEN2)
391 atadev->mode = ATA_SA300;
392 else
393 atadev->mode = ATA_SA150;
394 }
395 else {
396 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
397 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
398 atadev->mode = mode;
399 }
371 return ((ATA_IDX_INL(ch, ATA_IDX_DATA) & 0x0f0) >> 4);
400}
401
402static int
403ata_intel_31244_ch_attach(device_t dev)
404{
405 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
406 struct ata_channel *ch = device_get_softc(dev);
407 int i;

--- 26 unchanged lines hidden (view full) ---

434 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
435
436 /* setup SATA registers */
437 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
438 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
439 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
440
441 ch->flags |= ATA_NO_SLAVE;
372}
373
374static int
375ata_intel_31244_ch_attach(device_t dev)
376{
377 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
378 struct ata_channel *ch = device_get_softc(dev);
379 int i;

--- 26 unchanged lines hidden (view full) ---

406 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
407
408 /* setup SATA registers */
409 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
410 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
411 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
412
413 ch->flags |= ATA_NO_SLAVE;
414 ch->flags |= ATA_SATA;
442 ata_pci_hw(dev);
443 ch->hw.status = ata_intel_31244_status;
444 ch->hw.tf_write = ata_intel_31244_tf_write;
445
446 /* enable PHY state change interrupt */
447 ATA_OUTL(ctlr->r_res2, 0x4,
448 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
449 return 0;

--- 16 unchanged lines hidden (view full) ---

466 /* any drive action to take care of ? */
467 return ata_pci_status(dev);
468}
469
470static void
471ata_intel_31244_tf_write(struct ata_request *request)
472{
473 struct ata_channel *ch = device_get_softc(request->parent);
415 ata_pci_hw(dev);
416 ch->hw.status = ata_intel_31244_status;
417 ch->hw.tf_write = ata_intel_31244_tf_write;
418
419 /* enable PHY state change interrupt */
420 ATA_OUTL(ctlr->r_res2, 0x4,
421 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
422 return 0;

--- 16 unchanged lines hidden (view full) ---

439 /* any drive action to take care of ? */
440 return ata_pci_status(dev);
441}
442
443static void
444ata_intel_31244_tf_write(struct ata_request *request)
445{
446 struct ata_channel *ch = device_get_softc(request->parent);
447#ifndef ATA_CAM
474 struct ata_device *atadev = device_get_softc(request->dev);
448 struct ata_device *atadev = device_get_softc(request->dev);
449#endif
475
476 if (request->flags & ATA_R_48BIT) {
477 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
478 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
479 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
480 (request->u.ata.lba & 0x00ff));
481 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
482 ((request->u.ata.lba >> 8) & 0x00ff));
483 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
484 ((request->u.ata.lba >> 16) & 0x00ff));
485 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
486 }
487 else {
488 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
489 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
450
451 if (request->flags & ATA_R_48BIT) {
452 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
453 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
454 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
455 (request->u.ata.lba & 0x00ff));
456 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
457 ((request->u.ata.lba >> 8) & 0x00ff));
458 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
459 ((request->u.ata.lba >> 16) & 0x00ff));
460 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
461 }
462 else {
463 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
464 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
465#ifndef ATA_CAM
490 if (atadev->flags & ATA_D_USE_CHS) {
491 int heads, sectors;
492
493 if (atadev->param.atavalid & ATA_FLAG_54_58) {
494 heads = atadev->param.current_heads;
495 sectors = atadev->param.current_sectors;
496 }
497 else {

--- 5 unchanged lines hidden (view full) ---

503 (request->u.ata.lba / (sectors * heads)));
504 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
505 (request->u.ata.lba / (sectors * heads)) >> 8);
506 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
507 (((request->u.ata.lba% (sectors * heads)) /
508 sectors) & 0xf));
509 }
510 else {
466 if (atadev->flags & ATA_D_USE_CHS) {
467 int heads, sectors;
468
469 if (atadev->param.atavalid & ATA_FLAG_54_58) {
470 heads = atadev->param.current_heads;
471 sectors = atadev->param.current_sectors;
472 }
473 else {

--- 5 unchanged lines hidden (view full) ---

479 (request->u.ata.lba / (sectors * heads)));
480 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
481 (request->u.ata.lba / (sectors * heads)) >> 8);
482 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
483 (((request->u.ata.lba% (sectors * heads)) /
484 sectors) & 0xf));
485 }
486 else {
487#endif
511 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
512 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
513 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
514 ATA_IDX_OUTB(ch, ATA_DRIVE,
515 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
516 ((request->u.ata.lba >> 24) & 0x0f));
488 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
489 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
490 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
491 ATA_IDX_OUTB(ch, ATA_DRIVE,
492 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
493 ((request->u.ata.lba >> 24) & 0x0f));
494#ifndef ATA_CAM
517 }
495 }
496#endif
518 }
519}
520
521static void
522ata_intel_31244_reset(device_t dev)
523{
524 if (ata_sata_phy_reset(dev, -1, 1))
525 ata_generic_reset(dev);
526}
527
528ATA_DECLARE_DRIVER(ata_intel);
529MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);
497 }
498}
499
500static void
501ata_intel_31244_reset(device_t dev)
502{
503 if (ata_sata_phy_reset(dev, -1, 1))
504 ata_generic_reset(dev);
505}
506
507ATA_DECLARE_DRIVER(ata_intel);
508MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);