ata-acerlabs.c (677843147820e9e8d581cf9841ea01a567324d3b) ata-acerlabs.c (066f913a94b134b6d5e32b6af88f297c7da9c031)
1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_ali_chipinit(device_t dev);
56static int ata_ali_ch_attach(device_t dev);
57static int ata_ali_sata_ch_attach(device_t dev);
58static void ata_ali_reset(device_t dev);
1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_ali_chipinit(device_t dev);
56static int ata_ali_ch_attach(device_t dev);
57static int ata_ali_sata_ch_attach(device_t dev);
58static void ata_ali_reset(device_t dev);
59static void ata_ali_setmode(device_t dev, int mode);
59static int ata_ali_setmode(device_t dev, int target, int mode);
60
61/* misc defines */
62#define ALI_OLD 0x01
63#define ALI_NEW 0x02
64#define ALI_SATA 0x04
65
66struct ali_sata_resources {
67 struct resource *bars[4];

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108 return ENXIO;
109
110 switch (ctlr->chip->cfg2) {
111 case ALI_SATA:
112 ctlr->channels = ctlr->chip->cfg1;
113 ctlr->ch_attach = ata_ali_sata_ch_attach;
114 ctlr->ch_detach = ata_pci_ch_detach;
115 ctlr->setmode = ata_sata_setmode;
60
61/* misc defines */
62#define ALI_OLD 0x01
63#define ALI_NEW 0x02
64#define ALI_SATA 0x04
65
66struct ali_sata_resources {
67 struct resource *bars[4];

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108 return ENXIO;
109
110 switch (ctlr->chip->cfg2) {
111 case ALI_SATA:
112 ctlr->channels = ctlr->chip->cfg1;
113 ctlr->ch_attach = ata_ali_sata_ch_attach;
114 ctlr->ch_detach = ata_pci_ch_detach;
115 ctlr->setmode = ata_sata_setmode;
116 ctlr->getrev = ata_sata_getrev;
116
117 /* AHCI mode is correctly supported only on the ALi 5288. */
118 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
119 (ata_ahci_chipinit(dev) != ENXIO))
120 return 0;
121
122 /* Allocate resources for later use by channel attach routines. */
123 res = malloc(sizeof(struct ali_sata_resources), M_TEMP, M_WAITOK);

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171{
172 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
173 struct ata_channel *ch = device_get_softc(dev);
174
175 /* setup the usual register normal pci style */
176 if (ata_pci_ch_attach(dev))
177 return ENXIO;
178
117
118 /* AHCI mode is correctly supported only on the ALi 5288. */
119 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
120 (ata_ahci_chipinit(dev) != ENXIO))
121 return 0;
122
123 /* Allocate resources for later use by channel attach routines. */
124 res = malloc(sizeof(struct ali_sata_resources), M_TEMP, M_WAITOK);

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172{
173 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
174 struct ata_channel *ch = device_get_softc(dev);
175
176 /* setup the usual register normal pci style */
177 if (ata_pci_ch_attach(dev))
178 return ENXIO;
179
180 ch->flags |= ATA_CHECKS_CABLE;
179 /* older chips can't do 48bit DMA transfers */
180 if (ctlr->chip->chiprev <= 0xc4)
181 ch->flags |= ATA_NO_48BIT_DMA;
182
183 return 0;
184}
185
186static int

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213 ata_default_registers(dev);
214 if (ctlr->r_res1) {
215 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
216 ch->r_io[i].res = ctlr->r_res1;
217 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
218 }
219 }
220 ch->flags |= ATA_NO_SLAVE;
181 /* older chips can't do 48bit DMA transfers */
182 if (ctlr->chip->chiprev <= 0xc4)
183 ch->flags |= ATA_NO_48BIT_DMA;
184
185 return 0;
186}
187
188static int

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215 ata_default_registers(dev);
216 if (ctlr->r_res1) {
217 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
218 ch->r_io[i].res = ctlr->r_res1;
219 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
220 }
221 }
222 ch->flags |= ATA_NO_SLAVE;
223 ch->flags |= ATA_SATA;
221
222 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
223 ata_pci_hw(dev);
224 return 0;
225}
226
227static void
228ata_ali_reset(device_t dev)

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252 break;
253 }
254 }
255 free(children, M_TEMP);
256 }
257 }
258}
259
224
225 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
226 ata_pci_hw(dev);
227 return 0;
228}
229
230static void
231ata_ali_reset(device_t dev)

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255 break;
256 }
257 }
258 free(children, M_TEMP);
259 }
260 }
261}
262
260static void
261ata_ali_setmode(device_t dev, int mode)
263static int
264ata_ali_setmode(device_t dev, int target, int mode)
262{
265{
263 device_t gparent = GRANDPARENT(dev);
264 struct ata_pci_controller *ctlr = device_get_softc(gparent);
265 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
266 struct ata_device *atadev = device_get_softc(dev);
267 int devno = (ch->unit << 1) + atadev->unit;
268 int error;
266 device_t parent = device_get_parent(dev);
267 struct ata_pci_controller *ctlr = device_get_softc(parent);
268 struct ata_channel *ch = device_get_softc(dev);
269 int devno = (ch->unit << 1) + target;
270 int piomode;
271 u_int32_t piotimings[] =
272 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
273 0x00310001, 0x006d0003, 0x00330001, 0x00310001 };
274 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
275 u_int32_t word54;
269
276
270 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
277 mode = min(mode, ctlr->chip->max_dma);
271
278
272 if (ctlr->chip->cfg2 & ALI_NEW) {
273 if (mode > ATA_UDMA2 &&
274 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
275 ata_print_cable(dev, "controller");
276 mode = ATA_UDMA2;
279 if (ctlr->chip->cfg2 & ALI_NEW) {
280 if (mode > ATA_UDMA2 &&
281 pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) {
282 ata_print_cable(dev, "controller");
283 mode = ATA_UDMA2;
284 }
277 }
285 }
278 }
279 else
280 mode = ata_check_80pin(dev, mode);
281
282 if (ctlr->chip->cfg2 & ALI_OLD) {
283 /* doesn't support ATAPI DMA on write */
284 ch->flags |= ATA_ATAPI_DMA_RO;
285 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
286 /* doesn't support ATAPI DMA on two ATAPI devices */
287 device_printf(dev, "two atapi devices on this channel, no DMA\n");
288 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
286 if (ctlr->chip->cfg2 & ALI_OLD) {
287 /* doesn't support ATAPI DMA on write */
288 ch->flags |= ATA_ATAPI_DMA_RO;
289 if (ch->devices & ATA_ATAPI_MASTER &&
290 ch->devices & ATA_ATAPI_SLAVE) {
291 /* doesn't support ATAPI DMA on two ATAPI devices */
292 device_printf(dev, "two atapi devices on this channel,"
293 " no DMA\n");
294 mode = min(mode, ATA_PIO_MAX);
295 }
289 }
296 }
290 }
291
292 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
293
294 if (bootverbose)
295 device_printf(dev, "%ssetting %s on %s chip\n",
296 (error) ? "FAILURE " : "",
297 ata_mode2str(mode), ctlr->chip->text);
298 if (!error) {
297 /* Set UDMA mode */
298 word54 = pci_read_config(parent, 0x54, 4);
299 if (mode >= ATA_UDMA0) {
299 if (mode >= ATA_UDMA0) {
300 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
301 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
302
303 word54 &= ~(0x000f000f << (devno << 2));
304 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
300 word54 &= ~(0x000f000f << (devno << 2));
301 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
305 pci_write_config(gparent, 0x54, word54, 4);
306 pci_write_config(gparent, 0x58 + (ch->unit << 2),
307 0x00310001, 4);
302 piomode = ATA_PIO4;
308 }
309 else {
303 }
304 else {
310 u_int32_t piotimings[] =
311 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
312 0x00310001, 0x00440001, 0x00330001, 0x00310001};
313
314 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
315 ~(0x0008000f << (devno << 2)), 4);
316 pci_write_config(gparent, 0x58 + (ch->unit << 2),
317 piotimings[ata_mode2idx(mode)], 4);
305 word54 &= ~(0x0008000f << (devno << 2));
306 piomode = mode;
318 }
307 }
319 atadev->mode = mode;
320 }
308 pci_write_config(parent, 0x54, word54, 4);
309 /* Set PIO/WDMA mode */
310 pci_write_config(parent, 0x58 + (ch->unit << 2),
311 piotimings[ata_mode2idx(piomode)], 4);
312 return (mode);
321}
322
323ATA_DECLARE_DRIVER(ata_ali);
324MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);
313}
314
315ATA_DECLARE_DRIVER(ata_ali);
316MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);