arcmsr.h (e477abf734cc777a55286bfbd6b80a6760c96acf) | arcmsr.h (7a7bc9595c3df265047a164cd1c7c4233f4049bf) |
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1/* 2*********************************************************************************************** 3** O.S : FreeBSD 4** FILE NAME : arcmsr.h 5** BY : Erich Chen, Ching Huang 6** Description: SCSI RAID Device Driver for 7** ARECA SATA/SAS RAID HOST Adapter 8** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] --- 30 unchanged lines hidden (view full) --- 39*/ 40#define ARCMSR_SCSI_INITIATOR_ID 255 41#define ARCMSR_DEV_SECTOR_SIZE 512 42#define ARCMSR_MAX_XFER_SECTORS 4096 43#define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 44#define ARCMSR_MAX_TARGETLUN 8 /*8*/ 45#define ARCMSR_MAX_CHIPTYPE_NUM 4 46#define ARCMSR_MAX_OUTSTANDING_CMD 256 | 1/* 2*********************************************************************************************** 3** O.S : FreeBSD 4** FILE NAME : arcmsr.h 5** BY : Erich Chen, Ching Huang 6** Description: SCSI RAID Device Driver for 7** ARECA SATA/SAS RAID HOST Adapter 8** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] --- 30 unchanged lines hidden (view full) --- 39*/ 40#define ARCMSR_SCSI_INITIATOR_ID 255 41#define ARCMSR_DEV_SECTOR_SIZE 512 42#define ARCMSR_MAX_XFER_SECTORS 4096 43#define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 44#define ARCMSR_MAX_TARGETLUN 8 /*8*/ 45#define ARCMSR_MAX_CHIPTYPE_NUM 4 46#define ARCMSR_MAX_OUTSTANDING_CMD 256 |
47#define ARCMSR_MAX_START_JOB 257 | 47#define ARCMSR_MAX_START_JOB 256 |
48#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 49#define ARCMSR_MAX_FREESRB_NUM 384 50#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 51#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 52#define ARCMSR_MAX_ADAPTER 4 53#define ARCMSR_RELEASE_SIMQ_LEVEL 230 54#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ | 48#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 49#define ARCMSR_MAX_FREESRB_NUM 384 50#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 51#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 52#define ARCMSR_MAX_ADAPTER 4 53#define ARCMSR_RELEASE_SIMQ_LEVEL 230 54#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ |
55#define ARCMSR_MAX_HBD_POSTQUEUE 256 |
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55#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 56/* 57********************************************************************* 58*/ 59#ifndef TRUE 60 #define TRUE 1 61#endif 62#ifndef FALSE 63 #define FALSE 0 64#endif 65#ifndef INTR_ENTROPY 66 # define INTR_ENTROPY 0 67#endif 68 69#ifndef offsetof 70 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 71#endif | 56#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 57/* 58********************************************************************* 59*/ 60#ifndef TRUE 61 #define TRUE 1 62#endif 63#ifndef FALSE 64 #define FALSE 0 65#endif 66#ifndef INTR_ENTROPY 67 # define INTR_ENTROPY 0 68#endif 69 70#ifndef offsetof 71 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 72#endif |
73 74#if __FreeBSD_version >= 500005 75 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 76 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 77 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 78 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 79 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 80 #define arcmsr_htole32(x) htole32(x) 81 typedef struct mtx arcmsr_lock_t; 82#else 83 #define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l) 84 #define ARCMSR_LOCK_DESTROY(l) 85 #define ARCMSR_LOCK_ACQUIRE(l) simple_lock(l) 86 #define ARCMSR_LOCK_RELEASE(l) simple_unlock(l) 87 #define ARCMSR_LOCK_TRY(l) simple_lock_try(l) 88 #define arcmsr_htole32(x) (x) 89 typedef struct simplelock arcmsr_lock_t; 90#endif 91 |
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72/* 73********************************************************************************** 74** 75********************************************************************************** 76*/ 77#define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 78#define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 79#define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 80#define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 81#define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 82#define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 83#define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 84#define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 85#define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 86#define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ | 92/* 93********************************************************************************** 94** 95********************************************************************************** 96*/ 97#define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 98#define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 99#define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 100#define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 101#define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 102#define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 103#define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 104#define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 105#define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 106#define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ |
107#define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ |
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87#define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 88#define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 89#define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 90#define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 91#define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 92#define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 93#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 94#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ --- 15 unchanged lines hidden (view full) --- 110#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 111#define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 112#define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 113#define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 114#define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 115#define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 116#define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 117#define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ | 108#define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 109#define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 110#define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 111#define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 112#define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 113#define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 114#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 115#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ --- 15 unchanged lines hidden (view full) --- 131#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 132#define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 133#define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 134#define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 135#define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 136#define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 137#define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 138#define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ |
139#define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ |
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118#define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 119#define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 120#define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 121#define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 122#define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 123#define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 124#define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 125#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ --- 32 unchanged lines hidden (view full) --- 158*/ 159#define arcmsr_ccbsrb_ptr spriv_ptr0 160#define arcmsr_ccbacb_ptr spriv_ptr1 161#define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 162#define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 163#define get_min(x,y) ((x) < (y) ? (x) : (y)) 164#define get_max(x,y) ((x) < (y) ? (y) : (x)) 165/* | 140#define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 141#define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 142#define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 143#define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 144#define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 145#define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 146#define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 147#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ --- 32 unchanged lines hidden (view full) --- 180*/ 181#define arcmsr_ccbsrb_ptr spriv_ptr0 182#define arcmsr_ccbacb_ptr spriv_ptr1 183#define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 184#define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 185#define get_min(x,y) ((x) < (y) ? (x) : (y)) 186#define get_max(x,y) ((x) < (y) ? (y) : (x)) 187/* |
188************************************************************************** 189************************************************************************** 190*/ 191#define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 192#define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 193/* |
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166********************************************************************************** | 194********************************************************************************** |
167** | 195** IOCTL CONTROL Mail Box |
168********************************************************************************** 169*/ 170struct CMD_MESSAGE { 171 u_int32_t HeaderLength; 172 u_int8_t Signature[8]; 173 u_int32_t Timeout; 174 u_int32_t ControlCode; 175 u_int32_t ReturnCode; --- 30 unchanged lines hidden (view full) --- 206#define FUNCTION_CLEAR_WQBUFFER 0x0804 207#define FUNCTION_CLEAR_ALLQBUFFER 0x0805 208#define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 209#define FUNCTION_SAY_HELLO 0x0807 210#define FUNCTION_SAY_GOODBYE 0x0808 211#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 212/* 213************************************************************************ | 196********************************************************************************** 197*/ 198struct CMD_MESSAGE { 199 u_int32_t HeaderLength; 200 u_int8_t Signature[8]; 201 u_int32_t Timeout; 202 u_int32_t ControlCode; 203 u_int32_t ReturnCode; --- 30 unchanged lines hidden (view full) --- 234#define FUNCTION_CLEAR_WQBUFFER 0x0804 235#define FUNCTION_CLEAR_ALLQBUFFER 0x0805 236#define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 237#define FUNCTION_SAY_HELLO 0x0807 238#define FUNCTION_SAY_GOODBYE 0x0808 239#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 240/* 241************************************************************************ |
214** IOCTL CONTROL CODE | 242** IOCTL CONTROL CODE |
215************************************************************************ 216*/ 217/* ARECA IO CONTROL CODE*/ 218#define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 219#define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 220#define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 221#define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 222#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) --- 4 unchanged lines hidden (view full) --- 227 228/* ARECA IOCTL ReturnCode */ 229#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 230#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 231#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 232#define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 233/* 234************************************************************************ | 243************************************************************************ 244*/ 245/* ARECA IO CONTROL CODE*/ 246#define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 247#define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 248#define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 249#define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 250#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) --- 4 unchanged lines hidden (view full) --- 255 256/* ARECA IOCTL ReturnCode */ 257#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 258#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 259#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 260#define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 261/* 262************************************************************************ |
263** SPEC. for Areca HBA adapter 264************************************************************************ 265*/ 266/* signature of set and get firmware config */ 267#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 268#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 269/* message code of inbound message register */ 270#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 271#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 272#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 273#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 274#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 275#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 276#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 277#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 278#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 279/* doorbell interrupt generator */ 280#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 281#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 282#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 283#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 284/* srb areca cdb flag */ 285#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 286#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 287#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 288#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 289#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 290#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 291/* outbound firmware ok */ 292#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 293 294#define ARCMSR_ARC1680_BUS_RESET 0x00000003 295/* 296************************************************************************ |
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235** SPEC. for Areca HBB adapter 236************************************************************************ 237*/ 238/* ARECA HBB COMMAND for its FIRMWARE */ 239#define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 240#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 241#define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 242#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C --- 76 unchanged lines hidden (view full) --- 319#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 320#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 321#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 322#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 323#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 324#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 325#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 326#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ | 297** SPEC. for Areca HBB adapter 298************************************************************************ 299*/ 300/* ARECA HBB COMMAND for its FIRMWARE */ 301#define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 302#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 303#define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 304#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C --- 76 unchanged lines hidden (view full) --- 381#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 382#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 383#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 384#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 385#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 386#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 387#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 388#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ |
389#define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 390#define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 |
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327 328/* | 391 392/* |
393************************************************************************ 394** SPEC. for Areca HBD adapter 395************************************************************************ 396*/ 397#define ARCMSR_HBDMU_CHIP_ID 0x00004 398#define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 399#define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 400#define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 401#define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 402#define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 403#define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 404#define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 405#define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 406#define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 407#define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 408#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 409#define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 410#define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 411#define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 412#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 413#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 414#define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 415#define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 416#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 417#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 418 419#define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 420#define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 421#define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 422 423#define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 424#define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 425 426/* Host Interrupt Mask */ 427#define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 428#define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 429 430/* Host Interrupt Status */ 431#define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 432#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 433#define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 434 435/* DoorBell*/ 436#define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 437#define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 438 439#define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 440#define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 441 442/*outbound message 0 ready*/ 443#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 444 445#define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 446 447/*outbound message cmd isr door bell clear*/ 448#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 449 450/*outbound list */ 451#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 452#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 453 454/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 455#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 456/* 457********************************************************************* 458** Message Unit structure 459********************************************************************* 460*/ 461struct HBA_MessageUnit 462{ 463 u_int32_t resrved0[4]; /*0000 000F*/ 464 u_int32_t inbound_msgaddr0; /*0010 0013*/ 465 u_int32_t inbound_msgaddr1; /*0014 0017*/ 466 u_int32_t outbound_msgaddr0; /*0018 001B*/ 467 u_int32_t outbound_msgaddr1; /*001C 001F*/ 468 u_int32_t inbound_doorbell; /*0020 0023*/ 469 u_int32_t inbound_intstatus; /*0024 0027*/ 470 u_int32_t inbound_intmask; /*0028 002B*/ 471 u_int32_t outbound_doorbell; /*002C 002F*/ 472 u_int32_t outbound_intstatus; /*0030 0033*/ 473 u_int32_t outbound_intmask; /*0034 0037*/ 474 u_int32_t reserved1[2]; /*0038 003F*/ 475 u_int32_t inbound_queueport; /*0040 0043*/ 476 u_int32_t outbound_queueport; /*0044 0047*/ 477 u_int32_t reserved2[2]; /*0048 004F*/ 478 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 479 u_int32_t reserved4[128]; /*0800 09FF 128*/ 480 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 481 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 482 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 483 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 484 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 485}; 486/* 487********************************************************************* 488** 489********************************************************************* 490*/ 491struct HBB_DOORBELL 492{ 493 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 494 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 495 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 496 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 497 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 498}; 499/* 500********************************************************************* 501** 502********************************************************************* 503*/ 504struct HBB_RWBUFFER 505{ 506 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 507 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 508 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 509 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 510 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 511}; 512/* 513********************************************************************* 514** 515********************************************************************* 516*/ 517struct HBB_MessageUnit 518{ 519 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 520 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 521 int32_t postq_index; /* post queue index */ 522 int32_t doneq_index; /* done queue index */ 523 struct HBB_DOORBELL *hbb_doorbell; 524 struct HBB_RWBUFFER *hbb_rwbuffer; 525}; 526 527/* 528********************************************************************* 529** 530********************************************************************* 531*/ 532struct HBC_MessageUnit { 533 u_int32_t message_unit_status; /*0000 0003*/ 534 u_int32_t slave_error_attribute; /*0004 0007*/ 535 u_int32_t slave_error_address; /*0008 000B*/ 536 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 537 u_int32_t master_error_attribute; /*0010 0013*/ 538 u_int32_t master_error_address_low; /*0014 0017*/ 539 u_int32_t master_error_address_high; /*0018 001B*/ 540 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 541 u_int32_t inbound_doorbell; /*0020 0023*/ 542 u_int32_t diagnostic_rw_data; /*0024 0027*/ 543 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 544 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 545 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 546 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 547 u_int32_t dcr_data; /*0038 003B*/ 548 u_int32_t dcr_address; /*003C 003F*/ 549 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 550 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 551 u_int32_t hcb_pci_address_low; /*0048 004B*/ 552 u_int32_t hcb_pci_address_high; /*004C 004F*/ 553 u_int32_t iop_int_status; /*0050 0053*/ 554 u_int32_t iop_int_mask; /*0054 0057*/ 555 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 556 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 557 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 558 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 559 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 560 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 561 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 562 u_int32_t i2o_message_unit_control; /*0074 0077*/ 563 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 564 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 565 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 566 u_int32_t message_dest_address_index; /*0090 0093*/ 567 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 568 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 569 u_int32_t outbound_doorbell; /*009C 009F*/ 570 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 571 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 572 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 573 u_int32_t reserved0; /*00AC 00AF*/ 574 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 575 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 576 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 577 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 578 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 579 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 580 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 581 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 582 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 583 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 584 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 585 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 586 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 587 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 588 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 589 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 590 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 591 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 592 u_int32_t host_diagnostic; /*00F8 00FB*/ 593 u_int32_t write_sequence; /*00FC 00FF*/ 594 u_int32_t reserved1[34]; /*0100 0187*/ 595 u_int32_t reserved2[1950]; /*0188 1FFF*/ 596 u_int32_t message_wbuffer[32]; /*2000 207F*/ 597 u_int32_t reserved3[32]; /*2080 20FF*/ 598 u_int32_t message_rbuffer[32]; /*2100 217F*/ 599 u_int32_t reserved4[32]; /*2180 21FF*/ 600 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 601}; 602/* 603********************************************************************* 604** 605********************************************************************* 606*/ 607struct InBound_SRB { 608 uint32_t addressLow; //pointer to SRB block 609 uint32_t addressHigh; 610 uint32_t length; // in DWORDs 611 uint32_t reserved0; 612}; 613 614struct OutBound_SRB { 615 uint32_t addressLow; //pointer to SRB block 616 uint32_t addressHigh; 617}; 618 619struct HBD_MessageUnit { 620 uint32_t reserved0; 621 uint32_t chip_id; //0x0004 622 uint32_t cpu_mem_config; //0x0008 623 uint32_t reserved1[10]; //0x000C 624 uint32_t i2o_host_interrupt_mask; //0x0034 625 uint32_t reserved2[114]; //0x0038 626 uint32_t host_int_status; //0x0200 627 uint32_t host_int_enable; //0x0204 628 uint32_t reserved3[1]; //0x0208 629 uint32_t pcief0_int_enable; //0x020C 630 uint32_t reserved4[124]; //0x0210 631 uint32_t inbound_msgaddr0; //0x0400 632 uint32_t inbound_msgaddr1; //0x0404 633 uint32_t reserved5[6]; //0x0408 634 uint32_t outbound_msgaddr0; //0x0420 635 uint32_t outbound_msgaddr1; //0x0424 636 uint32_t reserved6[14]; //0x0428 637 uint32_t inbound_doorbell; //0x0460 638 uint32_t reserved7[7]; //0x0464 639 uint32_t outbound_doorbell; //0x0480 640 uint32_t outbound_doorbell_enable; //0x0484 641 uint32_t reserved8[734]; //0x0488 642 uint32_t inboundlist_base_low; //0x1000 643 uint32_t inboundlist_base_high; //0x1004 644 uint32_t reserved9[4]; //0x1008 645 uint32_t inboundlist_write_pointer; //0x1018 646 uint32_t inboundlist_read_pointer; //0x101C 647 uint32_t reserved10[16]; //0x1020 648 uint32_t outboundlist_base_low; //0x1060 649 uint32_t outboundlist_base_high; //0x1064 650 uint32_t reserved11; //0x1068 651 uint32_t outboundlist_copy_pointer; //0x106C 652 uint32_t outboundlist_read_pointer; //0x1070 0x1072 653 uint32_t reserved12[5]; //0x1074 654 uint32_t outboundlist_interrupt_cause; //0x1088 655 uint32_t outboundlist_interrupt_enable; //0x108C 656 uint32_t reserved13[988]; //0x1090 657 uint32_t message_wbuffer[32]; //0x2000 658 uint32_t reserved14[32]; //0x2080 659 uint32_t message_rbuffer[32]; //0x2100 660 uint32_t reserved15[32]; //0x2180 661 uint32_t msgcode_rwbuffer[256]; //0x2200 662}; 663 664struct HBD_MessageUnit0 { 665 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 666 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 667 uint16_t postq_index; 668 uint16_t doneq_index; 669 struct HBD_MessageUnit *phbdmu; 670}; 671 672/* 673********************************************************************* 674** 675********************************************************************* 676*/ 677struct MessageUnit_UNION 678{ 679 union { 680 struct HBA_MessageUnit hbamu; 681 struct HBB_MessageUnit hbbmu; 682 struct HBC_MessageUnit hbcmu; 683 struct HBD_MessageUnit0 hbdmu; 684 } muu; 685}; 686/* |
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329************************************************************* 330** structure for holding DMA address data 331************************************************************* 332*/ 333#define IS_SG64_ADDR 0x01000000 /* bit24 */ 334/* 335************************************************************************************************ 336** ARECA FIRMWARE SPEC --- 201 unchanged lines hidden (view full) --- 538** bit2:0 , reserved (will be 0) 539** bit3:0 , reserved (will be 0) 540** bit63-4: Completed command address 541** 542** <E> BIOS support, no special support is required. 543** LSI2108 support I/O register 544** All driver functionality is supported through I/O address 545** | 687************************************************************* 688** structure for holding DMA address data 689************************************************************* 690*/ 691#define IS_SG64_ADDR 0x01000000 /* bit24 */ 692/* 693************************************************************************************************ 694** ARECA FIRMWARE SPEC --- 201 unchanged lines hidden (view full) --- 896** bit2:0 , reserved (will be 0) 897** bit3:0 , reserved (will be 0) 898** bit63-4: Completed command address 899** 900** <E> BIOS support, no special support is required. 901** LSI2108 support I/O register 902** All driver functionality is supported through I/O address 903** |
546** For further spec, refer to 547** \spec\lsi\2108 for Areca\2108\LSISAS2108_PG_NoEncryption.pdf : Chapter 8 (8-11/8-28) 548** \spec\lsi\2108 for Areca\2108\SAS2108_RM_20.pdf : for configuration space | |
549************************************************************************************************ 550*/ | 904************************************************************************************************ 905*/ |
551/* signature of set and get firmware config */ 552#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 553#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 554/* message code of inbound message register */ 555#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 556#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 557#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 558#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 559#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 560#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 561#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 562#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 563#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 564/* doorbell interrupt generator */ 565#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 566#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 567#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 568#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 569/* srb areca cdb flag */ 570#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 571#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 572#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 573#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 574#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 575#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 576/* outbound firmware ok */ 577#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 | |
578/* 579********************************** 580** 581********************************** 582*/ 583/* size 8 bytes */ 584/* 32bit Scatter-Gather list */ 585struct SG32ENTRY { /* length bit 24 == 0 */ --- 18 unchanged lines hidden (view full) --- 604** 605********************************** 606*/ 607struct QBUFFER { 608 u_int32_t data_len; 609 u_int8_t data[124]; 610}; 611/* | 906/* 907********************************** 908** 909********************************** 910*/ 911/* size 8 bytes */ 912/* 32bit Scatter-Gather list */ 913struct SG32ENTRY { /* length bit 24 == 0 */ --- 18 unchanged lines hidden (view full) --- 932** 933********************************** 934*/ 935struct QBUFFER { 936 u_int32_t data_len; 937 u_int8_t data[124]; 938}; 939/* |
940********************************** 941*/ 942typedef struct PHYS_ADDR64 { 943 u_int32_t phyadd_low; 944 u_int32_t phyadd_high; 945}PHYSADDR64; 946/* |
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612************************************************************************************************ 613** FIRMWARE INFO 614************************************************************************************************ 615*/ 616#define ARCMSR_FW_MODEL_OFFSET 15 617#define ARCMSR_FW_VERS_OFFSET 17 618#define ARCMSR_FW_DEVMAP_OFFSET 21 619#define ARCMSR_FW_CFGVER_OFFSET 25 --- 48 unchanged lines hidden (view full) --- 668 u_int8_t Bus; /* 00h should be 0 */ 669 u_int8_t TargetID; /* 01h should be 0--15 */ 670 u_int8_t LUN; /* 02h should be 0--7 */ 671 u_int8_t Function; /* 03h should be 1 */ 672 673 u_int8_t CdbLength; /* 04h not used now */ 674 u_int8_t sgcount; /* 05h */ 675 u_int8_t Flags; /* 06h */ | 947************************************************************************************************ 948** FIRMWARE INFO 949************************************************************************************************ 950*/ 951#define ARCMSR_FW_MODEL_OFFSET 15 952#define ARCMSR_FW_VERS_OFFSET 17 953#define ARCMSR_FW_DEVMAP_OFFSET 21 954#define ARCMSR_FW_CFGVER_OFFSET 25 --- 48 unchanged lines hidden (view full) --- 1003 u_int8_t Bus; /* 00h should be 0 */ 1004 u_int8_t TargetID; /* 01h should be 0--15 */ 1005 u_int8_t LUN; /* 02h should be 0--7 */ 1006 u_int8_t Function; /* 03h should be 1 */ 1007 1008 u_int8_t CdbLength; /* 04h not used now */ 1009 u_int8_t sgcount; /* 05h */ 1010 u_int8_t Flags; /* 06h */ |
676#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 677#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 678#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 679#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 680#define ARCMSR_CDB_FLAG_HEADQ 0x08 681#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 | |
682 u_int8_t msgPages; /* 07h */ 683 684 u_int32_t Context; /* 08h Address of this request */ 685 u_int32_t DataLength; /* 0ch not used now */ 686 687 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 688 /* 689 ******************************************************** | 1011 u_int8_t msgPages; /* 07h */ 1012 1013 u_int32_t Context; /* 08h Address of this request */ 1014 u_int32_t DataLength; /* 0ch not used now */ 1015 1016 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1017 /* 1018 ******************************************************** |
690 **Device Status : the same from SCSI bus if error occur | 1019 ** Device Status : the same from SCSI bus if error occur |
691 ** SCSI bus status codes. 692 ******************************************************** 693 */ 694 u_int8_t DeviceStatus; /* 20h if error */ | 1020 ** SCSI bus status codes. 1021 ******************************************************** 1022 */ 1023 u_int8_t DeviceStatus; /* 20h if error */ |
1024 1025 u_int8_t SenseData[15]; /* 21h output */ 1026 1027 union { 1028 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1029 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1030 } u; 1031}; 1032/* CDB flag */ 1033#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1034#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1035#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1036#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1037#define ARCMSR_CDB_FLAG_HEADQ 0x08 1038#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1039/* scsi status */ |
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695#define SCSISTAT_GOOD 0x00 696#define SCSISTAT_CHECK_CONDITION 0x02 697#define SCSISTAT_CONDITION_MET 0x04 698#define SCSISTAT_BUSY 0x08 699#define SCSISTAT_INTERMEDIATE 0x10 700#define SCSISTAT_INTERMEDIATE_COND_MET 0x14 701#define SCSISTAT_RESERVATION_CONFLICT 0x18 702#define SCSISTAT_COMMAND_TERMINATED 0x22 703#define SCSISTAT_QUEUE_FULL 0x28 | 1040#define SCSISTAT_GOOD 0x00 1041#define SCSISTAT_CHECK_CONDITION 0x02 1042#define SCSISTAT_CONDITION_MET 0x04 1043#define SCSISTAT_BUSY 0x08 1044#define SCSISTAT_INTERMEDIATE 0x10 1045#define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1046#define SCSISTAT_RESERVATION_CONFLICT 0x18 1047#define SCSISTAT_COMMAND_TERMINATED 0x22 1048#define SCSISTAT_QUEUE_FULL 0x28 |
1049/* DeviceStatus */ |
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704#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 705#define ARCMSR_DEV_ABORTED 0xF1 706#define ARCMSR_DEV_INIT_FAIL 0xF2 | 1050#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1051#define ARCMSR_DEV_ABORTED 0xF1 1052#define ARCMSR_DEV_INIT_FAIL 0xF2 |
707 708 u_int8_t SenseData[15]; /* 21h output */ 709 710 union { 711 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 712 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 713 } u; 714}; | |
715/* 716********************************************************************* 717** Command Control Block (SrbExtension) 718** SRB must be not cross page boundary,and the order from offset 0 719** structure describing an ATA disk request 720** this SRB length must be 32 bytes boundary 721********************************************************************* 722*/ 723struct CommandControlBlock { 724 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ | 1053/* 1054********************************************************************* 1055** Command Control Block (SrbExtension) 1056** SRB must be not cross page boundary,and the order from offset 0 1057** structure describing an ATA disk request 1058** this SRB length must be 32 bytes boundary 1059********************************************************************* 1060*/ 1061struct CommandControlBlock { 1062 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ |
725 u_int32_t cdb_shifted_phyaddr; /* 504-507 */ | 1063 u_int32_t cdb_phyaddr_low; /* 504-507 */ |
726 u_int32_t arc_cdb_size; /* 508-511 */ 727 /* ======================512+32 bytes============================ */ 728 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 729 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 730 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 731 u_int16_t srb_flags; /* 536-537 */ | 1064 u_int32_t arc_cdb_size; /* 508-511 */ 1065 /* ======================512+32 bytes============================ */ 1066 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1067 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1068 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1069 u_int16_t srb_flags; /* 536-537 */ |
732 u_int16_t srb_state; /* 538-539 */ | 1070 u_int16_t srb_state; /* 538-539 */ 1071 u_int32_t cdb_phyaddr_high; /* 540-543 */ |
733 struct callout ccb_callout; 734 /* ========================================================== */ 735}; 736/* srb_flags */ 737#define SRB_FLAG_READ 0x0000 738#define SRB_FLAG_WRITE 0x0001 739#define SRB_FLAG_ERROR 0x0002 740#define SRB_FLAG_FLUSHCACHE 0x0004 --- 8 unchanged lines hidden (view full) --- 749#define ARCMSR_SRB_UNBUILD 0x0000 750#define ARCMSR_SRB_TIMEOUT 0x1111 751#define ARCMSR_SRB_RETRY 0x2222 752#define ARCMSR_SRB_START 0x55AA 753#define ARCMSR_SRB_PENDING 0xAA55 754#define ARCMSR_SRB_RESET 0xA5A5 755#define ARCMSR_SRB_ABORTED 0x5A5A 756#define ARCMSR_SRB_ILLEGAL 0xFFFF | 1072 struct callout ccb_callout; 1073 /* ========================================================== */ 1074}; 1075/* srb_flags */ 1076#define SRB_FLAG_READ 0x0000 1077#define SRB_FLAG_WRITE 0x0001 1078#define SRB_FLAG_ERROR 0x0002 1079#define SRB_FLAG_FLUSHCACHE 0x0004 --- 8 unchanged lines hidden (view full) --- 1088#define ARCMSR_SRB_UNBUILD 0x0000 1089#define ARCMSR_SRB_TIMEOUT 0x1111 1090#define ARCMSR_SRB_RETRY 0x2222 1091#define ARCMSR_SRB_START 0x55AA 1092#define ARCMSR_SRB_PENDING 0xAA55 1093#define ARCMSR_SRB_RESET 0xA5A5 1094#define ARCMSR_SRB_ABORTED 0x5A5A 1095#define ARCMSR_SRB_ILLEGAL 0xFFFF |
1096 1097#define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1098#define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1099 |
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757/* 758********************************************************************* 759** Adapter Control Block 760********************************************************************* 761*/ 762#define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 763#define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 764#define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ | 1100/* 1101********************************************************************* 1102** Adapter Control Block 1103********************************************************************* 1104*/ 1105#define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 1106#define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 1107#define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ |
765#define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ | 1108#define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd M IOP */ |
766 767struct AdapterControlBlock { 768 u_int32_t adapter_type; /* adapter A,B..... */ 769 770 bus_space_tag_t btag[2]; 771 bus_space_handle_t bhandle[2]; 772 bus_dma_tag_t parent_dmat; 773 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ --- 42 unchanged lines hidden (view full) --- 816 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 817 u_int32_t rqbuf_firstindex; /* first of read buffer */ 818 u_int32_t rqbuf_lastindex; /* last of read buffer */ 819 820 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 821 u_int32_t wqbuf_firstindex; /* first of write buffer */ 822 u_int32_t wqbuf_lastindex; /* last of write buffer */ 823 | 1109 1110struct AdapterControlBlock { 1111 u_int32_t adapter_type; /* adapter A,B..... */ 1112 1113 bus_space_tag_t btag[2]; 1114 bus_space_handle_t bhandle[2]; 1115 bus_dma_tag_t parent_dmat; 1116 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ --- 42 unchanged lines hidden (view full) --- 1159 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1160 u_int32_t rqbuf_firstindex; /* first of read buffer */ 1161 u_int32_t rqbuf_lastindex; /* last of read buffer */ 1162 1163 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1164 u_int32_t wqbuf_firstindex; /* first of write buffer */ 1165 u_int32_t wqbuf_lastindex; /* last of write buffer */ 1166 |
824 arcmsr_lock_t workingQ_done_lock; 825 arcmsr_lock_t workingQ_start_lock; | 1167 arcmsr_lock_t isr_lock; 1168 arcmsr_lock_t srb_lock; 1169 arcmsr_lock_t postDone_lock; |
826 arcmsr_lock_t qbuffer_lock; 827 828 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 829 u_int32_t num_resets; 830 u_int32_t num_aborts; 831 u_int32_t firm_request_len; /*1,04-07*/ 832 u_int32_t firm_numbers_queue; /*2,08-11*/ 833 u_int32_t firm_sdram_size; /*3,12-15*/ 834 u_int32_t firm_ide_channels; /*4,16-19*/ 835 u_int32_t firm_cfg_version; 836 char firm_model[12]; /*15,60-67*/ 837 char firm_version[20]; /*17,68-83*/ 838 char device_map[20]; /*21,84-99 */ 839 struct callout devmap_callout; | 1170 arcmsr_lock_t qbuffer_lock; 1171 1172 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1173 u_int32_t num_resets; 1174 u_int32_t num_aborts; 1175 u_int32_t firm_request_len; /*1,04-07*/ 1176 u_int32_t firm_numbers_queue; /*2,08-11*/ 1177 u_int32_t firm_sdram_size; /*3,12-15*/ 1178 u_int32_t firm_ide_channels; /*4,16-19*/ 1179 u_int32_t firm_cfg_version; 1180 char firm_model[12]; /*15,60-67*/ 1181 char firm_version[20]; /*17,68-83*/ 1182 char device_map[20]; /*21,84-99 */ 1183 struct callout devmap_callout; |
840#ifdef ARCMSR_DEBUG1 | |
841 u_int32_t pktRequestCount; 842 u_int32_t pktReturnCount; | 1184 u_int32_t pktRequestCount; 1185 u_int32_t pktReturnCount; |
843#endif | |
844 u_int32_t vendor_device_id; 845 u_int32_t adapter_bus_speed; 846};/* HW_DEVICE_EXTENSION */ 847/* acb_flags */ 848#define ACB_F_SCSISTOPADAPTER 0x0001 849#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 850#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 851#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ --- 9 unchanged lines hidden (view full) --- 861/* devstate */ 862#define ARECA_RAID_GONE 0x55 863#define ARECA_RAID_GOOD 0xaa 864/* adapter_bus_speed */ 865#define ACB_BUS_SPEED_3G 0 866#define ACB_BUS_SPEED_6G 1 867#define ACB_BUS_SPEED_12G 2 868/* | 1186 u_int32_t vendor_device_id; 1187 u_int32_t adapter_bus_speed; 1188};/* HW_DEVICE_EXTENSION */ 1189/* acb_flags */ 1190#define ACB_F_SCSISTOPADAPTER 0x0001 1191#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1192#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1193#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ --- 9 unchanged lines hidden (view full) --- 1203/* devstate */ 1204#define ARECA_RAID_GONE 0x55 1205#define ARECA_RAID_GOOD 0xaa 1206/* adapter_bus_speed */ 1207#define ACB_BUS_SPEED_3G 0 1208#define ACB_BUS_SPEED_6G 1 1209#define ACB_BUS_SPEED_12G 2 1210/* |
869********************************************************************* 870** Message Unit structure 871********************************************************************* 872*/ 873struct HBA_MessageUnit 874{ 875 u_int32_t resrved0[4]; /*0000 000F*/ 876 u_int32_t inbound_msgaddr0; /*0010 0013*/ 877 u_int32_t inbound_msgaddr1; /*0014 0017*/ 878 u_int32_t outbound_msgaddr0; /*0018 001B*/ 879 u_int32_t outbound_msgaddr1; /*001C 001F*/ 880 u_int32_t inbound_doorbell; /*0020 0023*/ 881 u_int32_t inbound_intstatus; /*0024 0027*/ 882 u_int32_t inbound_intmask; /*0028 002B*/ 883 u_int32_t outbound_doorbell; /*002C 002F*/ 884 u_int32_t outbound_intstatus; /*0030 0033*/ 885 u_int32_t outbound_intmask; /*0034 0037*/ 886 u_int32_t reserved1[2]; /*0038 003F*/ 887 u_int32_t inbound_queueport; /*0040 0043*/ 888 u_int32_t outbound_queueport; /*0044 0047*/ 889 u_int32_t reserved2[2]; /*0048 004F*/ 890 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 891 u_int32_t reserved4[128]; /*0800 09FF 128*/ 892 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 893 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 894 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 895 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 896 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 897}; 898/* 899********************************************************************* 900** 901********************************************************************* 902*/ 903struct HBB_DOORBELL 904{ 905 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 906 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 907 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 908 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 909 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 910}; 911/* 912********************************************************************* 913** 914********************************************************************* 915*/ 916struct HBB_RWBUFFER 917{ 918 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 919 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 920 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 921 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 922 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 923}; 924/* 925********************************************************************* 926** 927********************************************************************* 928*/ 929struct HBB_MessageUnit 930{ 931 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 932 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 933 int32_t postq_index; /* post queue index */ 934 int32_t doneq_index; /* done queue index */ 935 struct HBB_DOORBELL *hbb_doorbell; 936 struct HBB_RWBUFFER *hbb_rwbuffer; 937}; 938 939/* 940********************************************************************* 941** 942********************************************************************* 943*/ 944struct HBC_MessageUnit { 945 u_int32_t message_unit_status; /*0000 0003*/ 946 u_int32_t slave_error_attribute; /*0004 0007*/ 947 u_int32_t slave_error_address; /*0008 000B*/ 948 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 949 u_int32_t master_error_attribute; /*0010 0013*/ 950 u_int32_t master_error_address_low; /*0014 0017*/ 951 u_int32_t master_error_address_high; /*0018 001B*/ 952 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 953 u_int32_t inbound_doorbell; /*0020 0023*/ 954 u_int32_t diagnostic_rw_data; /*0024 0027*/ 955 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 956 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 957 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 958 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 959 u_int32_t dcr_data; /*0038 003B*/ 960 u_int32_t dcr_address; /*003C 003F*/ 961 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 962 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 963 u_int32_t hcb_pci_address_low; /*0048 004B*/ 964 u_int32_t hcb_pci_address_high; /*004C 004F*/ 965 u_int32_t iop_int_status; /*0050 0053*/ 966 u_int32_t iop_int_mask; /*0054 0057*/ 967 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 968 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 969 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 970 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 971 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 972 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 973 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 974 u_int32_t i2o_message_unit_control; /*0074 0077*/ 975 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 976 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 977 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 978 u_int32_t message_dest_address_index; /*0090 0093*/ 979 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 980 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 981 u_int32_t outbound_doorbell; /*009C 009F*/ 982 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 983 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 984 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 985 u_int32_t reserved0; /*00AC 00AF*/ 986 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 987 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 988 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 989 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 990 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 991 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 992 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 993 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 994 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 995 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 996 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 997 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 998 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 999 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 1000 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 1001 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 1002 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 1003 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 1004 u_int32_t host_diagnostic; /*00F8 00FB*/ 1005 u_int32_t write_sequence; /*00FC 00FF*/ 1006 u_int32_t reserved1[34]; /*0100 0187*/ 1007 u_int32_t reserved2[1950]; /*0188 1FFF*/ 1008 u_int32_t message_wbuffer[32]; /*2000 207F*/ 1009 u_int32_t reserved3[32]; /*2080 20FF*/ 1010 u_int32_t message_rbuffer[32]; /*2100 217F*/ 1011 u_int32_t reserved4[32]; /*2180 21FF*/ 1012 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 1013}; 1014 1015/* 1016********************************************************************* 1017** 1018********************************************************************* 1019*/ 1020struct MessageUnit_UNION 1021{ 1022 union { 1023 struct HBA_MessageUnit hbamu; 1024 struct HBB_MessageUnit hbbmu; 1025 struct HBC_MessageUnit hbcmu; 1026 } muu; 1027}; 1028 1029/* | |
1030************************************************************* 1031************************************************************* 1032*/ 1033struct SENSE_DATA { 1034 u_int8_t ErrorCode:7; 1035 u_int8_t Valid:1; 1036 u_int8_t SegmentNumber; 1037 u_int8_t SenseKey:4; --- 4518 unchanged lines hidden --- | 1211************************************************************* 1212************************************************************* 1213*/ 1214struct SENSE_DATA { 1215 u_int8_t ErrorCode:7; 1216 u_int8_t Valid:1; 1217 u_int8_t SegmentNumber; 1218 u_int8_t SenseKey:4; --- 4518 unchanged lines hidden --- |