arcmsr.h (b626f5a73a48f44a31a200291b141e1da408a2ff) arcmsr.h (a1103e048b0e0b6ddfd6d8b4f7d57b357efb0ad2)
1/*
2********************************************************************************
3** OS : FreeBSD
4** FILE NAME : arcmsr.h
5** BY : Erich Chen, Ching Huang
6** Description: SCSI RAID Device Driver for
7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8** SATA/SAS RAID HOST Adapter

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46#define ARCMSR_MAX_FREESRB_NUM 384
47#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
48#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/
49#define ARCMSR_MAX_ADAPTER 4
50#define ARCMSR_RELEASE_SIMQ_LEVEL 230
51#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
52#define ARCMSR_MAX_HBD_POSTQUEUE 256
53#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */
1/*
2********************************************************************************
3** OS : FreeBSD
4** FILE NAME : arcmsr.h
5** BY : Erich Chen, Ching Huang
6** Description: SCSI RAID Device Driver for
7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8** SATA/SAS RAID HOST Adapter

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46#define ARCMSR_MAX_FREESRB_NUM 384
47#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
48#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/
49#define ARCMSR_MAX_ADAPTER 4
50#define ARCMSR_RELEASE_SIMQ_LEVEL 230
51#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
52#define ARCMSR_MAX_HBD_POSTQUEUE 256
53#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */
54#define ARCMSR_NUM_MSIX_VECTORS 4
54/*
55*********************************************************************
56*/
57#ifndef TRUE
58 #define TRUE 1
59#endif
60#ifndef FALSE
61 #define FALSE 0

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111#define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */
112#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */
113#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */
114#define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */
115#define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */
116#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
117#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
118#define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */
55/*
56*********************************************************************
57*/
58#ifndef TRUE
59 #define TRUE 1
60#endif
61#ifndef FALSE
62 #define FALSE 0

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112#define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */
113#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */
114#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */
115#define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */
116#define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */
117#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
118#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
119#define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */
120#define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */
119
120#define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */
121#define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */
122#define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */
121
122#define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */
123#define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */
124#define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */
125#define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */
123#define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */
124#define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */
125#define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */
126#define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */
127
128#define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */
129#define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */
130#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */

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147#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */
148#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
149#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
150#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
151#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
152#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
153#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
154#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
126#define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */
127#define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */
128#define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */
129#define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */
130
131#define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */
132#define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */
133#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */

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150#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */
151#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
152#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
153#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
154#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
155#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
156#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
157#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
158#define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */
155
156#ifndef PCIR_BARS
157 #define PCIR_BARS 0x10
158 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
159#endif
160
161#define PCI_BASE_ADDR0 0x10
162#define PCI_BASE_ADDR1 0x14

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455#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000
456
457/*outbound list */
458#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001
459#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
460
461/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
462#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
159
160#ifndef PCIR_BARS
161 #define PCIR_BARS 0x10
162 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
163#endif
164
165#define PCI_BASE_ADDR0 0x10
166#define PCI_BASE_ADDR1 0x14

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459#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000
460
461/*outbound list */
462#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001
463#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
464
465/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
466#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
467/*
468*******************************************************************************
469** SPEC. for Areca HBE adapter
470*******************************************************************************
471*/
472#define ARCMSR_SIGNATURE_1884 0x188417D3
473#define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
474#define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
475#define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */
476
477#define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
478#define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
479#define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */
480#define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
481#define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
482#define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */
483#define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */
484/* ARC-1884 doorbell sync */
485#define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
486#define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
463/*
464*********************************************************************
465** Message Unit structure
466*********************************************************************
467*/
468struct HBA_MessageUnit
469{
470 u_int32_t resrved0[4]; /*0000 000F*/

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682
683struct HBD_MessageUnit0 {
684 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE];
685 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1];
686 uint16_t postq_index;
687 uint16_t doneq_index;
688 struct HBD_MessageUnit *phbdmu;
689};
487/*
488*********************************************************************
489** Message Unit structure
490*********************************************************************
491*/
492struct HBA_MessageUnit
493{
494 u_int32_t resrved0[4]; /*0000 000F*/

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706
707struct HBD_MessageUnit0 {
708 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE];
709 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1];
710 uint16_t postq_index;
711 uint16_t doneq_index;
712 struct HBD_MessageUnit *phbdmu;
713};
714/*
715*********************************************************************
716**
717*********************************************************************
718*/
719struct HBE_MessageUnit {
720 u_int32_t iobound_doorbell; /*0000 0003*/
721 u_int32_t write_sequence_3xxx; /*0004 0007*/
722 u_int32_t host_diagnostic_3xxx; /*0008 000B*/
723 u_int32_t posted_outbound_doorbell; /*000C 000F*/
724 u_int32_t master_error_attribute; /*0010 0013*/
725 u_int32_t master_error_address_low; /*0014 0017*/
726 u_int32_t master_error_address_high; /*0018 001B*/
727 u_int32_t hcb_size; /*001C 001F*/
728 u_int32_t inbound_doorbell; /*0020 0023*/
729 u_int32_t diagnostic_rw_data; /*0024 0027*/
730 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
731 u_int32_t diagnostic_rw_address_high; /*002C 002F*/
732 u_int32_t host_int_status; /*0030 0033 host interrupt status*/
733 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
734 u_int32_t dcr_data; /*0038 003B*/
735 u_int32_t dcr_address; /*003C 003F*/
736 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
737 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
738 u_int32_t hcb_pci_address_low; /*0048 004B*/
739 u_int32_t hcb_pci_address_high; /*004C 004F*/
740 u_int32_t iop_int_status; /*0050 0053*/
741 u_int32_t iop_int_mask; /*0054 0057*/
742 u_int32_t iop_inbound_queue_port; /*0058 005B*/
743 u_int32_t iop_outbound_queue_port; /*005C 005F*/
744 u_int32_t inbound_free_list_index; /*0060 0063*/
745 u_int32_t inbound_post_list_index; /*0064 0067*/
746 u_int32_t outbound_free_list_index; /*0068 006B*/
747 u_int32_t outbound_post_list_index; /*006C 006F*/
748 u_int32_t inbound_doorbell_clear; /*0070 0073*/
749 u_int32_t i2o_message_unit_control; /*0074 0077*/
750 u_int32_t last_used_message_source_address_low; /*0078 007B*/
751 u_int32_t last_used_message_source_address_high; /*007C 007F*/
752 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/
753 u_int32_t message_dest_address_index; /*0090 0093*/
754 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
755 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
756 u_int32_t outbound_doorbell; /*009C 009F*/
757 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
758 u_int32_t message_source_address_index; /*00A4 00A7*/
759 u_int32_t message_done_queue_index; /*00A8 00AB*/
760 u_int32_t reserved0; /*00AC 00AF*/
761 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
762 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
763 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
764 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
765 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
766 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
767 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
768 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
769 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
770 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
771 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
772 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
773 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/
774 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/
775 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/
776 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/
777 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/
778 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/
779 u_int32_t host_diagnostic; /*00F8 00FB*/
780 u_int32_t write_sequence; /*00FC 00FF*/
781 u_int32_t reserved1[46]; /*0100 01B7*/
782 u_int32_t reply_post_producer_index; /*01B8 01BB*/
783 u_int32_t reply_post_consumer_index; /*01BC 01BF*/
784 u_int32_t reserved2[1936]; /*01C0 1FFF*/
785 u_int32_t message_wbuffer[32]; /*2000 207F*/
786 u_int32_t reserved3[32]; /*2080 20FF*/
787 u_int32_t message_rbuffer[32]; /*2100 217F*/
788 u_int32_t reserved4[32]; /*2180 21FF*/
789 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
790};
690
791
792typedef struct deliver_completeQ {
793 u_int16_t cmdFlag;
794 u_int16_t cmdSMID;
795 u_int16_t cmdLMID; // reserved (0)
796 u_int16_t cmdFlag2; // reserved (0)
797} DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
798
799#define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128)
800
691/*
692*********************************************************************
693**
694*********************************************************************
695*/
696struct MessageUnit_UNION
697{
698 union {
699 struct HBA_MessageUnit hbamu;
700 struct HBB_MessageUnit hbbmu;
701 struct HBC_MessageUnit hbcmu;
702 struct HBD_MessageUnit0 hbdmu;
801/*
802*********************************************************************
803**
804*********************************************************************
805*/
806struct MessageUnit_UNION
807{
808 union {
809 struct HBA_MessageUnit hbamu;
810 struct HBB_MessageUnit hbbmu;
811 struct HBC_MessageUnit hbcmu;
812 struct HBD_MessageUnit0 hbdmu;
813 struct HBE_MessageUnit hbemu;
703 } muu;
704};
705/*
706*************************************************************
707** structure for holding DMA address data
708*************************************************************
709*/
710#define IS_SG64_ADDR 0x01000000 /* bit24 */

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1084 /* ======================512+32 bytes============================ */
1085 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
1086 struct AdapterControlBlock *acb; /* 520-523 524-527 */
1087 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
1088 u_int16_t srb_flags; /* 536-537 */
1089 u_int16_t srb_state; /* 538-539 */
1090 u_int32_t cdb_phyaddr_high; /* 540-543 */
1091 struct callout ccb_callout;
814 } muu;
815};
816/*
817*************************************************************
818** structure for holding DMA address data
819*************************************************************
820*/
821#define IS_SG64_ADDR 0x01000000 /* bit24 */

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1195 /* ======================512+32 bytes============================ */
1196 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
1197 struct AdapterControlBlock *acb; /* 520-523 524-527 */
1198 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
1199 u_int16_t srb_flags; /* 536-537 */
1200 u_int16_t srb_state; /* 538-539 */
1201 u_int32_t cdb_phyaddr_high; /* 540-543 */
1202 struct callout ccb_callout;
1203 u_int32_t smid;
1092 /* ========================================================== */
1093};
1094/* srb_flags */
1095#define SRB_FLAG_READ 0x0000
1096#define SRB_FLAG_WRITE 0x0001
1097#define SRB_FLAG_ERROR 0x0002
1098#define SRB_FLAG_FLUSHCACHE 0x0004
1099#define SRB_FLAG_MASTER_ABORTED 0x0008

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1116#define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
1117#define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM)
1118
1119/*
1120*********************************************************************
1121** Adapter Control Block
1122*********************************************************************
1123*/
1204 /* ========================================================== */
1205};
1206/* srb_flags */
1207#define SRB_FLAG_READ 0x0000
1208#define SRB_FLAG_WRITE 0x0001
1209#define SRB_FLAG_ERROR 0x0002
1210#define SRB_FLAG_FLUSHCACHE 0x0004
1211#define SRB_FLAG_MASTER_ABORTED 0x0008

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1228#define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
1229#define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM)
1230
1231/*
1232*********************************************************************
1233** Adapter Control Block
1234*********************************************************************
1235*/
1124#define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */
1125#define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */
1126#define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */
1127#define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd M IOP */
1236#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
1237#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
1238#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
1239#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
1240#define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */
1128
1129struct AdapterControlBlock {
1130 u_int32_t adapter_type; /* adapter A,B..... */
1131
1132 bus_space_tag_t btag[2];
1133 bus_space_handle_t bhandle[2];
1134 bus_dma_tag_t parent_dmat;
1135 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */
1136 bus_dma_tag_t srb_dmat; /* dmat for freesrb */
1137 bus_dmamap_t srb_dmamap;
1138 device_t pci_dev;
1139#if __FreeBSD_version < 503000
1140 dev_t ioctl_dev;
1141#else
1142 struct cdev *ioctl_dev;
1143#endif
1144 int pci_unit;
1145
1146 struct resource *sys_res_arcmsr[2];
1241
1242struct AdapterControlBlock {
1243 u_int32_t adapter_type; /* adapter A,B..... */
1244
1245 bus_space_tag_t btag[2];
1246 bus_space_handle_t bhandle[2];
1247 bus_dma_tag_t parent_dmat;
1248 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */
1249 bus_dma_tag_t srb_dmat; /* dmat for freesrb */
1250 bus_dmamap_t srb_dmamap;
1251 device_t pci_dev;
1252#if __FreeBSD_version < 503000
1253 dev_t ioctl_dev;
1254#else
1255 struct cdev *ioctl_dev;
1256#endif
1257 int pci_unit;
1258
1259 struct resource *sys_res_arcmsr[2];
1147 struct resource *irqres;
1148 void *ih; /* interrupt handle */
1260 struct resource *irqres[ARCMSR_NUM_MSIX_VECTORS];
1261 void *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */
1262 int irq_id[ARCMSR_NUM_MSIX_VECTORS];
1149
1150 /* Hooks into the CAM XPT */
1151 struct cam_sim *psim;
1152 struct cam_path *ppath;
1153 u_int8_t *uncacheptr;
1154 unsigned long vir2phy_offset;
1155 union {
1156 unsigned long phyaddr;

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1201 char device_map[20]; /*21,84-99 */
1202 struct callout devmap_callout;
1203 u_int32_t pktRequestCount;
1204 u_int32_t pktReturnCount;
1205 u_int32_t vendor_device_id;
1206 u_int32_t adapter_bus_speed;
1207 u_int32_t maxOutstanding;
1208 u_int16_t sub_device_id;
1263
1264 /* Hooks into the CAM XPT */
1265 struct cam_sim *psim;
1266 struct cam_path *ppath;
1267 u_int8_t *uncacheptr;
1268 unsigned long vir2phy_offset;
1269 union {
1270 unsigned long phyaddr;

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1315 char device_map[20]; /*21,84-99 */
1316 struct callout devmap_callout;
1317 u_int32_t pktRequestCount;
1318 u_int32_t pktReturnCount;
1319 u_int32_t vendor_device_id;
1320 u_int32_t adapter_bus_speed;
1321 u_int32_t maxOutstanding;
1322 u_int16_t sub_device_id;
1323 u_int32_t doneq_index;
1324 u_int32_t in_doorbell;
1325 u_int32_t out_doorbell;
1326 u_int32_t completionQ_entry;
1327 pCompletion_Q pCompletionQ;
1328 int msix_vectors;
1329 int rid;
1209};/* HW_DEVICE_EXTENSION */
1210/* acb_flags */
1211#define ACB_F_SCSISTOPADAPTER 0x0001
1212#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
1213#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
1214#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
1215#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
1216#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
1217#define ACB_F_MESSAGE_WQBUFFER_READ 0x0040
1218#define ACB_F_BUS_RESET 0x0080
1219#define ACB_F_IOP_INITED 0x0100 /* iop init */
1220#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */
1221#define ACB_F_CAM_DEV_QFRZN 0x0400
1222#define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */
1223#define ACB_F_SRB_FUNCTION_POWER 0x1000
1330};/* HW_DEVICE_EXTENSION */
1331/* acb_flags */
1332#define ACB_F_SCSISTOPADAPTER 0x0001
1333#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
1334#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
1335#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
1336#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
1337#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
1338#define ACB_F_MESSAGE_WQBUFFER_READ 0x0040
1339#define ACB_F_BUS_RESET 0x0080
1340#define ACB_F_IOP_INITED 0x0100 /* iop init */
1341#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */
1342#define ACB_F_CAM_DEV_QFRZN 0x0400
1343#define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */
1344#define ACB_F_SRB_FUNCTION_POWER 0x1000
1345#define ACB_F_MSIX_ENABLED 0x2000
1224/* devstate */
1225#define ARECA_RAID_GONE 0x55
1226#define ARECA_RAID_GOOD 0xaa
1227/* adapter_bus_speed */
1228#define ACB_BUS_SPEED_3G 0
1229#define ACB_BUS_SPEED_6G 1
1230#define ACB_BUS_SPEED_12G 2
1231/*

--- 4526 unchanged lines hidden --- 		1346/* devstate */
1347#define ARECA_RAID_GONE 0x55
1348#define ARECA_RAID_GOOD 0xaa
1349/* adapter_bus_speed */
1350#define ACB_BUS_SPEED_3G 0
1351#define ACB_BUS_SPEED_6G 1
1352#define ACB_BUS_SPEED_12G 2
1353/*

--- 4526 unchanged lines hidden ---