| arcmsr.h (22f2616bd70e913122e47edfe64ccb3fd2b62296) | arcmsr.h (dac366886ec6752cd98b433dee5e62b8ab7eb49d) |
|---|---|
| 1/* 2*********************************************************************************************** 3** O.S : FreeBSD 4** FILE NAME : arcmsr.h 5** BY : Erich Chen, Ching Huang 6** Description: SCSI RAID Device Driver for 7** ARECA SATA/SAS RAID HOST Adapter 8** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] --- 38 unchanged lines hidden (view full) --- 47#define ARCMSR_MAX_START_JOB 257 48#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 49#define ARCMSR_MAX_FREESRB_NUM 384 50#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 51#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 52#define ARCMSR_MAX_ADAPTER 4 53#define ARCMSR_RELEASE_SIMQ_LEVEL 230 54#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ | 1/* 2*********************************************************************************************** 3** O.S : FreeBSD 4** FILE NAME : arcmsr.h 5** BY : Erich Chen, Ching Huang 6** Description: SCSI RAID Device Driver for 7** ARECA SATA/SAS RAID HOST Adapter 8** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] --- 38 unchanged lines hidden (view full) --- 47#define ARCMSR_MAX_START_JOB 257 48#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 49#define ARCMSR_MAX_FREESRB_NUM 384 50#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 51#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 52#define ARCMSR_MAX_ADAPTER 4 53#define ARCMSR_RELEASE_SIMQ_LEVEL 230 54#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ |
| 55#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ |
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| 55/* 56********************************************************************* 57*/ 58#ifndef TRUE 59 #define TRUE 1 60#endif 61#ifndef FALSE 62 #define FALSE 0 --- 29 unchanged lines hidden (view full) --- 92#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 93#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 94#define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 95#define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 96#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 97#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 98#define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 99 | 56/* 57********************************************************************* 58*/ 59#ifndef TRUE 60 #define TRUE 1 61#endif 62#ifndef FALSE 63 #define FALSE 0 --- 29 unchanged lines hidden (view full) --- 93#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 94#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 95#define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 96#define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 97#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 98#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 99#define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 100 |
| 101#define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 102#define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 103#define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 104#define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 105#define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 106#define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 107 |
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| 100#define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 101#define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 102#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 103#define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 104#define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 105#define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 106#define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 107#define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 108#define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ | 108#define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 109#define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 110#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 111#define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 112#define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 113#define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 114#define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 115#define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 116#define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ |
| 117#define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ |
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| 109#define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 110#define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ | 118#define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 119#define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ |
| 120#define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ |
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| 111#define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 112#define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 113#define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 114#define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 115#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 116#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 117#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 118#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 119#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 120#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 121#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ | 121#define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 122#define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 123#define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 124#define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 125#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 126#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 127#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 128#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 129#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 130#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 131#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ |
| 132#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ |
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| 122 123#ifndef PCIR_BARS 124 #define PCIR_BARS 0x10 125 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 126#endif 127 128#define PCI_BASE_ADDR0 0x10 129#define PCI_BASE_ADDR1 0x14 --- 695 unchanged lines hidden (view full) --- 825 char firm_model[12]; /*15,60-67*/ 826 char firm_version[20]; /*17,68-83*/ 827 char device_map[20]; /*21,84-99 */ 828 struct callout devmap_callout; 829#ifdef ARCMSR_DEBUG1 830 u_int32_t pktRequestCount; 831 u_int32_t pktReturnCount; 832#endif | 133 134#ifndef PCIR_BARS 135 #define PCIR_BARS 0x10 136 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 137#endif 138 139#define PCI_BASE_ADDR0 0x10 140#define PCI_BASE_ADDR1 0x14 --- 695 unchanged lines hidden (view full) --- 836 char firm_model[12]; /*15,60-67*/ 837 char firm_version[20]; /*17,68-83*/ 838 char device_map[20]; /*21,84-99 */ 839 struct callout devmap_callout; 840#ifdef ARCMSR_DEBUG1 841 u_int32_t pktRequestCount; 842 u_int32_t pktReturnCount; 843#endif |
| 844 u_int32_t vendor_device_id; 845 u_int32_t adapter_bus_speed; |
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| 833};/* HW_DEVICE_EXTENSION */ 834/* acb_flags */ 835#define ACB_F_SCSISTOPADAPTER 0x0001 836#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 837#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 838#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 839#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 840#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 841#define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 842#define ACB_F_BUS_RESET 0x0080 843#define ACB_F_IOP_INITED 0x0100 /* iop init */ 844#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 845#define ACB_F_CAM_DEV_QFRZN 0x0400 846#define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 847#define ACB_F_SRB_FUNCTION_POWER 0x1000 848/* devstate */ 849#define ARECA_RAID_GONE 0x55 850#define ARECA_RAID_GOOD 0xaa | 846};/* HW_DEVICE_EXTENSION */ 847/* acb_flags */ 848#define ACB_F_SCSISTOPADAPTER 0x0001 849#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 850#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 851#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 852#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 853#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 854#define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 855#define ACB_F_BUS_RESET 0x0080 856#define ACB_F_IOP_INITED 0x0100 /* iop init */ 857#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 858#define ACB_F_CAM_DEV_QFRZN 0x0400 859#define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 860#define ACB_F_SRB_FUNCTION_POWER 0x1000 861/* devstate */ 862#define ARECA_RAID_GONE 0x55 863#define ARECA_RAID_GOOD 0xaa |
| 864/* adapter_bus_speed */ 865#define ACB_BUS_SPEED_3G 0 866#define ACB_BUS_SPEED_6G 1 867#define ACB_BUS_SPEED_12G 2 |
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| 851/* 852********************************************************************* 853** Message Unit structure 854********************************************************************* 855*/ 856struct HBA_MessageUnit 857{ 858 u_int32_t resrved0[4]; /*0000 000F*/ --- 4680 unchanged lines hidden --- | 868/* 869********************************************************************* 870** Message Unit structure 871********************************************************************* 872*/ 873struct HBA_MessageUnit 874{ 875 u_int32_t resrved0[4]; /*0000 000F*/ --- 4680 unchanged lines hidden --- |