arcmsr.h (1618c554b091b6c1745671c0a7836e398c0ccc4d) arcmsr.h (fa42a0bfa40342531df64873dcef74593702f4b3)
1/*
2********************************************************************************
3** OS : FreeBSD
4** FILE NAME : arcmsr.h
5** BY : Erich Chen, Ching Huang
6** Description: SCSI RAID Device Driver for
7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8** SATA/SAS RAID HOST Adapter

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145#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
146#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
147#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
148#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
149#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
150#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
151#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
152#define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */
1/*
2********************************************************************************
3** OS : FreeBSD
4** FILE NAME : arcmsr.h
5** BY : Erich Chen, Ching Huang
6** Description: SCSI RAID Device Driver for
7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8** SATA/SAS RAID HOST Adapter

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145#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
146#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
147#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
148#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
149#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
150#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
151#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
152#define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */
153#define PCIDevVenIDARC1886_ 0x188917D3 /* Vendor Device ID */
154#define PCIDevVenIDARC1886 0x188A17D3 /* Vendor Device ID */
153
154#ifndef PCIR_BARS
155 #define PCIR_BARS 0x10
156 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
157#endif
158
159#define PCI_BASE_ADDR0 0x10
160#define PCI_BASE_ADDR1 0x14

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453#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000
454
455/*outbound list */
456#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001
457#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
458
459/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
460#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
155
156#ifndef PCIR_BARS
157 #define PCIR_BARS 0x10
158 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
159#endif
160
161#define PCI_BASE_ADDR0 0x10
162#define PCI_BASE_ADDR1 0x14

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455#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000
456
457/*outbound list */
458#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001
459#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
460
461/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
462#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
461/*
463/*
462*******************************************************************************
463** SPEC. for Areca HBE adapter
464*******************************************************************************
465*/
466#define ARCMSR_SIGNATURE_1884 0x188417D3
467#define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
468#define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
469#define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */

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474#define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
475#define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
476#define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */
477#define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */
478/* ARC-1884 doorbell sync */
479#define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
480#define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
481/*
464*******************************************************************************
465** SPEC. for Areca HBE adapter
466*******************************************************************************
467*/
468#define ARCMSR_SIGNATURE_1884 0x188417D3
469#define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
470#define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
471#define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */

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476#define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
477#define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
478#define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */
479#define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */
480/* ARC-1884 doorbell sync */
481#define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
482#define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
483/*
484*******************************************************************************
485** SPEC. for Areca HBF adapter
486*******************************************************************************
487*/
488#define ARCMSR_SIGNATURE_1886 0x188617D3
489// Doorbell and interrupt definition are same as Type E adapter
490/* ARC-1886 doorbell sync */
491#define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
492//set host rw buffer physical address at inbound message 0, 1 (low,high)
493#define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
494#define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
495#define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
496
497/*
482*********************************************************************
498*********************************************************************
483** Message Unit structure
499** Messaging Unit (MU) of Type A processor
484*********************************************************************
485*/
486struct HBA_MessageUnit
487{
488 u_int32_t resrved0[4]; /*0000 000F*/
489 u_int32_t inbound_msgaddr0; /*0010 0013*/
490 u_int32_t inbound_msgaddr1; /*0014 0017*/
491 u_int32_t outbound_msgaddr0; /*0018 001B*/

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539 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */
540 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */
541 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
542 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/
543 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
544};
545/*
546*********************************************************************
500*********************************************************************
501*/
502struct HBA_MessageUnit
503{
504 u_int32_t resrved0[4]; /*0000 000F*/
505 u_int32_t inbound_msgaddr0; /*0010 0013*/
506 u_int32_t inbound_msgaddr1; /*0014 0017*/
507 u_int32_t outbound_msgaddr0; /*0018 001B*/

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555 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */
556 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */
557 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
558 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/
559 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
560};
561/*
562*********************************************************************
547**
563** Messaging Unit (MU) of Type B processor(MARVEL)
548*********************************************************************
549*/
550struct HBB_MessageUnit
551{
552 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */
553 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */
554 int32_t postq_index; /* post queue index */
555 int32_t doneq_index; /* done queue index */
556 struct HBB_DOORBELL *hbb_doorbell;
557 struct HBB_RWBUFFER *hbb_rwbuffer;
558 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */
559 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */
560 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */
561 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */
562};
563
564/*
565*********************************************************************
564*********************************************************************
565*/
566struct HBB_MessageUnit
567{
568 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */
569 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */
570 int32_t postq_index; /* post queue index */
571 int32_t doneq_index; /* done queue index */
572 struct HBB_DOORBELL *hbb_doorbell;
573 struct HBB_RWBUFFER *hbb_rwbuffer;
574 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */
575 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */
576 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */
577 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */
578};
579
580/*
581*********************************************************************
566**
582** Messaging Unit (MU) of Type C processor(LSI)
567*********************************************************************
568*/
569struct HBC_MessageUnit {
570 u_int32_t message_unit_status; /*0000 0003*/
571 u_int32_t slave_error_attribute; /*0004 0007*/
572 u_int32_t slave_error_address; /*0008 000B*/
573 u_int32_t posted_outbound_doorbell; /*000C 000F*/
574 u_int32_t master_error_attribute; /*0010 0013*/

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633 u_int32_t message_wbuffer[32]; /*2000 207F*/
634 u_int32_t reserved3[32]; /*2080 20FF*/
635 u_int32_t message_rbuffer[32]; /*2100 217F*/
636 u_int32_t reserved4[32]; /*2180 21FF*/
637 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
638};
639/*
640*********************************************************************
583*********************************************************************
584*/
585struct HBC_MessageUnit {
586 u_int32_t message_unit_status; /*0000 0003*/
587 u_int32_t slave_error_attribute; /*0004 0007*/
588 u_int32_t slave_error_address; /*0008 000B*/
589 u_int32_t posted_outbound_doorbell; /*000C 000F*/
590 u_int32_t master_error_attribute; /*0010 0013*/

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649 u_int32_t message_wbuffer[32]; /*2000 207F*/
650 u_int32_t reserved3[32]; /*2080 20FF*/
651 u_int32_t message_rbuffer[32]; /*2100 217F*/
652 u_int32_t reserved4[32]; /*2180 21FF*/
653 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
654};
655/*
656*********************************************************************
641**
657** Messaging Unit (MU) of Type D processor
642*********************************************************************
643*/
644struct InBound_SRB {
645 uint32_t addressLow; //pointer to SRB block
646 uint32_t addressHigh;
647 uint32_t length; // in DWORDs
648 uint32_t reserved0;
649};

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702 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE];
703 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1];
704 uint16_t postq_index;
705 uint16_t doneq_index;
706 struct HBD_MessageUnit *phbdmu;
707};
708/*
709*********************************************************************
658*********************************************************************
659*/
660struct InBound_SRB {
661 uint32_t addressLow; //pointer to SRB block
662 uint32_t addressHigh;
663 uint32_t length; // in DWORDs
664 uint32_t reserved0;
665};

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718 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE];
719 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1];
720 uint16_t postq_index;
721 uint16_t doneq_index;
722 struct HBD_MessageUnit *phbdmu;
723};
724/*
725*********************************************************************
710**
726** Messaging Unit (MU) of Type E processor(LSI)
711*********************************************************************
712*/
713struct HBE_MessageUnit {
714 u_int32_t iobound_doorbell; /*0000 0003*/
715 u_int32_t write_sequence_3xxx; /*0004 0007*/
716 u_int32_t host_diagnostic_3xxx; /*0008 000B*/
717 u_int32_t posted_outbound_doorbell; /*000C 000F*/
718 u_int32_t master_error_attribute; /*0010 0013*/

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778 u_int32_t reserved2[1936]; /*01C0 1FFF*/
779 u_int32_t message_wbuffer[32]; /*2000 207F*/
780 u_int32_t reserved3[32]; /*2080 20FF*/
781 u_int32_t message_rbuffer[32]; /*2100 217F*/
782 u_int32_t reserved4[32]; /*2180 21FF*/
783 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
784};
785
727*********************************************************************
728*/
729struct HBE_MessageUnit {
730 u_int32_t iobound_doorbell; /*0000 0003*/
731 u_int32_t write_sequence_3xxx; /*0004 0007*/
732 u_int32_t host_diagnostic_3xxx; /*0008 000B*/
733 u_int32_t posted_outbound_doorbell; /*000C 000F*/
734 u_int32_t master_error_attribute; /*0010 0013*/

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794 u_int32_t reserved2[1936]; /*01C0 1FFF*/
795 u_int32_t message_wbuffer[32]; /*2000 207F*/
796 u_int32_t reserved3[32]; /*2080 20FF*/
797 u_int32_t message_rbuffer[32]; /*2100 217F*/
798 u_int32_t reserved4[32]; /*2180 21FF*/
799 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
800};
801
802/*
803*********************************************************************
804** Messaging Unit (MU) of Type F processor(LSI)
805*********************************************************************
806*/
807struct HBF_MessageUnit {
808 u_int32_t iobound_doorbell; /*0000 0003*/
809 u_int32_t write_sequence_3xxx; /*0004 0007*/
810 u_int32_t host_diagnostic_3xxx; /*0008 000B*/
811 u_int32_t posted_outbound_doorbell; /*000C 000F*/
812 u_int32_t master_error_attribute; /*0010 0013*/
813 u_int32_t master_error_address_low; /*0014 0017*/
814 u_int32_t master_error_address_high; /*0018 001B*/
815 u_int32_t hcb_size; /*001C 001F*/
816 u_int32_t inbound_doorbell; /*0020 0023*/
817 u_int32_t diagnostic_rw_data; /*0024 0027*/
818 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
819 u_int32_t diagnostic_rw_address_high; /*002C 002F*/
820 u_int32_t host_int_status; /*0030 0033 host interrupt status*/
821 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
822 u_int32_t dcr_data; /*0038 003B*/
823 u_int32_t dcr_address; /*003C 003F*/
824 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
825 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
826 u_int32_t hcb_pci_address_low; /*0048 004B*/
827 u_int32_t hcb_pci_address_high; /*004C 004F*/
828 u_int32_t iop_int_status; /*0050 0053*/
829 u_int32_t iop_int_mask; /*0054 0057*/
830 u_int32_t iop_inbound_queue_port; /*0058 005B*/
831 u_int32_t iop_outbound_queue_port; /*005C 005F*/
832 u_int32_t inbound_free_list_index; /*0060 0063*/
833 u_int32_t inbound_post_list_index; /*0064 0067*/
834 u_int32_t reply_post_producer_index; /*0068 006B*/
835 u_int32_t reply_post_consumer_index; /*006C 006F*/
836 u_int32_t inbound_doorbell_clear; /*0070 0073*/
837 u_int32_t i2o_message_unit_control; /*0074 0077*/
838 u_int32_t last_used_message_source_address_low; /*0078 007B*/
839 u_int32_t last_used_message_source_address_high; /*007C 007F*/
840 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/
841 u_int32_t message_dest_address_index; /*0090 0093*/
842 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
843 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
844 u_int32_t outbound_doorbell; /*009C 009F*/
845 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
846 u_int32_t message_source_address_index; /*00A4 00A7*/
847 u_int32_t message_done_queue_index; /*00A8 00AB*/
848 u_int32_t reserved0; /*00AC 00AF*/
849 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
850 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
851 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
852 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
853 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
854 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
855 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
856 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
857 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
858 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
859 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
860 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
861 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/
862 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/
863 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/
864 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/
865 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/
866 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/
867 u_int32_t host_diagnostic; /*00F8 00FB*/
868 u_int32_t write_sequence; /*00FC 00FF*/
869 u_int32_t reserved1[46]; /*0100 01B7*/
870 u_int32_t reply_post_producer_index1; /*01B8 01BB*/
871 u_int32_t reply_post_consumer_index1; /*01BC 01BF*/
872};
873
874#define MESG_RW_BUFFER_SIZE (256 * 3)
875
786typedef struct deliver_completeQ {
787 u_int16_t cmdFlag;
788 u_int16_t cmdSMID;
789 u_int16_t cmdLMID; // reserved (0)
790 u_int16_t cmdFlag2; // reserved (0)
791} DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
792
793#define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128)

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800struct MessageUnit_UNION
801{
802 union {
803 struct HBA_MessageUnit hbamu;
804 struct HBB_MessageUnit hbbmu;
805 struct HBC_MessageUnit hbcmu;
806 struct HBD_MessageUnit0 hbdmu;
807 struct HBE_MessageUnit hbemu;
876typedef struct deliver_completeQ {
877 u_int16_t cmdFlag;
878 u_int16_t cmdSMID;
879 u_int16_t cmdLMID; // reserved (0)
880 u_int16_t cmdFlag2; // reserved (0)
881} DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
882
883#define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128)

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890struct MessageUnit_UNION
891{
892 union {
893 struct HBA_MessageUnit hbamu;
894 struct HBB_MessageUnit hbbmu;
895 struct HBC_MessageUnit hbcmu;
896 struct HBD_MessageUnit0 hbdmu;
897 struct HBE_MessageUnit hbemu;
898 struct HBF_MessageUnit hbfmu;
808 } muu;
809};
810/*
811*************************************************************
812** structure for holding DMA address data
813*************************************************************
814*/
815#define IS_SG64_ADDR 0x01000000 /* bit24 */

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1227** Adapter Control Block
1228*********************************************************************
1229*/
1230#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
1231#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
1232#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
1233#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
1234#define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */
899 } muu;
900};
901/*
902*************************************************************
903** structure for holding DMA address data
904*************************************************************
905*/
906#define IS_SG64_ADDR 0x01000000 /* bit24 */

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1318** Adapter Control Block
1319*********************************************************************
1320*/
1321#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
1322#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
1323#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
1324#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
1325#define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */
1326#define ACB_ADAPTER_TYPE_F 0x00000005 /* hbd L IOP */
1235
1236struct AdapterControlBlock {
1237 u_int32_t adapter_type; /* adapter A,B..... */
1238
1239 bus_space_tag_t btag[2];
1240 bus_space_handle_t bhandle[2];
1241 bus_dma_tag_t parent_dmat;
1242 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */

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1263 u_int32_t phyadd_high;
1264 }B;
1265 }srb_phyaddr;
1266// unsigned long srb_phyaddr;
1267 /* Offset is used in making arc cdb physical to virtual calculations */
1268 u_int32_t outbound_int_enable;
1269
1270 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
1327
1328struct AdapterControlBlock {
1329 u_int32_t adapter_type; /* adapter A,B..... */
1330
1331 bus_space_tag_t btag[2];
1332 bus_space_handle_t bhandle[2];
1333 bus_dma_tag_t parent_dmat;
1334 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */

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1355 u_int32_t phyadd_high;
1356 }B;
1357 }srb_phyaddr;
1358// unsigned long srb_phyaddr;
1359 /* Offset is used in making arc cdb physical to virtual calculations */
1360 u_int32_t outbound_int_enable;
1361
1362 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
1363 uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC)
1364 uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host)
1365 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
1271
1272 u_int8_t adapter_index;
1273 u_int8_t irq;
1274 u_int16_t acb_flags;
1275
1276 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */
1277 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */
1278 int32_t workingsrb_doneindex; /* done srb array index */

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1312 u_int16_t sub_device_id;
1313 u_int32_t doneq_index;
1314 u_int32_t in_doorbell;
1315 u_int32_t out_doorbell;
1316 u_int32_t completionQ_entry;
1317 pCompletion_Q pCompletionQ;
1318 int msix_vectors;
1319 int rid[2];
1366
1367 u_int8_t adapter_index;
1368 u_int8_t irq;
1369 u_int16_t acb_flags;
1370
1371 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */
1372 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */
1373 int32_t workingsrb_doneindex; /* done srb array index */

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1407 u_int16_t sub_device_id;
1408 u_int32_t doneq_index;
1409 u_int32_t in_doorbell;
1410 u_int32_t out_doorbell;
1411 u_int32_t completionQ_entry;
1412 pCompletion_Q pCompletionQ;
1413 int msix_vectors;
1414 int rid[2];
1415 unsigned long completeQ_phys;
1320};/* HW_DEVICE_EXTENSION */
1321/* acb_flags */
1322#define ACB_F_SCSISTOPADAPTER 0x0001
1323#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
1324#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
1325#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
1326#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
1327#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */

--- 4531 unchanged lines hidden --- 		1416};/* HW_DEVICE_EXTENSION */
1417/* acb_flags */
1418#define ACB_F_SCSISTOPADAPTER 0x0001
1419#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
1420#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
1421#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
1422#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
1423#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */

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