arcmsr.c (f9b2a21c9eb4d2715be82dc9049eae29fdb40d17) arcmsr.c (224a78aeed00a7ab617e3cbce92f030044a8b7cb)
1/*
2********************************************************************************
3** OS : FreeBSD
4** FILE NAME : arcmsr.c
5** BY : Erich Chen, Ching Huang
6** Description: SCSI RAID Device Driver for
7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8** SATA/SAS RAID HOST Adapter

--- 61 unchanged lines hidden (view full) ---

70** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start
71** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed
72** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command
73** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition
74** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
75** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
76** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
77** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
1/*
2********************************************************************************
3** OS : FreeBSD
4** FILE NAME : arcmsr.c
5** BY : Erich Chen, Ching Huang
6** Description: SCSI RAID Device Driver for
7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8** SATA/SAS RAID HOST Adapter

--- 61 unchanged lines hidden (view full) ---

70** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start
71** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed
72** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command
73** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition
74** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
75** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
76** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
77** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
78** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883
78******************************************************************************************
79*/
80
81#include <sys/cdefs.h>
82__FBSDID("$FreeBSD$");
83
84#if 0
85#define ARCMSR_DEBUG1 1

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141#endif
142
143#if __FreeBSD_version > 500000
144#define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
145#else
146#define arcmsr_callout_init(a) callout_init(a);
147#endif
148
79******************************************************************************************
80*/
81
82#include <sys/cdefs.h>
83__FBSDID("$FreeBSD$");
84
85#if 0
86#define ARCMSR_DEBUG1 1

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142#endif
143
144#if __FreeBSD_version > 500000
145#define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
146#else
147#define arcmsr_callout_init(a) callout_init(a);
148#endif
149
149#define ARCMSR_DRIVER_VERSION "arcmsr version 1.20.00.28 2013-09-13"
150#define ARCMSR_DRIVER_VERSION "arcmsr version 1.20.00.29 2013-12-18"
150#include <dev/arcmsr/arcmsr.h>
151/*
152**************************************************************************
153**************************************************************************
154*/
155static void arcmsr_free_srb(struct CommandControlBlock *srb);
156static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
157static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);

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1433*/
1434static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1435 struct QBUFFER *prbuffer) {
1436
1437 u_int8_t *pQbuffer;
1438 u_int8_t *iop_data;
1439 u_int32_t iop_len;
1440
151#include <dev/arcmsr/arcmsr.h>
152/*
153**************************************************************************
154**************************************************************************
155*/
156static void arcmsr_free_srb(struct CommandControlBlock *srb);
157static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
158static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);

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1434*/
1435static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1436 struct QBUFFER *prbuffer) {
1437
1438 u_int8_t *pQbuffer;
1439 u_int8_t *iop_data;
1440 u_int32_t iop_len;
1441
1441 if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
1442 if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1442 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1443 }
1444 iop_data = (u_int8_t *)prbuffer->data;
1445 iop_len = (u_int32_t)prbuffer->data_len;
1446 while (iop_len > 0) {
1447 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1448 *pQbuffer = *iop_data;
1449 acb->rqbuf_lastindex++;

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1528*/
1529static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1530{
1531 u_int8_t *pQbuffer;
1532 struct QBUFFER *pwbuffer;
1533 u_int8_t *iop_data;
1534 int32_t allxfer_len=0;
1535
1443 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1444 }
1445 iop_data = (u_int8_t *)prbuffer->data;
1446 iop_len = (u_int32_t)prbuffer->data_len;
1447 while (iop_len > 0) {
1448 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1449 *pQbuffer = *iop_data;
1450 acb->rqbuf_lastindex++;

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1529*/
1530static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1531{
1532 u_int8_t *pQbuffer;
1533 struct QBUFFER *pwbuffer;
1534 u_int8_t *iop_data;
1535 int32_t allxfer_len=0;
1536
1536 if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
1537 if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1537 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1538 return;
1539 }
1540 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1541 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1542 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1543 iop_data = (u_int8_t *)pwbuffer->data;
1544 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)

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1780 arcmsr_dr_handle( acb );
1781}
1782/*
1783**************************************************************************
1784**************************************************************************
1785*/
1786static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1787{
1538 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1539 return;
1540 }
1541 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1542 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1543 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1544 iop_data = (u_int8_t *)pwbuffer->data;
1545 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)

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1781 arcmsr_dr_handle( acb );
1782}
1783/*
1784**************************************************************************
1785**************************************************************************
1786*/
1787static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1788{
1788 u_int32_t outbound_doorbell;
1789 u_int32_t doorbell_status;
1789
1790 /*
1791 *******************************************************************
1792 ** Maybe here we need to check wrqbuffer_lock is lock or not
1793 ** DOORBELL: din! don!
1794 ** check if there are any mail need to pack from firmware
1795 *******************************************************************
1796 */
1790
1791 /*
1792 *******************************************************************
1793 ** Maybe here we need to check wrqbuffer_lock is lock or not
1794 ** DOORBELL: din! don!
1795 ** check if there are any mail need to pack from firmware
1796 *******************************************************************
1797 */
1797 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit,
1798 0, outbound_doorbell);
1799 CHIP_REG_WRITE32(HBA_MessageUnit,
1800 0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */
1801 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1798 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1799 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1800 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1802 arcmsr_iop2drv_data_wrote_handle(acb);
1803 }
1801 arcmsr_iop2drv_data_wrote_handle(acb);
1802 }
1804 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1803 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1805 arcmsr_iop2drv_data_read_handle(acb);
1806 }
1807}
1808/*
1809**************************************************************************
1810**************************************************************************
1811*/
1812static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1813{
1804 arcmsr_iop2drv_data_read_handle(acb);
1805 }
1806}
1807/*
1808**************************************************************************
1809**************************************************************************
1810*/
1811static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1812{
1814 u_int32_t outbound_doorbell;
1813 u_int32_t doorbell_status;
1815
1816 /*
1817 *******************************************************************
1818 ** Maybe here we need to check wrqbuffer_lock is lock or not
1819 ** DOORBELL: din! don!
1820 ** check if there are any mail need to pack from firmware
1821 *******************************************************************
1822 */
1814
1815 /*
1816 *******************************************************************
1817 ** Maybe here we need to check wrqbuffer_lock is lock or not
1818 ** DOORBELL: din! don!
1819 ** check if there are any mail need to pack from firmware
1820 *******************************************************************
1821 */
1823 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1824 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */
1825 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1822 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1823 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1824 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1826 arcmsr_iop2drv_data_wrote_handle(acb);
1827 }
1825 arcmsr_iop2drv_data_wrote_handle(acb);
1826 }
1828 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1827 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1829 arcmsr_iop2drv_data_read_handle(acb);
1830 }
1828 arcmsr_iop2drv_data_read_handle(acb);
1829 }
1831 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1830 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1832 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */
1833 }
1834}
1835/*
1836**************************************************************************
1837**************************************************************************
1838*/
1839static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1840{
1831 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */
1832 }
1833}
1834/*
1835**************************************************************************
1836**************************************************************************
1837*/
1838static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1839{
1841 u_int32_t outbound_Doorbell;
1840 u_int32_t doorbell_status;
1842
1843 /*
1844 *******************************************************************
1845 ** Maybe here we need to check wrqbuffer_lock is lock or not
1846 ** DOORBELL: din! don!
1847 ** check if there are any mail need to pack from firmware
1848 *******************************************************************
1849 */
1841
1842 /*
1843 *******************************************************************
1844 ** Maybe here we need to check wrqbuffer_lock is lock or not
1845 ** DOORBELL: din! don!
1846 ** check if there are any mail need to pack from firmware
1847 *******************************************************************
1848 */
1850 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1851 if(outbound_Doorbell)
1852 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
1853 while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1854 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1849 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1850 if(doorbell_status)
1851 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1852 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1853 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1855 arcmsr_iop2drv_data_wrote_handle(acb);
1856 }
1854 arcmsr_iop2drv_data_wrote_handle(acb);
1855 }
1857 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1856 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1858 arcmsr_iop2drv_data_read_handle(acb);
1859 }
1857 arcmsr_iop2drv_data_read_handle(acb);
1858 }
1860 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1859 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1861 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */
1862 }
1860 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */
1861 }
1863 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1864 if(outbound_Doorbell)
1865 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
1862 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1863 if(doorbell_status)
1864 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1866 }
1867}
1868/*
1869**************************************************************************
1870**************************************************************************
1871*/
1872static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1873{

--- 53 unchanged lines hidden (view full) ---

1927 u_int16_t error;
1928
1929 /*
1930 *****************************************************************************
1931 ** areca cdb command done
1932 *****************************************************************************
1933 */
1934 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1865 }
1866}
1867/*
1868**************************************************************************
1869**************************************************************************
1870*/
1871static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1872{

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1926 u_int16_t error;
1927
1928 /*
1929 *****************************************************************************
1930 ** areca cdb command done
1931 *****************************************************************************
1932 */
1933 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1935
1936 while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1937
1934 do {
1938 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1939 /* check if command done with no error*/
1940 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1941 arcmsr_drain_donequeue(acb, flag_srb, error);
1942 throttling++;
1943 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1944 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1945 throttling = 0;
1946 }
1935 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1936 /* check if command done with no error*/
1937 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1938 arcmsr_drain_donequeue(acb, flag_srb, error);
1939 throttling++;
1940 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1941 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1942 throttling = 0;
1943 }
1947 } /*drain reply FIFO*/
1944 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
1948}
1949/*
1950**********************************************************************
1951**
1952**********************************************************************
1953*/
1954static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
1955{

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2077static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2078{
2079 u_int32_t host_interrupt_status;
2080 /*
2081 *********************************************
2082 ** check outbound intstatus
2083 *********************************************
2084 */
1945}
1946/*
1947**********************************************************************
1948**
1949**********************************************************************
1950*/
1951static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
1952{

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2074static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2075{
2076 u_int32_t host_interrupt_status;
2077 /*
2078 *********************************************
2079 ** check outbound intstatus
2080 *********************************************
2081 */
2085 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2082 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2083 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2084 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2086 if(!host_interrupt_status) {
2087 /*it must be share irq*/
2088 return;
2089 }
2085 if(!host_interrupt_status) {
2086 /*it must be share irq*/
2087 return;
2088 }
2089 do {
2090 /* MU doorbell interrupts*/
2091 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2092 arcmsr_hbc_doorbell_isr(acb);
2093 }
2094 /* MU post queue interrupts*/
2095 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2096 arcmsr_hbc_postqueue_isr(acb);
2097 }
2090 /* MU doorbell interrupts*/
2091 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2092 arcmsr_hbc_doorbell_isr(acb);
2093 }
2094 /* MU post queue interrupts*/
2095 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2096 arcmsr_hbc_postqueue_isr(acb);
2097 }
2098 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2099 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2098}
2099/*
2100**********************************************************************
2101**********************************************************************
2102*/
2103static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2104{
2105 u_int32_t host_interrupt_status;

--- 771 unchanged lines hidden (view full) ---

2877 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */
2878 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2879 cpi->bus_id = cam_sim_bus(psim);
2880 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2881 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2882 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2883 cpi->unit_number = cam_sim_unit(psim);
2884 #ifdef CAM_NEW_TRAN_CODE
2100}
2101/*
2102**********************************************************************
2103**********************************************************************
2104*/
2105static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2106{
2107 u_int32_t host_interrupt_status;

--- 771 unchanged lines hidden (view full) ---

2879 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */
2880 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2881 cpi->bus_id = cam_sim_bus(psim);
2882 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2883 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2884 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2885 cpi->unit_number = cam_sim_unit(psim);
2886 #ifdef CAM_NEW_TRAN_CODE
2885 if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
2887 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
2888 cpi->base_transfer_speed = 1200000;
2889 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
2886 cpi->base_transfer_speed = 600000;
2887 else
2888 cpi->base_transfer_speed = 300000;
2889 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2890 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2891 (acb->vendor_device_id == PCIDevVenIDARC1214))
2892 {
2893 cpi->transport = XPORT_SAS;

--- 81 unchanged lines hidden (view full) ---

2975 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2976 (acb->vendor_device_id == PCIDevVenIDARC1214))
2977 {
2978 cts->protocol_version = SCSI_REV_SPC2;
2979 cts->transport_version = 0;
2980 cts->transport = XPORT_SAS;
2981 sas = &cts->xport_specific.sas;
2982 sas->valid = CTS_SAS_VALID_SPEED;
2890 cpi->base_transfer_speed = 600000;
2891 else
2892 cpi->base_transfer_speed = 300000;
2893 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2894 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2895 (acb->vendor_device_id == PCIDevVenIDARC1214))
2896 {
2897 cpi->transport = XPORT_SAS;

--- 81 unchanged lines hidden (view full) ---

2979 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2980 (acb->vendor_device_id == PCIDevVenIDARC1214))
2981 {
2982 cts->protocol_version = SCSI_REV_SPC2;
2983 cts->transport_version = 0;
2984 cts->transport = XPORT_SAS;
2985 sas = &cts->xport_specific.sas;
2986 sas->valid = CTS_SAS_VALID_SPEED;
2983 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2987 if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883)
2988 sas->bitrate = 1200000;
2989 else if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2984 (acb->vendor_device_id == PCIDevVenIDARC1214))
2985 sas->bitrate = 600000;
2986 else if(acb->vendor_device_id == PCIDevVenIDARC1680)
2987 sas->bitrate = 300000;
2988 }
2989 else
2990 {
2991 cts->protocol_version = SCSI_REV_2;

--- 951 unchanged lines hidden (view full) ---

3943{
3944 struct AdapterControlBlock *acb = device_get_softc(dev);
3945 u_int16_t pci_command;
3946 int i, j,max_coherent_size;
3947 u_int32_t vendor_dev_id;
3948
3949 vendor_dev_id = pci_get_devid(dev);
3950 acb->vendor_device_id = vendor_dev_id;
2990 (acb->vendor_device_id == PCIDevVenIDARC1214))
2991 sas->bitrate = 600000;
2992 else if(acb->vendor_device_id == PCIDevVenIDARC1680)
2993 sas->bitrate = 300000;
2994 }
2995 else
2996 {
2997 cts->protocol_version = SCSI_REV_2;

--- 951 unchanged lines hidden (view full) ---

3949{
3950 struct AdapterControlBlock *acb = device_get_softc(dev);
3951 u_int16_t pci_command;
3952 int i, j,max_coherent_size;
3953 u_int32_t vendor_dev_id;
3954
3955 vendor_dev_id = pci_get_devid(dev);
3956 acb->vendor_device_id = vendor_dev_id;
3957 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3951 switch (vendor_dev_id) {
3952 case PCIDevVenIDARC1880:
3953 case PCIDevVenIDARC1882:
3954 case PCIDevVenIDARC1213:
3955 case PCIDevVenIDARC1223: {
3956 acb->adapter_type = ACB_ADAPTER_TYPE_C;
3958 switch (vendor_dev_id) {
3959 case PCIDevVenIDARC1880:
3960 case PCIDevVenIDARC1882:
3961 case PCIDevVenIDARC1213:
3962 case PCIDevVenIDARC1223: {
3963 acb->adapter_type = ACB_ADAPTER_TYPE_C;
3964 if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883)
3965 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
3966 else
3957 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3958 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3959 }
3960 break;
3961 case PCIDevVenIDARC1214: {
3962 acb->adapter_type = ACB_ADAPTER_TYPE_D;
3963 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3964 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));

--- 316 unchanged lines hidden (view full) ---

4281 }
4282 acb->irqres = irqres;
4283 /*
4284 * Now let the CAM generic SCSI layer find the SCSI devices on
4285 * the bus * start queue to reset to the idle loop. *
4286 * Create device queue of SIM(s) * (MAX_START_JOB - 1) :
4287 * max_sim_transactions
4288 */
3967 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3968 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3969 }
3970 break;
3971 case PCIDevVenIDARC1214: {
3972 acb->adapter_type = ACB_ADAPTER_TYPE_D;
3973 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3974 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));

--- 316 unchanged lines hidden (view full) ---

4291 }
4292 acb->irqres = irqres;
4293 /*
4294 * Now let the CAM generic SCSI layer find the SCSI devices on
4295 * the bus * start queue to reset to the idle loop. *
4296 * Create device queue of SIM(s) * (MAX_START_JOB - 1) :
4297 * max_sim_transactions
4298 */
4289 devq = cam_simq_alloc(ARCMSR_MAX_START_JOB);
4299 devq = cam_simq_alloc(acb->maxOutstanding);
4290 if(devq == NULL) {
4291 arcmsr_free_resource(acb);
4292 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4293 arcmsr_mutex_destroy(acb);
4294 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4295 return ENXIO;
4296 }
4297#if __FreeBSD_version >= 700025

--- 57 unchanged lines hidden (view full) ---

4355
4356/*
4357************************************************************************
4358************************************************************************
4359*/
4360static int arcmsr_probe(device_t dev)
4361{
4362 u_int32_t id;
4300 if(devq == NULL) {
4301 arcmsr_free_resource(acb);
4302 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4303 arcmsr_mutex_destroy(acb);
4304 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4305 return ENXIO;
4306 }
4307#if __FreeBSD_version >= 700025

--- 57 unchanged lines hidden (view full) ---

4365
4366/*
4367************************************************************************
4368************************************************************************
4369*/
4370static int arcmsr_probe(device_t dev)
4371{
4372 u_int32_t id;
4373 u_int16_t sub_device_id;
4363 static char buf[256];
4364 char x_type[]={"unknown"};
4365 char *type;
4366 int raid6 = 1;
4367
4368 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4369 return (ENXIO);
4370 }
4374 static char buf[256];
4375 char x_type[]={"unknown"};
4376 char *type;
4377 int raid6 = 1;
4378
4379 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4380 return (ENXIO);
4381 }
4382 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4371 switch(id = pci_get_devid(dev)) {
4372 case PCIDevVenIDARC1110:
4373 case PCIDevVenIDARC1200:
4374 case PCIDevVenIDARC1201:
4375 case PCIDevVenIDARC1210:
4376 raid6 = 0;
4377 /*FALLTHRU*/
4378 case PCIDevVenIDARC1120:

--- 16 unchanged lines hidden (view full) ---

4395 case PCIDevVenIDARC1680:
4396 case PCIDevVenIDARC1681:
4397 type = "SAS 3G";
4398 break;
4399 case PCIDevVenIDARC1880:
4400 case PCIDevVenIDARC1882:
4401 case PCIDevVenIDARC1213:
4402 case PCIDevVenIDARC1223:
4383 switch(id = pci_get_devid(dev)) {
4384 case PCIDevVenIDARC1110:
4385 case PCIDevVenIDARC1200:
4386 case PCIDevVenIDARC1201:
4387 case PCIDevVenIDARC1210:
4388 raid6 = 0;
4389 /*FALLTHRU*/
4390 case PCIDevVenIDARC1120:

--- 16 unchanged lines hidden (view full) ---

4407 case PCIDevVenIDARC1680:
4408 case PCIDevVenIDARC1681:
4409 type = "SAS 3G";
4410 break;
4411 case PCIDevVenIDARC1880:
4412 case PCIDevVenIDARC1882:
4413 case PCIDevVenIDARC1213:
4414 case PCIDevVenIDARC1223:
4415 if (sub_device_id == ARECA_SUB_DEV_ID_1883)
4416 type = "SAS 12G";
4417 else
4403 type = "SAS 6G";
4404 break;
4405 case PCIDevVenIDARC1214:
4406 type = "SATA 6G";
4407 break;
4408 default:
4409 type = x_type;
4410 raid6 = 0;

--- 90 unchanged lines hidden ---
4418 type = "SAS 6G";
4419 break;
4420 case PCIDevVenIDARC1214:
4421 type = "SATA 6G";
4422 break;
4423 default:
4424 type = x_type;
4425 raid6 = 0;

--- 90 unchanged lines hidden ---