arcmsr.c (1618c554b091b6c1745671c0a7836e398c0ccc4d) arcmsr.c (fa42a0bfa40342531df64873dcef74593702f4b3)
1/*
2********************************************************************************
3** OS : FreeBSD
4** FILE NAME : arcmsr.c
5** BY : Erich Chen, Ching Huang
6** Description: SCSI RAID Device Driver for
7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8** SATA/SAS RAID HOST Adapter

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76** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
77** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
78** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
79** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
80** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883
81** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203
82** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884
83** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource
1/*
2********************************************************************************
3** OS : FreeBSD
4** FILE NAME : arcmsr.c
5** BY : Erich Chen, Ching Huang
6** Description: SCSI RAID Device Driver for
7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8** SATA/SAS RAID HOST Adapter

--- 67 unchanged lines hidden (view full) ---

76** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
77** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
78** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
79** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
80** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883
81** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203
82** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884
83** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource
84** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller
84******************************************************************************************
85*/
86
87#include <sys/cdefs.h>
88__FBSDID("$FreeBSD$");
89
90#if 0
91#define ARCMSR_DEBUG1 1

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133#include <sys/selinfo.h>
134#include <sys/mutex.h>
135#include <sys/endian.h>
136#include <dev/pci/pcivar.h>
137#include <dev/pci/pcireg.h>
138
139#define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
140
85******************************************************************************************
86*/
87
88#include <sys/cdefs.h>
89__FBSDID("$FreeBSD$");
90
91#if 0
92#define ARCMSR_DEBUG1 1

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134#include <sys/selinfo.h>
135#include <sys/mutex.h>
136#include <sys/endian.h>
137#include <dev/pci/pcivar.h>
138#include <dev/pci/pcireg.h>
139
140#define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
141
141#define ARCMSR_DRIVER_VERSION "arcmsr version 1.40.00.01 2017-10-30"
142#define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.00 2020-09-30"
142#include <dev/arcmsr/arcmsr.h>
143/*
144**************************************************************************
145**************************************************************************
146*/
147static void arcmsr_free_srb(struct CommandControlBlock *srb);
148static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
149static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);

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171static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
172static int arcmsr_resume(device_t dev);
173static int arcmsr_suspend(device_t dev);
174static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
175static void arcmsr_polling_devmap(void *arg);
176static void arcmsr_srb_timeout(void *arg);
177static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
178static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
143#include <dev/arcmsr/arcmsr.h>
144/*
145**************************************************************************
146**************************************************************************
147*/
148static void arcmsr_free_srb(struct CommandControlBlock *srb);
149static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
150static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);

--- 21 unchanged lines hidden (view full) ---

172static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
173static int arcmsr_resume(device_t dev);
174static int arcmsr_suspend(device_t dev);
175static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
176static void arcmsr_polling_devmap(void *arg);
177static void arcmsr_srb_timeout(void *arg);
178static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
179static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
180static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb);
179static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
180#ifdef ARCMSR_DEBUG1
181static void arcmsr_dump_data(struct AdapterControlBlock *acb);
182#endif
183/*
184**************************************************************************
185**************************************************************************
186*/

--- 102 unchanged lines hidden (view full) ---

289 /* disable all outbound interrupt */
290 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
291 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
292 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
293 }
294 break;
295 case ACB_ADAPTER_TYPE_C: {
296 /* disable all outbound interrupt */
181static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
182#ifdef ARCMSR_DEBUG1
183static void arcmsr_dump_data(struct AdapterControlBlock *acb);
184#endif
185/*
186**************************************************************************
187**************************************************************************
188*/

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291 /* disable all outbound interrupt */
292 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
293 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
294 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
295 }
296 break;
297 case ACB_ADAPTER_TYPE_C: {
298 /* disable all outbound interrupt */
297 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */
299 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
298 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
299 }
300 break;
301 case ACB_ADAPTER_TYPE_D: {
302 /* disable all outbound interrupt */
300 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
301 }
302 break;
303 case ACB_ADAPTER_TYPE_D: {
304 /* disable all outbound interrupt */
303 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */
305 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */
304 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
305 }
306 break;
306 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
307 }
308 break;
307 case ACB_ADAPTER_TYPE_E: {
309 case ACB_ADAPTER_TYPE_E:
310 case ACB_ADAPTER_TYPE_F: {
308 /* disable all outbound interrupt */
311 /* disable all outbound interrupt */
309 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */
312 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
310 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
311 }
312 break;
313 }
314 return (intmask_org);
315}
316/*
317**********************************************************************

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347 case ACB_ADAPTER_TYPE_D: {
348 /* enable outbound Post Queue, outbound doorbell Interrupt */
349 mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
350 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
351 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
352 acb->outbound_int_enable = mask;
353 }
354 break;
313 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
314 }
315 break;
316 }
317 return (intmask_org);
318}
319/*
320**********************************************************************

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350 case ACB_ADAPTER_TYPE_D: {
351 /* enable outbound Post Queue, outbound doorbell Interrupt */
352 mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
353 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
354 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
355 acb->outbound_int_enable = mask;
356 }
357 break;
355 case ACB_ADAPTER_TYPE_E: {
358 case ACB_ADAPTER_TYPE_E:
359 case ACB_ADAPTER_TYPE_F: {
356 /* enable outbound Post Queue, outbound doorbell Interrupt */
357 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
358 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
359 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
360 }
361 break;
362 }
363}

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572 case ACB_ADAPTER_TYPE_C: {
573 arcmsr_flush_hbc_cache(acb);
574 }
575 break;
576 case ACB_ADAPTER_TYPE_D: {
577 arcmsr_flush_hbd_cache(acb);
578 }
579 break;
360 /* enable outbound Post Queue, outbound doorbell Interrupt */
361 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
362 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
363 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
364 }
365 break;
366 }
367}

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576 case ACB_ADAPTER_TYPE_C: {
577 arcmsr_flush_hbc_cache(acb);
578 }
579 break;
580 case ACB_ADAPTER_TYPE_D: {
581 arcmsr_flush_hbd_cache(acb);
582 }
583 break;
580 case ACB_ADAPTER_TYPE_E: {
584 case ACB_ADAPTER_TYPE_E:
585 case ACB_ADAPTER_TYPE_F: {
581 arcmsr_flush_hbe_cache(acb);
582 }
583 break;
584 }
585}
586/*
587*******************************************************************************
588*******************************************************************************

--- 139 unchanged lines hidden (view full) ---

728 case ACB_ADAPTER_TYPE_C: {
729 arcmsr_abort_hbc_allcmd(acb);
730 }
731 break;
732 case ACB_ADAPTER_TYPE_D: {
733 arcmsr_abort_hbd_allcmd(acb);
734 }
735 break;
586 arcmsr_flush_hbe_cache(acb);
587 }
588 break;
589 }
590}
591/*
592*******************************************************************************
593*******************************************************************************

--- 139 unchanged lines hidden (view full) ---

733 case ACB_ADAPTER_TYPE_C: {
734 arcmsr_abort_hbc_allcmd(acb);
735 }
736 break;
737 case ACB_ADAPTER_TYPE_D: {
738 arcmsr_abort_hbd_allcmd(acb);
739 }
740 break;
736 case ACB_ADAPTER_TYPE_E: {
741 case ACB_ADAPTER_TYPE_E:
742 case ACB_ADAPTER_TYPE_F: {
737 arcmsr_abort_hbe_allcmd(acb);
738 }
739 break;
740 }
741}
742/*
743**********************************************************************
744**********************************************************************

--- 94 unchanged lines hidden (view full) ---

839 case ACB_ADAPTER_TYPE_B:
840 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
841 break;
842 case ACB_ADAPTER_TYPE_C:
843 case ACB_ADAPTER_TYPE_D:
844 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
845 break;
846 case ACB_ADAPTER_TYPE_E:
743 arcmsr_abort_hbe_allcmd(acb);
744 }
745 break;
746 }
747}
748/*
749**********************************************************************
750**********************************************************************

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845 case ACB_ADAPTER_TYPE_B:
846 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
847 break;
848 case ACB_ADAPTER_TYPE_C:
849 case ACB_ADAPTER_TYPE_D:
850 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
851 break;
852 case ACB_ADAPTER_TYPE_E:
853 case ACB_ADAPTER_TYPE_F:
847 srb = acb->psrb_pool[flag_srb];
848 break;
849 default:
850 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
851 break;
852 }
853 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
854 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {

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936 case ACB_ADAPTER_TYPE_C: {
937 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
938 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
939 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
940 arcmsr_drain_donequeue(acb, flag_srb, error);
941 }
942 }
943 break;
854 srb = acb->psrb_pool[flag_srb];
855 break;
856 default:
857 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
858 break;
859 }
860 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
861 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {

--- 81 unchanged lines hidden (view full) ---

943 case ACB_ADAPTER_TYPE_C: {
944 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
945 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
946 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
947 arcmsr_drain_donequeue(acb, flag_srb, error);
948 }
949 }
950 break;
944 case ACB_ADAPTER_TYPE_D: {
945 arcmsr_hbd_postqueue_isr(acb);
946 }
951 case ACB_ADAPTER_TYPE_D:
952 arcmsr_hbd_postqueue_isr(acb);
947 break;
953 break;
948 case ACB_ADAPTER_TYPE_E: {
949 arcmsr_hbe_postqueue_isr(acb);
950 }
954 case ACB_ADAPTER_TYPE_E:
955 arcmsr_hbe_postqueue_isr(acb);
951 break;
956 break;
957 case ACB_ADAPTER_TYPE_F:
958 arcmsr_hbf_postqueue_isr(acb);
959 break;
952 }
953}
954/*
955****************************************************************************
956****************************************************************************
957*/
958static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
959{

--- 202 unchanged lines hidden (view full) ---

1162 break;
1163 case ACB_ADAPTER_TYPE_E: {
1164 u_int32_t ccb_post_stamp, arc_cdb_size;
1165
1166 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1167 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
1168 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
1169 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
960 }
961}
962/*
963****************************************************************************
964****************************************************************************
965*/
966static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
967{

--- 202 unchanged lines hidden (view full) ---

1170 break;
1171 case ACB_ADAPTER_TYPE_E: {
1172 u_int32_t ccb_post_stamp, arc_cdb_size;
1173
1174 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1175 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
1176 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
1177 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1170 }
1178 }
1171 break;
1179 break;
1180 case ACB_ADAPTER_TYPE_F: {
1181 u_int32_t ccb_post_stamp, arc_cdb_size;
1182
1183 if (srb->arc_cdb_size <= 0x300)
1184 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1;
1185 else
1186 arc_cdb_size = (((srb->arc_cdb_size + 0xff) >> 8) + 2) << 1 | 1;
1187 ccb_post_stamp = (srb->smid | arc_cdb_size);
1188 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0);
1189 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1190 }
1191 break;
1172 }
1173}
1174/*
1175************************************************************************
1176************************************************************************
1177*/
1178static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1179{

--- 25 unchanged lines hidden (view full) ---

1205 }
1206 break;
1207 case ACB_ADAPTER_TYPE_E: {
1208 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1209
1210 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1211 }
1212 break;
1192 }
1193}
1194/*
1195************************************************************************
1196************************************************************************
1197*/
1198static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1199{

--- 25 unchanged lines hidden (view full) ---

1225 }
1226 break;
1227 case ACB_ADAPTER_TYPE_E: {
1228 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1229
1230 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1231 }
1232 break;
1233 case ACB_ADAPTER_TYPE_F:
1234 qbuffer = (struct QBUFFER *)acb->message_rbuffer;
1235 break;
1213 }
1214 return(qbuffer);
1215}
1216/*
1217************************************************************************
1218************************************************************************
1219*/
1220static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)

--- 26 unchanged lines hidden (view full) ---

1247 }
1248 break;
1249 case ACB_ADAPTER_TYPE_E: {
1250 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1251
1252 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1253 }
1254 break;
1236 }
1237 return(qbuffer);
1238}
1239/*
1240************************************************************************
1241************************************************************************
1242*/
1243static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)

--- 26 unchanged lines hidden (view full) ---

1270 }
1271 break;
1272 case ACB_ADAPTER_TYPE_E: {
1273 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1274
1275 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1276 }
1277 break;
1278 case ACB_ADAPTER_TYPE_F:
1279 qbuffer = (struct QBUFFER *)acb->message_wbuffer;
1280 break;
1255 }
1256 return(qbuffer);
1257}
1258/*
1259**************************************************************************
1260**************************************************************************
1261*/
1262static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)

--- 15 unchanged lines hidden (view full) ---

1278 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1279 }
1280 break;
1281 case ACB_ADAPTER_TYPE_D: {
1282 /* let IOP know data has been read */
1283 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1284 }
1285 break;
1281 }
1282 return(qbuffer);
1283}
1284/*
1285**************************************************************************
1286**************************************************************************
1287*/
1288static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)

--- 15 unchanged lines hidden (view full) ---

1304 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1305 }
1306 break;
1307 case ACB_ADAPTER_TYPE_D: {
1308 /* let IOP know data has been read */
1309 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1310 }
1311 break;
1286 case ACB_ADAPTER_TYPE_E: {
1312 case ACB_ADAPTER_TYPE_E:
1313 case ACB_ADAPTER_TYPE_F: {
1287 /* let IOP know data has been read */
1288 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1289 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1290 }
1291 break;
1292 }
1293}
1294/*

--- 31 unchanged lines hidden (view full) ---

1326 case ACB_ADAPTER_TYPE_D: {
1327 /*
1328 ** push inbound doorbell tell iop, driver data write ok
1329 ** and wait reply on next hwinterrupt for next Qbuffer post
1330 */
1331 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1332 }
1333 break;
1314 /* let IOP know data has been read */
1315 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1316 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1317 }
1318 break;
1319 }
1320}
1321/*

--- 31 unchanged lines hidden (view full) ---

1353 case ACB_ADAPTER_TYPE_D: {
1354 /*
1355 ** push inbound doorbell tell iop, driver data write ok
1356 ** and wait reply on next hwinterrupt for next Qbuffer post
1357 */
1358 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1359 }
1360 break;
1334 case ACB_ADAPTER_TYPE_E: {
1361 case ACB_ADAPTER_TYPE_E:
1362 case ACB_ADAPTER_TYPE_F: {
1335 /*
1336 ** push inbound doorbell tell iop, driver data write ok
1337 ** and wait reply on next hwinterrupt for next Qbuffer post
1338 */
1339 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1340 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1341 }
1342 break;

--- 84 unchanged lines hidden (view full) ---

1427 case ACB_ADAPTER_TYPE_C: {
1428 arcmsr_stop_hbc_bgrb(acb);
1429 }
1430 break;
1431 case ACB_ADAPTER_TYPE_D: {
1432 arcmsr_stop_hbd_bgrb(acb);
1433 }
1434 break;
1363 /*
1364 ** push inbound doorbell tell iop, driver data write ok
1365 ** and wait reply on next hwinterrupt for next Qbuffer post
1366 */
1367 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1368 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1369 }
1370 break;

--- 84 unchanged lines hidden (view full) ---

1455 case ACB_ADAPTER_TYPE_C: {
1456 arcmsr_stop_hbc_bgrb(acb);
1457 }
1458 break;
1459 case ACB_ADAPTER_TYPE_D: {
1460 arcmsr_stop_hbd_bgrb(acb);
1461 }
1462 break;
1435 case ACB_ADAPTER_TYPE_E: {
1463 case ACB_ADAPTER_TYPE_E:
1464 case ACB_ADAPTER_TYPE_F: {
1436 arcmsr_stop_hbe_bgrb(acb);
1437 }
1438 break;
1439 }
1440}
1441/*
1442************************************************************************
1443************************************************************************

--- 222 unchanged lines hidden (view full) ---

1666}
1667
1668static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1669{
1670 struct cam_path *path;
1671 union ccb *ccb;
1672
1673 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1465 arcmsr_stop_hbe_bgrb(acb);
1466 }
1467 break;
1468 }
1469}
1470/*
1471************************************************************************
1472************************************************************************

--- 222 unchanged lines hidden (view full) ---

1695}
1696
1697static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1698{
1699 struct cam_path *path;
1700 union ccb *ccb;
1701
1702 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1674 return;
1703 return;
1675 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1676 {
1677 xpt_free_ccb(ccb);
1678 return;
1679 }
1680/* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1681 bzero(ccb, sizeof(union ccb));
1682 xpt_setup_ccb(&ccb->ccb_h, path, 5);

--- 72 unchanged lines hidden (view full) ---

1755 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1756 devicemap += 4;
1757 }
1758 break;
1759 case ACB_ADAPTER_TYPE_E:
1760 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1761 for (target = 0; target < 4; target++)
1762 {
1704 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1705 {
1706 xpt_free_ccb(ccb);
1707 return;
1708 }
1709/* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1710 bzero(ccb, sizeof(union ccb));
1711 xpt_setup_ccb(&ccb->ccb_h, path, 5);

--- 72 unchanged lines hidden (view full) ---

1784 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1785 devicemap += 4;
1786 }
1787 break;
1788 case ACB_ADAPTER_TYPE_E:
1789 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1790 for (target = 0; target < 4; target++)
1791 {
1763 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1764 devicemap += 4;
1792 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1793 devicemap += 4;
1765 }
1766 break;
1794 }
1795 break;
1796 case ACB_ADAPTER_TYPE_F:
1797 devicemap = ARCMSR_FW_DEVMAP_OFFSET;
1798 for (target = 0; target < 4; target++)
1799 {
1800 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap];
1801 devicemap += 1;
1802 }
1803 break;
1767 }
1768
1769 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1770 {
1771 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1772 }
1773 /*
1774 ** adapter posted CONFIG message
1775 ** copy the new map, note if there are differences with the current map
1776 */
1804 }
1805
1806 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1807 {
1808 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1809 }
1810 /*
1811 ** adapter posted CONFIG message
1812 ** copy the new map, note if there are differences with the current map
1813 */
1777 pDevMap = (u_int8_t *)&deviceMapCurrent[0];
1814 pDevMap = (u_int8_t *)&deviceMapCurrent[0];
1778 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1779 {
1780 if (*pDevMap != acb->device_map[target])
1781 {
1782 u_int8_t difference, bit_check;
1783
1784 difference = *pDevMap ^ acb->device_map[target];
1785 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)

--- 211 unchanged lines hidden (view full) ---

1997 ** areca cdb command done
1998 *****************************************************************************
1999 */
2000 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2001 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2002 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
2003 0, outbound_queueport)) != 0xFFFFFFFF) {
2004 /* check if command done with no error*/
1815 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1816 {
1817 if (*pDevMap != acb->device_map[target])
1818 {
1819 u_int8_t difference, bit_check;
1820
1821 difference = *pDevMap ^ acb->device_map[target];
1822 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)

--- 211 unchanged lines hidden (view full) ---

2034 ** areca cdb command done
2035 *****************************************************************************
2036 */
2037 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2038 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2039 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
2040 0, outbound_queueport)) != 0xFFFFFFFF) {
2041 /* check if command done with no error*/
2005 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
2042 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
2006 arcmsr_drain_donequeue(acb, flag_srb, error);
2007 } /*drain reply FIFO*/
2008}
2009/*
2010**************************************************************************
2011**************************************************************************
2012*/
2013static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)

--- 12 unchanged lines hidden (view full) ---

2026 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2027 index = phbbmu->doneq_index;
2028 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
2029 phbbmu->done_qbuffer[index] = 0;
2030 index++;
2031 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
2032 phbbmu->doneq_index = index;
2033 /* check if command done with no error*/
2043 arcmsr_drain_donequeue(acb, flag_srb, error);
2044 } /*drain reply FIFO*/
2045}
2046/*
2047**************************************************************************
2048**************************************************************************
2049*/
2050static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)

--- 12 unchanged lines hidden (view full) ---

2063 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2064 index = phbbmu->doneq_index;
2065 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
2066 phbbmu->done_qbuffer[index] = 0;
2067 index++;
2068 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
2069 phbbmu->doneq_index = index;
2070 /* check if command done with no error*/
2034 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2071 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2035 arcmsr_drain_donequeue(acb, flag_srb, error);
2036 } /*drain reply FIFO*/
2037}
2038/*
2039**************************************************************************
2040**************************************************************************
2041*/
2042static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
2043{
2044 u_int32_t flag_srb,throttling = 0;
2045 u_int16_t error;
2046
2047 /*
2048 *****************************************************************************
2049 ** areca cdb command done
2050 *****************************************************************************
2051 */
2072 arcmsr_drain_donequeue(acb, flag_srb, error);
2073 } /*drain reply FIFO*/
2074}
2075/*
2076**************************************************************************
2077**************************************************************************
2078*/
2079static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
2080{
2081 u_int32_t flag_srb,throttling = 0;
2082 u_int16_t error;
2083
2084 /*
2085 *****************************************************************************
2086 ** areca cdb command done
2087 *****************************************************************************
2088 */
2052 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2089 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2053 do {
2054 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2055 if (flag_srb == 0xFFFFFFFF)
2056 break;
2057 /* check if command done with no error*/
2058 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2059 arcmsr_drain_donequeue(acb, flag_srb, error);
2060 throttling++;
2061 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2090 do {
2091 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2092 if (flag_srb == 0xFFFFFFFF)
2093 break;
2094 /* check if command done with no error*/
2095 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2096 arcmsr_drain_donequeue(acb, flag_srb, error);
2097 throttling++;
2098 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2062 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
2099 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
2063 throttling = 0;
2064 }
2065 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
2066}
2067/*
2068**********************************************************************
2069**
2070**********************************************************************

--- 75 unchanged lines hidden (view full) ---

2146 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2147 doneq_index++;
2148 if (doneq_index >= acb->completionQ_entry)
2149 doneq_index = 0;
2150 }
2151 acb->doneq_index = doneq_index;
2152 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2153}
2100 throttling = 0;
2101 }
2102 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
2103}
2104/*
2105**********************************************************************
2106**
2107**********************************************************************

--- 75 unchanged lines hidden (view full) ---

2183 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2184 doneq_index++;
2185 if (doneq_index >= acb->completionQ_entry)
2186 doneq_index = 0;
2187 }
2188 acb->doneq_index = doneq_index;
2189 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2190}
2191
2192static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb)
2193{
2194 uint16_t error;
2195 uint32_t doneq_index;
2196 uint16_t cmdSMID;
2197
2198 /*
2199 *****************************************************************************
2200 ** areca cdb command done
2201 *****************************************************************************
2202 */
2203 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2204 doneq_index = acb->doneq_index;
2205 while (1) {
2206 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2207 if (cmdSMID == 0xffff)
2208 break;
2209 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2210 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2211 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
2212 doneq_index++;
2213 if (doneq_index >= acb->completionQ_entry)
2214 doneq_index = 0;
2215 }
2216 acb->doneq_index = doneq_index;
2217 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2218}
2219
2154/*
2155**********************************************************************
2156**********************************************************************
2157*/
2158static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2159{
2160 u_int32_t outbound_intStatus;
2161 /*

--- 145 unchanged lines hidden (view full) ---

2307 }
2308 /* MU post queue interrupts*/
2309 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2310 arcmsr_hbe_postqueue_isr(acb);
2311 }
2312 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
2313 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2314}
2220/*
2221**********************************************************************
2222**********************************************************************
2223*/
2224static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2225{
2226 u_int32_t outbound_intStatus;
2227 /*

--- 145 unchanged lines hidden (view full) ---

2373 }
2374 /* MU post queue interrupts*/
2375 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2376 arcmsr_hbe_postqueue_isr(acb);
2377 }
2378 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
2379 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2380}
2381
2382static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb)
2383{
2384 u_int32_t host_interrupt_status;
2385 /*
2386 *********************************************
2387 ** check outbound intstatus
2388 *********************************************
2389 */
2390 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) &
2391 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2392 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2393 if(!host_interrupt_status) {
2394 /*it must be share irq*/
2395 return;
2396 }
2397 do {
2398 /* MU doorbell interrupts*/
2399 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2400 arcmsr_hbe_doorbell_isr(acb);
2401 }
2402 /* MU post queue interrupts*/
2403 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2404 arcmsr_hbf_postqueue_isr(acb);
2405 }
2406 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status);
2407 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2408}
2315/*
2316******************************************************************************
2317******************************************************************************
2318*/
2319static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2320{
2321 switch (acb->adapter_type) {
2322 case ACB_ADAPTER_TYPE_A:

--- 6 unchanged lines hidden (view full) ---

2329 arcmsr_handle_hbc_isr(acb);
2330 break;
2331 case ACB_ADAPTER_TYPE_D:
2332 arcmsr_handle_hbd_isr(acb);
2333 break;
2334 case ACB_ADAPTER_TYPE_E:
2335 arcmsr_handle_hbe_isr(acb);
2336 break;
2409/*
2410******************************************************************************
2411******************************************************************************
2412*/
2413static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2414{
2415 switch (acb->adapter_type) {
2416 case ACB_ADAPTER_TYPE_A:

--- 6 unchanged lines hidden (view full) ---

2423 arcmsr_handle_hbc_isr(acb);
2424 break;
2425 case ACB_ADAPTER_TYPE_D:
2426 arcmsr_handle_hbd_isr(acb);
2427 break;
2428 case ACB_ADAPTER_TYPE_E:
2429 arcmsr_handle_hbe_isr(acb);
2430 break;
2431 case ACB_ADAPTER_TYPE_F:
2432 arcmsr_handle_hbf_isr(acb);
2433 break;
2337 default:
2338 printf("arcmsr%d: interrupt service,"
2339 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2340 break;
2341 }
2342}
2343/*
2344**********************************************************************

--- 14 unchanged lines hidden (view full) ---

2359static void arcmsr_polling_devmap(void *arg)
2360{
2361 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2362 switch (acb->adapter_type) {
2363 case ACB_ADAPTER_TYPE_A:
2364 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2365 break;
2366
2434 default:
2435 printf("arcmsr%d: interrupt service,"
2436 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2437 break;
2438 }
2439}
2440/*
2441**********************************************************************

--- 14 unchanged lines hidden (view full) ---

2456static void arcmsr_polling_devmap(void *arg)
2457{
2458 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2459 switch (acb->adapter_type) {
2460 case ACB_ADAPTER_TYPE_A:
2461 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2462 break;
2463
2367 case ACB_ADAPTER_TYPE_B: {
2464 case ACB_ADAPTER_TYPE_B: {
2368 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2369 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2370 }
2371 break;
2372
2373 case ACB_ADAPTER_TYPE_C:
2374 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2375 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2376 break;
2377
2378 case ACB_ADAPTER_TYPE_D:
2379 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2380 break;
2381
2465 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2466 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2467 }
2468 break;
2469
2470 case ACB_ADAPTER_TYPE_C:
2471 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2472 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2473 break;
2474
2475 case ACB_ADAPTER_TYPE_D:
2476 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2477 break;
2478
2382 case ACB_ADAPTER_TYPE_E:
2479 case ACB_ADAPTER_TYPE_E:
2383 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2384 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2385 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2480 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2481 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2482 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2386 break;
2387 }
2483 break;
2388
2484
2485 case ACB_ADAPTER_TYPE_F: {
2486 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1);
2487 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
2488 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
2489 goto nxt6s;
2490 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2491 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2492 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2493 break;
2494 }
2495 }
2496nxt6s:
2389 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2390 {
2391 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */
2392 }
2393}
2394
2395/*
2396*******************************************************************************

--- 909 unchanged lines hidden (view full) ---

3306 break;
3307 case ACB_ADAPTER_TYPE_C:
3308 arcmsr_start_hbc_bgrb(acb);
3309 break;
3310 case ACB_ADAPTER_TYPE_D:
3311 arcmsr_start_hbd_bgrb(acb);
3312 break;
3313 case ACB_ADAPTER_TYPE_E:
2497 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2498 {
2499 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */
2500 }
2501}
2502
2503/*
2504*******************************************************************************

--- 909 unchanged lines hidden (view full) ---

3414 break;
3415 case ACB_ADAPTER_TYPE_C:
3416 arcmsr_start_hbc_bgrb(acb);
3417 break;
3418 case ACB_ADAPTER_TYPE_D:
3419 arcmsr_start_hbd_bgrb(acb);
3420 break;
3421 case ACB_ADAPTER_TYPE_E:
3422 case ACB_ADAPTER_TYPE_F:
3314 arcmsr_start_hbe_bgrb(acb);
3315 break;
3316 }
3317}
3318/*
3319**********************************************************************
3320**
3321**********************************************************************

--- 125 unchanged lines hidden (view full) ---

3447 if(poll_srb_done) {
3448 break;/*chip FIFO no ccb for completion already*/
3449 } else {
3450 UDELAY(25000);
3451 if ((poll_count > 100) && (poll_srb != NULL)) {
3452 break;
3453 }
3454 if (acb->srboutstandingcount == 0) {
3423 arcmsr_start_hbe_bgrb(acb);
3424 break;
3425 }
3426}
3427/*
3428**********************************************************************
3429**
3430**********************************************************************

--- 125 unchanged lines hidden (view full) ---

3556 if(poll_srb_done) {
3557 break;/*chip FIFO no ccb for completion already*/
3558 } else {
3559 UDELAY(25000);
3560 if ((poll_count > 100) && (poll_srb != NULL)) {
3561 break;
3562 }
3563 if (acb->srboutstandingcount == 0) {
3455 break;
3564 break;
3456 }
3457 goto polling_ccb_retry;
3458 }
3459 }
3460 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3461 /* check if command done with no error*/
3462 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3463 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;

--- 86 unchanged lines hidden (view full) ---

3550 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3551 while(1) {
3552 doneq_index = acb->doneq_index;
3553 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
3554 if(poll_srb_done) {
3555 break;/*chip FIFO no ccb for completion already*/
3556 } else {
3557 UDELAY(25000);
3565 }
3566 goto polling_ccb_retry;
3567 }
3568 }
3569 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3570 /* check if command done with no error*/
3571 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3572 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;

--- 86 unchanged lines hidden (view full) ---

3659 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3660 while(1) {
3661 doneq_index = acb->doneq_index;
3662 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
3663 if(poll_srb_done) {
3664 break;/*chip FIFO no ccb for completion already*/
3665 } else {
3666 UDELAY(25000);
3558 if ((poll_count > 100) && (poll_srb != NULL)) {
3667 if ((poll_count > 100) && (poll_srb != NULL)) {
3559 break;
3560 }
3668 break;
3669 }
3561 if (acb->srboutstandingcount == 0) {
3562 break;
3563 }
3670 if (acb->srboutstandingcount == 0) {
3671 break;
3672 }
3564 goto polling_ccb_retry;
3565 }
3566 }
3567 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3568 doneq_index++;
3569 if (doneq_index >= acb->completionQ_entry)
3570 doneq_index = 0;
3571 acb->doneq_index = doneq_index;

--- 19 unchanged lines hidden (view full) ---

3591}
3592/*
3593**********************************************************************
3594**********************************************************************
3595*/
3596static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3597{
3598 switch (acb->adapter_type) {
3673 goto polling_ccb_retry;
3674 }
3675 }
3676 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3677 doneq_index++;
3678 if (doneq_index >= acb->completionQ_entry)
3679 doneq_index = 0;
3680 acb->doneq_index = doneq_index;

--- 19 unchanged lines hidden (view full) ---

3700}
3701/*
3702**********************************************************************
3703**********************************************************************
3704*/
3705static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3706{
3707 switch (acb->adapter_type) {
3599 case ACB_ADAPTER_TYPE_A: {
3600 arcmsr_polling_hba_srbdone(acb, poll_srb);
3601 }
3708 case ACB_ADAPTER_TYPE_A:
3709 arcmsr_polling_hba_srbdone(acb, poll_srb);
3602 break;
3710 break;
3603 case ACB_ADAPTER_TYPE_B: {
3604 arcmsr_polling_hbb_srbdone(acb, poll_srb);
3605 }
3711 case ACB_ADAPTER_TYPE_B:
3712 arcmsr_polling_hbb_srbdone(acb, poll_srb);
3606 break;
3713 break;
3607 case ACB_ADAPTER_TYPE_C: {
3608 arcmsr_polling_hbc_srbdone(acb, poll_srb);
3609 }
3714 case ACB_ADAPTER_TYPE_C:
3715 arcmsr_polling_hbc_srbdone(acb, poll_srb);
3610 break;
3716 break;
3611 case ACB_ADAPTER_TYPE_D: {
3612 arcmsr_polling_hbd_srbdone(acb, poll_srb);
3613 }
3717 case ACB_ADAPTER_TYPE_D:
3718 arcmsr_polling_hbd_srbdone(acb, poll_srb);
3614 break;
3719 break;
3615 case ACB_ADAPTER_TYPE_E: {
3616 arcmsr_polling_hbe_srbdone(acb, poll_srb);
3617 }
3720 case ACB_ADAPTER_TYPE_E:
3721 case ACB_ADAPTER_TYPE_F:
3722 arcmsr_polling_hbe_srbdone(acb, poll_srb);
3618 break;
3619 }
3620}
3621/*
3622**********************************************************************
3623**********************************************************************
3624*/
3625static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)

--- 243 unchanged lines hidden (view full) ---

3869 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3870 else
3871 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3872}
3873/*
3874**********************************************************************
3875**********************************************************************
3876*/
3723 break;
3724 }
3725}
3726/*
3727**********************************************************************
3728**********************************************************************
3729*/
3730static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)

--- 243 unchanged lines hidden (view full) ---

3974 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3975 else
3976 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3977}
3978/*
3979**********************************************************************
3980**********************************************************************
3981*/
3982static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb)
3983{
3984 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model;
3985 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version;
3986 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map;
3987 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/
3988 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/
3989 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET;
3990 int i;
3991
3992 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3993 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3994 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3995 if(!arcmsr_hbe_wait_msgint_ready(acb))
3996 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3997
3998 i = 0;
3999 while(i < 2) {
4000 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model];
4001 /* 8 bytes firm_model, 15, 60-67*/
4002 acb_firm_model++;
4003 iop_firm_model++;
4004 i++;
4005 }
4006 i = 0;
4007 while(i < 4) {
4008 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version];
4009 /* 16 bytes firm_version, 17, 68-83*/
4010 acb_firm_version++;
4011 iop_firm_version++;
4012 i++;
4013 }
4014 i = 0;
4015 while(i < 4) {
4016 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map];
4017 acb_device_map++;
4018 iop_device_map++;
4019 i++;
4020 }
4021 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
4022 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/
4023 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/
4024 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/
4025 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/
4026 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/
4027 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4028 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4029 else
4030 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4031}
4032/*
4033**********************************************************************
4034**********************************************************************
4035*/
3877static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3878{
3879 switch (acb->adapter_type) {
4036static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
4037{
4038 switch (acb->adapter_type) {
3880 case ACB_ADAPTER_TYPE_A: {
3881 arcmsr_get_hba_config(acb);
3882 }
4039 case ACB_ADAPTER_TYPE_A:
4040 arcmsr_get_hba_config(acb);
3883 break;
4041 break;
3884 case ACB_ADAPTER_TYPE_B: {
3885 arcmsr_get_hbb_config(acb);
3886 }
4042 case ACB_ADAPTER_TYPE_B:
4043 arcmsr_get_hbb_config(acb);
3887 break;
4044 break;
3888 case ACB_ADAPTER_TYPE_C: {
3889 arcmsr_get_hbc_config(acb);
3890 }
4045 case ACB_ADAPTER_TYPE_C:
4046 arcmsr_get_hbc_config(acb);
3891 break;
4047 break;
3892 case ACB_ADAPTER_TYPE_D: {
3893 arcmsr_get_hbd_config(acb);
3894 }
4048 case ACB_ADAPTER_TYPE_D:
4049 arcmsr_get_hbd_config(acb);
3895 break;
4050 break;
3896 case ACB_ADAPTER_TYPE_E: {
3897 arcmsr_get_hbe_config(acb);
3898 }
4051 case ACB_ADAPTER_TYPE_E:
4052 arcmsr_get_hbe_config(acb);
3899 break;
4053 break;
4054 case ACB_ADAPTER_TYPE_F:
4055 arcmsr_get_hbf_config(acb);
4056 break;
3900 }
3901}
3902/*
3903**********************************************************************
3904**********************************************************************
3905*/
3906static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3907{

--- 45 unchanged lines hidden (view full) ---

3953 {
3954 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3955 return;
3956 }
3957 UDELAY(15000); /* wait 15 milli-seconds */
3958 }
3959 }
3960 break;
4057 }
4058}
4059/*
4060**********************************************************************
4061**********************************************************************
4062*/
4063static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
4064{

--- 45 unchanged lines hidden (view full) ---

4110 {
4111 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4112 return;
4113 }
4114 UDELAY(15000); /* wait 15 milli-seconds */
4115 }
4116 }
4117 break;
3961 case ACB_ADAPTER_TYPE_E: {
4118 case ACB_ADAPTER_TYPE_E:
4119 case ACB_ADAPTER_TYPE_F: {
3962 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
3963 {
3964 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
3965 {
3966 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3967 return;
3968 }
3969 UDELAY(15000); /* wait 15 milli-seconds */

--- 36 unchanged lines hidden (view full) ---

4006 break;
4007 case ACB_ADAPTER_TYPE_D: {
4008 /* empty doorbell Qbuffer if door bell ringed */
4009 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
4010 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
4011 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
4012 }
4013 break;
4120 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
4121 {
4122 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
4123 {
4124 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4125 return;
4126 }
4127 UDELAY(15000); /* wait 15 milli-seconds */

--- 36 unchanged lines hidden (view full) ---

4164 break;
4165 case ACB_ADAPTER_TYPE_D: {
4166 /* empty doorbell Qbuffer if door bell ringed */
4167 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
4168 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
4169 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
4170 }
4171 break;
4014 case ACB_ADAPTER_TYPE_E: {
4172 case ACB_ADAPTER_TYPE_E:
4173 case ACB_ADAPTER_TYPE_F: {
4015 /* empty doorbell Qbuffer if door bell ringed */
4016 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
4017 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */
4018 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4019 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4020 }
4021 break;
4022 }

--- 118 unchanged lines hidden (view full) ---

4141 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4142 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4143 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4144 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4145 return FALSE;
4146 }
4147 }
4148 break;
4174 /* empty doorbell Qbuffer if door bell ringed */
4175 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
4176 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */
4177 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4178 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4179 }
4180 break;
4181 }

--- 118 unchanged lines hidden (view full) ---

4300 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4301 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4302 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4303 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4304 return FALSE;
4305 }
4306 }
4307 break;
4308 case ACB_ADAPTER_TYPE_F: {
4309 u_int32_t cdb_phyaddr_lo32;
4310 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4311 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
4312 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
4313 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32;
4314 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32;
4315 acb->msgcode_rwbuffer[4] = SRB_SIZE;
4316 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4317 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32;
4318 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32;
4319 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE;
4320 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4321 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4322 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4323 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4324 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4325 return FALSE;
4326 }
4327 }
4328 break;
4149 }
4150 return (TRUE);
4151}
4152/*
4153************************************************************************
4154************************************************************************
4155*/
4156static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)

--- 47 unchanged lines hidden (view full) ---

4204 if(bus_dmamap_create(acb->dm_segs_dmat,
4205 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
4206 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
4207 printf("arcmsr%d:"
4208 " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
4209 return;
4210 }
4211 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
4329 }
4330 return (TRUE);
4331}
4332/*
4333************************************************************************
4334************************************************************************
4335*/
4336static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)

--- 47 unchanged lines hidden (view full) ---

4384 if(bus_dmamap_create(acb->dm_segs_dmat,
4385 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
4386 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
4387 printf("arcmsr%d:"
4388 " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
4389 return;
4390 }
4391 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
4212 || (acb->adapter_type == ACB_ADAPTER_TYPE_E))
4392 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F))
4213 {
4214 srb_tmp->cdb_phyaddr_low = srb_phyaddr;
4215 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
4216 }
4217 else
4218 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
4219 srb_tmp->acb = acb;
4220 srb_tmp->smid = i << 16;
4221 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
4222 srb_phyaddr = srb_phyaddr + SRB_SIZE;
4223 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
4224 }
4225 if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
4226 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4393 {
4394 srb_tmp->cdb_phyaddr_low = srb_phyaddr;
4395 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
4396 }
4397 else
4398 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
4399 srb_tmp->acb = acb;
4400 srb_tmp->smid = i << 16;
4401 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
4402 srb_phyaddr = srb_phyaddr + SRB_SIZE;
4403 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
4404 }
4405 if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
4406 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4407 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) {
4408 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4409 acb->completeQ_phys = srb_phyaddr;
4410 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE);
4411 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE);
4412 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100);
4413 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200);
4414 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
4415 }
4227 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
4228}
4229/*
4230************************************************************************
4231************************************************************************
4232*/
4233static void arcmsr_free_resource(struct AdapterControlBlock *acb)
4234{

--- 59 unchanged lines hidden (view full) ---

4294 }
4295 break;
4296 case PCIDevVenIDARC1884:
4297 acb->adapter_type = ACB_ADAPTER_TYPE_E;
4298 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4299 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
4300 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4301 break;
4416 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
4417}
4418/*
4419************************************************************************
4420************************************************************************
4421*/
4422static void arcmsr_free_resource(struct AdapterControlBlock *acb)
4423{

--- 59 unchanged lines hidden (view full) ---

4483 }
4484 break;
4485 case PCIDevVenIDARC1884:
4486 acb->adapter_type = ACB_ADAPTER_TYPE_E;
4487 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4488 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
4489 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4490 break;
4491 case PCIDevVenIDARC1886_:
4492 case PCIDevVenIDARC1886:
4493 acb->adapter_type = ACB_ADAPTER_TYPE_F;
4494 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4495 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE;
4496 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4497 break;
4302 case PCIDevVenIDARC1214: {
4303 acb->adapter_type = ACB_ADAPTER_TYPE_D;
4304 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4305 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4306 }
4307 break;
4308 case PCIDevVenIDARC1200:
4309 case PCIDevVenIDARC1201: {

--- 198 unchanged lines hidden (view full) ---

4508 acb->rid[0] = rid[0];
4509 acb->rid[1] = rid[1];
4510 }
4511 break;
4512 case ACB_ADAPTER_TYPE_C: {
4513 u_int32_t rid0 = PCIR_BAR(1);
4514 vm_offset_t mem_base0;
4515
4498 case PCIDevVenIDARC1214: {
4499 acb->adapter_type = ACB_ADAPTER_TYPE_D;
4500 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4501 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4502 }
4503 break;
4504 case PCIDevVenIDARC1200:
4505 case PCIDevVenIDARC1201: {

--- 198 unchanged lines hidden (view full) ---

4704 acb->rid[0] = rid[0];
4705 acb->rid[1] = rid[1];
4706 }
4707 break;
4708 case ACB_ADAPTER_TYPE_C: {
4709 u_int32_t rid0 = PCIR_BAR(1);
4710 vm_offset_t mem_base0;
4711
4516 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4712 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4517 if(acb->sys_res_arcmsr[0] == NULL) {
4518 arcmsr_free_resource(acb);
4519 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4520 return ENOMEM;
4521 }
4522 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4523 arcmsr_free_resource(acb);
4524 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));

--- 11 unchanged lines hidden (view full) ---

4536 acb->rid[0] = rid0;
4537 }
4538 break;
4539 case ACB_ADAPTER_TYPE_D: {
4540 struct HBD_MessageUnit0 *phbdmu;
4541 u_int32_t rid0 = PCIR_BAR(0);
4542 vm_offset_t mem_base0;
4543
4713 if(acb->sys_res_arcmsr[0] == NULL) {
4714 arcmsr_free_resource(acb);
4715 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4716 return ENOMEM;
4717 }
4718 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4719 arcmsr_free_resource(acb);
4720 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));

--- 11 unchanged lines hidden (view full) ---

4732 acb->rid[0] = rid0;
4733 }
4734 break;
4735 case ACB_ADAPTER_TYPE_D: {
4736 struct HBD_MessageUnit0 *phbdmu;
4737 u_int32_t rid0 = PCIR_BAR(0);
4738 vm_offset_t mem_base0;
4739
4544 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4740 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4545 if(acb->sys_res_arcmsr[0] == NULL) {
4546 arcmsr_free_resource(acb);
4547 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4548 return ENOMEM;
4549 }
4550 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4551 arcmsr_free_resource(acb);
4552 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));

--- 40 unchanged lines hidden (view full) ---

4593 acb->doneq_index = 0;
4594 acb->in_doorbell = 0;
4595 acb->out_doorbell = 0;
4596 acb->rid[0] = rid0;
4597 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4598 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4599 }
4600 break;
4741 if(acb->sys_res_arcmsr[0] == NULL) {
4742 arcmsr_free_resource(acb);
4743 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4744 return ENOMEM;
4745 }
4746 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4747 arcmsr_free_resource(acb);
4748 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));

--- 40 unchanged lines hidden (view full) ---

4789 acb->doneq_index = 0;
4790 acb->in_doorbell = 0;
4791 acb->out_doorbell = 0;
4792 acb->rid[0] = rid0;
4793 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4794 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4795 }
4796 break;
4797 case ACB_ADAPTER_TYPE_F: {
4798 u_int32_t rid0 = PCIR_BAR(0);
4799 vm_offset_t mem_base0;
4800 unsigned long host_buffer_dma;
4801
4802 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4803 if(acb->sys_res_arcmsr[0] == NULL) {
4804 arcmsr_free_resource(acb);
4805 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4806 return ENOMEM;
4807 }
4808 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4809 arcmsr_free_resource(acb);
4810 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4811 return ENXIO;
4812 }
4813 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4814 if(mem_base0 == 0) {
4815 arcmsr_free_resource(acb);
4816 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4817 return ENXIO;
4818 }
4819 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4820 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4821 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4822 acb->doneq_index = 0;
4823 acb->in_doorbell = 0;
4824 acb->out_doorbell = 0;
4825 acb->rid[0] = rid0;
4826 arcmsr_wait_firmware_ready(acb);
4827 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4828 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4829 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE;
4830 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */
4831 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */
4832 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */
4833 }
4834 break;
4601 }
4602 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4603 arcmsr_free_resource(acb);
4604 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4605 return ENXIO;
4606 }
4607 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4608 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;

--- 188 unchanged lines hidden (view full) ---

4797 (sub_device_id == ARECA_SUB_DEV_ID_1226))
4798 type = "SAS 12G";
4799 else
4800 type = "SAS 6G";
4801 break;
4802 case PCIDevVenIDARC1884:
4803 type = "SAS 12G";
4804 break;
4835 }
4836 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4837 arcmsr_free_resource(acb);
4838 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4839 return ENXIO;
4840 }
4841 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4842 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;

--- 188 unchanged lines hidden (view full) ---

5031 (sub_device_id == ARECA_SUB_DEV_ID_1226))
5032 type = "SAS 12G";
5033 else
5034 type = "SAS 6G";
5035 break;
5036 case PCIDevVenIDARC1884:
5037 type = "SAS 12G";
5038 break;
5039 case PCIDevVenIDARC1886_:
5040 case PCIDevVenIDARC1886:
5041 type = "NVME,SAS-12G,SATA-6G";
5042 break;
4805 case PCIDevVenIDARC1214:
4806 case PCIDevVenIDARC1203:
4807 type = "SATA 6G";
4808 break;
4809 default:
4810 type = x_type;
4811 raid6 = 0;
4812 break;

--- 116 unchanged lines hidden --- 		5043 case PCIDevVenIDARC1214:
5044 case PCIDevVenIDARC1203:
5045 type = "SATA 6G";
5046 break;
5047 default:
5048 type = x_type;
5049 raid6 = 0;
5050 break;

--- 116 unchanged lines hidden ---