| aic7xxx_reg.h (3e4756a1ce197aa5a05b7c5e9d07c81120c23efb) | aic7xxx_reg.h (adf516474d714ff67c338ab230be3883e6a73494) |
|---|---|
| 1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994, 1995 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 4 unchanged lines hidden (view full) --- 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Absolutely no warranty of function or purpose is made by the author 17 * Justin T. Gibbs. 18 * 4. Modifications may be freely made to this file if the above conditions 19 * are met. 20 * | 1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994, 1995 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 4 unchanged lines hidden (view full) --- 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Absolutely no warranty of function or purpose is made by the author 17 * Justin T. Gibbs. 18 * 4. Modifications may be freely made to this file if the above conditions 19 * are met. 20 * |
| 21 * $Id$ | 21 * $Id: aic7xxx_reg.h,v 1.1 1995/11/05 04:37:25 gibbs Exp $ |
| 22 */ 23 24/* | 22 */ 23 24/* |
| 25 * This header should be shared by the sequencer code and the kernel 26 * level driver. Unfortuanetly I haven't mangled the sequencer assembler 27 * into using cpp yet. Someday... | 25 * This header is shared by the sequencer code and the kernel level driver. |
| 28 * 29 * All page numbers refer to the Adaptec AIC-7770 Data Book availible from 30 * Adaptec's Technical Documents Department 1-800-934-2766 31 */ 32 33/* 34 * SCSI Sequence Control (p. 3-11). 35 * Each bit, when set starts a specific SCSI sequence on the bus --- 60 unchanged lines hidden (view full) --- 96#define MSGI 0x20 97#define ATNI 0x10 98#define SELI 0x08 99#define BSYI 0x04 100#define REQI 0x02 101#define ACKI 0x01 102 103/* | 26 * 27 * All page numbers refer to the Adaptec AIC-7770 Data Book availible from 28 * Adaptec's Technical Documents Department 1-800-934-2766 29 */ 30 31/* 32 * SCSI Sequence Control (p. 3-11). 33 * Each bit, when set starts a specific SCSI sequence on the bus --- 60 unchanged lines hidden (view full) --- 94#define MSGI 0x20 95#define ATNI 0x10 96#define SELI 0x08 97#define BSYI 0x04 98#define REQI 0x02 99#define ACKI 0x01 100 101/* |
| 102 * Possible phases in SCSISIGI 103 */ 104#define PHASE_MASK 0xe0 105#define P_DATAOUT 0x00 106#define P_DATAIN 0x40 107#define P_COMMAND 0x80 108#define P_MESGOUT 0xa0 109#define P_STATUS 0xc0 110#define P_MESGIN 0xe0 111/* |
|
| 104 * SCSI Contol Signal Write Register (p. 3-16). 105 * Writing to this register modifies the control signals on the bus. Only 106 * those signals that are allowed in the current mode (Initiator/Target) are 107 * asserted. 108 */ 109#define SCSISIGO 0x003 110#define CDO 0x80 111#define IOO 0x40 --- 7 unchanged lines hidden (view full) --- 119/* 120 * SCSI Rate Control (p. 3-17). 121 * Contents of this register determine the Synchronous SCSI data transfer 122 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 123 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 124 * greater than 0 enables synchronous transfers. 125 */ 126#define SCSIRATE 0x004 | 112 * SCSI Contol Signal Write Register (p. 3-16). 113 * Writing to this register modifies the control signals on the bus. Only 114 * those signals that are allowed in the current mode (Initiator/Target) are 115 * asserted. 116 */ 117#define SCSISIGO 0x003 118#define CDO 0x80 119#define IOO 0x40 --- 7 unchanged lines hidden (view full) --- 127/* 128 * SCSI Rate Control (p. 3-17). 129 * Contents of this register determine the Synchronous SCSI data transfer 130 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 131 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 132 * greater than 0 enables synchronous transfers. 133 */ 134#define SCSIRATE 0x004 |
| 127#define WIDEXFER 0x80 /* Wide transfer control */ 128#define SXFR 0x70 /* Sync transfer rate */ 129#define SOFS 0x0f /* Sync offset */ | 135#define WIDEXFER 0x80 /* Wide transfer control */ 136#define SXFR 0x70 /* Sync transfer rate */ 137#define SOFS 0x0f /* Sync offset */ |
| 130 131/* 132 * SCSI ID (p. 3-18). 133 * Contains the ID of the board and the current target on the | 138 139/* 140 * SCSI ID (p. 3-18). 141 * Contains the ID of the board and the current target on the |
| 134 * selected channel | 142 * selected channel. |
| 135 */ 136#define SCSIID 0x005 137#define TID 0xf0 /* Target ID mask */ 138#define OID 0x0f /* Our ID mask */ 139 140/* | 143 */ 144#define SCSIID 0x005 145#define TID 0xf0 /* Target ID mask */ 146#define OID 0x0f /* Our ID mask */ 147 148/* |
| 149 * SCSI Latched Data (p. 3-19). 150 * Read/Write latchs used to transfer data on the SCSI bus during 151 * Automatic or Manual PIO mode. SCSIDATH can be used for the 152 * upper byte of a 16bit wide asyncronouse data phase transfer. 153 */ 154#define SCSIDATL 0x006 155#define SCSIDATH 0x007 156 157/* |
|
| 141 * SCSI Transfer Count (pp. 3-19,20) 142 * These registers count down the number of bytes transfered 143 * across the SCSI bus. The counter is decremented only once 144 * the data has been safely transfered. SDONE in SSTAT0 is 145 * set when STCNT goes to 0 146 */ 147#define STCNT 0x008 | 158 * SCSI Transfer Count (pp. 3-19,20) 159 * These registers count down the number of bytes transfered 160 * across the SCSI bus. The counter is decremented only once 161 * the data has been safely transfered. SDONE in SSTAT0 is 162 * set when STCNT goes to 0 163 */ 164#define STCNT 0x008 |
| 165#define STCNT0 0x008 166#define STCNT1 0x009 167#define STCNT2 0x00a |
|
| 148 149/* | 168 169/* |
| 170 * Clear SCSI Interrupt 0 (p. 3-20) 171 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 172 */ 173#define CLRSINT0 0x00b 174#define CLRSELDO 0x40 175#define CLRSELDI 0x20 176#define CLRSELINGO 0x10 177#define CLRSWRAP 0x08 178/* UNUSED 0x04 */ 179#define CLRSPIORDY 0x02 180/* UNUSED 0x01 */ 181 182/* |
|
| 150 * SCSI Status 0 (p. 3-21) 151 * Contains one set of SCSI Interrupt codes 152 * These are most likely of interest to the sequencer 153 */ 154#define SSTAT0 0x00b | 183 * SCSI Status 0 (p. 3-21) 184 * Contains one set of SCSI Interrupt codes 185 * These are most likely of interest to the sequencer 186 */ 187#define SSTAT0 0x00b |
| 155#define TARGET 0x80 /* Board is a target */ | 188#define TARGET 0x80 /* Board acting as target */ |
| 156#define SELDO 0x40 /* Selection Done */ 157#define SELDI 0x20 /* Board has been selected */ 158#define SELINGO 0x10 /* Selection In Progress */ 159#define SWRAP 0x08 /* 24bit counter wrap */ 160#define SDONE 0x04 /* STCNT = 0x000000 */ 161#define SPIORDY 0x02 /* SCSI PIO Ready */ 162#define DMADONE 0x01 /* DMA transfer completed */ 163 --- 8 unchanged lines hidden (view full) --- 172/* UNUSED 0x10 */ 173#define CLRBUSFREE 0x08 174#define CLRSCSIPERR 0x04 175#define CLRPHASECHG 0x02 176#define CLRREQINIT 0x01 177 178/* 179 * SCSI Status 1 (p. 3-24) | 189#define SELDO 0x40 /* Selection Done */ 190#define SELDI 0x20 /* Board has been selected */ 191#define SELINGO 0x10 /* Selection In Progress */ 192#define SWRAP 0x08 /* 24bit counter wrap */ 193#define SDONE 0x04 /* STCNT = 0x000000 */ 194#define SPIORDY 0x02 /* SCSI PIO Ready */ 195#define DMADONE 0x01 /* DMA transfer completed */ 196 --- 8 unchanged lines hidden (view full) --- 205/* UNUSED 0x10 */ 206#define CLRBUSFREE 0x08 207#define CLRSCSIPERR 0x04 208#define CLRPHASECHG 0x02 209#define CLRREQINIT 0x01 210 211/* 212 * SCSI Status 1 (p. 3-24) |
| 180 * These interrupt bits are of interest to the kernel driver | |
| 181 */ 182#define SSTAT1 0x00c 183#define SELTO 0x80 184#define ATNTARG 0x40 185#define SCSIRSTI 0x20 186#define PHASEMIS 0x10 187#define BUSFREE 0x08 188#define SCSIPERR 0x04 189#define PHASECHG 0x02 190#define REQINIT 0x01 191 192/* | 213 */ 214#define SSTAT1 0x00c 215#define SELTO 0x80 216#define ATNTARG 0x40 217#define SCSIRSTI 0x20 218#define PHASEMIS 0x10 219#define BUSFREE 0x08 220#define SCSIPERR 0x04 221#define PHASECHG 0x02 222#define REQINIT 0x01 223 224/* |
| 225 * SCSI Interrupt Mode 1 (pp. 3-28,29) 226 * Setting any bit will enable the corresponding function 227 * in SIMODE1 to interrupt via the IRQ pin. 228 */ 229#define SIMODE1 0x011 230#define ENSELTIMO 0x80 231#define ENATNTARG 0x40 232#define ENSCSIRST 0x20 233#define ENPHASEMIS 0x10 234#define ENBUSFREE 0x08 235#define ENSCSIPERR 0x04 236#define ENPHASECHG 0x02 237#define ENREQINIT 0x01 238 239/* 240 * SCSI Data Bus (High) (p. 3-29) 241 * This register reads data on the SCSI Data bus directly. 242 */ 243#define SCSIBUSL 0x012 244#define SCSIBUSH 0x013 245 246/* |
|
| 193 * SCSI/Host Address (p. 3-30) 194 * These registers hold the host address for the byte about to be 195 * transfered on the SCSI bus. They are counted up in the same 196 * manner as STCNT is counted down. SHADDR should always be used 197 * to determine the address of the last byte transfered since HADDR 198 * can be squewed by write ahead. 199 */ 200#define SHADDR 0x014 --- 11 unchanged lines hidden (view full) --- 212/* 213 * SCSI Block Control (p. 3-32) 214 * Controls Bus type and channel selection. In a twin channel configuration 215 * addresses 0x00-0x1e are gated to the appropriate channel based on this 216 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 217 * on a wide bus. 218 */ 219#define SBLKCTL 0x01f | 247 * SCSI/Host Address (p. 3-30) 248 * These registers hold the host address for the byte about to be 249 * transfered on the SCSI bus. They are counted up in the same 250 * manner as STCNT is counted down. SHADDR should always be used 251 * to determine the address of the last byte transfered since HADDR 252 * can be squewed by write ahead. 253 */ 254#define SHADDR 0x014 --- 11 unchanged lines hidden (view full) --- 266/* 267 * SCSI Block Control (p. 3-32) 268 * Controls Bus type and channel selection. In a twin channel configuration 269 * addresses 0x00-0x1e are gated to the appropriate channel based on this 270 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 271 * on a wide bus. 272 */ 273#define SBLKCTL 0x01f |
| 220/* UNUSED 0xc0 */ | 274#define DIAGLEDEN 0x80 /* Aic78X0 only */ 275#define DIAGLEDON 0x40 /* Aic78X0 only */ |
| 221#define AUTOFLUSHDIS 0x20 222/* UNUSED 0x10 */ 223#define SELBUSB 0x08 224/* UNUSED 0x04 */ 225#define SELWIDE 0x02 226/* UNUSED 0x01 */ 227 228/* --- 29 unchanged lines hidden (view full) --- 258 259/* 260 * Accumulator 261 * We cheat by passing arguments in the Accumulator up to the kernel driver 262 */ 263#define ACCUM 0x064 264 265#define SINDEX 0x065 | 276#define AUTOFLUSHDIS 0x20 277/* UNUSED 0x10 */ 278#define SELBUSB 0x08 279/* UNUSED 0x04 */ 280#define SELWIDE 0x02 281/* UNUSED 0x01 */ 282 283/* --- 29 unchanged lines hidden (view full) --- 313 314/* 315 * Accumulator 316 * We cheat by passing arguments in the Accumulator up to the kernel driver 317 */ 318#define ACCUM 0x064 319 320#define SINDEX 0x065 |
| 321#define DINDEX 0x066 322#define ALLZEROS 0x06a 323#define NONE 0x06a 324#define SINDIR 0x06c 325#define DINDIR 0x06d 326#define FUNCTION1 0x06e |
|
| 266 267/* | 327 328/* |
| 329 * Host Address (p. 3-48) 330 * This register contains the address of the byte about 331 * to be transfered across the host bus. 332 */ 333#define HADDR 0x088 334#define HADDR0 0x088 335#define HADDR1 0x089 336#define HADDR2 0x08a 337#define HADDR3 0x08b 338 339#define HCNT 0x08c 340#define HCNT0 0x08c 341#define HCNT1 0x08d 342#define HCNT2 0x08e 343/* 344 * SCB Pointer (p. 3-49) 345 * Gate one of the four SCBs into the SCBARRAY window. 346 */ 347#define SCBPTR 0x090 348 349/* |
|
| 268 * Board Control (p. 3-43) 269 */ 270#define BCTL 0x084 271/* RSVD 0xf0 */ 272#define ACE 0x08 /* Support for external processors */ 273/* RSVD 0x06 */ 274#define ENABLE 0x01 275 276/* 277 * Bus On/Off Time (p. 3-44) 278 */ 279#define BUSTIME 0x085 280#define BOFF 0xf0 281#define BON 0x0f | 350 * Board Control (p. 3-43) 351 */ 352#define BCTL 0x084 353/* RSVD 0xf0 */ 354#define ACE 0x08 /* Support for external processors */ 355/* RSVD 0x06 */ 356#define ENABLE 0x01 357 358/* 359 * Bus On/Off Time (p. 3-44) 360 */ 361#define BUSTIME 0x085 362#define BOFF 0xf0 363#define BON 0x0f |
| 364#define BOFF_60BCLKS 0xf0 |
|
| 282 283/* 284 * Bus Speed (p. 3-45) 285 */ 286#define BUSSPD 0x086 287#define DFTHRSH 0xc0 288#define STBOFF 0x38 289#define STBON 0x07 | 365 366/* 367 * Bus Speed (p. 3-45) 368 */ 369#define BUSSPD 0x086 370#define DFTHRSH 0xc0 371#define STBOFF 0x38 372#define STBON 0x07 |
| 373#define DFTHRSH_100 0xc0 |
|
| 290 291/* 292 * Host Control (p. 3-47) R/W 293 * Overal host control of the device. 294 */ 295#define HCNTRL 0x087 296/* UNUSED 0x80 */ 297#define POWRDN 0x40 298/* UNUSED 0x20 */ 299#define SWINT 0x10 300#define IRQMS 0x08 301#define PAUSE 0x04 302#define INTEN 0x02 303#define CHIPRST 0x01 304 305/* | 374 375/* 376 * Host Control (p. 3-47) R/W 377 * Overal host control of the device. 378 */ 379#define HCNTRL 0x087 380/* UNUSED 0x80 */ 381#define POWRDN 0x40 382/* UNUSED 0x20 */ 383#define SWINT 0x10 384#define IRQMS 0x08 385#define PAUSE 0x04 386#define INTEN 0x02 387#define CHIPRST 0x01 388 389/* |
| 306 * Host Address (p. 3-48) 307 * This register contains the address of the byte about 308 * to be transfered across the host bus. 309 */ 310#define HADDR 0x088 311/* 312 * SCB Pointer (p. 3-49) 313 * Gate one of the four SCBs into the SCBARRAY window. 314 */ 315#define SCBPTR 0x090 316 317/* | |
| 318 * Interrupt Status (p. 3-50) 319 * Status for system interrupts 320 */ 321#define INTSTAT 0x091 | 390 * Interrupt Status (p. 3-50) 391 * Status for system interrupts 392 */ 393#define INTSTAT 0x091 |
| 322#define SEQINT_MASK 0xf0 /* SEQINT Status Codes */ 323#define BAD_PHASE 0x00 324#define SEND_REJECT 0x10 325#define NO_IDENT 0x20 326#define NO_MATCH 0x30 327#define MSG_SDTR 0x40 328#define MSG_WDTR 0x50 329#define MSG_REJECT 0x60 330#define BAD_STATUS 0x70 331#define RESIDUAL 0x80 332#define ABORT_TAG 0x90 333#define AWAITING_MSG 0xa0 334#define IMMEDDONE 0xb0 | 394#define SEQINT_MASK 0xf1 /* SEQINT Status Codes */ 395#define BAD_PHASE 0x01 /* unknown scsi bus phase */ 396#define SEND_REJECT 0x11 /* sending a message reject */ 397#define NO_IDENT 0x21 /* no IDENTIFY after reconnect*/ 398#define NO_MATCH 0x31 /* no cmd match for reconnect */ 399#define SDTR_MSG 0x41 /* SDTR message recieved */ 400#define WDTR_MSG 0x51 /* WDTR message recieved */ 401#define REJECT_MSG 0x61 /* Reject message recieved */ 402#define BAD_STATUS 0x71 /* Bad status from target */ 403#define RESIDUAL 0x81 /* Residual byte count != 0 */ 404#define ABORT_TAG 0x91 /* Sent an ABORT_TAG message */ 405#define AWAITING_MSG 0xa1 /* 406 * Kernel requested to specify 407 * a message to this target 408 * (command was null), so tell 409 * it that it can fill the 410 * message buffer. 411 */ 412#define IMMEDDONE 0xb1 /* 413 * An immediate command has 414 * completed 415 */ 416#define MSG_BUFFER_BUSY 0xc1 /* 417 * Sequencer wants to use the 418 * message buffer, but it 419 * already contains a message 420 */ 421#define MSGIN_PHASEMIS 0xd1 /* 422 * Target changed phase on us 423 * when we were expecting 424 * another msgin byte. 425 */ |
| 335#define BRKADRINT 0x08 336#define SCSIINT 0x04 337#define CMDCMPLT 0x02 338#define SEQINT 0x01 339#define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) 340 341/* 342 * Hard Error (p. 3-53) --- 11 unchanged lines hidden (view full) --- 354 * Clear Interrupt Status (p. 3-52) 355 */ 356#define CLRINT 0x092 357#define CLRBRKADRINT 0x08 358#define CLRSCSIINT 0x04 359#define CLRCMDINT 0x02 360#define CLRSEQINT 0x01 361 | 426#define BRKADRINT 0x08 427#define SCSIINT 0x04 428#define CMDCMPLT 0x02 429#define SEQINT 0x01 430#define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) 431 432/* 433 * Hard Error (p. 3-53) --- 11 unchanged lines hidden (view full) --- 445 * Clear Interrupt Status (p. 3-52) 446 */ 447#define CLRINT 0x092 448#define CLRBRKADRINT 0x08 449#define CLRSCSIINT 0x04 450#define CLRCMDINT 0x02 451#define CLRSEQINT 0x01 452 |
| 453#define DFCNTRL 0x093 454#define WIDEODD 0x40 455#define SCSIEN 0x20 456#define SDMAEN 0x10 457#define SDMAENACK 0x10 458#define HDMAEN 0x08 459#define HDMAENACK 0x08 460#define DIRECTION 0x04 461#define FIFOFLUSH 0x02 462#define FIFORESET 0x01 463 464#define DFSTATUS 0x094 465#define HDONE 0x08 466#define FIFOEMP 0x01 467 468#define DFDAT 0x099 469 |
|
| 362/* 363 * SCB Auto Increment (p. 3-59) 364 * Byte offset into the SCB Array and an optional bit to allow auto 365 * incrementing of the address during download and upload operations 366 */ 367#define SCBCNT 0x09a 368#define SCBAUTO 0x80 369#define SCBCNT_MASK 0x1f --- 17 unchanged lines hidden (view full) --- 387#define QOUTFIFO 0x09d 388 389/* 390 * Queue Out Count (p. 3-61) 391 * Number of queued SCBs in the Out FIFO 392 */ 393#define QOUTCNT 0x09e 394 | 470/* 471 * SCB Auto Increment (p. 3-59) 472 * Byte offset into the SCB Array and an optional bit to allow auto 473 * incrementing of the address during download and upload operations 474 */ 475#define SCBCNT 0x09a 476#define SCBAUTO 0x80 477#define SCBCNT_MASK 0x1f --- 17 unchanged lines hidden (view full) --- 495#define QOUTFIFO 0x09d 496 497/* 498 * Queue Out Count (p. 3-61) 499 * Number of queued SCBs in the Out FIFO 500 */ 501#define QOUTCNT 0x09e 502 |
| 503/* 504 * SCB Definition (p. 5-4) 505 * The two reserved bytes at SCBARRAY+1[23] are expected to be set to 506 * zero. Bit 3 in SCBARRAY+0 is used as an internal flag to indicate 507 * whether or not to DMA an SCB from host ram. This flag prevents the 508 * "re-fetching" of transactions that are requed because the target is 509 * busy with another command. We also use bits 6 & 7 to indicate whether 510 * or not to initiate SDTR or WDTR repectively when starting this command. 511 */ |
|
| 395#define SCBARRAY 0x0a0 | 512#define SCBARRAY 0x0a0 |
| 513#define SCB_CONTROL 0x0a0 514#define NEEDWDTR 0x80 515#define DISCENB 0x40 516#define TAG_ENB 0x20 517#define NEEDSDTR 0x10 518#define NEEDDMA 0x08 519#define DISCONNECTED 0x04 520#define SCB_TAG_TYPE 0x03 521#define SCB_TCL 0x0a1 522#define SCB_TARGET_STATUS 0x0a2 523#define SCB_SGCOUNT 0x0a3 524#define SCB_SGPTR 0x0a4 525#define SCB_SGPTR0 0x0a4 526#define SCB_SGPTR1 0x0a5 527#define SCB_SGPTR2 0x0a6 528#define SCB_SGPTR3 0x0a7 529#define SCB_RESID_SGCNT 0x0a8 530#define SCB_RESID_DCNT 0x0a9 531#define SCB_RESID_DCNT0 0x0a9 532#define SCB_RESID_DCNT1 0x0aa 533#define SCB_RESID_DCNT2 0x0ab 534#define SCB_DATAPTR 0x0ac 535#define SCB_DATAPTR0 0x0ac 536#define SCB_DATAPTR1 0x0ad 537#define SCB_DATAPTR2 0x0ae 538#define SCB_DATAPTR3 0x0af 539#define SCB_DATACNT 0x0b0 540#define SCB_DATACNT0 0x0b0 541#define SCB_DATACNT1 0x0b1 542#define SCB_DATACNT2 0x0b2 543/* UNUSED - QUAD PADDING 0x0b3 */ 544#define SCB_CMDPTR 0x0b4 545#define SCB_CMDPTR0 0x0b4 546#define SCB_CMDPTR1 0x0b5 547#define SCB_CMDPTR2 0x0b6 548#define SCB_CMDPTR3 0x0b7 549#define SCB_CMDLEN 0x0b8 550/* RESERVED - MUST BE ZERO 0x0b9 */ 551/* RESERVED - MUST BE ZERO 0x0ba */ 552#define SCB_NEXT_WAITING 0x0bb 553#define SCB_PHYSADDR 0x0bc 554#define SCB_PHYSADDR0 0x0bc 555#define SCB_PHYSADDR1 0x0bd 556#define SCB_PHYSADDR2 0x0be 557#define SCB_PHYSADDR3 0x0bf |
|
| 396 | 558 |
| 559#ifdef LINUX 560#define SG_SIZEOF 0x0c /* sizeof(struct scatterlist) */ 561#else 562#define SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 563#endif 564#define SCB_SIZEOF 0x1a /* sizeof SCB to DMA */ 565 |
|
| 397/* --------------------- AIC-7870-only definitions -------------------- */ 398 399#define DSPCISTATUS 0x086 400 401/* 402 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 403 * Controls the reading and writing of an external serial 1-bit 404 * EEPROM Device. In order to access the serial EEPROM, you must --- 24 unchanged lines hidden (view full) --- 429#define SEERDY 0x10 430#define SEECS 0x08 431#define SEECK 0x04 432#define SEEDO 0x02 433#define SEEDI 0x01 434 435/* ---------------------- Scratch RAM Offsets ------------------------- */ 436/* These offsets are either to values that are initialized by the board's | 566/* --------------------- AIC-7870-only definitions -------------------- */ 567 568#define DSPCISTATUS 0x086 569 570/* 571 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 572 * Controls the reading and writing of an external serial 1-bit 573 * EEPROM Device. In order to access the serial EEPROM, you must --- 24 unchanged lines hidden (view full) --- 598#define SEERDY 0x10 599#define SEECS 0x08 600#define SEECK 0x04 601#define SEEDO 0x02 602#define SEEDI 0x01 603 604/* ---------------------- Scratch RAM Offsets ------------------------- */ 605/* These offsets are either to values that are initialized by the board's |
| 437 * BIOS or are specified by the Linux sequencer code. If I can figure out 438 * how to read the EISA configuration info at probe time, the cards could 439 * be run without BIOS support installed | 606 * BIOS or are specified by the sequencer code. 607 * 608 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 609 * device information, 32-33 and 5a-5f as well. As it turns out, the 610 * BIOS trashes 20-2f, writing the synchronous negotiation results 611 * on top of the BIOS values, so we re-use those for our per-target 612 * scratchspace (actually a value that can be copied directly into 613 * SCSIRATE). The kernel driver will enable synchronous negotiation 614 * for all targets that have a value other than 0 in the lower four 615 * bits of the target scratch space. This should work regardless of 616 * whether the bios has been installed. |
| 440 */ 441 442/* 443 * 1 byte per target starting at this address for configuration values 444 */ | 617 */ 618 619/* 620 * 1 byte per target starting at this address for configuration values 621 */ |
| 445#define HA_TARG_SCRATCH 0x020 | 622#define TARG_SCRATCH 0x020 |
| 446 447/* 448 * The sequencer will stick the frist byte of any rejected message here so 449 * we can see what is getting thrown away. 450 */ | 623 624/* 625 * The sequencer will stick the frist byte of any rejected message here so 626 * we can see what is getting thrown away. 627 */ |
| 451#define HA_REJBYTE 0x031 | 628#define REJBYTE 0x031 |
| 452 453/* 454 * Bit vector of targets that have disconnection disabled. 455 */ | 629 630/* 631 * Bit vector of targets that have disconnection disabled. 632 */ |
| 456#define HA_DISC_DSB 0x032 | 633#define DISC_DSB 0x032 634#define DISC_DSB_A 0x032 635#define DISC_DSB_B 0x033 |
| 457 458/* 459 * Length of pending message 460 */ | 636 637/* 638 * Length of pending message 639 */ |
| 461#define HA_MSG_LEN 0x034 | 640#define MSG_LEN 0x034 |
| 462 | 641 |
| 463/* 464 * message body 465 */ 466#define HA_MSG_START 0x035 /* outgoing message body */ | 642#define MSG0 0x035 643#define COMP_MSG0 0xcb /* 2's complement of MSG0 */ 644#define MSG1 0x036 645#define MSG2 0x037 646#define MSG3 0x038 647#define MSG4 0x039 648#define MSG5 0x03a |
| 467 468/* 469 * These are offsets into the card's scratch ram. Some of the values are 470 * specified in the AHA2742 technical reference manual and are initialized 471 * by the BIOS at boot time. 472 */ | 649 650/* 651 * These are offsets into the card's scratch ram. Some of the values are 652 * specified in the AHA2742 technical reference manual and are initialized 653 * by the BIOS at boot time. 654 */ |
| 473#define HA_ARG_1 0x04a 474#define HA_RETURN_1 0x04a | 655#define ARG_1 0x04a 656#define RETURN_1 0x04a |
| 475#define SEND_SENSE 0x80 476#define SEND_WDTR 0x80 477#define SEND_SDTR 0x80 478#define SEND_REJ 0x40 479 | 657#define SEND_SENSE 0x80 658#define SEND_WDTR 0x80 659#define SEND_SDTR 0x80 660#define SEND_REJ 0x40 661 |
| 662#define SIGSTATE 0x04b 663 664#define DMAPARAMS 0x04c /* Parameters for DMA Logic */ 665 |
|
| 480#define SG_COUNT 0x04d | 666#define SG_COUNT 0x04d |
| 481#define SG_NEXT 0x04e 482#define HA_SIGSTATE 0x04b | 667#define SG_NEXT 0x04e /* working value of SG pointer */ 668#define SG_NEXT0 0x04e 669#define SG_NEXT1 0x04f 670#define SG_NEXT2 0x050 671#define SG_NEXT3 0x051 |
| 483 | 672 |
| 484#define HA_SCBCOUNT 0x052 485#define HA_FLAGS 0x053 | 673#define SCBCOUNT 0x052 /* 674 * Number of SCBs supported by 675 * this card. 676 */ 677#define FLAGS 0x053 |
| 486#define SINGLE_BUS 0x00 487#define TWIN_BUS 0x01 488#define WIDE_BUS 0x02 | 678#define SINGLE_BUS 0x00 679#define TWIN_BUS 0x01 680#define WIDE_BUS 0x02 |
| 489#define ACTIVE_MSG 0x20 | 681#define DPHASE 0x04 682#define MAXOFFSET 0x08 |
| 490#define IDENTIFY_SEEN 0x40 | 683#define IDENTIFY_SEEN 0x40 |
| 491#define RESELECTING 0x80 | 684#define RESELECTED 0x80 |
| 492 | 685 |
| 493#define HA_ACTIVE0 0x054 494#define HA_ACTIVE1 0x055 495#define SAVED_TCL 0x056 496#define WAITING_SCBH 0x057 497#define WAITING_SCBT 0x058 | 686#define ACTIVE_A 0x054 687#define ACTIVE_B 0x055 688#define SAVED_TCL 0x056 /* 689 * Temporary storage for the 690 * target/channel/lun of a 691 * reconnecting target 692 */ 693#define WAITING_SCBH 0x057 /* 694 * head of list of SCBs awaiting 695 * selection 696 */ 697#define WAITING_SCBT 0x058 /* 698 * tail of list of SCBs awaiting 699 * selection 700 */ 701#define COMP_SCBCOUNT 0x059 702#define SCB_LIST_NULL 0xff |
| 498 | 703 |
| 499#define HA_SCSICONF 0x05a 500#define HA_HOSTCONF 0x05d | 704#define SCSICONF 0x05a 705#define HOSTCONF 0x05d |
| 501 502#define HA_274_BIOSCTRL 0x05f 503#define BIOSMODE 0x30 504#define BIOSDISABLED 0x30 505 | 706 707#define HA_274_BIOSCTRL 0x05f 708#define BIOSMODE 0x30 709#define BIOSDISABLED 0x30 710 |
| 711/* Message codes */ 712#define MSG_EXTENDED 0x01 713#define MSG_SDTR 0x01 714#define MSG_WDTR 0x03 715#define MSG_SDPTRS 0x02 716#define MSG_RDPTRS 0x03 717#define MSG_DISCONNECT 0x04 718#define MSG_INITIATOR_DET_ERROR 0x05 |
|
| 506#define MSG_ABORT 0x06 | 719#define MSG_ABORT 0x06 |
| 720#define MSG_REJECT 0x07 721#define MSG_NOP 0x08 722#define MSG_MSG_PARITY_ERROR 0x09 |
|
| 507#define MSG_BUS_DEVICE_RESET 0x0c | 723#define MSG_BUS_DEVICE_RESET 0x0c |
| 724#define MSG_SIMPLE_TAG 0x20 725#define MSG_IDENTIFY 0x80 726 727/* WDTR Message values */ |
|
| 508#define BUS_8_BIT 0x00 509#define BUS_16_BIT 0x01 510#define BUS_32_BIT 0x02 511 | 728#define BUS_8_BIT 0x00 729#define BUS_16_BIT 0x01 730#define BUS_32_BIT 0x02 731 |
| 732#define MAX_OFFSET_8BIT 0x0f 733#define MAX_OFFSET_16BIT 0x08 |
|
| 512 513 514 | 734 735 736 |