aic79xx.reg (098ca2bda93c701c5331d4e6aace072495b4caaa) aic79xx.reg (17d2475554610175f0673ee69aa703ce3972909b)
1/*-
1/*
2 * Aic79xx register and scratch ram definitions.
3 *
2 * Aic79xx register and scratch ram definitions.
3 *
4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.

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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $FreeBSD$
41 */
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.

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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $FreeBSD$
41 */
42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $"
42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#34 $"
43
44/*
45 * This file is processed by the aic7xxx_asm utility for use in assembling
46 * firmware for the aic79xx family of SCSI host adapters as well as to generate
47 * a C header file for use in the kernel portion of the Aic79xx driver.
48 */
49
50/* Register window Modes */
51#define M_DFF0 0
52#define M_DFF1 1
53#define M_CCHAN 2
54#define M_SCSI 3
55#define M_CFG 4
56#define M_DST_SHIFT 4
57
58#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
43
44/*
45 * This file is processed by the aic7xxx_asm utility for use in assembling
46 * firmware for the aic79xx family of SCSI host adapters as well as to generate
47 * a C header file for use in the kernel portion of the Aic79xx driver.
48 */
49
50/* Register window Modes */
51#define M_DFF0 0
52#define M_DFF1 1
53#define M_CCHAN 2
54#define M_SCSI 3
55#define M_CFG 4
56#define M_DST_SHIFT 4
57
58#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
59#define SET_MODE(src, dst) \
60 SET_SRC_MODE src; \
61 SET_DST_MODE dst; \
62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
63 mvi MK_MODE(src, dst) call set_mode_work_around; \
64 } else { \
65 mvi MODE_PTR, MK_MODE(src, dst); \
66 }
59#define SET_MODE(src, dst) \
60 SET_SRC_MODE src; \
61 SET_DST_MODE dst; \
62 mvi MK_MODE(src, dst) call set_mode_work_around
67
63
68#define RESTORE_MODE(mode) \
69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
70 mov mode call set_mode_work_around; \
71 } else { \
72 mov MODE_PTR, mode; \
73 }
74
75#define SET_SEQINTCODE(code) \
76 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
77 mvi code call set_seqint_work_around; \
78 } else { \
79 mvi SEQINTCODE, code; \
80 }
81
82/*
83 * Mode Pointer
84 * Controls which of the 5, 512byte, address spaces should be used
85 * as the source and destination of any register accesses in our
86 * register window.
87 */
88register MODE_PTR {
89 address 0x000
90 access_mode RW
64/*
65 * Mode Pointer
66 * Controls which of the 5, 512byte, address spaces should be used
67 * as the source and destination of any register accesses in our
68 * register window.
69 */
70register MODE_PTR {
71 address 0x000
72 access_mode RW
91 field DST_MODE 0x70
92 field SRC_MODE 0x07
73 mask DST_MODE 0x70
74 mask SRC_MODE 0x07
93 mode_pointer
94}
95
96const SRC_MODE_SHIFT 0
97const DST_MODE_SHIFT 4
98
99/*
100 * Host Interrupt Status
101 */
102register INTSTAT {
103 address 0x001
104 access_mode RW
75 mode_pointer
76}
77
78const SRC_MODE_SHIFT 0
79const DST_MODE_SHIFT 4
80
81/*
82 * Host Interrupt Status
83 */
84register INTSTAT {
85 address 0x001
86 access_mode RW
105 field HWERRINT 0x80
106 field BRKADRINT 0x40
107 field SWTMINT 0x20
108 field PCIINT 0x10
109 field SCSIINT 0x08
110 field SEQINT 0x04
111 field CMDCMPLT 0x02
112 field SPLTINT 0x01
87 bit HWERRINT 0x80
88 bit BRKADRINT 0x40
89 bit SWTMINT 0x20
90 bit PCIINT 0x10
91 bit SCSIINT 0x08
92 bit SEQINT 0x04
93 bit CMDCMPLT 0x02
94 bit SPLTINT 0x01
113 mask INT_PEND 0xFF
114}
115
116/*
117 * Sequencer Interrupt Code
118 */
119register SEQINTCODE {
120 address 0x002
121 access_mode RW
95 mask INT_PEND 0xFF
96}
97
98/*
99 * Sequencer Interrupt Code
100 */
101register SEQINTCODE {
102 address 0x002
103 access_mode RW
122 field {
123 NO_SEQINT, /* No seqint pending. */
124 BAD_PHASE, /* unknown scsi bus phase */
125 SEND_REJECT, /* sending a message reject */
126 PROTO_VIOLATION, /* Protocol Violation */
127 NO_MATCH, /* no cmd match for reconnect */
128 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */
129 PDATA_REINIT, /*
104 mask BAD_PHASE 1 /* unknown scsi bus phase */
105 mask SEND_REJECT 2 /* sending a message reject */
106 mask PROTO_VIOLATION 3 /* Protocol Violation */
107 mask NO_MATCH 4 /* no cmd match for reconnect */
108 mask IGN_WIDE_RES 5 /* Complex IGN Wide Res Msg */
109 mask PDATA_REINIT 6 /*
130 * Returned to data phase
131 * that requires data
132 * transfer pointers to be
133 * recalculated from the
134 * transfer residual.
135 */
110 * Returned to data phase
111 * that requires data
112 * transfer pointers to be
113 * recalculated from the
114 * transfer residual.
115 */
136 HOST_MSG_LOOP, /*
116 mask HOST_MSG_LOOP 7 /*
137 * The bus is ready for the
138 * host to perform another
139 * message transaction. This
140 * mechanism is used for things
141 * like sync/wide negotiation
142 * that require a kernel based
143 * message state engine.
144 */
117 * The bus is ready for the
118 * host to perform another
119 * message transaction. This
120 * mechanism is used for things
121 * like sync/wide negotiation
122 * that require a kernel based
123 * message state engine.
124 */
145 BAD_STATUS, /* Bad status from target */
146 DATA_OVERRUN, /*
125 mask BAD_STATUS 8 /* Bad status from target */
126 mask DATA_OVERRUN 9 /*
147 * Target attempted to write
148 * beyond the bounds of its
149 * command.
150 */
127 * Target attempted to write
128 * beyond the bounds of its
129 * command.
130 */
151 MKMSG_FAILED, /*
131 mask MKMSG_FAILED 10 /*
152 * Target completed command
153 * without honoring our ATN
154 * request to issue a message.
155 */
132 * Target completed command
133 * without honoring our ATN
134 * request to issue a message.
135 */
156 MISSED_BUSFREE, /*
136 mask MISSED_BUSFREE 11 /*
157 * The sequencer never saw
158 * the bus go free after
159 * either a command complete
160 * or disconnect message.
161 */
137 * The sequencer never saw
138 * the bus go free after
139 * either a command complete
140 * or disconnect message.
141 */
162 DUMP_CARD_STATE,
163 ILLEGAL_PHASE,
164 INVALID_SEQINT,
165 CFG4ISTAT_INTR,
166 STATUS_OVERRUN,
167 CFG4OVERRUN,
168 ENTERING_NONPACK,
169 TASKMGMT_FUNC_COMPLETE, /*
170 * Task management function
171 * request completed with
172 * an expected busfree.
142 mask SCB_MISMATCH 12 /*
143 * Downloaded SCB's tag does
144 * not match the entry we
145 * intended to download.
173 */
146 */
174 TASKMGMT_CMD_CMPLT_OKAY, /*
175 * A command with a non-zero
176 * task management function
177 * has completed via the normal
178 * command completion method
179 * for commands with a zero
180 * task management function.
181 * This happens when an attempt
182 * to abort a command loses
183 * the race for the command to
184 * complete normally.
147 mask NO_FREE_SCB 13 /*
148 * get_free_or_disc_scb failed.
185 */
149 */
186 TRACEPOINT0,
187 TRACEPOINT1,
188 TRACEPOINT2,
189 TRACEPOINT3,
190 SAW_HWERR,
191 BAD_SCB_STATUS
192 }
150 mask OUT_OF_RANGE 14
151 mask NO_FREE_FIFO 15
152 mask DUMP_CARD_STATE 16
153 mask ILLEGAL_PHASE 17
154 mask INVALID_SEQINT 18
155 mask CFG4ISTAT_INTR 19
156 mask STATUS_OVERRUN 20
157 mask CFG4OVERRUN 21
158 mask SNAPSHOTCLRCHN 22
159 mask MONITORDRAIN 23
160 mask ENTERING_NONPACK 24
161 mask PCIX_ARBITOR_WW 25
193}
194
195/*
196 * Clear Host Interrupt
197 */
198register CLRINT {
199 address 0x003
200 access_mode WO
162}
163
164/*
165 * Clear Host Interrupt
166 */
167register CLRINT {
168 address 0x003
169 access_mode WO
201 field CLRHWERRINT 0x80 /* Rev B or greater */
202 field CLRBRKADRINT 0x40
203 field CLRSWTMINT 0x20
204 field CLRPCIINT 0x10
205 field CLRSCSIINT 0x08
206 field CLRSEQINT 0x04
207 field CLRCMDINT 0x02
208 field CLRSPLTINT 0x01
170 bit CLRBRKADRINT 0x40
171 bit CLRSWTMINT 0x20
172 bit CLRSCSIINT 0x08
173 bit CLRSEQINT 0x04
174 bit CLRCMDINT 0x02
175 bit CLRSPLTINT 0x01
209}
210
211/*
212 * Error Register
213 */
214register ERROR {
215 address 0x004
216 access_mode RO
176}
177
178/*
179 * Error Register
180 */
181register ERROR {
182 address 0x004
183 access_mode RO
217 field CIOPARERR 0x80
218 field CIOACCESFAIL 0x40 /* Rev B or greater */
219 field MPARERR 0x20
220 field DPARERR 0x10
221 field SQPARERR 0x08
222 field ILLOPCODE 0x04
223 field DSCTMOUT 0x02
184 bit CIOPARERR 0x80
185 bit MPARERR 0x20
186 bit DPARERR 0x10
187 bit SQPARERR 0x08
188 bit ILLOPCODE 0x04
189 bit DSCTMOUT 0x02
224}
225
226/*
227 * Clear Error
228 */
229register CLRERR {
230 address 0x004
231 access_mode WO
190}
191
192/*
193 * Clear Error
194 */
195register CLRERR {
196 address 0x004
197 access_mode WO
232 field CLRCIOPARERR 0x80
233 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */
234 field CLRMPARERR 0x20
235 field CLRDPARERR 0x10
236 field CLRSQPARERR 0x08
237 field CLRILLOPCODE 0x04
238 field CLRDSCTMOUT 0x02
198 bit CLRCIOPARERR 0x80
199 bit CLRMPARERR 0x20
200 bit CLRDPARERR 0x10
201 bit CLRSQPARERR 0x08
202 bit CLRILLOPCODE 0x04
203 bit CLRDSCTMOUT 0x02
239}
240
241/*
242 * Host Control Register
243 * Overall host control of the device.
244 */
245register HCNTRL {
246 address 0x005
247 access_mode RW
204}
205
206/*
207 * Host Control Register
208 * Overall host control of the device.
209 */
210register HCNTRL {
211 address 0x005
212 access_mode RW
248 field SEQ_RESET 0x80 /* Rev B or greater */
249 field POWRDN 0x40
250 field SWINT 0x10
251 field SWTIMER_START_B 0x08 /* Rev B or greater */
252 field PAUSE 0x04
253 field INTEN 0x02
254 field CHIPRST 0x01
255 field CHIPRSTACK 0x01
213 bit POWRDN 0x40
214 bit SWINT 0x10
215 bit HCNTRL3 0x08
216 bit PAUSE 0x04
217 bit INTEN 0x02
218 bit CHIPRST 0x01
219 bit CHIPRSTACK 0x01
256}
257
258/*
259 * Host New SCB Queue Offset
260 */
261register HNSCB_QOFF {
262 address 0x006
263 access_mode RW

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271 address 0x008
272 access_mode RW
273}
274
275/*
276 * Host Mailbox
277 */
278register HS_MAILBOX {
220}
221
222/*
223 * Host New SCB Queue Offset
224 */
225register HNSCB_QOFF {
226 address 0x006
227 access_mode RW

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235 address 0x008
236 access_mode RW
237}
238
239/*
240 * Host Mailbox
241 */
242register HS_MAILBOX {
279 address 0x00B
243 address 0x0B
280 access_mode RW
281 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
244 access_mode RW
245 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
282 mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */
283}
284
285/*
286 * Sequencer Interupt Status
287 */
288register SEQINTSTAT {
246}
247
248/*
249 * Sequencer Interupt Status
250 */
251register SEQINTSTAT {
289 address 0x00C
252 address 0x0C
290 access_mode RO
253 access_mode RO
291 field SEQ_SWTMRTO 0x10
292 field SEQ_SEQINT 0x08
293 field SEQ_SCSIINT 0x04
294 field SEQ_PCIINT 0x02
295 field SEQ_SPLTINT 0x01
254 bit SEQ_SWTMRTO 0x10
255 bit SEQ_SEQINT 0x08
256 bit SEQ_SCSIINT 0x04
257 bit SEQ_PCIINT 0x02
258 bit SEQ_SPLTINT 0x01
296}
297
298/*
299 * Clear SEQ Interrupt
300 */
301register CLRSEQINTSTAT {
259}
260
261/*
262 * Clear SEQ Interrupt
263 */
264register CLRSEQINTSTAT {
302 address 0x00C
265 address 0x0C0
303 access_mode WO
266 access_mode WO
304 field CLRSEQ_SWTMRTO 0x10
305 field CLRSEQ_SEQINT 0x08
306 field CLRSEQ_SCSIINT 0x04
307 field CLRSEQ_PCIINT 0x02
308 field CLRSEQ_SPLTINT 0x01
267 bit CLRSEQ_SWTMRTO 0x10
268 bit CLRSEQ_SEQINT 0x08
269 bit CLRSEQ_SCSIINT 0x04
270 bit CLRSEQ_PCIINT 0x02
271 bit CLRSEQ_SPLTINT 0x01
309}
310
311/*
312 * Software Timer
313 */
314register SWTIMER {
272}
273
274/*
275 * Software Timer
276 */
277register SWTIMER {
315 address 0x00E
278 address 0x0E0
316 access_mode RW
317 size 2
318}
319
320/*
321 * SEQ New SCB Queue Offset
322 */
323register SNSCB_QOFF {

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348
349/*
350 * Queue Offset Control & Status
351 */
352register QOFF_CTLSTA {
353 address 0x016
354 access_mode RW
355 modes M_CCHAN
279 access_mode RW
280 size 2
281}
282
283/*
284 * SEQ New SCB Queue Offset
285 */
286register SNSCB_QOFF {

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311
312/*
313 * Queue Offset Control & Status
314 */
315register QOFF_CTLSTA {
316 address 0x016
317 access_mode RW
318 modes M_CCHAN
356 field EMPTY_SCB_AVAIL 0x80
357 field NEW_SCB_AVAIL 0x40
358 field SDSCB_ROLLOVR 0x20
359 field HS_MAILBOX_ACT 0x10
360 field SCB_QSIZE 0x0F {
361 SCB_QSIZE_4,
362 SCB_QSIZE_8,
363 SCB_QSIZE_16,
364 SCB_QSIZE_32,
365 SCB_QSIZE_64,
366 SCB_QSIZE_128,
367 SCB_QSIZE_256,
368 SCB_QSIZE_512,
369 SCB_QSIZE_1024,
370 SCB_QSIZE_2048,
371 SCB_QSIZE_4096,
372 SCB_QSIZE_8192,
373 SCB_QSIZE_16384
374 }
319 bit EMPTY_SCB_AVAIL 0x80
320 bit NEW_SCB_AVAIL 0x40
321 bit SDSCB_ROLLOVR 0x20
322 bit HS_MAILBOX_ACT 0x10
323 mask SCB_QSIZE 0x0F
324 mask SCB_QSIZE_4 0x00
325 mask SCB_QSIZE_8 0x01
326 mask SCB_QSIZE_16 0x02
327 mask SCB_QSIZE_32 0x03
328 mask SCB_QSIZE_64 0x04
329 mask SCB_QSIZE_128 0x05
330 mask SCB_QSIZE_256 0x06
331 mask SCB_QSIZE_512 0x07
332 mask SCB_QSIZE_1024 0x08
333 mask SCB_QSIZE_2048 0x09
334 mask SCB_QSIZE_4096 0x0A
335 mask SCB_QSIZE_8192 0x0B
336 mask SCB_QSIZE_16384 0x0C
375}
376
377/*
378 * Interrupt Control
379 */
380register INTCTL {
381 address 0x018
382 access_mode RW
337}
338
339/*
340 * Interrupt Control
341 */
342register INTCTL {
343 address 0x018
344 access_mode RW
383 field SWTMINTMASK 0x80
384 field SWTMINTEN 0x40
385 field SWTIMER_START 0x20
386 field AUTOCLRCMDINT 0x10
387 field PCIINTEN 0x08
388 field SCSIINTEN 0x04
389 field SEQINTEN 0x02
390 field SPLTINTEN 0x01
345 bit SWTMINTMASK 0x80
346 bit SWTMINTEN 0x40
347 bit SWTIMER_START 0x20
348 bit AUTOCLRCMDINT 0x10
349 bit PCIINTEN 0x08
350 bit SCSIINTEN 0x04
351 bit SEQINTEN 0x02
352 bit SPLTINTEN 0x01
391}
392
393/*
394 * Data FIFO Control
395 */
396register DFCNTRL {
397 address 0x019
398 access_mode RW
399 modes M_DFF0, M_DFF1
353}
354
355/*
356 * Data FIFO Control
357 */
358register DFCNTRL {
359 address 0x019
360 access_mode RW
361 modes M_DFF0, M_DFF1
400 field PRELOADEN 0x80
401 field SCSIENWRDIS 0x40 /* Rev B only. */
402 field SCSIEN 0x20
403 field SCSIENACK 0x20
404 field HDMAEN 0x08
405 field HDMAENACK 0x08
406 field DIRECTION 0x04
407 field DIRECTIONACK 0x04
408 field FIFOFLUSH 0x02
409 field FIFOFLUSHACK 0x02
410 field DIRECTIONEN 0x01
362 bit PRELOADEN 0x80
363 bit SCSIEN 0x20
364 bit SCSIENACK 0x20
365 bit HDMAEN 0x08
366 bit HDMAENACK 0x08
367 bit DIRECTION 0x04
368 bit DIRECTIONACK 0x04
369 bit FIFOFLUSH 0x02
370 bit FIFOFLUSHACK 0x02
371 bit DIRECTIONEN 0x01
411}
412
413/*
414 * Device Space Command 0
415 */
416register DSCOMMAND0 {
417 address 0x019
418 access_mode RW
419 modes M_CFG
372}
373
374/*
375 * Device Space Command 0
376 */
377register DSCOMMAND0 {
378 address 0x019
379 access_mode RW
380 modes M_CFG
420 field CACHETHEN 0x80 /* Cache Threshold enable */
421 field DPARCKEN 0x40 /* Data Parity Check Enable */
422 field MPARCKEN 0x20 /* Memory Parity Check Enable */
423 field EXTREQLCK 0x10 /* External Request Lock */
424 field DISABLE_TWATE 0x02 /* Rev B or greater */
425 field CIOPARCKEN 0x01 /* Internal bus parity error enable */
381 bit CACHETHEN 0x80 /* Cache Threshold enable */
382 bit DPARCKEN 0x40 /* Data Parity Check Enable */
383 bit MPARCKEN 0x20 /* Memory Parity Check Enable */
384 bit EXTREQLCK 0x10 /* External Request Lock */
385 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */
426}
427
428/*
429 * Data FIFO Status
430 */
431register DFSTATUS {
432 address 0x01A
433 access_mode RO
434 modes M_DFF0, M_DFF1
386}
387
388/*
389 * Data FIFO Status
390 */
391register DFSTATUS {
392 address 0x01A
393 access_mode RO
394 modes M_DFF0, M_DFF1
435 field PRELOAD_AVAIL 0x80
436 field PKT_PRELOAD_AVAIL 0x40
437 field MREQPEND 0x10
438 field HDONE 0x08
439 field DFTHRESH 0x04
440 field FIFOFULL 0x02
441 field FIFOEMP 0x01
395 bit PRELOAD_AVAIL 0x80
396 bit PKT_PRELOAD_AVAIL 0x40
397 bit MREQPEND 0x10
398 bit HDONE 0x08
399 bit DFTHRESH 0x04
400 bit FIFOFULL 0x02
401 bit FIFOEMP 0x01
442}
443
444/*
445 * S/G Cache Pointer
446 */
447register SG_CACHE_PRE {
448 address 0x01B
449 access_mode WO
450 modes M_DFF0, M_DFF1
402}
403
404/*
405 * S/G Cache Pointer
406 */
407register SG_CACHE_PRE {
408 address 0x01B
409 access_mode WO
410 modes M_DFF0, M_DFF1
451 field SG_ADDR_MASK 0xf8
452 field ODD_SEG 0x04
453 field LAST_SEG 0x02
411 mask SG_ADDR_MASK 0xf8
412 bit ODD_SEG 0x04
413 bit LAST_SEG 0x02
454}
455
456register SG_CACHE_SHADOW {
457 address 0x01B
458 access_mode RO
459 modes M_DFF0, M_DFF1
414}
415
416register SG_CACHE_SHADOW {
417 address 0x01B
418 access_mode RO
419 modes M_DFF0, M_DFF1
460 field SG_ADDR_MASK 0xf8
461 field ODD_SEG 0x04
462 field LAST_SEG 0x02
463 field LAST_SEG_DONE 0x01
420 mask SG_ADDR_MASK 0xf8
421 bit ODD_SEG 0x04
422 bit LAST_SEG 0x02
423 bit LAST_SEG_DONE 0x01
464}
465
466/*
467 * Arbiter Control
468 */
469register ARBCTL {
470 address 0x01B
471 access_mode RW
472 modes M_CFG
424}
425
426/*
427 * Arbiter Control
428 */
429register ARBCTL {
430 address 0x01B
431 access_mode RW
432 modes M_CFG
473 field RESET_HARB 0x80
474 field RETRY_SWEN 0x08
475 field USE_TIME 0x07
433 bit RESET_HARB 0x80
434 bit RETRY_SWEN 0x08
435 mask USE_TIME 0x07
476}
477
478/*
479 * Data Channel Host Address
480 */
481register HADDR {
482 address 0x070
483 access_mode RW

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491register HODMAADR {
492 address 0x070
493 access_mode RW
494 size 8
495 modes M_SCSI
496}
497
498/*
436}
437
438/*
439 * Data Channel Host Address
440 */
441register HADDR {
442 address 0x070
443 access_mode RW

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451register HODMAADR {
452 address 0x070
453 access_mode RW
454 size 8
455 modes M_SCSI
456}
457
458/*
499 * PCI PLL Delay.
500 */
501register PLLDELAY {
502 address 0x070
503 access_mode RW
504 size 1
505 modes M_CFG
506 field SPLIT_DROP_REQ 0x80
507}
508
509/*
510 * Data Channel Host Count
511 */
512register HCNT {
513 address 0x078
514 access_mode RW
515 size 3
516 modes M_DFF0, M_DFF1
517}

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575
576/*
577 * Data FIFO Threshold
578 */
579register DFF_THRSH {
580 address 0x088
581 access_mode RW
582 modes M_CFG
459 * Data Channel Host Count
460 */
461register HCNT {
462 address 0x078
463 access_mode RW
464 size 3
465 modes M_DFF0, M_DFF1
466}

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524
525/*
526 * Data FIFO Threshold
527 */
528register DFF_THRSH {
529 address 0x088
530 access_mode RW
531 modes M_CFG
583 field WR_DFTHRSH 0x70 {
584 WR_DFTHRSH_MIN,
585 WR_DFTHRSH_25,
586 WR_DFTHRSH_50,
587 WR_DFTHRSH_63,
588 WR_DFTHRSH_75,
589 WR_DFTHRSH_85,
590 WR_DFTHRSH_90,
591 WR_DFTHRSH_MAX
592 }
593 field RD_DFTHRSH 0x07 {
594 RD_DFTHRSH_MIN,
595 RD_DFTHRSH_25,
596 RD_DFTHRSH_50,
597 RD_DFTHRSH_63,
598 RD_DFTHRSH_75,
599 RD_DFTHRSH_85,
600 RD_DFTHRSH_90,
601 RD_DFTHRSH_MAX
602 }
532 mask WR_DFTHRSH 0x70
533 mask RD_DFTHRSH 0x07
534 mask RD_DFTHRSH_MIN 0x00
535 mask RD_DFTHRSH_25 0x01
536 mask RD_DFTHRSH_50 0x02
537 mask RD_DFTHRSH_63 0x03
538 mask RD_DFTHRSH_75 0x04
539 mask RD_DFTHRSH_85 0x05
540 mask RD_DFTHRSH_90 0x06
541 mask RD_DFTHRSH_MAX 0x07
542 mask WR_DFTHRSH_MIN 0x00
543 mask WR_DFTHRSH_25 0x10
544 mask WR_DFTHRSH_50 0x20
545 mask WR_DFTHRSH_63 0x30
546 mask WR_DFTHRSH_75 0x40
547 mask WR_DFTHRSH_85 0x50
548 mask WR_DFTHRSH_90 0x60
549 mask WR_DFTHRSH_MAX 0x70
603}
604
605/*
606 * ROM Address
607 */
608register ROMADDR {
609 address 0x08A
610 access_mode RW
611 size 3
612}
613
614/*
615 * ROM Control
616 */
617register ROMCNTRL {
618 address 0x08D
619 access_mode RW
550}
551
552/*
553 * ROM Address
554 */
555register ROMADDR {
556 address 0x08A
557 access_mode RW
558 size 3
559}
560
561/*
562 * ROM Control
563 */
564register ROMCNTRL {
565 address 0x08D
566 access_mode RW
620 field ROMOP 0xE0
621 field ROMSPD 0x18
622 field REPEAT 0x02
623 field RDY 0x01
567 mask ROMOP 0xE0
568 mask ROMSPD 0x18
569 bit REPEAT 0x02
570 bit RDY 0x01
624}
625
626/*
627 * ROM Data
628 */
629register ROMDATA {
630 address 0x08E
631 access_mode RW
632}
633
634/*
635 * Data Channel Receive Message 0
636 */
637register DCHRXMSG0 {
638 address 0x090
639 access_mode RO
640 modes M_DFF0, M_DFF1
571}
572
573/*
574 * ROM Data
575 */
576register ROMDATA {
577 address 0x08E
578 access_mode RW
579}
580
581/*
582 * Data Channel Receive Message 0
583 */
584register DCHRXMSG0 {
585 address 0x090
586 access_mode RO
587 modes M_DFF0, M_DFF1
641 field CDNUM 0xF8
642 field CFNUM 0x07
588 mask CDNUM 0xF8
589 mask CFNUM 0x07
643}
644
645/*
646 * CMC Recieve Message 0
647 */
648register CMCRXMSG0 {
649 address 0x090
650 access_mode RO
651 modes M_CCHAN
590}
591
592/*
593 * CMC Recieve Message 0
594 */
595register CMCRXMSG0 {
596 address 0x090
597 access_mode RO
598 modes M_CCHAN
652 field CDNUM 0xF8
653 field CFNUM 0x07
599 mask CDNUM 0xF8
600 mask CFNUM 0x07
654}
655
656/*
657 * Overlay Recieve Message 0
658 */
659register OVLYRXMSG0 {
660 address 0x090
661 access_mode RO
662 modes M_SCSI
601}
602
603/*
604 * Overlay Recieve Message 0
605 */
606register OVLYRXMSG0 {
607 address 0x090
608 access_mode RO
609 modes M_SCSI
663 field CDNUM 0xF8
664 field CFNUM 0x07
610 mask CDNUM 0xF8
611 mask CFNUM 0x07
665}
666
667/*
668 * Relaxed Order Enable
669 */
670register ROENABLE {
671 address 0x090
672 access_mode RW
673 modes M_CFG
612}
613
614/*
615 * Relaxed Order Enable
616 */
617register ROENABLE {
618 address 0x090
619 access_mode RW
620 modes M_CFG
674 field MSIROEN 0x20
675 field OVLYROEN 0x10
676 field CMCROEN 0x08
677 field SGROEN 0x04
678 field DCH1ROEN 0x02
679 field DCH0ROEN 0x01
621 bit MSIROEN 0x20
622 bit OVLYROEN 0x10
623 bit CMCROEN 0x08
624 bit SGROEN 0x04
625 bit DCH1ROEN 0x02
626 bit DCH0ROEN 0x01
680}
681
682/*
683 * Data Channel Receive Message 1
684 */
685register DCHRXMSG1 {
686 address 0x091
687 access_mode RO
688 modes M_DFF0, M_DFF1
627}
628
629/*
630 * Data Channel Receive Message 1
631 */
632register DCHRXMSG1 {
633 address 0x091
634 access_mode RO
635 modes M_DFF0, M_DFF1
689 field CBNUM 0xFF
636 mask CBNUM 0xFF
690}
691
692/*
693 * CMC Recieve Message 1
694 */
695register CMCRXMSG1 {
696 address 0x091
697 access_mode RO
698 modes M_CCHAN
637}
638
639/*
640 * CMC Recieve Message 1
641 */
642register CMCRXMSG1 {
643 address 0x091
644 access_mode RO
645 modes M_CCHAN
699 field CBNUM 0xFF
646 mask CBNUM 0xFF
700}
701
702/*
703 * Overlay Recieve Message 1
704 */
705register OVLYRXMSG1 {
706 address 0x091
707 access_mode RO
708 modes M_SCSI
647}
648
649/*
650 * Overlay Recieve Message 1
651 */
652register OVLYRXMSG1 {
653 address 0x091
654 access_mode RO
655 modes M_SCSI
709 field CBNUM 0xFF
656 mask CBNUM 0xFF
710}
711
712/*
713 * No Snoop Enable
714 */
715register NSENABLE {
716 address 0x091
717 access_mode RW
718 modes M_CFG
657}
658
659/*
660 * No Snoop Enable
661 */
662register NSENABLE {
663 address 0x091
664 access_mode RW
665 modes M_CFG
719 field MSINSEN 0x20
720 field OVLYNSEN 0x10
721 field CMCNSEN 0x08
722 field SGNSEN 0x04
723 field DCH1NSEN 0x02
724 field DCH0NSEN 0x01
666 bit MSINSEN 0x20
667 bit OVLYNSEN 0x10
668 bit CMCNSEN 0x08
669 bit SGNSEN 0x04
670 bit DCH1NSEN 0x02
671 bit DCH0NSEN 0x01
725}
726
727/*
728 * Data Channel Receive Message 2
729 */
730register DCHRXMSG2 {
731 address 0x092
732 access_mode RO
733 modes M_DFF0, M_DFF1
672}
673
674/*
675 * Data Channel Receive Message 2
676 */
677register DCHRXMSG2 {
678 address 0x092
679 access_mode RO
680 modes M_DFF0, M_DFF1
734 field MINDEX 0xFF
681 mask MINDEX 0xFF
735}
736
737/*
738 * CMC Recieve Message 2
739 */
740register CMCRXMSG2 {
741 address 0x092
742 access_mode RO
743 modes M_CCHAN
682}
683
684/*
685 * CMC Recieve Message 2
686 */
687register CMCRXMSG2 {
688 address 0x092
689 access_mode RO
690 modes M_CCHAN
744 field MINDEX 0xFF
691 mask MINDEX 0xFF
745}
746
747/*
748 * Overlay Recieve Message 2
749 */
750register OVLYRXMSG2 {
751 address 0x092
752 access_mode RO
753 modes M_SCSI
692}
693
694/*
695 * Overlay Recieve Message 2
696 */
697register OVLYRXMSG2 {
698 address 0x092
699 access_mode RO
700 modes M_SCSI
754 field MINDEX 0xFF
701 mask MINDEX 0xFF
755}
756
757/*
758 * Outstanding Split Transactions
759 */
760register OST {
761 address 0x092
762 access_mode RW
763 modes M_CFG
764}
765
766/*
767 * Data Channel Receive Message 3
768 */
769register DCHRXMSG3 {
770 address 0x093
771 access_mode RO
772 modes M_DFF0, M_DFF1
702}
703
704/*
705 * Outstanding Split Transactions
706 */
707register OST {
708 address 0x092
709 access_mode RW
710 modes M_CFG
711}
712
713/*
714 * Data Channel Receive Message 3
715 */
716register DCHRXMSG3 {
717 address 0x093
718 access_mode RO
719 modes M_DFF0, M_DFF1
773 field MCLASS 0x0F
720 mask MCLASS 0x0F
774}
775
776/*
777 * CMC Recieve Message 3
778 */
779register CMCRXMSG3 {
780 address 0x093
781 access_mode RO
782 modes M_CCHAN
721}
722
723/*
724 * CMC Recieve Message 3
725 */
726register CMCRXMSG3 {
727 address 0x093
728 access_mode RO
729 modes M_CCHAN
783 field MCLASS 0x0F
730 mask MCLASS 0x0F
784}
785
786/*
787 * Overlay Recieve Message 3
788 */
789register OVLYRXMSG3 {
790 address 0x093
791 access_mode RO
792 modes M_SCSI
731}
732
733/*
734 * Overlay Recieve Message 3
735 */
736register OVLYRXMSG3 {
737 address 0x093
738 access_mode RO
739 modes M_SCSI
793 field MCLASS 0x0F
740 mask MCLASS 0x0F
794}
795
796/*
797 * PCI-X Control
798 */
799register PCIXCTL {
800 address 0x093
801 access_mode RW
802 modes M_CFG
741}
742
743/*
744 * PCI-X Control
745 */
746register PCIXCTL {
747 address 0x093
748 access_mode RW
749 modes M_CFG
803 field SERRPULSE 0x80
804 field UNEXPSCIEN 0x20
805 field SPLTSMADIS 0x10
806 field SPLTSTADIS 0x08
807 field SRSPDPEEN 0x04
808 field TSCSERREN 0x02
809 field CMPABCDIS 0x01
750 bit SERRPULSE 0x80
751 bit UNEXPSCIEN 0x20
752 bit SPLTSMADIS 0x10
753 bit SPLTSTADIS 0x08
754 bit SRSPDPEEN 0x04
755 bit TSCSERREN 0x02
756 bit CMPABCDIS 0x01
810}
811
812/*
813 * CMC Sequencer Byte Count
814 */
815register CMCSEQBCNT {
816 address 0x094
817 access_mode RO

--- 21 unchanged lines hidden (view full) ---

839
840/*
841 * Data Channel Split Status 0
842 */
843register DCHSPLTSTAT0 {
844 address 0x096
845 access_mode RW
846 modes M_DFF0, M_DFF1
757}
758
759/*
760 * CMC Sequencer Byte Count
761 */
762register CMCSEQBCNT {
763 address 0x094
764 access_mode RO

--- 21 unchanged lines hidden (view full) ---

786
787/*
788 * Data Channel Split Status 0
789 */
790register DCHSPLTSTAT0 {
791 address 0x096
792 access_mode RW
793 modes M_DFF0, M_DFF1
847 field STAETERM 0x80
848 field SCBCERR 0x40
849 field SCADERR 0x20
850 field SCDATBUCKET 0x10
851 field CNTNOTCMPLT 0x08
852 field RXOVRUN 0x04
853 field RXSCEMSG 0x02
854 field RXSPLTRSP 0x01
794 bit STAETERM 0x80
795 bit SCBCERR 0x40
796 bit SCADERR 0x20
797 bit SCDATBUCKET 0x10
798 bit CNTNOTCMPLT 0x08
799 bit RXOVRUN 0x04
800 bit RXSCEMSG 0x02
801 bit RXSPLTRSP 0x01
855}
856
857/*
858 * CMC Split Status 0
859 */
860register CMCSPLTSTAT0 {
861 address 0x096
862 access_mode RW
863 modes M_CCHAN
802}
803
804/*
805 * CMC Split Status 0
806 */
807register CMCSPLTSTAT0 {
808 address 0x096
809 access_mode RW
810 modes M_CCHAN
864 field STAETERM 0x80
865 field SCBCERR 0x40
866 field SCADERR 0x20
867 field SCDATBUCKET 0x10
868 field CNTNOTCMPLT 0x08
869 field RXOVRUN 0x04
870 field RXSCEMSG 0x02
871 field RXSPLTRSP 0x01
811 bit STAETERM 0x80
812 bit SCBCERR 0x40
813 bit SCADERR 0x20
814 bit SCDATBUCKET 0x10
815 bit CNTNOTCMPLT 0x08
816 bit RXOVRUN 0x04
817 bit RXSCEMSG 0x02
818 bit RXSPLTRSP 0x01
872}
873
874/*
875 * Overlay Split Status 0
876 */
877register OVLYSPLTSTAT0 {
878 address 0x096
879 access_mode RW
880 modes M_SCSI
819}
820
821/*
822 * Overlay Split Status 0
823 */
824register OVLYSPLTSTAT0 {
825 address 0x096
826 access_mode RW
827 modes M_SCSI
881 field STAETERM 0x80
882 field SCBCERR 0x40
883 field SCADERR 0x20
884 field SCDATBUCKET 0x10
885 field CNTNOTCMPLT 0x08
886 field RXOVRUN 0x04
887 field RXSCEMSG 0x02
888 field RXSPLTRSP 0x01
828 bit STAETERM 0x80
829 bit SCBCERR 0x40
830 bit SCADERR 0x20
831 bit SCDATBUCKET 0x10
832 bit CNTNOTCMPLT 0x08
833 bit RXOVRUN 0x04
834 bit RXSCEMSG 0x02
835 bit RXSPLTRSP 0x01
889}
890
891/*
892 * Data Channel Split Status 1
893 */
894register DCHSPLTSTAT1 {
895 address 0x097
896 access_mode RW
897 modes M_DFF0, M_DFF1
836}
837
838/*
839 * Data Channel Split Status 1
840 */
841register DCHSPLTSTAT1 {
842 address 0x097
843 access_mode RW
844 modes M_DFF0, M_DFF1
898 field RXDATABUCKET 0x01
845 bit RXDATABUCKET 0x01
899}
900
901/*
902 * CMC Split Status 1
903 */
904register CMCSPLTSTAT1 {
905 address 0x097
906 access_mode RW
907 modes M_CCHAN
846}
847
848/*
849 * CMC Split Status 1
850 */
851register CMCSPLTSTAT1 {
852 address 0x097
853 access_mode RW
854 modes M_CCHAN
908 field RXDATABUCKET 0x01
855 bit RXDATABUCKET 0x01
909}
910
911/*
912 * Overlay Split Status 1
913 */
914register OVLYSPLTSTAT1 {
915 address 0x097
916 access_mode RW
917 modes M_SCSI
856}
857
858/*
859 * Overlay Split Status 1
860 */
861register OVLYSPLTSTAT1 {
862 address 0x097
863 access_mode RW
864 modes M_SCSI
918 field RXDATABUCKET 0x01
865 bit RXDATABUCKET 0x01
919}
920
921/*
922 * S/G Receive Message 0
923 */
924register SGRXMSG0 {
925 address 0x098
926 access_mode RO
927 modes M_DFF0, M_DFF1
866}
867
868/*
869 * S/G Receive Message 0
870 */
871register SGRXMSG0 {
872 address 0x098
873 access_mode RO
874 modes M_DFF0, M_DFF1
928 field CDNUM 0xF8
929 field CFNUM 0x07
875 mask CDNUM 0xF8
876 mask CFNUM 0x07
930}
931
932/*
933 * S/G Receive Message 1
934 */
935register SGRXMSG1 {
936 address 0x099
937 access_mode RO
938 modes M_DFF0, M_DFF1
877}
878
879/*
880 * S/G Receive Message 1
881 */
882register SGRXMSG1 {
883 address 0x099
884 access_mode RO
885 modes M_DFF0, M_DFF1
939 field CBNUM 0xFF
886 mask CBNUM 0xFF
940}
941
942/*
943 * S/G Receive Message 2
944 */
945register SGRXMSG2 {
946 address 0x09A
947 access_mode RO
948 modes M_DFF0, M_DFF1
887}
888
889/*
890 * S/G Receive Message 2
891 */
892register SGRXMSG2 {
893 address 0x09A
894 access_mode RO
895 modes M_DFF0, M_DFF1
949 field MINDEX 0xFF
896 mask MINDEX 0xFF
950}
951
952/*
953 * S/G Receive Message 3
954 */
955register SGRXMSG3 {
956 address 0x09B
957 access_mode RO
958 modes M_DFF0, M_DFF1
897}
898
899/*
900 * S/G Receive Message 3
901 */
902register SGRXMSG3 {
903 address 0x09B
904 access_mode RO
905 modes M_DFF0, M_DFF1
959 field MCLASS 0x0F
906 mask MCLASS 0x0F
960}
961
962/*
963 * Slave Split Out Address 0
964 */
965register SLVSPLTOUTADR0 {
966 address 0x098
967 access_mode RO
968 modes M_SCSI
907}
908
909/*
910 * Slave Split Out Address 0
911 */
912register SLVSPLTOUTADR0 {
913 address 0x098
914 access_mode RO
915 modes M_SCSI
969 field LOWER_ADDR 0x7F
916 mask LOWER_ADDR 0x7F
970}
971
972/*
973 * Slave Split Out Address 1
974 */
975register SLVSPLTOUTADR1 {
976 address 0x099
977 access_mode RO
978 modes M_SCSI
917}
918
919/*
920 * Slave Split Out Address 1
921 */
922register SLVSPLTOUTADR1 {
923 address 0x099
924 access_mode RO
925 modes M_SCSI
979 field REQ_DNUM 0xF8
980 field REQ_FNUM 0x07
926 mask REQ_DNUM 0xF8
927 mask REQ_FNUM 0x07
981}
982
983/*
984 * Slave Split Out Address 2
985 */
986register SLVSPLTOUTADR2 {
987 address 0x09A
988 access_mode RO
989 modes M_SCSI
928}
929
930/*
931 * Slave Split Out Address 2
932 */
933register SLVSPLTOUTADR2 {
934 address 0x09A
935 access_mode RO
936 modes M_SCSI
990 field REQ_BNUM 0xFF
937 mask REQ_BNUM 0xFF
991}
992
993/*
994 * Slave Split Out Address 3
995 */
996register SLVSPLTOUTADR3 {
997 address 0x09B
998 access_mode RO
999 modes M_SCSI
938}
939
940/*
941 * Slave Split Out Address 3
942 */
943register SLVSPLTOUTADR3 {
944 address 0x09B
945 access_mode RO
946 modes M_SCSI
1000 field RLXORD 020
1001 field TAG_NUM 0x1F
947 bit RLXORD 020
948 mask TAG_NUM 0x1F
1002}
1003
1004/*
1005 * SG Sequencer Byte Count
1006 */
1007register SGSEQBCNT {
1008 address 0x09C
1009 access_mode RO
1010 modes M_DFF0, M_DFF1
1011}
1012
1013/*
1014 * Slave Split Out Attribute 0
1015 */
1016register SLVSPLTOUTATTR0 {
1017 address 0x09C
1018 access_mode RO
1019 modes M_SCSI
949}
950
951/*
952 * SG Sequencer Byte Count
953 */
954register SGSEQBCNT {
955 address 0x09C
956 access_mode RO
957 modes M_DFF0, M_DFF1
958}
959
960/*
961 * Slave Split Out Attribute 0
962 */
963register SLVSPLTOUTATTR0 {
964 address 0x09C
965 access_mode RO
966 modes M_SCSI
1020 field LOWER_BCNT 0xFF
967 mask LOWER_BCNT 0xFF
1021}
1022
1023/*
1024 * Slave Split Out Attribute 1
1025 */
1026register SLVSPLTOUTATTR1 {
1027 address 0x09D
1028 access_mode RO
1029 modes M_SCSI
968}
969
970/*
971 * Slave Split Out Attribute 1
972 */
973register SLVSPLTOUTATTR1 {
974 address 0x09D
975 access_mode RO
976 modes M_SCSI
1030 field CMPLT_DNUM 0xF8
1031 field CMPLT_FNUM 0x07
977 mask CMPLT_DNUM 0xF8
978 mask CMPLT_FNUM 0x07
1032}
1033
1034/*
1035 * Slave Split Out Attribute 2
1036 */
1037register SLVSPLTOUTATTR2 {
1038 address 0x09E
1039 access_mode RO
1040 size 2
1041 modes M_SCSI
979}
980
981/*
982 * Slave Split Out Attribute 2
983 */
984register SLVSPLTOUTATTR2 {
985 address 0x09E
986 access_mode RO
987 size 2
988 modes M_SCSI
1042 field CMPLT_BNUM 0xFF
989 mask CMPLT_BNUM 0xFF
1043}
1044/*
1045 * S/G Split Status 0
1046 */
1047register SGSPLTSTAT0 {
1048 address 0x09E
1049 access_mode RW
1050 modes M_DFF0, M_DFF1
990}
991/*
992 * S/G Split Status 0
993 */
994register SGSPLTSTAT0 {
995 address 0x09E
996 access_mode RW
997 modes M_DFF0, M_DFF1
1051 field STAETERM 0x80
1052 field SCBCERR 0x40
1053 field SCADERR 0x20
1054 field SCDATBUCKET 0x10
1055 field CNTNOTCMPLT 0x08
1056 field RXOVRUN 0x04
1057 field RXSCEMSG 0x02
1058 field RXSPLTRSP 0x01
998 bit STAETERM 0x80
999 bit SCBCERR 0x40
1000 bit SCADERR 0x20
1001 bit SCDATBUCKET 0x10
1002 bit CNTNOTCMPLT 0x08
1003 bit RXOVRUN 0x04
1004 bit RXSCEMSG 0x02
1005 bit RXSPLTRSP 0x01
1059}
1060
1061/*
1062 * S/G Split Status 1
1063 */
1064register SGSPLTSTAT1 {
1065 address 0x09F
1066 access_mode RW
1067 modes M_DFF0, M_DFF1
1006}
1007
1008/*
1009 * S/G Split Status 1
1010 */
1011register SGSPLTSTAT1 {
1012 address 0x09F
1013 access_mode RW
1014 modes M_DFF0, M_DFF1
1068 field RXDATABUCKET 0x01
1015 bit RXDATABUCKET 0x01
1069}
1070
1071/*
1072 * Special Function
1073 */
1074register SFUNCT {
1075 address 0x09f
1076 access_mode RW
1077 modes M_CFG
1016}
1017
1018/*
1019 * Special Function
1020 */
1021register SFUNCT {
1022 address 0x09f
1023 access_mode RW
1024 modes M_CFG
1078 field TEST_GROUP 0xF0
1079 field TEST_NUM 0x0F
1025 mask TEST_GROUP 0xF0
1026 mask TEST_NUM 0x0F
1080}
1081
1082/*
1083 * Data FIFO 0 PCI Status
1084 */
1085register DF0PCISTAT {
1086 address 0x0A0
1087 access_mode RW
1088 modes M_CFG
1027}
1028
1029/*
1030 * Data FIFO 0 PCI Status
1031 */
1032register DF0PCISTAT {
1033 address 0x0A0
1034 access_mode RW
1035 modes M_CFG
1089 field DPE 0x80
1090 field SSE 0x40
1091 field RMA 0x20
1092 field RTA 0x10
1093 field SCAAPERR 0x08
1094 field RDPERR 0x04
1095 field TWATERR 0x02
1096 field DPR 0x01
1036 bit DPE 0x80
1037 bit SSE 0x40
1038 bit RMA 0x20
1039 bit RTA 0x10
1040 bit SCAAPERR 0x08
1041 bit RDPERR 0x04
1042 bit TWATERR 0x02
1043 bit DPR 0x01
1097}
1098
1099/*
1100 * Data FIFO 1 PCI Status
1101 */
1102register DF1PCISTAT {
1103 address 0x0A1
1104 access_mode RW
1105 modes M_CFG
1044}
1045
1046/*
1047 * Data FIFO 1 PCI Status
1048 */
1049register DF1PCISTAT {
1050 address 0x0A1
1051 access_mode RW
1052 modes M_CFG
1106 field DPE 0x80
1107 field SSE 0x40
1108 field RMA 0x20
1109 field RTA 0x10
1110 field SCAAPERR 0x08
1111 field RDPERR 0x04
1112 field TWATERR 0x02
1113 field DPR 0x01
1053 bit DPE 0x80
1054 bit SSE 0x40
1055 bit RMA 0x20
1056 bit RTA 0x10
1057 bit SCAAPERR 0x08
1058 bit RDPERR 0x04
1059 bit TWATERR 0x02
1060 bit DPR 0x01
1114}
1115
1116/*
1117 * S/G PCI Status
1118 */
1119register SGPCISTAT {
1120 address 0x0A2
1121 access_mode RW
1122 modes M_CFG
1061}
1062
1063/*
1064 * S/G PCI Status
1065 */
1066register SGPCISTAT {
1067 address 0x0A2
1068 access_mode RW
1069 modes M_CFG
1123 field DPE 0x80
1124 field SSE 0x40
1125 field RMA 0x20
1126 field RTA 0x10
1127 field SCAAPERR 0x08
1128 field RDPERR 0x04
1129 field DPR 0x01
1070 bit DPE 0x80
1071 bit SSE 0x40
1072 bit RMA 0x20
1073 bit RTA 0x10
1074 bit SCAAPERR 0x08
1075 bit RDPERR 0x04
1076 bit DPR 0x01
1130}
1131
1132/*
1133 * CMC PCI Status
1134 */
1135register CMCPCISTAT {
1136 address 0x0A3
1137 access_mode RW
1138 modes M_CFG
1077}
1078
1079/*
1080 * CMC PCI Status
1081 */
1082register CMCPCISTAT {
1083 address 0x0A3
1084 access_mode RW
1085 modes M_CFG
1139 field DPE 0x80
1140 field SSE 0x40
1141 field RMA 0x20
1142 field RTA 0x10
1143 field SCAAPERR 0x08
1144 field RDPERR 0x04
1145 field TWATERR 0x02
1146 field DPR 0x01
1086 bit DPE 0x80
1087 bit SSE 0x40
1088 bit RMA 0x20
1089 bit RTA 0x10
1090 bit SCAAPERR 0x08
1091 bit RDPERR 0x04
1092 bit TWATERR 0x02
1093 bit DPR 0x01
1147}
1148
1149/*
1150 * Overlay PCI Status
1151 */
1152register OVLYPCISTAT {
1153 address 0x0A4
1154 access_mode RW
1155 modes M_CFG
1094}
1095
1096/*
1097 * Overlay PCI Status
1098 */
1099register OVLYPCISTAT {
1100 address 0x0A4
1101 access_mode RW
1102 modes M_CFG
1156 field DPE 0x80
1157 field SSE 0x40
1158 field RMA 0x20
1159 field RTA 0x10
1160 field SCAAPERR 0x08
1161 field RDPERR 0x04
1162 field DPR 0x01
1103 bit DPE 0x80
1104 bit SSE 0x40
1105 bit RMA 0x20
1106 bit RTA 0x10
1107 bit SCAAPERR 0x08
1108 bit RDPERR 0x04
1109 bit DPR 0x01
1163}
1164
1165/*
1166 * PCI Status for MSI Master DMA Transfer
1167 */
1168register MSIPCISTAT {
1169 address 0x0A6
1170 access_mode RW
1171 modes M_CFG
1110}
1111
1112/*
1113 * PCI Status for MSI Master DMA Transfer
1114 */
1115register MSIPCISTAT {
1116 address 0x0A6
1117 access_mode RW
1118 modes M_CFG
1172 field SSE 0x40
1173 field RMA 0x20
1174 field RTA 0x10
1175 field CLRPENDMSI 0x08
1176 field TWATERR 0x02
1177 field DPR 0x01
1119 bit SSE 0x40
1120 bit RMA 0x20
1121 bit RTA 0x10
1122 bit CLRPENDMSI 0x08
1123 bit TWATERR 0x02
1124 bit DPR 0x01
1178}
1179
1180/*
1181 * PCI Status for Target
1182 */
1183register TARGPCISTAT {
1125}
1126
1127/*
1128 * PCI Status for Target
1129 */
1130register TARGPCISTAT {
1184 address 0x0A7
1131 address 0x0A6
1185 access_mode RW
1186 modes M_CFG
1132 access_mode RW
1133 modes M_CFG
1187 field DPE 0x80
1188 field SSE 0x40
1189 field STA 0x08
1190 field TWATERR 0x02
1134 bit DPE 0x80
1135 bit SSE 0x40
1136 bit STA 0x08
1137 bit TWATERR 0x02
1191}
1192
1193/*
1194 * LQ Packet In
1195 * The last LQ Packet recieved
1196 */
1197register LQIN {
1198 address 0x020

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1331 */
1332register ABRTBITPTR {
1333 address 0x02C
1334 access_mode RW
1335 modes M_CFG
1336}
1337
1338/*
1138}
1139
1140/*
1141 * LQ Packet In
1142 * The last LQ Packet recieved
1143 */
1144register LQIN {
1145 address 0x020

--- 132 unchanged lines hidden (view full) ---

1278 */
1279register ABRTBITPTR {
1280 address 0x02C
1281 access_mode RW
1282 modes M_CFG
1283}
1284
1285/*
1339 * Rev B or greater.
1340 */
1341register MAXCMDBYTES {
1342 address 0x02D
1343 access_mode RW
1344 modes M_CFG
1345}
1346
1347/*
1348 * Rev B or greater.
1349 */
1350register MAXCMD2RCV {
1351 address 0x02E
1352 access_mode RW
1353 modes M_CFG
1354}
1355
1356/*
1357 * Rev B or greater.
1358 */
1359register SHORTTHRESH {
1360 address 0x02F
1361 access_mode RW
1362 modes M_CFG
1363}
1364
1365/*
1366 * Logical Unit Number Length
1367 * The length, in bytes, of the SCB lun field.
1368 */
1369register LUNLEN {
1370 address 0x030
1371 access_mode RW
1372 modes M_CFG
1286 * Logical Unit Number Length
1287 * The length, in bytes, of the SCB lun field.
1288 */
1289register LUNLEN {
1290 address 0x030
1291 access_mode RW
1292 modes M_CFG
1373 mask ILUNLEN 0x0F
1374 mask TLUNLEN 0xF0
1375}
1293}
1376const LUNLEN_SINGLE_LEVEL_LUN 0xF
1377
1378/*
1379 * CDB Limit
1380 * The size, in bytes, of the embedded CDB field in initator SCBs.
1381 */
1382register CDBLIMIT {
1383 address 0x031
1384 access_mode RW

--- 55 unchanged lines hidden (view full) ---

1440
1441/*
1442 * LQ Manager Control 0
1443 */
1444register LQCTL0 {
1445 address 0x038
1446 access_mode RW
1447 modes M_CFG
1294
1295/*
1296 * CDB Limit
1297 * The size, in bytes, of the embedded CDB field in initator SCBs.
1298 */
1299register CDBLIMIT {
1300 address 0x031
1301 access_mode RW

--- 55 unchanged lines hidden (view full) ---

1357
1358/*
1359 * LQ Manager Control 0
1360 */
1361register LQCTL0 {
1362 address 0x038
1363 access_mode RW
1364 modes M_CFG
1448 field LQITARGCLT 0xC0
1449 field LQIINITGCLT 0x30
1450 field LQ0TARGCLT 0x0C
1451 field LQ0INITGCLT 0x03
1365 mask LQITARGCLT 0xC0
1366 mask LQIINITGCLT 0x30
1367 mask LQ0TARGCLT 0x0C
1368 mask LQ0INITGCLT 0x03
1452}
1453
1454/*
1455 * LQ Manager Control 1
1456 */
1457register LQCTL1 {
1458 address 0x038
1459 access_mode RW
1460 modes M_DFF0, M_DFF1, M_SCSI
1369}
1370
1371/*
1372 * LQ Manager Control 1
1373 */
1374register LQCTL1 {
1375 address 0x038
1376 access_mode RW
1377 modes M_DFF0, M_DFF1, M_SCSI
1461 field PCI2PCI 0x04
1462 field SINGLECMD 0x02
1463 field ABORTPENDING 0x01
1378 bit PCI2PCI 0x04
1379 bit SINGLECMD 0x02
1380 bit ABORTPENDING 0x01
1464}
1465
1466/*
1467 * LQ Manager Control 2
1468 */
1469register LQCTL2 {
1470 address 0x039
1471 access_mode RW
1472 modes M_DFF0, M_DFF1, M_SCSI
1381}
1382
1383/*
1384 * LQ Manager Control 2
1385 */
1386register LQCTL2 {
1387 address 0x039
1388 access_mode RW
1389 modes M_DFF0, M_DFF1, M_SCSI
1473 field LQIRETRY 0x80
1474 field LQICONTINUE 0x40
1475 field LQITOIDLE 0x20
1476 field LQIPAUSE 0x10
1477 field LQORETRY 0x08
1478 field LQOCONTINUE 0x04
1479 field LQOTOIDLE 0x02
1480 field LQOPAUSE 0x01
1390 bit LQIRETRY 0x80
1391 bit LQICONTINUE 0x40
1392 bit LQITOIDLE 0x20
1393 bit LQIPAUSE 0x10
1394 bit LQORETRY 0x08
1395 bit LQOCONTINUE 0x04
1396 bit LQOTOIDLE 0x02
1397 bit LQOPAUSE 0x01
1481}
1482
1483/*
1484 * SCSI RAM BIST0
1485 */
1486register SCSBIST0 {
1487 address 0x039
1488 access_mode RW
1489 modes M_CFG
1398}
1399
1400/*
1401 * SCSI RAM BIST0
1402 */
1403register SCSBIST0 {
1404 address 0x039
1405 access_mode RW
1406 modes M_CFG
1490 field GSBISTERR 0x40
1491 field GSBISTDONE 0x20
1492 field GSBISTRUN 0x10
1493 field OSBISTERR 0x04
1494 field OSBISTDONE 0x02
1495 field OSBISTRUN 0x01
1407 bit GSBISTERR 0x40
1408 bit GSBISTDONE 0x20
1409 bit GSBISTRUN 0x10
1410 bit OSBISTERR 0x04
1411 bit OSBISTDONE 0x02
1412 bit OSBISTRUN 0x01
1496}
1497
1498/*
1499 * SCSI Sequence Control0
1500 */
1501register SCSISEQ0 {
1502 address 0x03A
1503 access_mode RW
1504 modes M_DFF0, M_DFF1, M_SCSI
1413}
1414
1415/*
1416 * SCSI Sequence Control0
1417 */
1418register SCSISEQ0 {
1419 address 0x03A
1420 access_mode RW
1421 modes M_DFF0, M_DFF1, M_SCSI
1505 field TEMODEO 0x80
1506 field ENSELO 0x40
1507 field ENARBO 0x20
1508 field FORCEBUSFREE 0x10
1509 field SCSIRSTO 0x01
1422 bit TEMODEO 0x80
1423 bit ENSELO 0x40
1424 bit ENARBO 0x20
1425 bit FORCEBUSFREE 0x10
1426 bit SCSIRSTO 0x01
1510}
1511
1512/*
1513 * SCSI RAM BIST 1
1514 */
1515register SCSBIST1 {
1516 address 0x03A
1517 access_mode RW
1518 modes M_CFG
1427}
1428
1429/*
1430 * SCSI RAM BIST 1
1431 */
1432register SCSBIST1 {
1433 address 0x03A
1434 access_mode RW
1435 modes M_CFG
1519 field NTBISTERR 0x04
1520 field NTBISTDONE 0x02
1521 field NTBISTRUN 0x01
1436 bit NTBISTERR 0x04
1437 bit NTBISTDONE 0x02
1438 bit NTBISTRUN 0x01
1522}
1523
1524/*
1525 * SCSI Sequence Control 1
1526 */
1527register SCSISEQ1 {
1528 address 0x03B
1529 access_mode RW
1530 modes M_DFF0, M_DFF1, M_SCSI
1439}
1440
1441/*
1442 * SCSI Sequence Control 1
1443 */
1444register SCSISEQ1 {
1445 address 0x03B
1446 access_mode RW
1447 modes M_DFF0, M_DFF1, M_SCSI
1531 field MANUALCTL 0x40
1532 field ENSELI 0x20
1533 field ENRSELI 0x10
1534 field MANUALP 0x0C
1535 field ENAUTOATNP 0x02
1536 field ALTSTIM 0x01
1448 bit MANUALCTL 0x40
1449 bit ENSELI 0x20
1450 bit ENRSELI 0x10
1451 mask MANUALP 0x0C
1452 bit ENAUTOATNP 0x02
1453 bit ALTSTIM 0x01
1537}
1538
1539/*
1540 * SCSI Transfer Control 0
1541 */
1542register SXFRCTL0 {
1543 address 0x03C
1544 access_mode RW
1545 modes M_SCSI
1454}
1455
1456/*
1457 * SCSI Transfer Control 0
1458 */
1459register SXFRCTL0 {
1460 address 0x03C
1461 access_mode RW
1462 modes M_SCSI
1546 field DFON 0x80
1547 field DFPEXP 0x40
1548 field BIOSCANCELEN 0x10
1549 field SPIOEN 0x08
1463 bit DFON 0x80
1464 bit DFPEXP 0x40
1465 bit BIOSCANCELEN 0x10
1466 bit SPIOEN 0x08
1550}
1551
1552/*
1553 * SCSI Transfer Control 1
1554 */
1555register SXFRCTL1 {
1556 address 0x03D
1557 access_mode RW
1558 modes M_SCSI
1467}
1468
1469/*
1470 * SCSI Transfer Control 1
1471 */
1472register SXFRCTL1 {
1473 address 0x03D
1474 access_mode RW
1475 modes M_SCSI
1559 field BITBUCKET 0x80
1560 field ENSACHK 0x40
1561 field ENSPCHK 0x20
1562 field STIMESEL 0x18
1563 field ENSTIMER 0x04
1564 field ACTNEGEN 0x02
1565 field STPWEN 0x01
1476 bit BITBUCKET 0x80
1477 bit ENSACHK 0x40
1478 bit ENSPCHK 0x20
1479 mask STIMESEL 0x18
1480 bit ENSTIMER 0x04
1481 bit ACTNEGEN 0x02
1482 bit STPWEN 0x01
1566}
1567
1568/*
1569 * SCSI Transfer Control 2
1570 */
1571register SXFRCTL2 {
1572 address 0x03E
1573 access_mode RW
1574 modes M_SCSI
1483}
1484
1485/*
1486 * SCSI Transfer Control 2
1487 */
1488register SXFRCTL2 {
1489 address 0x03E
1490 access_mode RW
1491 modes M_SCSI
1575 field AUTORSTDIS 0x10
1576 field CMDDMAEN 0x08
1577 field ASU 0x07
1492 bit AUTORSTDIS 0x10
1493 bit CMDDMAEN 0x08
1494 mask ASU 0x07
1578}
1579
1580/*
1581 * SCSI Bus Initiator IDs
1582 * Bitmask of observed initiators on the bus.
1583 */
1584register BUSINITID {
1585 address 0x03C

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1601
1602/*
1603 * Data FIFO Status
1604 */
1605register DFFSTAT {
1606 address 0x03F
1607 access_mode RW
1608 modes M_SCSI
1495}
1496
1497/*
1498 * SCSI Bus Initiator IDs
1499 * Bitmask of observed initiators on the bus.
1500 */
1501register BUSINITID {
1502 address 0x03C

--- 15 unchanged lines hidden (view full) ---

1518
1519/*
1520 * Data FIFO Status
1521 */
1522register DFFSTAT {
1523 address 0x03F
1524 access_mode RW
1525 modes M_SCSI
1609 field FIFO1FREE 0x20
1610 field FIFO0FREE 0x10
1611 /*
1612 * On the B, this enum only works
1613 * in the read direction. For writes,
1614 * you must use the B version of the
1615 * CURRFIFO_0 definition which is defined
1616 * as a constant outside of this register
1617 * definition to avoid confusing the
1618 * register pretty printing code.
1619 */
1620 enum CURRFIFO 0x03 {
1621 CURRFIFO_0,
1622 CURRFIFO_1,
1623 CURRFIFO_NONE 0x3
1624 }
1526 bit FIFO1FREE 0x20
1527 bit FIFO0FREE 0x10
1528 bit CURRFIFO 0x01
1625}
1626
1529}
1530
1627const B_CURRFIFO_0 0x2
1628
1629/*
1630 * SCSI Bus Target IDs
1631 * Bitmask of observed targets on the bus.
1632 */
1633register BUSTARGID {
1634 address 0x03E
1635 access_mode RW
1636 modes M_CFG
1637 size 2
1638}
1639
1640/*
1641 * SCSI Control Signal Out
1642 */
1643register SCSISIGO {
1644 address 0x040
1645 access_mode RW
1646 modes M_DFF0, M_DFF1, M_SCSI
1531/*
1532 * SCSI Bus Target IDs
1533 * Bitmask of observed targets on the bus.
1534 */
1535register BUSTARGID {
1536 address 0x03E
1537 access_mode RW
1538 modes M_CFG
1539 size 2
1540}
1541
1542/*
1543 * SCSI Control Signal Out
1544 */
1545register SCSISIGO {
1546 address 0x040
1547 access_mode RW
1548 modes M_DFF0, M_DFF1, M_SCSI
1647 field CDO 0x80
1648 field IOO 0x40
1649 field MSGO 0x20
1650 field ATNO 0x10
1651 field SELO 0x08
1652 field BSYO 0x04
1653 field REQO 0x02
1654 field ACKO 0x01
1549 bit CDO 0x80
1550 bit IOO 0x40
1551 bit MSGO 0x20
1552 bit ATNO 0x10
1553 bit SELO 0x08
1554 bit BSYO 0x04
1555 bit REQO 0x02
1556 bit ACKO 0x01
1655/*
1656 * Possible phases to write into SCSISIG0
1657 */
1557/*
1558 * Possible phases to write into SCSISIG0
1559 */
1658 enum PHASE_MASK CDO|IOO|MSGO {
1659 P_DATAOUT 0x0,
1660 P_DATAIN IOO,
1661 P_DATAOUT_DT P_DATAOUT|MSGO,
1662 P_DATAIN_DT P_DATAIN|MSGO,
1663 P_COMMAND CDO,
1664 P_MESGOUT CDO|MSGO,
1665 P_STATUS CDO|IOO,
1666 P_MESGIN CDO|IOO|MSGO
1667 }
1560 mask PHASE_MASK CDO|IOO|MSGO
1561 mask P_DATAOUT 0x00
1562 mask P_DATAIN IOO
1563 mask P_DATAOUT_DT P_DATAOUT|MSGO
1564 mask P_DATAIN_DT P_DATAIN|MSGO
1565 mask P_COMMAND CDO
1566 mask P_MESGOUT CDO|MSGO
1567 mask P_STATUS CDO|IOO
1568 mask P_MESGIN CDO|IOO|MSGO
1668}
1669
1670register SCSISIGI {
1671 address 0x041
1672 access_mode RO
1673 modes M_DFF0, M_DFF1, M_SCSI
1569}
1570
1571register SCSISIGI {
1572 address 0x041
1573 access_mode RO
1574 modes M_DFF0, M_DFF1, M_SCSI
1674 field CDI 0x80
1675 field IOI 0x40
1676 field MSGI 0x20
1677 field ATNI 0x10
1678 field SELI 0x08
1679 field BSYI 0x04
1680 field REQI 0x02
1681 field ACKI 0x01
1575 bit CDI 0x80
1576 bit IOI 0x40
1577 bit MSGI 0x20
1578 bit ATNI 0x10
1579 bit SELI 0x08
1580 bit BSYI 0x04
1581 bit REQI 0x02
1582 bit ACKI 0x01
1682/*
1683 * Possible phases in SCSISIGI
1684 */
1583/*
1584 * Possible phases in SCSISIGI
1585 */
1685 enum PHASE_MASK CDO|IOO|MSGO {
1686 P_DATAOUT 0x0,
1687 P_DATAIN IOO,
1688 P_DATAOUT_DT P_DATAOUT|MSGO,
1689 P_DATAIN_DT P_DATAIN|MSGO,
1690 P_COMMAND CDO,
1691 P_MESGOUT CDO|MSGO,
1692 P_STATUS CDO|IOO,
1693 P_MESGIN CDO|IOO|MSGO
1694 }
1586 mask PHASE_MASK CDI|IOI|MSGI
1587 mask P_DATAOUT 0x00
1588 mask P_DATAIN IOI
1589 mask P_DATAOUT_DT P_DATAOUT|MSGI
1590 mask P_DATAIN_DT P_DATAIN|MSGI
1591 mask P_COMMAND CDI
1592 mask P_MESGOUT CDI|MSGI
1593 mask P_STATUS CDI|IOI
1594 mask P_MESGIN CDI|IOI|MSGI
1695}
1696
1697/*
1698 * Multiple Target IDs
1699 * Bitmask of ids to respond as a target.
1700 */
1701register MULTARGID {
1702 address 0x040

--- 4 unchanged lines hidden (view full) ---

1707
1708/*
1709 * SCSI Phase
1710 */
1711register SCSIPHASE {
1712 address 0x042
1713 access_mode RO
1714 modes M_DFF0, M_DFF1, M_SCSI
1595}
1596
1597/*
1598 * Multiple Target IDs
1599 * Bitmask of ids to respond as a target.
1600 */
1601register MULTARGID {
1602 address 0x040

--- 4 unchanged lines hidden (view full) ---

1607
1608/*
1609 * SCSI Phase
1610 */
1611register SCSIPHASE {
1612 address 0x042
1613 access_mode RO
1614 modes M_DFF0, M_DFF1, M_SCSI
1715 field STATUS_PHASE 0x20
1716 field COMMAND_PHASE 0x10
1717 field MSG_IN_PHASE 0x08
1718 field MSG_OUT_PHASE 0x04
1719 field DATA_PHASE_MASK 0x03 {
1720 DATA_OUT_PHASE 0x01,
1721 DATA_IN_PHASE 0x02
1722 }
1615 bit STATUS_PHASE 0x20
1616 bit COMMAND_PHASE 0x10
1617 bit MSG_IN_PHASE 0x08
1618 bit MSG_OUT_PHASE 0x04
1619 bit DATA_IN_PHASE 0x02
1620 bit DATA_OUT_PHASE 0x01
1621 mask DATA_PHASE_MASK 0x03
1723}
1724
1725/*
1726 * SCSI Data 0 Image
1727 */
1728register SCSIDAT0_IMG {
1729 address 0x043
1730 access_mode RW

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1753
1754/*
1755 * Target ID In
1756 */
1757register TARGIDIN {
1758 address 0x048
1759 access_mode RO
1760 modes M_DFF0, M_DFF1, M_SCSI
1622}
1623
1624/*
1625 * SCSI Data 0 Image
1626 */
1627register SCSIDAT0_IMG {
1628 address 0x043
1629 access_mode RW

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1652
1653/*
1654 * Target ID In
1655 */
1656register TARGIDIN {
1657 address 0x048
1658 access_mode RO
1659 modes M_DFF0, M_DFF1, M_SCSI
1761 field CLKOUT 0x80
1762 field TARGID 0x0F
1660 bit CLKOUT 0x80
1661 mask TARGID 0x0F
1763}
1764
1765/*
1766 * Selection/Reselection ID
1767 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
1768 * device did not set its own ID.
1769 */
1770register SELID {
1771 address 0x049
1772 access_mode RW
1773 modes M_DFF0, M_DFF1, M_SCSI
1662}
1663
1664/*
1665 * Selection/Reselection ID
1666 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
1667 * device did not set its own ID.
1668 */
1669register SELID {
1670 address 0x049
1671 access_mode RW
1672 modes M_DFF0, M_DFF1, M_SCSI
1774 field SELID_MASK 0xf0
1775 field ONEBIT 0x08
1673 mask SELID_MASK 0xf0
1674 bit ONEBIT 0x08
1776}
1777
1778/*
1779 * SCSI Block Control
1780 * Controls Bus type and channel selection. SELWIDE allows for the
1781 * coexistence of 8bit and 16bit devices on a wide bus.
1782 */
1783register SBLKCTL {
1784 address 0x04A
1785 access_mode RW
1786 modes M_DFF0, M_DFF1, M_SCSI
1675}
1676
1677/*
1678 * SCSI Block Control
1679 * Controls Bus type and channel selection. SELWIDE allows for the
1680 * coexistence of 8bit and 16bit devices on a wide bus.
1681 */
1682register SBLKCTL {
1683 address 0x04A
1684 access_mode RW
1685 modes M_DFF0, M_DFF1, M_SCSI
1787 field DIAGLEDEN 0x80
1788 field DIAGLEDON 0x40
1789 field ENAB40 0x08 /* LVD transceiver active */
1790 field ENAB20 0x04 /* SE/HVD transceiver active */
1791 field SELWIDE 0x02
1686 bit DIAGLEDEN 0x80
1687 bit DIAGLEDON 0x40
1688 bit ENAB40 0x08 /* LVD transceiver active */
1689 bit ENAB20 0x04 /* SE/HVD transceiver active */
1690 bit SELWIDE 0x02
1792}
1793
1794/*
1795 * Option Mode
1796 */
1797register OPTIONMODE {
1798 address 0x04A
1799 access_mode RW
1800 modes M_CFG
1691}
1692
1693/*
1694 * Option Mode
1695 */
1696register OPTIONMODE {
1697 address 0x04A
1698 access_mode RW
1699 modes M_CFG
1801 field BIOSCANCTL 0x80
1802 field AUTOACKEN 0x40
1803 field BIASCANCTL 0x20
1804 field BUSFREEREV 0x10
1805 field ENDGFORMCHK 0x04
1806 field AUTO_MSGOUT_DE 0x02
1700 bit BIOSCANCTL 0x80
1701 bit AUTOACKEN 0x40
1702 bit BIASCANCTL 0x20
1703 bit BUSFREEREV 0x10
1704 bit ENDGFORMCHK 0x04
1705 bit AUTO_MSGOUT_DE 0x02
1807 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE
1808}
1809
1810/*
1811 * SCSI Status 0
1812 */
1813register SSTAT0 {
1814 address 0x04B
1815 access_mode RO
1816 modes M_DFF0, M_DFF1, M_SCSI
1706 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE
1707}
1708
1709/*
1710 * SCSI Status 0
1711 */
1712register SSTAT0 {
1713 address 0x04B
1714 access_mode RO
1715 modes M_DFF0, M_DFF1, M_SCSI
1817 field TARGET 0x80 /* Board acting as target */
1818 field SELDO 0x40 /* Selection Done */
1819 field SELDI 0x20 /* Board has been selected */
1820 field SELINGO 0x10 /* Selection In Progress */
1821 field IOERR 0x08 /* LVD Tranceiver mode changed */
1822 field OVERRUN 0x04 /* SCSI Offset overrun detected */
1823 field SPIORDY 0x02 /* SCSI PIO Ready */
1824 field ARBDO 0x01 /* Arbitration Done Out */
1716 bit TARGET 0x80 /* Board acting as target */
1717 bit SELDO 0x40 /* Selection Done */
1718 bit SELDI 0x20 /* Board has been selected */
1719 bit SELINGO 0x10 /* Selection In Progress */
1720 bit IOERR 0x08 /* LVD Tranceiver mode changed */
1721 bit OVERRUN 0x04 /* SCSI Offset overrun detected */
1722 bit SPIORDY 0x02 /* SCSI PIO Ready */
1723 bit ARBDO 0x01 /* Arbitration Done Out */
1825}
1826
1827/*
1828 * Clear SCSI Interrupt 0
1829 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
1830 */
1831register CLRSINT0 {
1832 address 0x04B
1833 access_mode WO
1834 modes M_DFF0, M_DFF1, M_SCSI
1724}
1725
1726/*
1727 * Clear SCSI Interrupt 0
1728 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
1729 */
1730register CLRSINT0 {
1731 address 0x04B
1732 access_mode WO
1733 modes M_DFF0, M_DFF1, M_SCSI
1835 field CLRSELDO 0x40
1836 field CLRSELDI 0x20
1837 field CLRSELINGO 0x10
1838 field CLRIOERR 0x08
1839 field CLROVERRUN 0x04
1840 field CLRSPIORDY 0x02
1841 field CLRARBDO 0x01
1734 bit CLRSELDO 0x40
1735 bit CLRSELDI 0x20
1736 bit CLRSELINGO 0x10
1737 bit CLRIOERR 0x08
1738 bit CLROVERRUN 0x04
1739 bit CLRSPIORDY 0x02
1740 bit CLRARBDO 0x01
1842}
1843
1844/*
1845 * SCSI Interrupt Mode 0
1846 * Setting any bit will enable the corresponding function
1847 * in SIMODE0 to interrupt via the IRQ pin.
1848 */
1849register SIMODE0 {
1850 address 0x04B
1851 access_mode RW
1852 modes M_CFG
1741}
1742
1743/*
1744 * SCSI Interrupt Mode 0
1745 * Setting any bit will enable the corresponding function
1746 * in SIMODE0 to interrupt via the IRQ pin.
1747 */
1748register SIMODE0 {
1749 address 0x04B
1750 access_mode RW
1751 modes M_CFG
1853 field ENSELDO 0x40
1854 field ENSELDI 0x20
1855 field ENSELINGO 0x10
1856 field ENIOERR 0x08
1857 field ENOVERRUN 0x04
1858 field ENSPIORDY 0x02
1859 field ENARBDO 0x01
1752 bit ENSELDO 0x40
1753 bit ENSELDI 0x20
1754 bit ENSELINGO 0x10
1755 bit ENIOERR 0x08
1756 bit ENOVERRUN 0x04
1757 bit ENSPIORDY 0x02
1758 bit ENARBDO 0x01
1860}
1861
1862/*
1863 * SCSI Status 1
1864 */
1865register SSTAT1 {
1866 address 0x04C
1867 access_mode RO
1868 modes M_DFF0, M_DFF1, M_SCSI
1759}
1760
1761/*
1762 * SCSI Status 1
1763 */
1764register SSTAT1 {
1765 address 0x04C
1766 access_mode RO
1767 modes M_DFF0, M_DFF1, M_SCSI
1869 field SELTO 0x80
1870 field ATNTARG 0x40
1871 field SCSIRSTI 0x20
1872 field PHASEMIS 0x10
1873 field BUSFREE 0x08
1874 field SCSIPERR 0x04
1875 field STRB2FAST 0x02
1876 field REQINIT 0x01
1768 bit SELTO 0x80
1769 bit ATNTARG 0x40
1770 bit SCSIRSTI 0x20
1771 bit PHASEMIS 0x10
1772 bit BUSFREE 0x08
1773 bit SCSIPERR 0x04
1774 bit STRB2FAST 0x02
1775 bit REQINIT 0x01
1877}
1878
1879/*
1880 * Clear SCSI Interrupt 1
1881 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
1882 */
1883register CLRSINT1 {
1776}
1777
1778/*
1779 * Clear SCSI Interrupt 1
1780 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
1781 */
1782register CLRSINT1 {
1884 address 0x04C
1783 address 0x04c
1885 access_mode WO
1886 modes M_DFF0, M_DFF1, M_SCSI
1784 access_mode WO
1785 modes M_DFF0, M_DFF1, M_SCSI
1887 field CLRSELTIMEO 0x80
1888 field CLRATNO 0x40
1889 field CLRSCSIRSTI 0x20
1890 field CLRBUSFREE 0x08
1891 field CLRSCSIPERR 0x04
1892 field CLRSTRB2FAST 0x02
1893 field CLRREQINIT 0x01
1786 bit CLRSELTIMEO 0x80
1787 bit CLRATNO 0x40
1788 bit CLRSCSIRSTI 0x20
1789 bit CLRBUSFREE 0x08
1790 bit CLRSCSIPERR 0x04
1791 bit CLRSTRB2FAST 0x02
1792 bit CLRREQINIT 0x01
1894}
1895
1896/*
1897 * SCSI Status 2
1898 */
1899register SSTAT2 {
1900 address 0x04d
1901 access_mode RO
1902 modes M_DFF0, M_DFF1, M_SCSI
1793}
1794
1795/*
1796 * SCSI Status 2
1797 */
1798register SSTAT2 {
1799 address 0x04d
1800 access_mode RO
1801 modes M_DFF0, M_DFF1, M_SCSI
1903 field BUSFREETIME 0xc0 {
1904 BUSFREE_LQO 0x40,
1905 BUSFREE_DFF0 0x80,
1906 BUSFREE_DFF1 0xC0
1907 }
1908 field NONPACKREQ 0x20
1909 field EXP_ACTIVE 0x10 /* SCSI Expander Active */
1910 field BSYX 0x08 /* Busy Expander */
1911 field WIDE_RES 0x04 /* Modes 0 and 1 only */
1912 field SDONE 0x02 /* Modes 0 and 1 only */
1913 field DMADONE 0x01 /* Modes 0 and 1 only */
1802 mask BUSFREETIME 0xc0
1803 mask BUSFREE_LQO 0x40
1804 mask BUSFREE_DFF0 0x80
1805 mask BUSFREE_DFF1 0xC0
1806 bit NONPACKREQ 0x20
1807 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */
1808 bit BSYX 0x08 /* Busy Expander */
1809 bit WIDE_RES 0x04 /* Modes 0 and 1 only */
1810 bit SDONE 0x02 /* Modes 0 and 1 only */
1811 bit DMADONE 0x01 /* Modes 0 and 1 only */
1914}
1915
1916/*
1917 * Clear SCSI Interrupt 2
1918 */
1919register CLRSINT2 {
1920 address 0x04D
1921 access_mode WO
1922 modes M_DFF0, M_DFF1, M_SCSI
1812}
1813
1814/*
1815 * Clear SCSI Interrupt 2
1816 */
1817register CLRSINT2 {
1818 address 0x04D
1819 access_mode WO
1820 modes M_DFF0, M_DFF1, M_SCSI
1923 field CLRNONPACKREQ 0x20
1924 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */
1925 field CLRSDONE 0x02 /* Modes 0 and 1 only */
1926 field CLRDMADONE 0x01 /* Modes 0 and 1 only */
1821 bit CLRNONPACKREQ 0x20
1822 bit CLRWIDE_RES 0x04 /* Modes 0 and 1 only */
1823 bit CLRSDONE 0x02 /* Modes 0 and 1 only */
1824 bit CLRDMADONE 0x01 /* Modes 0 and 1 only */
1927}
1928
1929/*
1930 * SCSI Interrupt Mode 2
1931 */
1932register SIMODE2 {
1933 address 0x04D
1934 access_mode RW
1935 modes M_CFG
1825}
1826
1827/*
1828 * SCSI Interrupt Mode 2
1829 */
1830register SIMODE2 {
1831 address 0x04D
1832 access_mode RW
1833 modes M_CFG
1936 field ENWIDE_RES 0x04
1937 field ENSDONE 0x02
1938 field ENDMADONE 0x01
1834 bit ENWIDE_RES 0x04
1835 bit ENSDONE 0x02
1836 bit ENDMADONE 0x01
1939}
1940
1941/*
1942 * Physical Error Diagnosis
1943 */
1944register PERRDIAG {
1945 address 0x04E
1946 access_mode RO
1947 modes M_DFF0, M_DFF1, M_SCSI
1837}
1838
1839/*
1840 * Physical Error Diagnosis
1841 */
1842register PERRDIAG {
1843 address 0x04E
1844 access_mode RO
1845 modes M_DFF0, M_DFF1, M_SCSI
1948 field HIZERO 0x80
1949 field HIPERR 0x40
1950 field PREVPHASE 0x20
1951 field PARITYERR 0x10
1952 field AIPERR 0x08
1953 field CRCERR 0x04
1954 field DGFORMERR 0x02
1955 field DTERR 0x01
1846 bit HIZERO 0x80
1847 bit HIPERR 0x40
1848 bit PREVPHASE 0x20
1849 bit PARITYERR 0x10
1850 bit AIPERR 0x08
1851 bit CRCERR 0x04
1852 bit DGFORMERR 0x02
1853 bit DTERR 0x01
1956}
1957
1958/*
1959 * LQI Manager Current State
1960 */
1961register LQISTATE {
1962 address 0x04E
1963 access_mode RO

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1984
1985/*
1986 * LQI Manager Status
1987 */
1988register LQISTAT0 {
1989 address 0x050
1990 access_mode RO
1991 modes M_DFF0, M_DFF1, M_SCSI
1854}
1855
1856/*
1857 * LQI Manager Current State
1858 */
1859register LQISTATE {
1860 address 0x04E
1861 access_mode RO

--- 20 unchanged lines hidden (view full) ---

1882
1883/*
1884 * LQI Manager Status
1885 */
1886register LQISTAT0 {
1887 address 0x050
1888 access_mode RO
1889 modes M_DFF0, M_DFF1, M_SCSI
1992 field LQIATNQAS 0x20
1993 field LQICRCT1 0x10
1994 field LQICRCT2 0x08
1995 field LQIBADLQT 0x04
1996 field LQIATNLQ 0x02
1997 field LQIATNCMD 0x01
1890 bit LQIATNQAS 0x20
1891 bit LQICRCT1 0x10
1892 bit LQICRCT2 0x08
1893 bit LQIBADLQT 0x04
1894 bit LQIATNLQ 0x02
1895 bit LQIATNCMD 0x01
1998}
1999
2000/*
2001 * Clear LQI Interrupts 0
2002 */
1896}
1897
1898/*
1899 * Clear LQI Interrupts 0
1900 */
2003register CLRLQIINT0 {
1901register CLRLQIINTO {
2004 address 0x050
2005 access_mode WO
2006 modes M_DFF0, M_DFF1, M_SCSI
1902 address 0x050
1903 access_mode WO
1904 modes M_DFF0, M_DFF1, M_SCSI
2007 field CLRLQIATNQAS 0x20
2008 field CLRLQICRCT1 0x10
2009 field CLRLQICRCT2 0x08
2010 field CLRLQIBADLQT 0x04
2011 field CLRLQIATNLQ 0x02
2012 field CLRLQIATNCMD 0x01
1905 bit CLRLQIATNQAS 0x20
1906 bit CLRLQICRCT1 0x10
1907 bit CLRLQICRCT2 0x08
1908 bit CLRLQIBADLQT 0x04
1909 bit CLRLQIATNLQ 0x02
1910 bit CLRLQIATNCMD 0x01
2013}
2014
2015/*
2016 * LQI Manager Interrupt Mode 0
2017 */
2018register LQIMODE0 {
2019 address 0x050
2020 access_mode RW
2021 modes M_CFG
1911}
1912
1913/*
1914 * LQI Manager Interrupt Mode 0
1915 */
1916register LQIMODE0 {
1917 address 0x050
1918 access_mode RW
1919 modes M_CFG
2022 field ENLQIATNQASK 0x20
2023 field ENLQICRCT1 0x10
2024 field ENLQICRCT2 0x08
2025 field ENLQIBADLQT 0x04
2026 field ENLQIATNLQ 0x02
2027 field ENLQIATNCMD 0x01
1920 bit ENLQIATNQASK 0x20
1921 bit ENLQICRCT1 0x10
1922 bit ENLQICRCT2 0x08
1923 bit ENLQIBADLQT 0x04
1924 bit ENLQIATNLQ 0x02
1925 bit ENLQIATNCMD 0x01
2028}
2029
2030/*
2031 * LQI Manager Status 1
2032 */
2033register LQISTAT1 {
2034 address 0x051
2035 access_mode RO
2036 modes M_DFF0, M_DFF1, M_SCSI
1926}
1927
1928/*
1929 * LQI Manager Status 1
1930 */
1931register LQISTAT1 {
1932 address 0x051
1933 access_mode RO
1934 modes M_DFF0, M_DFF1, M_SCSI
2037 field LQIPHASE_LQ 0x80
2038 field LQIPHASE_NLQ 0x40
2039 field LQIABORT 0x20
2040 field LQICRCI_LQ 0x10
2041 field LQICRCI_NLQ 0x08
2042 field LQIBADLQI 0x04
2043 field LQIOVERI_LQ 0x02
2044 field LQIOVERI_NLQ 0x01
1935 mask LQIPHASE_LQ 0x80
1936 mask LQIPHASE_NLQ 0x40
1937 bit LQIABORT 0x20
1938 mask LQICRCI_LQ 0x10
1939 mask LQICRCI_NLQ 0x08
1940 bit LQIBADLQI 0x04
1941 mask LQIOVERI_LQ 0x02
1942 mask LQIOVERI_NLQ 0x01
2045}
2046
2047/*
2048 * Clear LQI Manager Interrupts1
2049 */
2050register CLRLQIINT1 {
2051 address 0x051
2052 access_mode WO
2053 modes M_DFF0, M_DFF1, M_SCSI
1943}
1944
1945/*
1946 * Clear LQI Manager Interrupts1
1947 */
1948register CLRLQIINT1 {
1949 address 0x051
1950 access_mode WO
1951 modes M_DFF0, M_DFF1, M_SCSI
2054 field CLRLQIPHASE_LQ 0x80
2055 field CLRLQIPHASE_NLQ 0x40
2056 field CLRLIQABORT 0x20
2057 field CLRLQICRCI_LQ 0x10
2058 field CLRLQICRCI_NLQ 0x08
2059 field CLRLQIBADLQI 0x04
2060 field CLRLQIOVERI_LQ 0x02
2061 field CLRLQIOVERI_NLQ 0x01
1952 mask CLRLQIPHASE_LQ 0x80
1953 mask CLRLQIPHASE_NLQ 0x40
1954 bit CLRLIQABORT 0x20
1955 mask CLRLQICRCI_LQ 0x10
1956 mask CLRLQICRCI_NLQ 0x08
1957 bit CLRLQIBADLQI 0x04
1958 mask CLRLQIOVERI_LQ 0x02
1959 mask CLRLQIOVERI_NLQ 0x01
2062}
2063
2064/*
2065 * LQI Manager Interrupt Mode 1
2066 */
2067register LQIMODE1 {
2068 address 0x051
2069 access_mode RW
2070 modes M_CFG
1960}
1961
1962/*
1963 * LQI Manager Interrupt Mode 1
1964 */
1965register LQIMODE1 {
1966 address 0x051
1967 access_mode RW
1968 modes M_CFG
2071 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */
2072 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */
2073 field ENLIQABORT 0x20
2074 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */
2075 field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */
2076 field ENLQIBADLQI 0x04
2077 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */
2078 field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */
1969 mask ENLQIPHASE_LQ 0x80
1970 mask ENLQIPHASE_NLQ 0x40
1971 bit ENLIQABORT 0x20
1972 mask ENLQICRCI_LQ 0x10
1973 mask ENLQICRCI_NLQ 0x08
1974 bit ENLQIBADLQI 0x04
1975 mask ENLQIOVERI_LQ 0x02
1976 mask ENLQIOVERI_NLQ 0x01
2079}
2080
2081/*
2082 * LQI Manager Status 2
2083 */
2084register LQISTAT2 {
2085 address 0x052
2086 access_mode RO
2087 modes M_DFF0, M_DFF1, M_SCSI
1977}
1978
1979/*
1980 * LQI Manager Status 2
1981 */
1982register LQISTAT2 {
1983 address 0x052
1984 access_mode RO
1985 modes M_DFF0, M_DFF1, M_SCSI
2088 field PACKETIZED 0x80
2089 field LQIPHASE_OUTPKT 0x40
2090 field LQIWORKONLQ 0x20
2091 field LQIWAITFIFO 0x10
2092 field LQISTOPPKT 0x08
2093 field LQISTOPLQ 0x04
2094 field LQISTOPCMD 0x02
2095 field LQIGSAVAIL 0x01
1986 bit PACKETIZED 0x80
1987 bit LQIPHASE_OUTPKT 0x40
1988 bit LQIWORKONLQ 0x20
1989 bit LQIWAITFIFO 0x10
1990 bit LQISTOPPKT 0x08
1991 bit LQISTOPLQ 0x04
1992 bit LQISTOPCMD 0x02
1993 bit LQIGSAVAIL 0x01
2096}
2097
2098/*
2099 * SCSI Status 3
2100 */
2101register SSTAT3 {
2102 address 0x053
2103 access_mode RO
2104 modes M_DFF0, M_DFF1, M_SCSI
1994}
1995
1996/*
1997 * SCSI Status 3
1998 */
1999register SSTAT3 {
2000 address 0x053
2001 access_mode RO
2002 modes M_DFF0, M_DFF1, M_SCSI
2105 field NTRAMPERR 0x02
2106 field OSRAMPERR 0x01
2003 bit NTRAMPERR 0x02
2004 bit OSRAMPERR 0x01
2107}
2108
2109/*
2110 * Clear SCSI Status 3
2111 */
2112register CLRSINT3 {
2113 address 0x053
2114 access_mode WO
2115 modes M_DFF0, M_DFF1, M_SCSI
2005}
2006
2007/*
2008 * Clear SCSI Status 3
2009 */
2010register CLRSINT3 {
2011 address 0x053
2012 access_mode WO
2013 modes M_DFF0, M_DFF1, M_SCSI
2116 field CLRNTRAMPERR 0x02
2117 field CLROSRAMPERR 0x01
2014 bit CLRNTRAMPERR 0x02
2015 bit CLROSRAMPERR 0x01
2118}
2119
2120/*
2121 * SCSI Interrupt Mode 3
2122 */
2123register SIMODE3 {
2124 address 0x053
2125 access_mode RW
2126 modes M_CFG
2016}
2017
2018/*
2019 * SCSI Interrupt Mode 3
2020 */
2021register SIMODE3 {
2022 address 0x053
2023 access_mode RW
2024 modes M_CFG
2127 field ENNTRAMPERR 0x02
2128 field ENOSRAMPERR 0x01
2025 bit ENNTRAMPERR 0x02
2026 bit ENOSRAMPERR 0x01
2129}
2130
2131/*
2132 * LQO Manager Status 0
2133 */
2134register LQOSTAT0 {
2135 address 0x054
2136 access_mode RO
2137 modes M_DFF0, M_DFF1, M_SCSI
2027}
2028
2029/*
2030 * LQO Manager Status 0
2031 */
2032register LQOSTAT0 {
2033 address 0x054
2034 access_mode RO
2035 modes M_DFF0, M_DFF1, M_SCSI
2138 field LQOTARGSCBPERR 0x10
2139 field LQOSTOPT2 0x08
2140 field LQOATNLQ 0x04
2141 field LQOATNPKT 0x02
2142 field LQOTCRC 0x01
2036 bit LQOTARGSCBPERR 0x10
2037 bit LQOSTOPT2 0x08
2038 bit LQOATNLQ 0x04
2039 bit LQOATNPKT 0x02
2040 bit LQOTCRC 0x01
2143}
2144
2145/*
2146 * Clear LQO Manager interrupt 0
2147 */
2148register CLRLQOINT0 {
2149 address 0x054
2150 access_mode WO
2151 modes M_DFF0, M_DFF1, M_SCSI
2041}
2042
2043/*
2044 * Clear LQO Manager interrupt 0
2045 */
2046register CLRLQOINT0 {
2047 address 0x054
2048 access_mode WO
2049 modes M_DFF0, M_DFF1, M_SCSI
2152 field CLRLQOTARGSCBPERR 0x10
2153 field CLRLQOSTOPT2 0x08
2154 field CLRLQOATNLQ 0x04
2155 field CLRLQOATNPKT 0x02
2156 field CLRLQOTCRC 0x01
2050 bit CLRLQOTARGSCBPERR 0x10
2051 bit CLRLQOSTOPT2 0x08
2052 bit CLRLQOATNLQ 0x04
2053 bit CLRLQOATNPKT 0x02
2054 bit CLRLQOTCRC 0x01
2157}
2158
2159/*
2160 * LQO Manager Interrupt Mode 0
2161 */
2162register LQOMODE0 {
2163 address 0x054
2164 access_mode RW
2165 modes M_CFG
2055}
2056
2057/*
2058 * LQO Manager Interrupt Mode 0
2059 */
2060register LQOMODE0 {
2061 address 0x054
2062 access_mode RW
2063 modes M_CFG
2166 field ENLQOTARGSCBPERR 0x10
2167 field ENLQOSTOPT2 0x08
2168 field ENLQOATNLQ 0x04
2169 field ENLQOATNPKT 0x02
2170 field ENLQOTCRC 0x01
2064 bit ENLQOTARGSCBPERR 0x10
2065 bit ENLQOSTOPT2 0x08
2066 bit ENLQOATNLQ 0x04
2067 bit ENLQOATNPKT 0x02
2068 bit ENLQOTCRC 0x01
2171}
2172
2173/*
2174 * LQO Manager Status 1
2175 */
2176register LQOSTAT1 {
2177 address 0x055
2178 access_mode RO
2179 modes M_DFF0, M_DFF1, M_SCSI
2069}
2070
2071/*
2072 * LQO Manager Status 1
2073 */
2074register LQOSTAT1 {
2075 address 0x055
2076 access_mode RO
2077 modes M_DFF0, M_DFF1, M_SCSI
2180 field LQOINITSCBPERR 0x10
2181 field LQOSTOPI2 0x08
2182 field LQOBADQAS 0x04
2183 field LQOBUSFREE 0x02
2184 field LQOPHACHGINPKT 0x01
2078 bit LQOINITSCBPERR 0x10
2079 bit LQOSTOPI2 0x08
2080 bit LQOBADQAS 0x04
2081 bit LQOBUSFREE 0x02
2082 bit LQOPHACHGINPKT 0x01
2185}
2186
2187/*
2188 * Clear LOQ Interrupt 1
2189 */
2190register CLRLQOINT1 {
2191 address 0x055
2192 access_mode WO
2193 modes M_DFF0, M_DFF1, M_SCSI
2083}
2084
2085/*
2086 * Clear LOQ Interrupt 1
2087 */
2088register CLRLQOINT1 {
2089 address 0x055
2090 access_mode WO
2091 modes M_DFF0, M_DFF1, M_SCSI
2194 field CLRLQOINITSCBPERR 0x10
2195 field CLRLQOSTOPI2 0x08
2196 field CLRLQOBADQAS 0x04
2197 field CLRLQOBUSFREE 0x02
2198 field CLRLQOPHACHGINPKT 0x01
2092 bit CLRLQOINITSCBPERR 0x10
2093 bit CLRLQOSTOPI2 0x08
2094 bit CLRLQOBADQAS 0x04
2095 bit CLRLQOBUSFREE 0x02
2096 bit CLRLQOPHACHGINPKT 0x01
2199}
2200
2201/*
2202 * LQO Manager Interrupt Mode 1
2203 */
2204register LQOMODE1 {
2205 address 0x055
2206 access_mode RW
2207 modes M_CFG
2097}
2098
2099/*
2100 * LQO Manager Interrupt Mode 1
2101 */
2102register LQOMODE1 {
2103 address 0x055
2104 access_mode RW
2105 modes M_CFG
2208 field ENLQOINITSCBPERR 0x10
2209 field ENLQOSTOPI2 0x08
2210 field ENLQOBADQAS 0x04
2211 field ENLQOBUSFREE 0x02
2212 field ENLQOPHACHGINPKT 0x01
2106 bit ENLQOINITSCBPERR 0x10
2107 bit ENLQOSTOPI2 0x08
2108 bit ENLQOBADQAS 0x04
2109 bit ENLQOBUSFREE 0x02
2110 bit ENLQOPHACHGINPKT 0x01
2213}
2214
2215/*
2216 * LQO Manager Status 2
2217 */
2218register LQOSTAT2 {
2219 address 0x056
2220 access_mode RO
2221 modes M_DFF0, M_DFF1, M_SCSI
2111}
2112
2113/*
2114 * LQO Manager Status 2
2115 */
2116register LQOSTAT2 {
2117 address 0x056
2118 access_mode RO
2119 modes M_DFF0, M_DFF1, M_SCSI
2222 field LQOPKT 0xE0
2223 field LQOWAITFIFO 0x10
2224 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */
2225 field LQOSTOP0 0x01 /* Stopped after sending all packets */
2120 mask LQOPKT 0xE0
2121 bit LQOWAITFIFO 0x10
2122 bit LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */
2123 bit LQOSTOP0 0x01 /* Stopped after sending all packets */
2226}
2227
2228/*
2229 * Output Synchronizer Space Count
2230 */
2231register OS_SPACE_CNT {
2232 address 0x056
2233 access_mode RO

--- 4 unchanged lines hidden (view full) ---

2238 * SCSI Interrupt Mode 1
2239 * Setting any bit will enable the corresponding function
2240 * in SIMODE1 to interrupt via the IRQ pin.
2241 */
2242register SIMODE1 {
2243 address 0x057
2244 access_mode RW
2245 modes M_DFF0, M_DFF1, M_SCSI
2124}
2125
2126/*
2127 * Output Synchronizer Space Count
2128 */
2129register OS_SPACE_CNT {
2130 address 0x056
2131 access_mode RO

--- 4 unchanged lines hidden (view full) ---

2136 * SCSI Interrupt Mode 1
2137 * Setting any bit will enable the corresponding function
2138 * in SIMODE1 to interrupt via the IRQ pin.
2139 */
2140register SIMODE1 {
2141 address 0x057
2142 access_mode RW
2143 modes M_DFF0, M_DFF1, M_SCSI
2246 field ENSELTIMO 0x80
2247 field ENATNTARG 0x40
2248 field ENSCSIRST 0x20
2249 field ENPHASEMIS 0x10
2250 field ENBUSFREE 0x08
2251 field ENSCSIPERR 0x04
2252 field ENSTRB2FAST 0x02
2253 field ENREQINIT 0x01
2144 bit ENSELTIMO 0x80
2145 bit ENATNTARG 0x40
2146 bit ENSCSIRST 0x20
2147 bit ENPHASEMIS 0x10
2148 bit ENBUSFREE 0x08
2149 bit ENSCSIPERR 0x04
2150 bit ENSTRB2FAST 0x02
2151 bit ENREQINIT 0x01
2254}
2255
2256/*
2257 * Good Status FIFO
2258 */
2259register GSFIFO {
2260 address 0x058
2261 access_mode RO
2262 size 2
2263 modes M_DFF0, M_DFF1, M_SCSI
2264}
2265
2266/*
2267 * Data FIFO SCSI Transfer Control
2268 */
2269register DFFSXFRCTL {
2270 address 0x05A
2271 access_mode RW
2272 modes M_DFF0, M_DFF1
2152}
2153
2154/*
2155 * Good Status FIFO
2156 */
2157register GSFIFO {
2158 address 0x058
2159 access_mode RO
2160 size 2
2161 modes M_DFF0, M_DFF1, M_SCSI
2162}
2163
2164/*
2165 * Data FIFO SCSI Transfer Control
2166 */
2167register DFFSXFRCTL {
2168 address 0x05A
2169 access_mode RW
2170 modes M_DFF0, M_DFF1
2273 field DFFBITBUCKET 0x08
2274 field CLRSHCNT 0x04
2275 field CLRCHN 0x02
2276 field RSTCHN 0x01
2171 bit CLRSHCNT 0x04
2172 bit CLRCHN 0x02
2173 bit RSTCHN 0x01
2277}
2278
2279/*
2280 * Next SCSI Control Block
2281 */
2282register NEXTSCB {
2283 address 0x05A
2284 access_mode RW
2285 size 2
2286 modes M_SCSI
2287}
2174}
2175
2176/*
2177 * Next SCSI Control Block
2178 */
2179register NEXTSCB {
2180 address 0x05A
2181 access_mode RW
2182 size 2
2183 modes M_SCSI
2184}
2288
2289/* Rev B only. */
2290register LQOSCSCTL {
2291 address 0x05A
2292 access_mode RW
2293 size 1
2294 modes M_CFG
2295 field LQOH2A_VERSION 0x80
2296 field LQONOCHKOVER 0x01
2297}
2298
2185
2299/*
2300 * SEQ Interrupts
2301 */
2302register SEQINTSRC {
2303 address 0x05B
2304 access_mode RO
2305 modes M_DFF0, M_DFF1
2186/*
2187 * SEQ Interrupts
2188 */
2189register SEQINTSRC {
2190 address 0x05B
2191 access_mode RO
2192 modes M_DFF0, M_DFF1
2306 field CTXTDONE 0x40
2307 field SAVEPTRS 0x20
2308 field CFG4DATA 0x10
2309 field CFG4ISTAT 0x08
2310 field CFG4TSTAT 0x04
2311 field CFG4ICMD 0x02
2312 field CFG4TCMD 0x01
2193 bit CTXTDONE 0x40
2194 bit SAVEPTRS 0x20
2195 bit CFG4DATA 0x10
2196 bit CFG4ISTAT 0x08
2197 bit CFG4TSTAT 0x04
2198 bit CFG4ICMD 0x02
2199 bit CFG4TCMD 0x01
2313}
2314
2315/*
2316 * Clear Arp Interrupts
2317 */
2318register CLRSEQINTSRC {
2319 address 0x05B
2320 access_mode WO
2321 modes M_DFF0, M_DFF1
2200}
2201
2202/*
2203 * Clear Arp Interrupts
2204 */
2205register CLRSEQINTSRC {
2206 address 0x05B
2207 access_mode WO
2208 modes M_DFF0, M_DFF1
2322 field CLRCTXTDONE 0x40
2323 field CLRSAVEPTRS 0x20
2324 field CLRCFG4DATA 0x10
2325 field CLRCFG4ISTAT 0x08
2326 field CLRCFG4TSTAT 0x04
2327 field CLRCFG4ICMD 0x02
2328 field CLRCFG4TCMD 0x01
2209 bit CLRCTXTDONE 0x40
2210 bit CLRSAVEPTRS 0x20
2211 bit CLRCFG4DATA 0x10
2212 bit CLRCFG4ISTAT 0x08
2213 bit CLRCFG4TSTAT 0x04
2214 bit CLRCFG4ICMD 0x02
2215 bit CLRCFG4TCMD 0x01
2329}
2330
2331/*
2332 * SEQ Interrupt Enabled (Shared)
2333 */
2334register SEQIMODE {
2335 address 0x05C
2336 access_mode RW
2337 modes M_DFF0, M_DFF1
2216}
2217
2218/*
2219 * SEQ Interrupt Enabled (Shared)
2220 */
2221register SEQIMODE {
2222 address 0x05C
2223 access_mode RW
2224 modes M_DFF0, M_DFF1
2338 field ENCTXTDONE 0x40
2339 field ENSAVEPTRS 0x20
2340 field ENCFG4DATA 0x10
2341 field ENCFG4ISTAT 0x08
2342 field ENCFG4TSTAT 0x04
2343 field ENCFG4ICMD 0x02
2344 field ENCFG4TCMD 0x01
2225 bit ENCTXTDONE 0x40
2226 bit ENSAVEPTRS 0x20
2227 bit ENCFG4DATA 0x10
2228 bit ENCFG4ISTAT 0x08
2229 bit ENCFG4TSTAT 0x04
2230 bit ENCFG4ICMD 0x02
2231 bit ENCFG4TCMD 0x01
2345}
2346
2347/*
2348 * Current SCSI Control Block
2349 */
2350register CURRSCB {
2351 address 0x05C
2352 access_mode RW
2353 size 2
2354 modes M_SCSI
2355}
2356
2357/*
2358 * Data FIFO Status
2359 */
2360register MDFFSTAT {
2361 address 0x05D
2362 access_mode RO
2363 modes M_DFF0, M_DFF1
2232}
2233
2234/*
2235 * Current SCSI Control Block
2236 */
2237register CURRSCB {
2238 address 0x05C
2239 access_mode RW
2240 size 2
2241 modes M_SCSI
2242}
2243
2244/*
2245 * Data FIFO Status
2246 */
2247register MDFFSTAT {
2248 address 0x05D
2249 access_mode RO
2250 modes M_DFF0, M_DFF1
2364 field SHCNTNEGATIVE 0x40 /* Rev B or higher */
2365 field SHCNTMINUS1 0x20 /* Rev B or higher */
2366 field LASTSDONE 0x10
2367 field SHVALID 0x08
2368 field DLZERO 0x04 /* FIFO data ends on packet boundary. */
2369 field DATAINFIFO 0x02
2370 field FIFOFREE 0x01
2251 bit LASTSDONE 0x10
2252 bit SHVALID 0x08
2253 bit DLZERO 0x04 /* FIFO data ends on packet boundary. */
2254 bit DATAINFIFO 0x02
2255 bit FIFOFREE 0x01
2371}
2372
2373/*
2374 * CRC Control
2375 */
2376register CRCCONTROL {
2377 address 0x05d
2378 access_mode RW
2379 modes M_CFG
2256}
2257
2258/*
2259 * CRC Control
2260 */
2261register CRCCONTROL {
2262 address 0x05d
2263 access_mode RW
2264 modes M_CFG
2380 field CRCVALCHKEN 0x40
2265 bit CRCVALCHKEN 0x40
2381}
2382
2383/*
2384 * SCSI Test Control
2385 */
2386register SCSITEST {
2387 address 0x05E
2388 access_mode RW
2389 modes M_CFG
2266}
2267
2268/*
2269 * SCSI Test Control
2270 */
2271register SCSITEST {
2272 address 0x05E
2273 access_mode RW
2274 modes M_CFG
2390 field CNTRTEST 0x08
2391 field SEL_TXPLL_DEBUG 0x04
2275 bit CNTRTEST 0x08
2276 bit SEL_TXPLL_DEBUG 0x04
2392}
2393
2394/*
2395 * Data FIFO Queue Tag
2396 */
2397register DFFTAG {
2398 address 0x05E
2399 access_mode RW

--- 13 unchanged lines hidden (view full) ---

2413
2414/*
2415 * SCSI I/O Cell Power-down Control
2416 */
2417register IOPDNCTL {
2418 address 0x05F
2419 access_mode RW
2420 modes M_CFG
2277}
2278
2279/*
2280 * Data FIFO Queue Tag
2281 */
2282register DFFTAG {
2283 address 0x05E
2284 access_mode RW

--- 13 unchanged lines hidden (view full) ---

2298
2299/*
2300 * SCSI I/O Cell Power-down Control
2301 */
2302register IOPDNCTL {
2303 address 0x05F
2304 access_mode RW
2305 modes M_CFG
2421 field DISABLE_OE 0x80
2422 field PDN_IDIST 0x04
2423 field PDN_DIFFSENSE 0x01
2306 bit DISABLE_OE 0x80
2307 bit PDN_IDIST 0x04
2308 bit PDN_DIFFSENSE 0x01
2424}
2425
2426/*
2427 * Shaddow Host Address.
2428 */
2429register SHADDR {
2430 address 0x060
2431 access_mode RO

--- 50 unchanged lines hidden (view full) ---

2482
2483/*
2484 * Data Transfer Negotiation Data - PPR Options
2485 */
2486register NEGPPROPTS {
2487 address 0x063
2488 access_mode RW
2489 modes M_SCSI
2309}
2310
2311/*
2312 * Shaddow Host Address.
2313 */
2314register SHADDR {
2315 address 0x060
2316 access_mode RO

--- 50 unchanged lines hidden (view full) ---

2367
2368/*
2369 * Data Transfer Negotiation Data - PPR Options
2370 */
2371register NEGPPROPTS {
2372 address 0x063
2373 access_mode RW
2374 modes M_SCSI
2490 field PPROPT_PACE 0x08
2491 field PPROPT_QAS 0x04
2492 field PPROPT_DT 0x02
2493 field PPROPT_IUT 0x01
2375 bit PPROPT_PACE 0x08
2376 bit PPROPT_QAS 0x04
2377 bit PPROPT_DT 0x02
2378 bit PPROPT_IUT 0x01
2494}
2495
2496/*
2497 * Data Transfer Negotiation Data - Connection Options
2498 */
2499register NEGCONOPTS {
2500 address 0x064
2501 access_mode RW
2502 modes M_SCSI
2379}
2380
2381/*
2382 * Data Transfer Negotiation Data - Connection Options
2383 */
2384register NEGCONOPTS {
2385 address 0x064
2386 access_mode RW
2387 modes M_SCSI
2503 field ENSNAPSHOT 0x40
2504 field RTI_WRTDIS 0x20
2505 field RTI_OVRDTRN 0x10
2506 field ENSLOWCRC 0x08
2507 field ENAUTOATNI 0x04
2508 field ENAUTOATNO 0x02
2509 field WIDEXFER 0x01
2388 bit ENAIP 0x08
2389 bit ENAUTOATNI 0x04
2390 bit ENAUTOATNO 0x02
2391 bit WIDEXFER 0x01
2510}
2511
2512/*
2513 * Negotiation Table Annex Column Index.
2514 */
2515register ANNEXCOL {
2516 address 0x065
2517 access_mode RW
2518 modes M_SCSI
2519}
2520
2392}
2393
2394/*
2395 * Negotiation Table Annex Column Index.
2396 */
2397register ANNEXCOL {
2398 address 0x065
2399 access_mode RW
2400 modes M_SCSI
2401}
2402
2521register SCSCHKN {
2522 address 0x066
2523 access_mode RW
2524 modes M_CFG
2525 field STSELSKIDDIS 0x40
2526 field CURRFIFODEF 0x20
2527 field WIDERESEN 0x10
2528 field SDONEMSKDIS 0x08
2529 field DFFACTCLR 0x04
2530 field SHVALIDSTDIS 0x02
2531 field LSTSGCLRDIS 0x01
2532}
2533
2534const AHD_ANNEXCOL_PER_DEV0 4
2535const AHD_NUM_PER_DEV_ANNEXCOLS 4
2536const AHD_ANNEXCOL_PRECOMP_SLEW 4
2403const AHD_ANNEXCOL_PRECOMP 4
2537const AHD_PRECOMP_MASK 0x07
2404const AHD_PRECOMP_MASK 0x07
2538const AHD_PRECOMP_SHIFT 0
2539const AHD_PRECOMP_CUTBACK_17 0x04
2540const AHD_PRECOMP_CUTBACK_29 0x06
2541const AHD_PRECOMP_CUTBACK_37 0x07
2405const AHD_PRECOMP_CUTBACK_17 0x04
2406const AHD_PRECOMP_CUTBACK_29 0x06
2407const AHD_PRECOMP_CUTBACK_37 0x07
2542const AHD_SLEWRATE_MASK 0x78
2543const AHD_SLEWRATE_SHIFT 3
2544/*
2545 * Rev A has only a single bit (high bit of field) of slew adjustment.
2546 * Rev B has 4 bits. The current default happens to be the same for both.
2547 */
2548const AHD_SLEWRATE_DEF_REVA 0x08
2549const AHD_SLEWRATE_DEF_REVB 0x08
2408const AHD_PRECOMP_FASTSLEW 0x40
2409const AHD_NUM_ANNEXCOLS 4
2550
2410
2551/* Rev A does not have any amplitude setting. */
2552const AHD_ANNEXCOL_AMPLITUDE 6
2553const AHD_AMPLITUDE_MASK 0x7
2554const AHD_AMPLITUDE_SHIFT 0
2555const AHD_AMPLITUDE_DEF 0x7
2556
2557/*
2558 * Negotiation Table Annex Data Port.
2559 */
2560register ANNEXDAT {
2561 address 0x066
2562 access_mode RW
2563 modes M_SCSI
2564}

--- 10 unchanged lines hidden (view full) ---

2575
2576/*
2577 * 960MHz Phase-Locked Loop Control 0
2578 */
2579register PLL960CTL0 {
2580 address 0x068
2581 access_mode RW
2582 modes M_CFG
2411/*
2412 * Negotiation Table Annex Data Port.
2413 */
2414register ANNEXDAT {
2415 address 0x066
2416 access_mode RW
2417 modes M_SCSI
2418}

--- 10 unchanged lines hidden (view full) ---

2429
2430/*
2431 * 960MHz Phase-Locked Loop Control 0
2432 */
2433register PLL960CTL0 {
2434 address 0x068
2435 access_mode RW
2436 modes M_CFG
2583 field PLL_VCOSEL 0x80
2584 field PLL_PWDN 0x40
2585 field PLL_NS 0x30
2586 field PLL_ENLUD 0x08
2587 field PLL_ENLPF 0x04
2588 field PLL_DLPF 0x02
2589 field PLL_ENFBM 0x01
2437 bit PLL_VCOSEL 0x80
2438 bit PLL_PWDN 0x40
2439 mask PLL_NS 0x30
2440 bit PLL_ENLUD 0x08
2441 bit PLL_ENLPF 0x04
2442 bit PLL_DLPF 0x02
2443 bit PLL_ENFBM 0x01
2590}
2591
2592/*
2593 * Target Own Id
2594 */
2595register TOWNID {
2596 address 0x069
2597 access_mode RW
2598 modes M_SCSI
2599}
2600
2601/*
2602 * 960MHz Phase-Locked Loop Control 1
2603 */
2604register PLL960CTL1 {
2605 address 0x069
2606 access_mode RW
2607 modes M_CFG
2444}
2445
2446/*
2447 * Target Own Id
2448 */
2449register TOWNID {
2450 address 0x069
2451 access_mode RW
2452 modes M_SCSI
2453}
2454
2455/*
2456 * 960MHz Phase-Locked Loop Control 1
2457 */
2458register PLL960CTL1 {
2459 address 0x069
2460 access_mode RW
2461 modes M_CFG
2608 field PLL_CNTEN 0x80
2609 field PLL_CNTCLR 0x40
2610 field PLL_RST 0x01
2462 bit PLL_CNTEN 0x80
2463 bit PLL_CNTCLR 0x40
2464 bit PLL_RST 0x01
2611}
2612
2613/*
2614 * Expander Signature
2615 */
2616register XSIG {
2617 address 0x06A
2618 access_mode RW

--- 31 unchanged lines hidden (view full) ---

2650
2651/*
2652 * 400-MHz Phase-Locked Loop Control 0
2653 */
2654register PLL400CTL0 {
2655 address 0x06C
2656 access_mode RW
2657 modes M_CFG
2465}
2466
2467/*
2468 * Expander Signature
2469 */
2470register XSIG {
2471 address 0x06A
2472 access_mode RW

--- 31 unchanged lines hidden (view full) ---

2504
2505/*
2506 * 400-MHz Phase-Locked Loop Control 0
2507 */
2508register PLL400CTL0 {
2509 address 0x06C
2510 access_mode RW
2511 modes M_CFG
2658 field PLL_VCOSEL 0x80
2659 field PLL_PWDN 0x40
2660 field PLL_NS 0x30
2661 field PLL_ENLUD 0x08
2662 field PLL_ENLPF 0x04
2663 field PLL_DLPF 0x02
2664 field PLL_ENFBM 0x01
2512 bit PLL_VCOSEL 0x80
2513 bit PLL_PWDN 0x40
2514 mask PLL_NS 0x30
2515 bit PLL_ENLUD 0x08
2516 bit PLL_ENLPF 0x04
2517 bit PLL_DLPF 0x02
2518 bit PLL_ENFBM 0x01
2665}
2666
2667/*
2668 * Arbitration Fairness
2669 */
2670register FAIRNESS {
2671 address 0x06C
2672 access_mode RW
2673 size 2
2674 modes M_SCSI
2675}
2676
2677/*
2678 * 400-MHz Phase-Locked Loop Control 1
2679 */
2680register PLL400CTL1 {
2681 address 0x06D
2682 access_mode RW
2683 modes M_CFG
2519}
2520
2521/*
2522 * Arbitration Fairness
2523 */
2524register FAIRNESS {
2525 address 0x06C
2526 access_mode RW
2527 size 2
2528 modes M_SCSI
2529}
2530
2531/*
2532 * 400-MHz Phase-Locked Loop Control 1
2533 */
2534register PLL400CTL1 {
2535 address 0x06D
2536 access_mode RW
2537 modes M_CFG
2684 field PLL_CNTEN 0x80
2685 field PLL_CNTCLR 0x40
2686 field PLL_RST 0x01
2538 bit PLL_CNTEN 0x80
2539 bit PLL_CNTCLR 0x40
2540 bit PLL_RST 0x01
2687}
2688
2689/*
2690 * Arbitration Unfairness
2691 */
2692register UNFAIRNESS {
2693 address 0x06E
2694 access_mode RW

--- 37 unchanged lines hidden (view full) ---

2732 * SCB-Next Address Snooping logic. When an SCB is transferred to
2733 * the card, the next SCB address to be used by the CMC array can
2734 * be autoloaded from that transfer.
2735 */
2736register SCBAUTOPTR {
2737 address 0x0AB
2738 access_mode RW
2739 modes M_CFG
2541}
2542
2543/*
2544 * Arbitration Unfairness
2545 */
2546register UNFAIRNESS {
2547 address 0x06E
2548 access_mode RW

--- 37 unchanged lines hidden (view full) ---

2586 * SCB-Next Address Snooping logic. When an SCB is transferred to
2587 * the card, the next SCB address to be used by the CMC array can
2588 * be autoloaded from that transfer.
2589 */
2590register SCBAUTOPTR {
2591 address 0x0AB
2592 access_mode RW
2593 modes M_CFG
2740 field AUSCBPTR_EN 0x80
2741 field SCBPTR_ADDR 0x38
2742 field SCBPTR_OFF 0x07
2594 bit AUSCBPTR_EN 0x80
2595 mask SCBPTR_ADDR 0x38
2596 mask SCBPTR_OFF 0x07
2743}
2744
2745/*
2746 * CMC SG Ram Address Pointer
2747 */
2748register CCSGADDR {
2749 address 0x0AC
2750 access_mode RW

--- 22 unchanged lines hidden (view full) ---

2773
2774/*
2775 * CMC SG Control
2776 */
2777register CCSGCTL {
2778 address 0x0AD
2779 access_mode RW
2780 modes M_DFF0, M_DFF1
2597}
2598
2599/*
2600 * CMC SG Ram Address Pointer
2601 */
2602register CCSGADDR {
2603 address 0x0AC
2604 access_mode RW

--- 22 unchanged lines hidden (view full) ---

2627
2628/*
2629 * CMC SG Control
2630 */
2631register CCSGCTL {
2632 address 0x0AD
2633 access_mode RW
2634 modes M_DFF0, M_DFF1
2781 field CCSGDONE 0x80
2782 field SG_CACHE_AVAIL 0x10
2783 field CCSGENACK 0x08
2784 mask CCSGEN 0x0C
2785 field SG_FETCH_REQ 0x02
2786 field CCSGRESET 0x01
2635 bit CCSGDONE 0x80
2636 bit SG_CACHE_AVAIL 0x10
2637 bit CCSGEN 0x08
2638 bit SG_FETCH_REQ 0x02
2639 bit CCSGRESET 0x01
2787}
2788
2789/*
2790 * CMD SCB Control
2791 */
2792register CCSCBCTL {
2793 address 0x0AD
2794 access_mode RW
2795 modes M_CCHAN
2640}
2641
2642/*
2643 * CMD SCB Control
2644 */
2645register CCSCBCTL {
2646 address 0x0AD
2647 access_mode RW
2648 modes M_CCHAN
2796 field CCSCBDONE 0x80
2797 field ARRDONE 0x40
2798 field CCARREN 0x10
2799 field CCSCBEN 0x08
2800 field CCSCBDIR 0x04
2801 field CCSCBRESET 0x01
2649 bit CCSCBDONE 0x80
2650 bit ARRDONE 0x40
2651 bit CCARREN 0x10
2652 bit CCSCBEN 0x08
2653 bit CCSCBDIR 0x04
2654 bit CCSCBRESET 0x01
2802}
2803
2804/*
2805 * CMC Ram BIST
2806 */
2807register CMC_RAMBIST {
2808 address 0x0AD
2809 access_mode RW
2810 modes M_CFG
2655}
2656
2657/*
2658 * CMC Ram BIST
2659 */
2660register CMC_RAMBIST {
2661 address 0x0AD
2662 access_mode RW
2663 modes M_CFG
2811 field SG_ELEMENT_SIZE 0x80
2812 field SCBRAMBIST_FAIL 0x40
2813 field SG_BIST_FAIL 0x20
2814 field SG_BIST_EN 0x10
2815 field CMC_BUFFER_BIST_FAIL 0x02
2816 field CMC_BUFFER_BIST_EN 0x01
2664 bit SG_ELEMENT_SIZE 0x80
2665 bit SCBRAMBIST_FAIL 0x40
2666 bit SG_BIST_FAIL 0x20
2667 bit SG_BIST_EN 0x10
2668 bit CMC_BUFFER_BIST_FAIL 0x02
2669 bit CMC_BUFFER_BIST_EN 0x01
2817}
2818
2819/*
2820 * CMC SG RAM Data Port
2821 */
2822register CCSGRAM {
2823 address 0x0B0
2824 access_mode RW

--- 31 unchanged lines hidden (view full) ---

2856
2857/*
2858 * Flex DMA Status
2859 */
2860register FLEXDMASTAT {
2861 address 0x0B5
2862 access_mode RW
2863 modes M_SCSI
2670}
2671
2672/*
2673 * CMC SG RAM Data Port
2674 */
2675register CCSGRAM {
2676 address 0x0B0
2677 access_mode RW

--- 31 unchanged lines hidden (view full) ---

2709
2710/*
2711 * Flex DMA Status
2712 */
2713register FLEXDMASTAT {
2714 address 0x0B5
2715 access_mode RW
2716 modes M_SCSI
2864 field FLEXDMAERR 0x02
2865 field FLEXDMADONE 0x01
2717 bit FLEXDMAERR 0x02
2718 bit FLEXDMADONE 0x01
2866}
2867
2868/*
2869 * Flex DMA Data Port
2870 */
2871register FLEXDATA {
2872 address 0x0B6
2873 access_mode RW

--- 11 unchanged lines hidden (view full) ---

2885
2886/*
2887 * Board Control
2888 */
2889register BRDCTL {
2890 address 0x0B9
2891 access_mode RW
2892 modes M_SCSI
2719}
2720
2721/*
2722 * Flex DMA Data Port
2723 */
2724register FLEXDATA {
2725 address 0x0B6
2726 access_mode RW

--- 11 unchanged lines hidden (view full) ---

2738
2739/*
2740 * Board Control
2741 */
2742register BRDCTL {
2743 address 0x0B9
2744 access_mode RW
2745 modes M_SCSI
2893 field FLXARBACK 0x80
2894 field FLXARBREQ 0x40
2895 field BRDADDR 0x38
2896 field BRDEN 0x04
2897 field BRDRW 0x02
2898 field BRDSTB 0x01
2746 bit FLXARBACK 0x80
2747 bit FLXARBREQ 0x40
2748 mask BRDADDR 0x38
2749 bit BRDEN 0x04
2750 bit BRDRW 0x02
2751 bit BRDSTB 0x01
2899}
2900
2901/*
2902 * Serial EEPROM Address
2903 */
2904register SEEADR {
2905 address 0x0BA
2906 access_mode RW

--- 12 unchanged lines hidden (view full) ---

2919
2920/*
2921 * Serial EEPROM Status
2922 */
2923register SEESTAT {
2924 address 0x0BE
2925 access_mode RO
2926 modes M_SCSI
2752}
2753
2754/*
2755 * Serial EEPROM Address
2756 */
2757register SEEADR {
2758 address 0x0BA
2759 access_mode RW

--- 12 unchanged lines hidden (view full) ---

2772
2773/*
2774 * Serial EEPROM Status
2775 */
2776register SEESTAT {
2777 address 0x0BE
2778 access_mode RO
2779 modes M_SCSI
2927 field INIT_DONE 0x80
2928 field SEEOPCODE 0x70
2929 field LDALTID_L 0x08
2930 field SEEARBACK 0x04
2931 field SEEBUSY 0x02
2932 field SEESTART 0x01
2780 bit INIT_DONE 0x80
2781 mask SEEOPCODE 0x70
2782 bit LDALTID_L 0x08
2783 bit SEEARBACK 0x04
2784 bit SEEBUSY 0x02
2785 bit SEESTART 0x01
2933}
2934
2935/*
2936 * Serial EEPROM Control
2937 */
2938register SEECTL {
2939 address 0x0BE
2940 access_mode RW
2941 modes M_SCSI
2786}
2787
2788/*
2789 * Serial EEPROM Control
2790 */
2791register SEECTL {
2792 address 0x0BE
2793 access_mode RW
2794 modes M_SCSI
2942 field SEEOPCODE 0x70 {
2943 SEEOP_ERASE 0x70,
2944 SEEOP_READ 0x60,
2945 SEEOP_WRITE 0x50,
2795 mask SEEOPCODE 0x70
2796 mask SEEOP_ERASE 0x70
2797 mask SEEOP_READ 0x60
2798 mask SEEOP_WRITE 0x50
2946 /*
2947 * The following four commands use special
2948 * addresses for differentiation.
2949 */
2799 /*
2800 * The following four commands use special
2801 * addresses for differentiation.
2802 */
2950 SEEOP_ERAL 0x40
2951 }
2803 mask SEEOP_ERAL 0x40
2952 mask SEEOP_EWEN 0x40
2953 mask SEEOP_WALL 0x40
2954 mask SEEOP_EWDS 0x40
2804 mask SEEOP_EWEN 0x40
2805 mask SEEOP_WALL 0x40
2806 mask SEEOP_EWDS 0x40
2955 field SEERST 0x02
2956 field SEESTART 0x01
2807 bit SEERST 0x02
2808 bit SEESTART 0x01
2957}
2958
2959const SEEOP_ERAL_ADDR 0x80
2960const SEEOP_EWEN_ADDR 0xC0
2961const SEEOP_WRAL_ADDR 0x40
2962const SEEOP_EWDS_ADDR 0x00
2963
2964/*

--- 18 unchanged lines hidden (view full) ---

2983
2984/*
2985 * DSP Filter Control
2986 */
2987register DSPFLTRCTL {
2988 address 0x0C0
2989 access_mode RW
2990 modes M_CFG
2809}
2810
2811const SEEOP_ERAL_ADDR 0x80
2812const SEEOP_EWEN_ADDR 0xC0
2813const SEEOP_WRAL_ADDR 0x40
2814const SEEOP_EWDS_ADDR 0x00
2815
2816/*

--- 18 unchanged lines hidden (view full) ---

2835
2836/*
2837 * DSP Filter Control
2838 */
2839register DSPFLTRCTL {
2840 address 0x0C0
2841 access_mode RW
2842 modes M_CFG
2991 field FLTRDISABLE 0x20
2992 field EDGESENSE 0x10
2993 field DSPFCNTSEL 0x0F
2843 bit FLTRDISABLE 0x20
2844 bit EDGESENSE 0x10
2845 mask DSPFCNTSEL 0x0F
2994}
2995
2996/*
2997 * DSP Data Channel Control
2998 */
2999register DSPDATACTL {
3000 address 0x0C1
3001 access_mode RW
3002 modes M_CFG
2846}
2847
2848/*
2849 * DSP Data Channel Control
2850 */
2851register DSPDATACTL {
2852 address 0x0C1
2853 access_mode RW
2854 modes M_CFG
3003 field BYPASSENAB 0x80
3004 field DESQDIS 0x10
3005 field RCVROFFSTDIS 0x04
3006 field XMITOFFSTDIS 0x02
2855 bit BYPASSENAB 0x80
2856 bit DESQDIS 0x10
2857 bit RCVROFFSTDIS 0x04
2858 bit XMITOFFSTDIS 0x02
3007}
3008
3009/*
3010 * Data FIFO Read Address
3011 * Pointer to the next QWD location to be read from the data FIFO.
3012 */
3013register DFRADDR {
3014 address 0x0C2

--- 4 unchanged lines hidden (view full) ---

3019
3020/*
3021 * DSP REQ Control
3022 */
3023register DSPREQCTL {
3024 address 0x0C2
3025 access_mode RW
3026 modes M_CFG
2859}
2860
2861/*
2862 * Data FIFO Read Address
2863 * Pointer to the next QWD location to be read from the data FIFO.
2864 */
2865register DFRADDR {
2866 address 0x0C2

--- 4 unchanged lines hidden (view full) ---

2871
2872/*
2873 * DSP REQ Control
2874 */
2875register DSPREQCTL {
2876 address 0x0C2
2877 access_mode RW
2878 modes M_CFG
3027 field MANREQCTL 0xC0
3028 field MANREQDLY 0x3F
2879 mask MANREQCTL 0xC0
2880 mask MANREQDLY 0x3F
3029}
3030
3031/*
3032 * DSP ACK Control
3033 */
3034register DSPACKCTL {
3035 address 0x0C3
3036 access_mode RW
3037 modes M_CFG
2881}
2882
2883/*
2884 * DSP ACK Control
2885 */
2886register DSPACKCTL {
2887 address 0x0C3
2888 access_mode RW
2889 modes M_CFG
3038 field MANACKCTL 0xC0
3039 field MANACKDLY 0x3F
2890 mask MANACKCTL 0xC0
2891 mask MANACKDLY 0x3F
3040}
3041
3042/*
3043 * Data FIFO Data
3044 * Read/Write byte port into the data FIFO. The read and write
3045 * FIFO pointers increment with each read and write respectively
3046 * to this port.
3047 */

--- 5 unchanged lines hidden (view full) ---

3053
3054/*
3055 * DSP Channel Select
3056 */
3057register DSPSELECT {
3058 address 0x0C4
3059 access_mode RW
3060 modes M_CFG
2892}
2893
2894/*
2895 * Data FIFO Data
2896 * Read/Write byte port into the data FIFO. The read and write
2897 * FIFO pointers increment with each read and write respectively
2898 * to this port.
2899 */

--- 5 unchanged lines hidden (view full) ---

2905
2906/*
2907 * DSP Channel Select
2908 */
2909register DSPSELECT {
2910 address 0x0C4
2911 access_mode RW
2912 modes M_CFG
3061 field AUTOINCEN 0x80
3062 field DSPSEL 0x1F
2913 bit AUTOINCEN 0x80
2914 mask DSPSEL 0x1F
3063}
3064
3065const NUMDSPS 0x14
3066
3067/*
3068 * Write Bias Control
3069 */
3070register WRTBIASCTL {
3071 address 0x0C5
3072 access_mode WO
3073 modes M_CFG
2915}
2916
2917const NUMDSPS 0x14
2918
2919/*
2920 * Write Bias Control
2921 */
2922register WRTBIASCTL {
2923 address 0x0C5
2924 access_mode WO
2925 modes M_CFG
3074 field AUTOXBCDIS 0x80
3075 field XMITMANVAL 0x3F
2926 bit AUTOXBCDIS 0x80
2927 mask XMITMANVAL 0x3F
3076}
3077
2928}
2929
3078/*
3079 * Currently the WRTBIASCTL is the same as the default.
3080 */
3081const WRTBIASCTL_HP_DEFAULT 0x0
2930const WRTBIASCTL_CPQ_DEFAULT 0x97
3082
3083/*
3084 * Receiver Bias Control
3085 */
3086register RCVRBIOSCTL {
3087 address 0x0C6
3088 access_mode WO
3089 modes M_CFG
2931
2932/*
2933 * Receiver Bias Control
2934 */
2935register RCVRBIOSCTL {
2936 address 0x0C6
2937 access_mode WO
2938 modes M_CFG
3090 field AUTORBCDIS 0x80
3091 field RCVRMANVAL 0x3F
2939 bit AUTORBCDIS 0x80
2940 mask RCVRMANVAL 0x3F
3092}
3093
3094/*
3095 * Write Bias Calculator
3096 */
3097register WRTBIASCALC {
3098 address 0x0C7
3099 access_mode RO

--- 16 unchanged lines hidden (view full) ---

3116 */
3117register RCVRBIASCALC {
3118 address 0x0C8
3119 access_mode RO
3120 modes M_CFG
3121}
3122
3123/*
2941}
2942
2943/*
2944 * Write Bias Calculator
2945 */
2946register WRTBIASCALC {
2947 address 0x0C7
2948 access_mode RO

--- 16 unchanged lines hidden (view full) ---

2965 */
2966register RCVRBIASCALC {
2967 address 0x0C8
2968 access_mode RO
2969 modes M_CFG
2970}
2971
2972/*
2973 * Data FIFO Debug Control
2974 */
2975register DFDBCTL {
2976 address 0x0C8
2977 access_mode RW
2978 modes M_DFF0, M_DFF1
2979 bit DFF_CIO_WR_RDY 0x20
2980 bit DFF_CIO_RD_RDY 0x10
2981 bit DFF_DIR_ERR 0x08
2982 bit DFF_RAMBIST_FAIL 0x04
2983 bit DFF_RAMBIST_DONE 0x02
2984 bit DFF_RAMBIST_EN 0x01
2985}
2986
2987/*
3124 * Data FIFO Backup Read Pointer
3125 * Contains the data FIFO address to be restored if the last
3126 * data accessed from the data FIFO was not transferred successfully.
3127 */
3128register DFBKPTR {
3129 address 0x0C9
3130 access_mode RW
3131 size 2

--- 5 unchanged lines hidden (view full) ---

3137 */
3138register SKEWCALC {
3139 address 0x0C9
3140 access_mode RO
3141 modes M_CFG
3142}
3143
3144/*
2988 * Data FIFO Backup Read Pointer
2989 * Contains the data FIFO address to be restored if the last
2990 * data accessed from the data FIFO was not transferred successfully.
2991 */
2992register DFBKPTR {
2993 address 0x0C9
2994 access_mode RW
2995 size 2

--- 5 unchanged lines hidden (view full) ---

3001 */
3002register SKEWCALC {
3003 address 0x0C9
3004 access_mode RO
3005 modes M_CFG
3006}
3007
3008/*
3145 * Data FIFO Debug Control
3146 */
3147register DFDBCTL {
3148 address 0x0CB
3149 access_mode RW
3150 modes M_DFF0, M_DFF1
3151 field DFF_CIO_WR_RDY 0x20
3152 field DFF_CIO_RD_RDY 0x10
3153 field DFF_DIR_ERR 0x08
3154 field DFF_RAMBIST_FAIL 0x04
3155 field DFF_RAMBIST_DONE 0x02
3156 field DFF_RAMBIST_EN 0x01
3157}
3158
3159/*
3160 * Data FIFO Space Count
3161 * Number of FIFO locations that are free.
3162 */
3163register DFSCNT {
3164 address 0x0CC
3165 access_mode RO
3166 size 2
3167 modes M_DFF0, M_DFF1

--- 24 unchanged lines hidden (view full) ---

3192/*
3193 * Sequencer Control 0
3194 * Error detection mode, speed configuration,
3195 * single step, breakpoints and program load.
3196 */
3197register SEQCTL0 {
3198 address 0x0D6
3199 access_mode RW
3009 * Data FIFO Space Count
3010 * Number of FIFO locations that are free.
3011 */
3012register DFSCNT {
3013 address 0x0CC
3014 access_mode RO
3015 size 2
3016 modes M_DFF0, M_DFF1

--- 24 unchanged lines hidden (view full) ---

3041/*
3042 * Sequencer Control 0
3043 * Error detection mode, speed configuration,
3044 * single step, breakpoints and program load.
3045 */
3046register SEQCTL0 {
3047 address 0x0D6
3048 access_mode RW
3200 field PERRORDIS 0x80
3201 field PAUSEDIS 0x40
3202 field FAILDIS 0x20
3203 field FASTMODE 0x10
3204 field BRKADRINTEN 0x08
3205 field STEP 0x04
3206 field SEQRESET 0x02
3207 field LOADRAM 0x01
3049 bit PERRORDIS 0x80
3050 bit PAUSEDIS 0x40
3051 bit FAILDIS 0x20
3052 bit FASTMODE 0x10
3053 bit BRKADRINTEN 0x08
3054 bit STEP 0x04
3055 bit SEQRESET 0x02
3056 bit LOADRAM 0x01
3208}
3209
3210/*
3211 * Sequencer Control 1
3212 * Instruction RAM Diagnostics
3213 */
3214register SEQCTL1 {
3215 address 0x0D7
3216 access_mode RW
3057}
3058
3059/*
3060 * Sequencer Control 1
3061 * Instruction RAM Diagnostics
3062 */
3063register SEQCTL1 {
3064 address 0x0D7
3065 access_mode RW
3217 field OVRLAY_DATA_CHK 0x08
3218 field RAMBIST_DONE 0x04
3219 field RAMBIST_FAIL 0x02
3220 field RAMBIST_EN 0x01
3066 bit OVRLAY_DATA_CHK 0x08
3067 bit RAMBIST_DONE 0x04
3068 bit RAMBIST_FAIL 0x02
3069 bit RAMBIST_EN 0x01
3221}
3222
3223/*
3224 * Sequencer Flags
3225 * Zero and Carry state of the ALU.
3226 */
3227register FLAGS {
3228 address 0x0D8
3229 access_mode RO
3070}
3071
3072/*
3073 * Sequencer Flags
3074 * Zero and Carry state of the ALU.
3075 */
3076register FLAGS {
3077 address 0x0D8
3078 access_mode RO
3230 field ZERO 0x02
3231 field CARRY 0x01
3079 bit ZERO 0x02
3080 bit CARRY 0x01
3232}
3233
3234/*
3235 * Sequencer Interrupt Control
3236 */
3237register SEQINTCTL {
3238 address 0x0D9
3239 access_mode RW
3081}
3082
3083/*
3084 * Sequencer Interrupt Control
3085 */
3086register SEQINTCTL {
3087 address 0x0D9
3088 access_mode RW
3240 field INTVEC1DSL 0x80
3241 field INT1_CONTEXT 0x20
3242 field SCS_SEQ_INT1M1 0x10
3243 field SCS_SEQ_INT1M0 0x08
3244 field INTMASK2 0x04
3245 field INTMASK1 0x02
3246 field IRET 0x01
3089 bit INTVEC1DSL 0x80
3090 bit INT1_CONTEXT 0x20
3091 bit SCS_SEQ_INT1M1 0x10
3092 bit SCS_SEQ_INT1M0 0x08
3093 mask INTMASK 0x06
3094 bit IRET 0x01
3247}
3248
3249/*
3250 * Sequencer RAM Data Port
3251 * Single byte window into the Sequencer Instruction Ram area starting
3252 * at the address specified by OVLYADDR. To write a full instruction word,
3253 * simply write four bytes in succession. OVLYADDR will increment after the
3254 * most significant instrution byte (the byte with the parity bit) is written.

--- 55 unchanged lines hidden (view full) ---

3310register BRKADDR0 {
3311 address 0x0E6
3312 access_mode RW
3313}
3314
3315register BRKADDR1 {
3316 address 0x0E6
3317 access_mode RW
3095}
3096
3097/*
3098 * Sequencer RAM Data Port
3099 * Single byte window into the Sequencer Instruction Ram area starting
3100 * at the address specified by OVLYADDR. To write a full instruction word,
3101 * simply write four bytes in succession. OVLYADDR will increment after the
3102 * most significant instrution byte (the byte with the parity bit) is written.

--- 55 unchanged lines hidden (view full) ---

3158register BRKADDR0 {
3159 address 0x0E6
3160 access_mode RW
3161}
3162
3163register BRKADDR1 {
3164 address 0x0E6
3165 access_mode RW
3318 field BRKDIS 0x80 /* Disable Breakpoint */
3166 bit BRKDIS 0x80 /* Disable Breakpoint */
3319}
3320
3321/*
3322 * All Ones
3323 * All reads to this register return the value 0xFF.
3324 */
3325register ALLONES {
3326 address 0x0E8

--- 123 unchanged lines hidden (view full) ---

3450 size 8
3451 modes 0, 1, 2, 3
3452 REG0 {
3453 size 2
3454 }
3455 REG1 {
3456 size 2
3457 }
3167}
3168
3169/*
3170 * All Ones
3171 * All reads to this register return the value 0xFF.
3172 */
3173register ALLONES {
3174 address 0x0E8

--- 123 unchanged lines hidden (view full) ---

3298 size 8
3299 modes 0, 1, 2, 3
3300 REG0 {
3301 size 2
3302 }
3303 REG1 {
3304 size 2
3305 }
3458 REG_ISR {
3306 REG2 {
3459 size 2
3460 }
3461 SG_STATE {
3462 size 1
3307 size 2
3308 }
3309 SG_STATE {
3310 size 1
3463 field SEGS_AVAIL 0x01
3464 field LOADING_NEEDED 0x02
3465 field FETCH_INPROG 0x04
3311 bit SEGS_AVAIL 0x01
3312 bit LOADING_NEEDED 0x02
3313 bit FETCH_INPROG 0x04
3466 }
3467 /*
3468 * Track whether the transfer byte count for
3469 * the current data phase is odd.
3470 */
3471 DATA_COUNT_ODD {
3472 size 1
3473 }
3474}
3475
3476scratch_ram {
3477 /* Mode Specific */
3478 address 0x0F8
3479 size 8
3480 modes 0, 1, 2, 3
3481 LONGJMP_ADDR {
3482 size 2
3483 }
3314 }
3315 /*
3316 * Track whether the transfer byte count for
3317 * the current data phase is odd.
3318 */
3319 DATA_COUNT_ODD {
3320 size 1
3321 }
3322}
3323
3324scratch_ram {
3325 /* Mode Specific */
3326 address 0x0F8
3327 size 8
3328 modes 0, 1, 2, 3
3329 LONGJMP_ADDR {
3330 size 2
3331 }
3332 LONGJMP_SCB {
3333 size 2
3334 }
3484 ACCUM_SAVE {
3485 size 1
3486 }
3487}
3488
3489
3490scratch_ram {
3491 address 0x100

--- 38 unchanged lines hidden (view full) ---

3530 /*
3531 * head of list of SCBs that have
3532 * completed but need to be uploaded
3533 * to the host prior to being completed.
3534 */
3535 COMPLETE_DMA_SCB_HEAD {
3536 size 2
3537 }
3335 ACCUM_SAVE {
3336 size 1
3337 }
3338}
3339
3340
3341scratch_ram {
3342 address 0x100

--- 38 unchanged lines hidden (view full) ---

3381 /*
3382 * head of list of SCBs that have
3383 * completed but need to be uploaded
3384 * to the host prior to being completed.
3385 */
3386 COMPLETE_DMA_SCB_HEAD {
3387 size 2
3388 }
3538 /*
3539 * tail of list of SCBs that have
3540 * completed but need to be uploaded
3541 * to the host prior to being completed.
3542 */
3543 COMPLETE_DMA_SCB_TAIL {
3544 size 2
3545 }
3546 /*
3547 * head of list of SCBs that have
3548 * been uploaded to the host, but cannot
3549 * be completed until the QFREEZE is in
3550 * full effect (i.e. no selections pending).
3551 */
3552 COMPLETE_ON_QFREEZE_HEAD {
3553 size 2
3554 }
3555 /*
3556 * Counting semaphore to prevent new select-outs
3557 * The queue is frozen so long as the sequencer
3558 * and kernel freeze counts differ.
3559 */
3389 /* Counting semaphore to prevent new select-outs */
3560 QFREEZE_COUNT {
3561 size 2
3562 }
3390 QFREEZE_COUNT {
3391 size 2
3392 }
3563 KERNEL_QFREEZE_COUNT {
3564 size 2
3565 }
3566 /*
3393 /*
3567 * Mode to restore on legacy idle loop exit.
3394 * Mode to restore on idle_loop exit.
3568 */
3569 SAVED_MODE {
3570 size 1
3571 }
3572 /*
3573 * Single byte buffer used to designate the type or message
3574 * to send to a target.
3575 */
3576 MSG_OUT {
3577 size 1
3578 }
3579 /* Parameters for DMA Logic */
3580 DMAPARAMS {
3581 size 1
3395 */
3396 SAVED_MODE {
3397 size 1
3398 }
3399 /*
3400 * Single byte buffer used to designate the type or message
3401 * to send to a target.
3402 */
3403 MSG_OUT {
3404 size 1
3405 }
3406 /* Parameters for DMA Logic */
3407 DMAPARAMS {
3408 size 1
3582 field PRELOADEN 0x80
3583 field WIDEODD 0x40
3584 field SCSIEN 0x20
3585 field SDMAEN 0x10
3586 field SDMAENACK 0x10
3587 field HDMAEN 0x08
3588 field HDMAENACK 0x08
3589 field DIRECTION 0x04 /* Set indicates PCI->SCSI */
3590 field FIFOFLUSH 0x02
3591 field FIFORESET 0x01
3409 bit PRELOADEN 0x80
3410 bit WIDEODD 0x40
3411 bit SCSIEN 0x20
3412 bit SDMAEN 0x10
3413 bit SDMAENACK 0x10
3414 bit HDMAEN 0x08
3415 bit HDMAENACK 0x08
3416 bit DIRECTION 0x04 /* Set indicates PCI->SCSI */
3417 bit FIFOFLUSH 0x02
3418 bit FIFORESET 0x01
3592 }
3593 SEQ_FLAGS {
3594 size 1
3419 }
3420 SEQ_FLAGS {
3421 size 1
3595 field NOT_IDENTIFIED 0x80
3596 field NO_CDB_SENT 0x40
3597 field TARGET_CMD_IS_TAGGED 0x40
3598 field DPHASE 0x20
3422 bit NOT_IDENTIFIED 0x80
3423 bit TARGET_CMD_IS_TAGGED 0x40
3424 bit NO_CDB_SENT 0x40
3425 bit DPHASE 0x20
3599 /* Target flags */
3426 /* Target flags */
3600 field TARG_CMD_PENDING 0x10
3601 field CMDPHASE_PENDING 0x08
3602 field DPHASE_PENDING 0x04
3603 field SPHASE_PENDING 0x02
3604 field NO_DISCONNECT 0x01
3427 bit TARG_CMD_PENDING 0x10
3428 bit CMDPHASE_PENDING 0x08
3429 bit DPHASE_PENDING 0x04
3430 bit SPHASE_PENDING 0x02
3431 bit NO_DISCONNECT 0x01
3605 }
3606 /*
3607 * Temporary storage for the
3608 * target/channel/lun of a
3609 * reconnecting target
3610 */
3611 SAVED_SCSIID {
3612 size 1
3613 }
3614 SAVED_LUN {
3615 size 1
3616 }
3617 /*
3618 * The last bus phase as seen by the sequencer.
3619 */
3620 LASTPHASE {
3621 size 1
3432 }
3433 /*
3434 * Temporary storage for the
3435 * target/channel/lun of a
3436 * reconnecting target
3437 */
3438 SAVED_SCSIID {
3439 size 1
3440 }
3441 SAVED_LUN {
3442 size 1
3443 }
3444 /*
3445 * The last bus phase as seen by the sequencer.
3446 */
3447 LASTPHASE {
3448 size 1
3622 field CDI 0x80
3623 field IOI 0x40
3624 field MSGI 0x20
3625 field P_BUSFREE 0x01
3626 enum PHASE_MASK CDO|IOO|MSGO {
3627 P_DATAOUT 0x0,
3628 P_DATAIN IOO,
3629 P_DATAOUT_DT P_DATAOUT|MSGO,
3630 P_DATAIN_DT P_DATAIN|MSGO,
3631 P_COMMAND CDO,
3632 P_MESGOUT CDO|MSGO,
3633 P_STATUS CDO|IOO,
3634 P_MESGIN CDO|IOO|MSGO
3635 }
3449 bit CDI 0x80
3450 bit IOI 0x40
3451 bit MSGI 0x20
3452 mask PHASE_MASK CDI|IOI|MSGI
3453 mask P_DATAOUT 0x00
3454 mask P_DATAIN IOI
3455 mask P_DATAOUT_DT P_DATAOUT|MSGO
3456 mask P_DATAIN_DT P_DATAIN|MSGO
3457 mask P_COMMAND CDI
3458 mask P_MESGOUT CDI|MSGI
3459 mask P_STATUS CDI|IOI
3460 mask P_MESGIN CDI|IOI|MSGI
3461 mask P_BUSFREE 0x01
3636 }
3637 /*
3462 }
3463 /*
3638 * Value to "or" into the SCBPTR[1] value to
3639 * indicate that an entry in the QINFIFO is valid.
3640 */
3641 QOUTFIFO_ENTRY_VALID_TAG {
3642 size 1
3643 }
3644 /*
3645 * Kernel and sequencer offsets into the queue of
3646 * incoming target mode command descriptors. The
3647 * queue is full when the KERNEL_TQINPOS == TQINPOS.
3648 */
3649 KERNEL_TQINPOS {
3650 size 1
3651 }
3652 TQINPOS {
3653 size 1
3654 }
3655 /*
3656 * Base address of our shared data with the kernel driver in host
3657 * memory. This includes the qoutfifo and target mode
3658 * incoming command queue.
3659 */
3660 SHARED_DATA_ADDR {
3661 size 4
3662 }
3663 /*
3664 * Pointer to location in host memory for next
3665 * position in the qoutfifo.
3666 */
3667 QOUTFIFO_NEXT_ADDR {
3668 size 4
3669 }
3464 * Base address of our shared data with the kernel driver in host
3465 * memory. This includes the qoutfifo and target mode
3466 * incoming command queue.
3467 */
3468 SHARED_DATA_ADDR {
3469 size 4
3470 }
3471 /*
3472 * Pointer to location in host memory for next
3473 * position in the qoutfifo.
3474 */
3475 QOUTFIFO_NEXT_ADDR {
3476 size 4
3477 }
3478 /*
3479 * Kernel and sequencer offsets into the queue of
3480 * incoming target mode command descriptors. The
3481 * queue is full when the KERNEL_TQINPOS == TQINPOS.
3482 */
3483 KERNEL_TQINPOS {
3484 size 1
3485 }
3486 TQINPOS {
3487 size 1
3488 }
3670 ARG_1 {
3671 size 1
3672 mask SEND_MSG 0x80
3673 mask SEND_SENSE 0x40
3674 mask SEND_REJ 0x20
3675 mask MSGOUT_PHASEMIS 0x10
3676 mask EXIT_MSG_LOOP 0x08
3677 mask CONT_MSG_LOOP_WRITE 0x04

--- 15 unchanged lines hidden (view full) ---

3693
3694 /*
3695 * Sequences the kernel driver has okayed for us. This allows
3696 * the driver to do things like prevent initiator or target
3697 * operations.
3698 */
3699 SCSISEQ_TEMPLATE {
3700 size 1
3489 ARG_1 {
3490 size 1
3491 mask SEND_MSG 0x80
3492 mask SEND_SENSE 0x40
3493 mask SEND_REJ 0x20
3494 mask MSGOUT_PHASEMIS 0x10
3495 mask EXIT_MSG_LOOP 0x08
3496 mask CONT_MSG_LOOP_WRITE 0x04

--- 15 unchanged lines hidden (view full) ---

3512
3513 /*
3514 * Sequences the kernel driver has okayed for us. This allows
3515 * the driver to do things like prevent initiator or target
3516 * operations.
3517 */
3518 SCSISEQ_TEMPLATE {
3519 size 1
3701 field MANUALCTL 0x40
3702 field ENSELI 0x20
3703 field ENRSELI 0x10
3704 field MANUALP 0x0C
3705 field ENAUTOATNP 0x02
3706 field ALTSTIM 0x01
3520 bit MANUALCTL 0x40
3521 bit ENSELI 0x20
3522 bit ENRSELI 0x10
3523 mask MANUALP 0x0C
3524 bit ENAUTOATNP 0x02
3525 bit ALTSTIM 0x01
3707 }
3708
3709 /*
3710 * The initiator specified tag for this target mode transaction.
3711 */
3712 INITIATOR_TAG {
3713 size 1
3714 }
3715
3716 SEQ_FLAGS2 {
3717 size 1
3526 }
3527
3528 /*
3529 * The initiator specified tag for this target mode transaction.
3530 */
3531 INITIATOR_TAG {
3532 size 1
3533 }
3534
3535 SEQ_FLAGS2 {
3536 size 1
3718 field PENDING_MK_MESSAGE 0x01
3719 field TARGET_MSG_PENDING 0x02
3720 field SELECTOUT_QFROZEN 0x04
3537 bit SCB_DMA 0x01
3538 bit TARGET_MSG_PENDING 0x02
3539 bit SELECTOUT_QFROZEN 0x04
3721 }
3540 }
3722
3723 ALLOCFIFO_SCBPTR {
3724 size 2
3725 }
3726
3727 /*
3541 /*
3728 * The maximum amount of time to wait, when interrupt coalescing
3729 * is enabled, before issueing a CMDCMPLT interrupt for a completed
3730 * command.
3731 */
3732 INT_COALESCING_TIMER {
3733 size 2
3734 }
3735
3736 /*
3737 * The maximum number of commands to coalesce into a single interrupt.
3738 * Actually the 2's complement of that value to simplify sequencer
3739 * code.
3740 */
3741 INT_COALESCING_MAXCMDS {
3742 size 1
3743 }
3744
3745 /*
3746 * The minimum number of commands still outstanding required
3747 * to continue coalescing (2's complement of value).
3748 */
3749 INT_COALESCING_MINCMDS {
3750 size 1
3751 }
3752
3753 /*
3754 * Number of commands "in-flight".
3755 */
3756 CMDS_PENDING {
3757 size 2
3758 }
3759
3760 /*
3761 * The count of commands that have been coalesced.
3762 */
3763 INT_COALESCING_CMDCOUNT {
3764 size 1
3765 }
3766
3767 /*
3768 * Since the HS_MAIBOX is self clearing, copy its contents to
3769 * this position in scratch ram every time it changes.
3770 */
3771 LOCAL_HS_MAILBOX {
3772 size 1
3773 }
3774 /*
3775 * Target-mode CDB type to CDB length table used
3776 * in non-packetized operation.
3777 */
3778 CMDSIZE_TABLE {
3779 size 8
3780 }
3542 * Target-mode CDB type to CDB length table used
3543 * in non-packetized operation.
3544 */
3545 CMDSIZE_TABLE {
3546 size 8
3547 }
3781 /*
3782 * When an SCB with the MK_MESSAGE flag is
3783 * queued to the controller, it cannot enter
3784 * the waiting for selection list until the
3785 * selections for any previously queued
3786 * commands to that target complete. During
3787 * the wait, the MK_MESSAGE SCB is queued
3788 * here.
3789 */
3790 MK_MESSAGE_SCB {
3791 size 2
3792 }
3793 /*
3794 * Saved SCSIID of MK_MESSAGE_SCB to avoid
3795 * an extra SCBPTR operation when deciding
3796 * if the MK_MESSAGE_SCB can be run.
3797 */
3798 MK_MESSAGE_SCSIID {
3799 size 1
3800 }
3801}
3802
3803/************************* Hardware SCB Definition ****************************/
3804scb {
3805 address 0x180
3806 size 64
3807 modes 0, 1, 2, 3
3808 SCB_RESIDUAL_DATACNT {
3809 size 4
3810 alias SCB_CDB_STORE
3548}
3549
3550/************************* Hardware SCB Definition ****************************/
3551scb {
3552 address 0x180
3553 size 64
3554 modes 0, 1, 2, 3
3555 SCB_RESIDUAL_DATACNT {
3556 size 4
3557 alias SCB_CDB_STORE
3811 alias SCB_HOST_CDB_PTR
3812 }
3813 SCB_RESIDUAL_SGPTR {
3814 size 4
3558 }
3559 SCB_RESIDUAL_SGPTR {
3560 size 4
3815 field SG_ADDR_MASK 0xf8 /* In the last byte */
3816 field SG_OVERRUN_RESID 0x02 /* In the first byte */
3817 field SG_LIST_NULL 0x01 /* In the first byte */
3561 alias SCB_CDB_PTR
3562 mask SG_ADDR_MASK 0xf8 /* In the last byte */
3563 bit SG_OVERRUN_RESID 0x02 /* In the first byte */
3564 bit SG_LIST_NULL 0x01 /* In the first byte */
3818 }
3819 SCB_SCSI_STATUS {
3820 size 1
3565 }
3566 SCB_SCSI_STATUS {
3567 size 1
3821 alias SCB_HOST_CDB_LEN
3822 }
3823 SCB_TARGET_PHASES {
3824 size 1
3825 }
3826 SCB_TARGET_DATA_DIR {
3827 size 1
3828 }
3829 SCB_TARGET_ITAG {
3830 size 1
3831 }
3832 SCB_SENSE_BUSADDR {
3833 /*
3834 * Only valid if CDB length is less than 13 bytes or
3835 * we are using a CDB pointer. Otherwise contains
3836 * the last 4 bytes of embedded cdb information.
3837 */
3838 size 4
3839 alias SCB_NEXT_COMPLETE
3840 }
3568 }
3569 SCB_TARGET_PHASES {
3570 size 1
3571 }
3572 SCB_TARGET_DATA_DIR {
3573 size 1
3574 }
3575 SCB_TARGET_ITAG {
3576 size 1
3577 }
3578 SCB_SENSE_BUSADDR {
3579 /*
3580 * Only valid if CDB length is less than 13 bytes or
3581 * we are using a CDB pointer. Otherwise contains
3582 * the last 4 bytes of embedded cdb information.
3583 */
3584 size 4
3585 alias SCB_NEXT_COMPLETE
3586 }
3841 SCB_TAG {
3842 alias SCB_FIFO_USE_COUNT
3843 size 2
3844 }
3845 SCB_CONTROL {
3587 SCB_CDB_LEN {
3846 size 1
3588 size 1
3847 field TARGET_SCB 0x80
3848 field DISCENB 0x40
3849 field TAG_ENB 0x20
3850 field MK_MESSAGE 0x10
3851 field STATUS_RCVD 0x08
3852 field DISCONNECTED 0x04
3853 field SCB_TAG_TYPE 0x03
3589 bit SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */
3854 }
3590 }
3855 SCB_SCSIID {
3591 SCB_TASK_MANAGEMENT {
3856 size 1
3592 size 1
3857 field TID 0xF0
3858 field OID 0x0F
3859 }
3593 }
3860 SCB_LUN {
3861 size 1
3862 field LID 0xff
3594 SCB_TAG {
3595 size 2
3863 }
3596 }
3864 SCB_TASK_ATTRIBUTE {
3865 size 1
3866 /*
3867 * Overloaded field for non-packetized
3868 * ignore wide residue message handling.
3869 */
3870 field SCB_XFERLEN_ODD 0x01
3597 SCB_NEXT {
3598 alias SCB_NEXT_SCB_BUSADDR
3599 size 2
3871 }
3600 }
3872 SCB_CDB_LEN {
3873 size 1
3874 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */
3601 SCB_NEXT2 {
3602 size 2
3875 }
3603 }
3876 SCB_TASK_MANAGEMENT {
3877 size 1
3878 }
3879 SCB_DATAPTR {
3880 size 8
3881 }
3882 SCB_DATACNT {
3883 /*
3884 * The last byte is really the high address bits for
3885 * the data address.
3886 */
3887 size 4
3604 SCB_DATAPTR {
3605 size 8
3606 }
3607 SCB_DATACNT {
3608 /*
3609 * The last byte is really the high address bits for
3610 * the data address.
3611 */
3612 size 4
3888 field SG_LAST_SEG 0x80 /* In the fourth byte */
3889 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
3613 bit SG_LAST_SEG 0x80 /* In the fourth byte */
3614 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
3890 }
3891 SCB_SGPTR {
3892 size 4
3615 }
3616 SCB_SGPTR {
3617 size 4
3893 field SG_STATUS_VALID 0x04 /* In the first byte */
3894 field SG_FULL_RESID 0x02 /* In the first byte */
3895 field SG_LIST_NULL 0x01 /* In the first byte */
3618 bit SG_STATUS_VALID 0x04 /* In the first byte */
3619 bit SG_FULL_RESID 0x02 /* In the first byte */
3620 bit SG_LIST_NULL 0x01 /* In the first byte */
3896 }
3621 }
3897 SCB_BUSADDR {
3898 size 4
3622 SCB_CONTROL {
3623 size 1
3624 bit TARGET_SCB 0x80
3625 bit DISCENB 0x40
3626 bit TAG_ENB 0x20
3627 bit MK_MESSAGE 0x10
3628 bit STATUS_RCVD 0x08
3629 bit DISCONNECTED 0x04
3630 mask SCB_TAG_TYPE 0x03
3899 }
3631 }
3900 SCB_NEXT {
3901 alias SCB_NEXT_SCB_BUSADDR
3902 size 2
3632 SCB_SCSIID {
3633 size 1
3634 mask TID 0xF0
3635 mask OID 0x0F
3903 }
3636 }
3904 SCB_NEXT2 {
3905 size 2
3637 SCB_LUN {
3638 size 1
3639 mask LID 0xff
3906 }
3640 }
3907 SCB_SPARE {
3908 size 8
3909 alias SCB_PKT_LUN
3641 SCB_TASK_ATTRIBUTE {
3642 size 1
3643 alias SCB_NONPACKET_TAG
3910 }
3644 }
3645 SCB_BUSADDR {
3646 size 4
3647 }
3911 SCB_DISCONNECTED_LISTS {
3648 SCB_DISCONNECTED_LISTS {
3912 size 8
3649 size 16
3913 }
3914}
3915
3916/*********************************** Constants ********************************/
3650 }
3651}
3652
3653/*********************************** Constants ********************************/
3654const SEQ_STACK_SIZE 8
3917const MK_MESSAGE_BIT_OFFSET 4
3918const TID_SHIFT 4
3919const TARGET_CMD_CMPLT 0xfe
3920const INVALID_ADDR 0x80
3921#define SCB_LIST_NULL 0xff
3655const MK_MESSAGE_BIT_OFFSET 4
3656const TID_SHIFT 4
3657const TARGET_CMD_CMPLT 0xfe
3658const INVALID_ADDR 0x80
3659#define SCB_LIST_NULL 0xff
3922#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80
3923
3924const CCSGADDR_MAX 0x80
3925const CCSCBADDR_MAX 0x80
3926const CCSGRAM_MAXSEGS 16
3927
3928/* Selection Timeout Timer Constants */
3929const STIMESEL_SHIFT 3
3930const STIMESEL_MIN 0x18
3931const STIMESEL_BUG_ADJ 0x8
3932
3933/* WDTR Message values */
3934const BUS_8_BIT 0x00
3935const BUS_16_BIT 0x01
3936const BUS_32_BIT 0x02
3937
3938/* Offset maximums */
3939const MAX_OFFSET 0xfe
3660
3661const CCSGADDR_MAX 0x80
3662const CCSCBADDR_MAX 0x80
3663const CCSGRAM_MAXSEGS 16
3664
3665/* Selection Timeout Timer Constants */
3666const STIMESEL_SHIFT 3
3667const STIMESEL_MIN 0x18
3668const STIMESEL_BUG_ADJ 0x8
3669
3670/* WDTR Message values */
3671const BUS_8_BIT 0x00
3672const BUS_16_BIT 0x01
3673const BUS_32_BIT 0x02
3674
3675/* Offset maximums */
3676const MAX_OFFSET 0xfe
3940const MAX_OFFSET_PACED 0xfe
3941const MAX_OFFSET_PACED_BUG 0x7f
3942/*
3943 * Some 160 devices incorrectly accept 0xfe as a
3944 * sync offset, but will overrun this value. Limit
3945 * to 0x7f for speed lower than U320 which will
3946 * avoid the persistent sync offset overruns.
3947 */
3948const MAX_OFFSET_NON_PACED 0x7f
3677const MAX_OFFSET_PACED 0x7f
3949const HOST_MSG 0xff
3950
3951/*
3952 * The size of our sense buffers.
3953 * Sense buffer mapping can be handled in either of two ways.
3954 * The first is to allocate a dmamap for each transaction.
3955 * Depending on the architecture, dmamaps can be costly. The
3956 * alternative is to statically map the buffers in much the same

--- 5 unchanged lines hidden (view full) ---

3962/* Target mode command processing constants */
3963const CMD_GROUP_CODE_SHIFT 0x05
3964
3965const STATUS_BUSY 0x08
3966const STATUS_QUEUE_FULL 0x28
3967const STATUS_PKT_SENSE 0xFF
3968const TARGET_DATA_IN 1
3969
3678const HOST_MSG 0xff
3679
3680/*
3681 * The size of our sense buffers.
3682 * Sense buffer mapping can be handled in either of two ways.
3683 * The first is to allocate a dmamap for each transaction.
3684 * Depending on the architecture, dmamaps can be costly. The
3685 * alternative is to statically map the buffers in much the same

--- 5 unchanged lines hidden (view full) ---

3691/* Target mode command processing constants */
3692const CMD_GROUP_CODE_SHIFT 0x05
3693
3694const STATUS_BUSY 0x08
3695const STATUS_QUEUE_FULL 0x28
3696const STATUS_PKT_SENSE 0xFF
3697const TARGET_DATA_IN 1
3698
3970const SCB_TRANSFER_SIZE_FULL_LUN 56
3971const SCB_TRANSFER_SIZE_1BYTE_LUN 48
3699const SCB_TRANSFER_SIZE 48
3972/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
3973const PKT_OVERRUN_BUFSIZE 512
3974
3975/*
3700/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
3701const PKT_OVERRUN_BUFSIZE 512
3702
3703/*
3976 * Timer parameters.
3977 */
3978const AHD_TIMER_US_PER_TICK 25
3979const AHD_TIMER_MAX_TICKS 0xFFFF
3980const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK)
3981
3982/*
3983 * Downloaded (kernel inserted) constants
3984 */
3985const SG_PREFETCH_CNT download
3986const SG_PREFETCH_CNT_LIMIT download
3987const SG_PREFETCH_ALIGN_MASK download
3988const SG_PREFETCH_ADDR_MASK download
3989const SG_SIZEOF download
3990const PKT_OVERRUN_BUFOFFSET download
3704 * Downloaded (kernel inserted) constants
3705 */
3706const SG_PREFETCH_CNT download
3707const SG_PREFETCH_CNT_LIMIT download
3708const SG_PREFETCH_ALIGN_MASK download
3709const SG_PREFETCH_ADDR_MASK download
3710const SG_SIZEOF download
3711const PKT_OVERRUN_BUFOFFSET download
3991const SCB_TRANSFER_SIZE download
3992const CACHELINE_MASK download
3993
3994/*
3995 * BIOS SCB offsets
3996 */
3997const NVRAM_SCB_OFFSET 0x2C
3712
3713/*
3714 * BIOS SCB offsets
3715 */
3716const NVRAM_SCB_OFFSET 0x2C