aic79xx.c (9199c09a159c4e3e98c212d4eec1edc5252d9e33) aic79xx.c (17d2475554610175f0673ee69aa703ce3972909b)
1/*-
1/*
2 * Core routines and tables shareable across OS platforms.
3 *
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.

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32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.

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32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#79 $
41 *
42 * $FreeBSD$
41 */
42
43#ifdef __linux__
44#include "aic79xx_osm.h"
45#include "aic79xx_inline.h"
46#include "aicasm/aicasm_insformat.h"
47#else
43 */
44
45#ifdef __linux__
46#include "aic79xx_osm.h"
47#include "aic79xx_inline.h"
48#include "aicasm/aicasm_insformat.h"
49#else
48#include <sys/cdefs.h>
49__FBSDID("$FreeBSD$");
50#include <dev/aic7xxx/aic79xx_osm.h>
51#include <dev/aic7xxx/aic79xx_inline.h>
52#include <dev/aic7xxx/aicasm/aicasm_insformat.h>
53#endif
54
50#include <dev/aic7xxx/aic79xx_osm.h>
51#include <dev/aic7xxx/aic79xx_inline.h>
52#include <dev/aic7xxx/aicasm/aicasm_insformat.h>
53#endif
54
55/******************************** Globals *************************************/
55/****************************** Softc Data ************************************/
56struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq);
56struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq);
57uint32_t ahd_attach_to_HostRAID_controllers = 1;
58
59/***************************** Lookup Tables **********************************/
60char *ahd_chip_names[] =
61{
62 "NONE",
63 "aic7901",
57
58/***************************** Lookup Tables **********************************/
59char *ahd_chip_names[] =
60{
61 "NONE",
62 "aic7901",
64 "aic7902",
65 "aic7901A"
63 "aic7902"
66};
67static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names);
68
69/*
70 * Hardware error codes.
71 */
72struct ahd_hard_error_entry {
73 uint8_t errno;

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109
110/**************************** Function Declarations ***************************/
111static void ahd_handle_transmission_error(struct ahd_softc *ahd);
112static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
113 u_int lqistat1);
114static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
115 u_int busfreetime);
116static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
64};
65static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names);
66
67/*
68 * Hardware error codes.
69 */
70struct ahd_hard_error_entry {
71 uint8_t errno;

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107
108/**************************** Function Declarations ***************************/
109static void ahd_handle_transmission_error(struct ahd_softc *ahd);
110static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
111 u_int lqistat1);
112static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
113 u_int busfreetime);
114static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
117static void ahd_handle_proto_violation(struct ahd_softc *ahd);
118static void ahd_force_renegotiation(struct ahd_softc *ahd,
119 struct ahd_devinfo *devinfo);
120
121static struct ahd_tmode_tstate*
122 ahd_alloc_tstate(struct ahd_softc *ahd,
123 u_int scsi_id, char channel);
124#ifdef AHD_TARGET_MODE
125static void ahd_free_tstate(struct ahd_softc *ahd,

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167 struct ahd_devinfo *devinfo);
168static int ahd_handle_msg_reject(struct ahd_softc *ahd,
169 struct ahd_devinfo *devinfo);
170static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
171 struct ahd_devinfo *devinfo);
172static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
173static void ahd_handle_devreset(struct ahd_softc *ahd,
174 struct ahd_devinfo *devinfo,
115static void ahd_force_renegotiation(struct ahd_softc *ahd,
116 struct ahd_devinfo *devinfo);
117
118static struct ahd_tmode_tstate*
119 ahd_alloc_tstate(struct ahd_softc *ahd,
120 u_int scsi_id, char channel);
121#ifdef AHD_TARGET_MODE
122static void ahd_free_tstate(struct ahd_softc *ahd,

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164 struct ahd_devinfo *devinfo);
165static int ahd_handle_msg_reject(struct ahd_softc *ahd,
166 struct ahd_devinfo *devinfo);
167static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
168 struct ahd_devinfo *devinfo);
169static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
170static void ahd_handle_devreset(struct ahd_softc *ahd,
171 struct ahd_devinfo *devinfo,
175 u_int lun, cam_status status,
176 char *message, int verbose_level);
177#ifdef AHD_TARGET_MODE
172 cam_status status, char *message,
173 int verbose_level);
174#if AHD_TARGET_MODE
178static void ahd_setup_target_msgin(struct ahd_softc *ahd,
179 struct ahd_devinfo *devinfo,
180 struct scb *scb);
181#endif
182
175static void ahd_setup_target_msgin(struct ahd_softc *ahd,
176 struct ahd_devinfo *devinfo,
177 struct scb *scb);
178#endif
179
183static u_int ahd_sglist_size(struct ahd_softc *ahd);
184static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
180static bus_size_t ahd_sglist_size(struct ahd_softc *ahd);
181static bus_size_t ahd_sglist_allocsize(struct ahd_softc *ahd);
185static bus_dmamap_callback_t
186 ahd_dmamap_cb;
187static void ahd_initialize_hscbs(struct ahd_softc *ahd);
188static int ahd_init_scbdata(struct ahd_softc *ahd);
189static void ahd_fini_scbdata(struct ahd_softc *ahd);
190static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
191static void ahd_iocell_first_selection(struct ahd_softc *ahd);
182static bus_dmamap_callback_t
183 ahd_dmamap_cb;
184static void ahd_initialize_hscbs(struct ahd_softc *ahd);
185static int ahd_init_scbdata(struct ahd_softc *ahd);
186static void ahd_fini_scbdata(struct ahd_softc *ahd);
187static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
188static void ahd_iocell_first_selection(struct ahd_softc *ahd);
192static void ahd_add_col_list(struct ahd_softc *ahd,
193 struct scb *scb, u_int col_idx);
194static void ahd_rem_col_list(struct ahd_softc *ahd,
195 struct scb *scb);
196static void ahd_chip_init(struct ahd_softc *ahd);
197static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
198 struct scb *prev_scb,
199 struct scb *scb);
200static int ahd_qinfifo_count(struct ahd_softc *ahd);
201static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
202 char channel, int lun, u_int tag,
203 role_t role, uint32_t status,
204 ahd_search_action action,
189static void ahd_chip_init(struct ahd_softc *ahd);
190static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
191 struct scb *prev_scb,
192 struct scb *scb);
193static int ahd_qinfifo_count(struct ahd_softc *ahd);
194static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
195 char channel, int lun, u_int tag,
196 role_t role, uint32_t status,
197 ahd_search_action action,
205 u_int *list_head, u_int *list_tail,
206 u_int tid);
198 u_int *list_head, u_int tid);
207static void ahd_stitch_tid_list(struct ahd_softc *ahd,
208 u_int tid_prev, u_int tid_cur,
209 u_int tid_next);
210static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
211 u_int scbid);
212static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
213 u_int prev, u_int next, u_int tid);
214static void ahd_reset_current_bus(struct ahd_softc *ahd);
215static ahd_callback_t ahd_reset_poll;
199static void ahd_stitch_tid_list(struct ahd_softc *ahd,
200 u_int tid_prev, u_int tid_cur,
201 u_int tid_next);
202static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
203 u_int scbid);
204static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
205 u_int prev, u_int next, u_int tid);
206static void ahd_reset_current_bus(struct ahd_softc *ahd);
207static ahd_callback_t ahd_reset_poll;
216static ahd_callback_t ahd_stat_timer;
217#ifdef AHD_DUMP_SEQ
218static void ahd_dumpseq(struct ahd_softc *ahd);
219#endif
220static void ahd_loadseq(struct ahd_softc *ahd);
221static int ahd_check_patch(struct ahd_softc *ahd,
222 struct patch **start_patch,
223 u_int start_instr, u_int *skip_addr);
224static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
225 u_int address);
226static void ahd_download_instr(struct ahd_softc *ahd,
227 u_int instrptr, uint8_t *dconsts);
208#ifdef AHD_DUMP_SEQ
209static void ahd_dumpseq(struct ahd_softc *ahd);
210#endif
211static void ahd_loadseq(struct ahd_softc *ahd);
212static int ahd_check_patch(struct ahd_softc *ahd,
213 struct patch **start_patch,
214 u_int start_instr, u_int *skip_addr);
215static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
216 u_int address);
217static void ahd_download_instr(struct ahd_softc *ahd,
218 u_int instrptr, uint8_t *dconsts);
228static int ahd_probe_stack_size(struct ahd_softc *ahd);
229static int ahd_other_scb_timeout(struct ahd_softc *ahd,
230 struct scb *scb,
231 struct scb *other_scb);
232static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
233 struct scb *scb);
234static void ahd_run_data_fifo(struct ahd_softc *ahd,
235 struct scb *scb);
236
237#ifdef AHD_TARGET_MODE
238static void ahd_queue_lstate_event(struct ahd_softc *ahd,
239 struct ahd_tmode_lstate *lstate,
240 u_int initiator_id,
241 u_int event_type,
242 u_int event_arg);
243static void ahd_update_scsiid(struct ahd_softc *ahd,
244 u_int targid_mask);

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288
289static __inline int
290ahd_set_active_fifo(struct ahd_softc *ahd)
291{
292 u_int active_fifo;
293
294 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
295 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
219#ifdef AHD_TARGET_MODE
220static void ahd_queue_lstate_event(struct ahd_softc *ahd,
221 struct ahd_tmode_lstate *lstate,
222 u_int initiator_id,
223 u_int event_type,
224 u_int event_arg);
225static void ahd_update_scsiid(struct ahd_softc *ahd,
226 u_int targid_mask);

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270
271static __inline int
272ahd_set_active_fifo(struct ahd_softc *ahd)
273{
274 u_int active_fifo;
275
276 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
277 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
278/* XXX This is a three possition switch in the B. */
296 switch (active_fifo) {
297 case 0:
298 case 1:
299 ahd_set_modes(ahd, active_fifo, active_fifo);
300 return (1);
301 default:
302 return (0);
303 }

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333 * occur before the increment leaving the kernel to believe
334 * the command arrived but the sequencer to not.
335 */
336 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
337
338 /* Always allow reselection */
339 ahd_outb(ahd, SCSISEQ1,
340 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
279 switch (active_fifo) {
280 case 0:
281 case 1:
282 ahd_set_modes(ahd, active_fifo, active_fifo);
283 return (1);
284 default:
285 return (0);
286 }

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316 * occur before the increment leaving the kernel to believe
317 * the command arrived but the sequencer to not.
318 */
319 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
320
321 /* Always allow reselection */
322 ahd_outb(ahd, SCSISEQ1,
323 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
324 /* Ensure that no DMA operations are in progress */
341 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
325 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
326 ahd_outb(ahd, SCBHCNT, 0);
327 ahd_outb(ahd, CCSCBCTL, CCSCBRESET);
342
328
343 /*
344 * Clear any pending sequencer interrupt. It is no
345 * longer relevant since we're resetting the Program
346 * Counter.
347 */
348 ahd_outb(ahd, CLRINT, CLRSEQINT);
349
350 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
351 ahd_unpause(ahd);
352}
353
354void
355ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
356{
357 ahd_mode_state saved_modes;

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366 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
367 ahd_outb(ahd, CCSGCTL, CCSGRESET);
368 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
369 ahd_outb(ahd, SG_STATE, 0);
370 ahd_restore_modes(ahd, saved_modes);
371}
372
373/************************* Input/Output Queues ********************************/
329 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
330 ahd_unpause(ahd);
331}
332
333void
334ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
335{
336 ahd_mode_state saved_modes;

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345 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
346 ahd_outb(ahd, CCSGCTL, CCSGRESET);
347 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
348 ahd_outb(ahd, SG_STATE, 0);
349 ahd_restore_modes(ahd, saved_modes);
350}
351
352/************************* Input/Output Queues ********************************/
374/*
375 * Flush and completed commands that are sitting in the command
376 * complete queues down on the chip but have yet to be dma'ed back up.
377 */
378void
353void
379ahd_flush_qoutfifo(struct ahd_softc *ahd)
354ahd_run_qoutfifo(struct ahd_softc *ahd)
380{
355{
381 struct scb *scb;
382 ahd_mode_state saved_modes;
383 u_int saved_scbptr;
384 u_int ccscbctl;
385 u_int scbid;
386 u_int next_scbid;
356 struct scb *scb;
357 u_int scb_index;
387
358
388 saved_modes = ahd_save_modes(ahd);
359 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
360 while (ahd->qoutfifo[ahd->qoutfifonext] != SCB_LIST_NULL_LE) {
389
361
390 /*
391 * Flush the good status FIFO for completed packetized commands.
392 */
393 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
394 saved_scbptr = ahd_get_scbptr(ahd);
395 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
396 u_int fifo_mode;
397 u_int i;
398
399 scbid = ahd_inw(ahd, GSFIFO);
400 scb = ahd_lookup_scb(ahd, scbid);
362 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext]);
363 scb = ahd_lookup_scb(ahd, scb_index);
401 if (scb == NULL) {
364 if (scb == NULL) {
402 printf("%s: Warning - GSFIFO SCB %d invalid\n",
403 ahd_name(ahd), scbid);
404 AHD_CORRECTABLE_ERROR(ahd);
365 printf("%s: WARNING no command for scb %d "
366 "(cmdcmplt)\nQOUTPOS = %d\n",
367 ahd_name(ahd), scb_index,
368 ahd->qoutfifonext);
369 ahd_dump_card_state(ahd);
370 ahd->qoutfifonext = AHD_QOUT_WRAP(ahd->qoutfifonext+1);
405 continue;
406 }
371 continue;
372 }
407 /*
408 * Determine if this transaction is still active in
409 * any FIFO. If it is, we must flush that FIFO to
410 * the host before completing the command.
411 */
412 fifo_mode = 0;
413rescan_fifos:
414 for (i = 0; i < 2; i++) {
415 /* Toggle to the other mode. */
416 fifo_mode ^= 1;
417 ahd_set_modes(ahd, fifo_mode, fifo_mode);
418
373
419 if (ahd_scb_active_in_fifo(ahd, scb) == 0)
420 continue;
374 if ((ahd->qoutfifonext & 0x01) == 0x01) {
421
375
422 ahd_run_data_fifo(ahd, scb);
423
424 /*
376 /*
425 * Running this FIFO may cause a CFG4DATA for
426 * this same transaction to assert in the other
427 * FIFO or a new snapshot SAVEPTRS interrupt
428 * in this FIFO. Even running a FIFO may not
429 * clear the transaction if we are still waiting
430 * for data to drain to the host. We must loop
431 * until the transaction is not active in either
432 * FIFO just to be sure. Reset our loop counter
433 * so we will visit both FIFOs again before
434 * declaring this transaction finished. We
435 * also delay a bit so that status has a chance
436 * to change before we look at this FIFO again.
377 * Clear 32bits of QOUTFIFO at a time
378 * so that we don't clobber an incoming
379 * 16bit DMA to the array on architectures
380 * that only support 32bit load and store
381 * operations.
437 */
382 */
438 aic_delay(200);
439 goto rescan_fifos;
383 ahd->qoutfifo[ahd->qoutfifonext - 1] = SCB_LIST_NULL_LE;
384 ahd->qoutfifo[ahd->qoutfifonext] = SCB_LIST_NULL_LE;
385 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
386 ahd->shared_data_dmamap,
387 /*offset*/(ahd->qoutfifonext - 1)*2,
388 /*len*/4, BUS_DMASYNC_PREREAD);
440 }
389 }
441 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
442 ahd_set_scbptr(ahd, scbid);
443 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
444 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
445 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
446 & SG_LIST_NULL) != 0)) {
447 u_int comp_head;
390 ahd->qoutfifonext = AHD_QOUT_WRAP(ahd->qoutfifonext+1);
448
391
449 /*
450 * The transfer completed with a residual.
451 * Place this SCB on the complete DMA list
452 * so that we update our in-core copy of the
453 * SCB before completing the command.
454 */
455 ahd_outb(ahd, SCB_SCSI_STATUS, 0);
456 ahd_outb(ahd, SCB_SGPTR,
457 ahd_inb_scbram(ahd, SCB_SGPTR)
458 | SG_STATUS_VALID);
459 ahd_outw(ahd, SCB_TAG, scbid);
460 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
461 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
462 if (SCBID_IS_NULL(comp_head)) {
463 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
464 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
465 } else {
466 u_int tail;
467
468 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
469 ahd_set_scbptr(ahd, tail);
470 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
471 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
472 ahd_set_scbptr(ahd, scbid);
473 }
474 } else
475 ahd_complete_scb(ahd, scb);
476 }
477 ahd_set_scbptr(ahd, saved_scbptr);
478
479 /*
480 * Setup for command channel portion of flush.
481 */
482 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
483
484 /*
485 * Wait for any inprogress DMA to complete and clear DMA state
486 * if this if for an SCB in the qinfifo.
487 */
488 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
489
490 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
491 if ((ccscbctl & ARRDONE) != 0)
492 break;
493 } else if ((ccscbctl & CCSCBDONE) != 0)
494 break;
495 aic_delay(200);
496 }
497 /*
498 * We leave the sequencer to cleanup in the case of DMA's to
499 * update the qoutfifo. In all other cases (DMA's to the
500 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
501 * we disable the DMA engine so that the sequencer will not
502 * attempt to handle the DMA completion.
503 */
504 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
505 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
506
507 /*
508 * Complete any SCBs that just finished
509 * being DMA'ed into the qoutfifo.
510 */
511 ahd_run_qoutfifo(ahd);
512
513 saved_scbptr = ahd_get_scbptr(ahd);
514 /*
515 * Manually update/complete any completed SCBs that are waiting to be
516 * DMA'ed back up to the host.
517 */
518 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
519 while (!SCBID_IS_NULL(scbid)) {
520 uint8_t *hscb_ptr;
521 u_int i;
522
523 ahd_set_scbptr(ahd, scbid);
524 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
525 scb = ahd_lookup_scb(ahd, scbid);
526 if (scb == NULL) {
527 printf("%s: Warning - DMA-up and complete "
528 "SCB %d invalid\n", ahd_name(ahd), scbid);
529 AHD_CORRECTABLE_ERROR(ahd);
530 continue;
531 }
532 hscb_ptr = (uint8_t *)scb->hscb;
533 for (i = 0; i < sizeof(struct hardware_scb); i++)
534 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
535
536 ahd_complete_scb(ahd, scb);
392 ahd_complete_scb(ahd, scb);
537 scbid = next_scbid;
538 }
393 }
539 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
540 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
541
542 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
543 while (!SCBID_IS_NULL(scbid)) {
544
545 ahd_set_scbptr(ahd, scbid);
546 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
547 scb = ahd_lookup_scb(ahd, scbid);
548 if (scb == NULL) {
549 printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
550 ahd_name(ahd), scbid);
551 AHD_CORRECTABLE_ERROR(ahd);
552 continue;
553 }
554
555 ahd_complete_scb(ahd, scb);
556 scbid = next_scbid;
557 }
558 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
559
560 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
561 while (!SCBID_IS_NULL(scbid)) {
562
563 ahd_set_scbptr(ahd, scbid);
564 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
565 scb = ahd_lookup_scb(ahd, scbid);
566 if (scb == NULL) {
567 printf("%s: Warning - Complete SCB %d invalid\n",
568 ahd_name(ahd), scbid);
569 AHD_CORRECTABLE_ERROR(ahd);
570 continue;
571 }
572
573 ahd_complete_scb(ahd, scb);
574 scbid = next_scbid;
575 }
576 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
577
578 /*
579 * Restore state.
580 */
581 ahd_set_scbptr(ahd, saved_scbptr);
582 ahd_restore_modes(ahd, saved_modes);
583 ahd->flags |= AHD_UPDATE_PEND_CMDS;
584}
585
394}
395
586/*
587 * Determine if an SCB for a packetized transaction
588 * is active in a FIFO.
589 */
590static int
591ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
396void
397ahd_run_untagged_queues(struct ahd_softc *ahd)
592{
398{
399 int i;
593
400
594 /*
595 * The FIFO is only active for our transaction if
596 * the SCBPTR matches the SCB's ID and the firmware
597 * has installed a handler for the FIFO or we have
598 * a pending SAVEPTRS or CFG4DATA interrupt.
599 */
600 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
601 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
602 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
603 return (0);
604
605 return (1);
401 for (i = 0; i < 16; i++)
402 ahd_run_untagged_queue(ahd, &ahd->untagged_queues[i]);
606}
607
403}
404
608/*
609 * Run a data fifo to completion for a transaction we know
610 * has completed across the SCSI bus (good status has been
611 * received). We are already set to the correct FIFO mode
612 * on entry to this routine.
613 *
614 * This function attempts to operate exactly as the firmware
615 * would when running this FIFO. Care must be taken to update
616 * this routine any time the firmware's FIFO algorithm is
617 * changed.
618 */
619static void
620ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
621{
622 u_int seqintsrc;
623
624 seqintsrc = ahd_inb(ahd, SEQINTSRC);
625 if ((seqintsrc & CFG4DATA) != 0) {
626 uint32_t datacnt;
627 uint32_t sgptr;
628
629 /*
630 * Clear full residual flag.
631 */
632 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
633 ahd_outb(ahd, SCB_SGPTR, sgptr);
634
635 /*
636 * Load datacnt and address.
637 */
638 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
639 if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
640 sgptr |= LAST_SEG;
641 ahd_outb(ahd, SG_STATE, 0);
642 } else
643 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
644 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
645 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
646 ahd_outb(ahd, SG_CACHE_PRE, sgptr);
647 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
648
649 /*
650 * Initialize Residual Fields.
651 */
652 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
653 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
654
655 /*
656 * Mark the SCB as having a FIFO in use.
657 */
658 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
659 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
660
661 /*
662 * Install a "fake" handler for this FIFO.
663 */
664 ahd_outw(ahd, LONGJMP_ADDR, 0);
665
666 /*
667 * Notify the hardware that we have satisfied
668 * this sequencer interrupt.
669 */
670 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
671 } else if ((seqintsrc & SAVEPTRS) != 0) {
672 uint32_t sgptr;
673 uint32_t resid;
674
675 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
676 /*
677 * Snapshot Save Pointers. All that
678 * is necessary to clear the snapshot
679 * is a CLRCHN.
680 */
681 goto clrchn;
682 }
683
684 /*
685 * Disable S/G fetch so the DMA engine
686 * is available to future users.
687 */
688 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
689 ahd_outb(ahd, CCSGCTL, 0);
690 ahd_outb(ahd, SG_STATE, 0);
691
692 /*
693 * Flush the data FIFO. Strickly only
694 * necessary for Rev A parts.
695 */
696 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
697
698 /*
699 * Calculate residual.
700 */
701 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
702 resid = ahd_inl(ahd, SHCNT);
703 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
704 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
705 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
706 /*
707 * Must back up to the correct S/G element.
708 * Typically this just means resetting our
709 * low byte to the offset in the SG_CACHE,
710 * but if we wrapped, we have to correct
711 * the other bytes of the sgptr too.
712 */
713 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
714 && (sgptr & 0x80) == 0)
715 sgptr -= 0x100;
716 sgptr &= ~0xFF;
717 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
718 & SG_ADDR_MASK;
719 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
720 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
721 } else if ((resid & AHD_SG_LEN_MASK) == 0) {
722 ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
723 sgptr | SG_LIST_NULL);
724 }
725 /*
726 * Save Pointers.
727 */
728 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
729 ahd_outl(ahd, SCB_DATACNT, resid);
730 ahd_outl(ahd, SCB_SGPTR, sgptr);
731 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
732 ahd_outb(ahd, SEQIMODE,
733 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
734 /*
735 * If the data is to the SCSI bus, we are
736 * done, otherwise wait for FIFOEMP.
737 */
738 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
739 goto clrchn;
740 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
741 uint32_t sgptr;
742 uint64_t data_addr;
743 uint32_t data_len;
744 u_int dfcntrl;
745
746 /*
747 * Disable S/G fetch so the DMA engine
748 * is available to future users. We won't
749 * be using the DMA engine to load segments.
750 */
751 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
752 ahd_outb(ahd, CCSGCTL, 0);
753 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
754 }
755
756 /*
757 * Wait for the DMA engine to notice that the
758 * host transfer is enabled and that there is
759 * space in the S/G FIFO for new segments before
760 * loading more segments.
761 */
762 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
763 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
764
765 /*
766 * Determine the offset of the next S/G
767 * element to load.
768 */
769 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
770 sgptr &= SG_PTR_MASK;
771 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
772 struct ahd_dma64_seg *sg;
773
774 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
775 data_addr = sg->addr;
776 data_len = sg->len;
777 sgptr += sizeof(*sg);
778 } else {
779 struct ahd_dma_seg *sg;
780
781 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
782 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
783 data_addr <<= 8;
784 data_addr |= sg->addr;
785 data_len = sg->len;
786 sgptr += sizeof(*sg);
787 }
788
789 /*
790 * Update residual information.
791 */
792 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
793 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
794
795 /*
796 * Load the S/G.
797 */
798 if (data_len & AHD_DMA_LAST_SEG) {
799 sgptr |= LAST_SEG;
800 ahd_outb(ahd, SG_STATE, 0);
801 }
802 ahd_outq(ahd, HADDR, data_addr);
803 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
804 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
805
806 /*
807 * Advertise the segment to the hardware.
808 */
809 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
810 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
811 /*
812 * Use SCSIENWRDIS so that SCSIEN
813 * is never modified by this
814 * operation.
815 */
816 dfcntrl |= SCSIENWRDIS;
817 }
818 ahd_outb(ahd, DFCNTRL, dfcntrl);
819 }
820 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
821
822 /*
823 * Transfer completed to the end of SG list
824 * and has flushed to the host.
825 */
826 ahd_outb(ahd, SCB_SGPTR,
827 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
828 goto clrchn;
829 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
830clrchn:
831 /*
832 * Clear any handler for this FIFO, decrement
833 * the FIFO use count for the SCB, and release
834 * the FIFO.
835 */
836 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
837 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
838 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
839 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
840 }
841}
842
843/*
844 * Look for entries in the QoutFIFO that have completed.
845 * The valid_tag completion field indicates the validity
846 * of the entry - the valid value toggles each time through
847 * the queue. We use the sg_status field in the completion
848 * entry to avoid referencing the hscb if the completion
849 * occurred with no errors and no residual. sg_status is
850 * a copy of the first byte (little endian) of the sgptr
851 * hscb field.
852 */
853void
405void
854ahd_run_qoutfifo(struct ahd_softc *ahd)
406ahd_run_untagged_queue(struct ahd_softc *ahd, struct scb_tailq *queue)
855{
407{
856 struct ahd_completion *completion;
857 struct scb *scb;
408 struct scb *scb;
858 u_int scb_index;
859
409
860 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
861 panic("ahd_run_qoutfifo recursion");
862 ahd->flags |= AHD_RUNNING_QOUTFIFO;
863 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
864 for (;;) {
865 completion = &ahd->qoutfifo[ahd->qoutfifonext];
410 if (ahd->untagged_queue_lock != 0)
411 return;
866
412
867 if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
868 break;
869
870 scb_index = aic_le16toh(completion->tag);
871 scb = ahd_lookup_scb(ahd, scb_index);
872 if (scb == NULL) {
873 printf("%s: WARNING no command for scb %d "
874 "(cmdcmplt)\nQOUTPOS = %d\n",
875 ahd_name(ahd), scb_index,
876 ahd->qoutfifonext);
877 AHD_CORRECTABLE_ERROR(ahd);
878 ahd_dump_card_state(ahd);
879 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
880 ahd_handle_scb_status(ahd, scb);
881 } else {
882 ahd_done(ahd, scb);
883 }
884
885 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
886 if (ahd->qoutfifonext == 0)
887 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
413 if ((scb = TAILQ_FIRST(queue)) != NULL
414 && (scb->flags & SCB_ACTIVE) == 0) {
415 scb->flags |= SCB_ACTIVE;
416 ahd_queue_scb(ahd, scb);
888 }
417 }
889 ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
890}
891
892/************************* Interrupt Handling *********************************/
893void
894ahd_handle_hwerrint(struct ahd_softc *ahd)
895{
896 /*
897 * Some catastrophic hardware error has occurred.
898 * Print it for the user and disable the controller.
899 */
900 int i;
901 int error;
902
903 error = ahd_inb(ahd, ERROR);
904 for (i = 0; i < num_errors; i++) {
418}
419
420/************************* Interrupt Handling *********************************/
421void
422ahd_handle_hwerrint(struct ahd_softc *ahd)
423{
424 /*
425 * Some catastrophic hardware error has occurred.
426 * Print it for the user and disable the controller.
427 */
428 int i;
429 int error;
430
431 error = ahd_inb(ahd, ERROR);
432 for (i = 0; i < num_errors; i++) {
905 if ((error & ahd_hard_errors[i].errno) != 0) {
433 if ((error & ahd_hard_errors[i].errno) != 0)
906 printf("%s: hwerrint, %s\n",
907 ahd_name(ahd), ahd_hard_errors[i].errmesg);
434 printf("%s: hwerrint, %s\n",
435 ahd_name(ahd), ahd_hard_errors[i].errmesg);
908 AHD_UNCORRECTABLE_ERROR(ahd);
909 }
910 }
911
912 ahd_dump_card_state(ahd);
913 panic("BRKADRINT");
914
436 }
437
438 ahd_dump_card_state(ahd);
439 panic("BRKADRINT");
440
915 /* Tell everyone that this HBA is no longer available */
441 /* Tell everyone that this HBA is no longer availible */
916 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
917 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
918 CAM_NO_HBA);
919
920 /* Tell the system that this controller has gone away. */
921 ahd_free(ahd);
922}
923

--- 4 unchanged lines hidden (view full) ---

928
929 /*
930 * Save the sequencer interrupt code and clear the SEQINT
931 * bit. We will unpause the sequencer, if appropriate,
932 * after servicing the request.
933 */
934 seqintcode = ahd_inb(ahd, SEQINTCODE);
935 ahd_outb(ahd, CLRINT, CLRSEQINT);
442 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
443 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
444 CAM_NO_HBA);
445
446 /* Tell the system that this controller has gone away. */
447 ahd_free(ahd);
448}
449

--- 4 unchanged lines hidden (view full) ---

454
455 /*
456 * Save the sequencer interrupt code and clear the SEQINT
457 * bit. We will unpause the sequencer, if appropriate,
458 * after servicing the request.
459 */
460 seqintcode = ahd_inb(ahd, SEQINTCODE);
461 ahd_outb(ahd, CLRINT, CLRSEQINT);
936 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
937 /*
938 * Unpause the sequencer and let it clear
939 * SEQINT by writing NO_SEQINT to it. This
940 * will cause the sequencer to be paused again,
941 * which is the expected state of this routine.
942 */
943 ahd_unpause(ahd);
944 while (!ahd_is_paused(ahd))
945 ;
946 ahd_outb(ahd, CLRINT, CLRSEQINT);
947 }
948 ahd_update_modes(ahd);
949#ifdef AHD_DEBUG
950 if ((ahd_debug & AHD_SHOW_MISC) != 0)
951 printf("%s: Handle Seqint Called for code %d\n",
952 ahd_name(ahd), seqintcode);
953#endif
954 switch (seqintcode) {
955 case ENTERING_NONPACK:

--- 4 unchanged lines hidden (view full) ---

960 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
961 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
962 scbid = ahd_get_scbptr(ahd);
963 scb = ahd_lookup_scb(ahd, scbid);
964 if (scb == NULL) {
965 /*
966 * Somehow need to know if this
967 * is from a selection or reselection.
462 ahd_update_modes(ahd);
463#ifdef AHD_DEBUG
464 if ((ahd_debug & AHD_SHOW_MISC) != 0)
465 printf("%s: Handle Seqint Called for code %d\n",
466 ahd_name(ahd), seqintcode);
467#endif
468 switch (seqintcode) {
469 case ENTERING_NONPACK:

--- 4 unchanged lines hidden (view full) ---

474 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
475 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
476 scbid = ahd_get_scbptr(ahd);
477 scb = ahd_lookup_scb(ahd, scbid);
478 if (scb == NULL) {
479 /*
480 * Somehow need to know if this
481 * is from a selection or reselection.
968 * From that, we can determine target
482 * From that, we can termine target
969 * ID so we at least have an I_T nexus.
970 */
971 } else {
972 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
973 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
974 ahd_outb(ahd, SEQ_FLAGS, 0x0);
975 }
976 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
977 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
978 /*
979 * Phase change after read stream with
980 * CRC error with P0 asserted on last
981 * packet.
982 */
483 * ID so we at least have an I_T nexus.
484 */
485 } else {
486 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
487 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
488 ahd_outb(ahd, SEQ_FLAGS, 0x0);
489 }
490 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
491 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
492 /*
493 * Phase change after read stream with
494 * CRC error with P0 asserted on last
495 * packet.
496 */
983#ifdef AHD_DEBUG
984 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
985 printf("%s: Assuming LQIPHASE_NLQ with "
986 "P0 assertion\n", ahd_name(ahd));
987#endif
497 printf("Assuming LQIPHASE_NLQ with P0 assertion\n");
988 }
498 }
989#ifdef AHD_DEBUG
990 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
991 printf("%s: Entering NONPACK\n", ahd_name(ahd));
992#endif
499 printf("Entering NONPACK\n");
993 break;
994 }
995 case INVALID_SEQINT:
996 printf("%s: Invalid Sequencer interrupt occurred.\n",
997 ahd_name(ahd));
998 ahd_dump_card_state(ahd);
500 break;
501 }
502 case INVALID_SEQINT:
503 printf("%s: Invalid Sequencer interrupt occurred.\n",
504 ahd_name(ahd));
505 ahd_dump_card_state(ahd);
506 printf("invalid seqint");
999 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
507 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1000 AHD_UNCORRECTABLE_ERROR(ahd);
1001 break;
1002 case STATUS_OVERRUN:
1003 {
508 break;
509 case STATUS_OVERRUN:
510 {
1004 struct scb *scb;
1005 u_int scbid;
1006
1007 scbid = ahd_get_scbptr(ahd);
1008 scb = ahd_lookup_scb(ahd, scbid);
1009 if (scb != NULL)
1010 ahd_print_path(ahd, scb);
1011 else
1012 printf("%s: ", ahd_name(ahd));
1013 printf("SCB %d Packetized Status Overrun", scbid);
511 printf("%s: Status Overrun", ahd_name(ahd));
1014 ahd_dump_card_state(ahd);
1015 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
512 ahd_dump_card_state(ahd);
513 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1016 AHD_UNCORRECTABLE_ERROR(ahd);
1017 break;
1018 }
1019 case CFG4ISTAT_INTR:
1020 {
1021 struct scb *scb;
1022 u_int scbid;
1023
514 break;
515 }
516 case CFG4ISTAT_INTR:
517 {
518 struct scb *scb;
519 u_int scbid;
520
521 ahd_update_modes(ahd);
1024 scbid = ahd_get_scbptr(ahd);
1025 scb = ahd_lookup_scb(ahd, scbid);
1026 if (scb == NULL) {
1027 ahd_dump_card_state(ahd);
1028 printf("CFG4ISTAT: Free SCB %d referenced", scbid);
522 scbid = ahd_get_scbptr(ahd);
523 scb = ahd_lookup_scb(ahd, scbid);
524 if (scb == NULL) {
525 ahd_dump_card_state(ahd);
526 printf("CFG4ISTAT: Free SCB %d referenced", scbid);
1029 AHD_FATAL_ERROR(ahd);
1030 panic("For safety");
1031 }
1032 ahd_outq(ahd, HADDR, scb->sense_busaddr);
1033 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
1034 ahd_outb(ahd, HCNT + 2, 0);
1035 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
1036 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
1037 break;

--- 11 unchanged lines hidden (view full) ---

1049 case P_DATAIN:
1050 case P_DATAOUT_DT:
1051 case P_DATAIN_DT:
1052 case P_MESGOUT:
1053 case P_STATUS:
1054 case P_MESGIN:
1055 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1056 printf("%s: Issued Bus Reset.\n", ahd_name(ahd));
527 panic("For safety");
528 }
529 ahd_outq(ahd, HADDR, scb->sense_busaddr);
530 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
531 ahd_outb(ahd, HCNT + 2, 0);
532 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
533 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
534 break;

--- 11 unchanged lines hidden (view full) ---

546 case P_DATAIN:
547 case P_DATAOUT_DT:
548 case P_DATAIN_DT:
549 case P_MESGOUT:
550 case P_STATUS:
551 case P_MESGIN:
552 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
553 printf("%s: Issued Bus Reset.\n", ahd_name(ahd));
1057 AHD_UNCORRECTABLE_ERROR(ahd);
1058 break;
1059 case P_COMMAND:
1060 {
1061 struct ahd_devinfo devinfo;
1062 struct scb *scb;
1063 struct ahd_initiator_tinfo *targ_info;
1064 struct ahd_tmode_tstate *tstate;
1065 struct ahd_transinfo *tinfo;

--- 8 unchanged lines hidden (view full) ---

1074 * connection, we change our command to TUR, assert
1075 * ATN and ABORT the task when we go to message in
1076 * phase. The OSM will see the REQUEUE_REQUEST
1077 * status and retry the command.
1078 */
1079 scbid = ahd_get_scbptr(ahd);
1080 scb = ahd_lookup_scb(ahd, scbid);
1081 if (scb == NULL) {
554 break;
555 case P_COMMAND:
556 {
557 struct ahd_devinfo devinfo;
558 struct scb *scb;
559 struct ahd_initiator_tinfo *targ_info;
560 struct ahd_tmode_tstate *tstate;
561 struct ahd_transinfo *tinfo;

--- 8 unchanged lines hidden (view full) ---

570 * connection, we change our command to TUR, assert
571 * ATN and ABORT the task when we go to message in
572 * phase. The OSM will see the REQUEUE_REQUEST
573 * status and retry the command.
574 */
575 scbid = ahd_get_scbptr(ahd);
576 scb = ahd_lookup_scb(ahd, scbid);
577 if (scb == NULL) {
1082 AHD_CORRECTABLE_ERROR(ahd);
1083 printf("Invalid phase with no valid SCB. "
1084 "Resetting bus.\n");
1085 ahd_reset_channel(ahd, 'A',
1086 /*Initiate Reset*/TRUE);
1087 break;
1088 }
1089 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1090 SCB_GET_TARGET(ahd, scb),
1091 SCB_GET_LUN(scb),
1092 SCB_GET_CHANNEL(ahd, scb),
1093 ROLE_INITIATOR);
1094 targ_info = ahd_fetch_transinfo(ahd,
1095 devinfo.channel,
1096 devinfo.our_scsiid,
1097 devinfo.target,
1098 &tstate);
1099 tinfo = &targ_info->curr;
1100 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
578 printf("Invalid phase with no valid SCB. "
579 "Resetting bus.\n");
580 ahd_reset_channel(ahd, 'A',
581 /*Initiate Reset*/TRUE);
582 break;
583 }
584 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
585 SCB_GET_TARGET(ahd, scb),
586 SCB_GET_LUN(scb),
587 SCB_GET_CHANNEL(ahd, scb),
588 ROLE_INITIATOR);
589 targ_info = ahd_fetch_transinfo(ahd,
590 devinfo.channel,
591 devinfo.our_scsiid,
592 devinfo.target,
593 &tstate);
594 tinfo = &targ_info->curr;
595 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1101 AHD_TRANS_ACTIVE, /*paused*/TRUE);
596 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
597 /*paused*/TRUE);
1102 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1103 /*offset*/0, /*ppr_options*/0,
1104 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1105 ahd_outb(ahd, SCB_CDB_STORE, 0);
1106 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1107 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1108 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1109 ahd_outb(ahd, SCB_CDB_STORE+4, 0);

--- 6 unchanged lines hidden (view full) ---

1116 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1117 /*
1118 * The lun is 0, regardless of the SCB's lun
1119 * as we have not sent an identify message.
1120 */
1121 ahd_outb(ahd, SAVED_LUN, 0);
1122 ahd_outb(ahd, SEQ_FLAGS, 0);
1123 ahd_assert_atn(ahd);
598 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
599 /*offset*/0, /*ppr_options*/0,
600 AHD_TRANS_ACTIVE, /*paused*/TRUE);
601 ahd_outb(ahd, SCB_CDB_STORE, 0);
602 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
603 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
604 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
605 ahd_outb(ahd, SCB_CDB_STORE+4, 0);

--- 6 unchanged lines hidden (view full) ---

612 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
613 /*
614 * The lun is 0, regardless of the SCB's lun
615 * as we have not sent an identify message.
616 */
617 ahd_outb(ahd, SAVED_LUN, 0);
618 ahd_outb(ahd, SEQ_FLAGS, 0);
619 ahd_assert_atn(ahd);
1124 scb->flags &= ~SCB_PACKETIZED;
620 scb->flags &= ~(SCB_PACKETIZED);
1125 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1126 ahd_freeze_devq(ahd, scb);
621 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
622 ahd_freeze_devq(ahd, scb);
1127 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
1128 aic_freeze_scb(scb);
623 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
624 ahd_freeze_scb(scb);
1129
1130 /*
1131 * Allow the sequencer to continue with
1132 * non-pack processing.
1133 */
1134 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1135 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1136 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1137 ahd_outb(ahd, CLRLQOINT1, 0);
1138 }
625
626 /*
627 * Allow the sequencer to continue with
628 * non-pack processing.
629 */
630 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
631 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
632 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
633 ahd_outb(ahd, CLRLQOINT1, 0);
634 }
1139#ifdef AHD_DEBUG
1140 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1141 ahd_print_path(ahd, scb);
1142 AHD_CORRECTABLE_ERROR(ahd);
1143 printf("Unexpected command phase from "
1144 "packetized target\n");
1145 }
1146#endif
635 printf("Continuing non-pack processing...\n");
1147 break;
1148 }
1149 }
1150 break;
1151 }
1152 case CFG4OVERRUN:
636 break;
637 }
638 }
639 break;
640 }
641 case CFG4OVERRUN:
1153 {
1154 struct scb *scb;
1155 u_int scb_index;
1156
1157#ifdef AHD_DEBUG
1158 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1159 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1160 ahd_inb(ahd, MODE_PTR));
1161 }
1162#endif
1163 scb_index = ahd_get_scbptr(ahd);
1164 scb = ahd_lookup_scb(ahd, scb_index);
1165 if (scb == NULL) {
1166 /*
1167 * Attempt to transfer to an SCB that is
1168 * not outstanding.
1169 */
1170 ahd_assert_atn(ahd);
1171 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1172 ahd->msgout_buf[0] = MSG_ABORT_TASK;
1173 ahd->msgout_len = 1;
1174 ahd->msgout_index = 0;
1175 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1176 /*
1177 * Clear status received flag to prevent any
1178 * attempt to complete this bogus SCB.
1179 */
1180 ahd_outb(ahd, SCB_CONTROL,
1181 ahd_inb_scbram(ahd, SCB_CONTROL)
1182 & ~STATUS_RCVD);
1183 }
642 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
643 ahd_inb(ahd, MODE_PTR));
1184 break;
644 break;
1185 }
1186 case DUMP_CARD_STATE:
1187 {
1188 ahd_dump_card_state(ahd);
1189 break;
1190 }
1191 case PDATA_REINIT:
1192 {
645 case DUMP_CARD_STATE:
646 {
647 ahd_dump_card_state(ahd);
648 break;
649 }
650 case PDATA_REINIT:
651 {
1193#ifdef AHD_DEBUG
1194 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1195 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1196 "SG_CACHE_SHADOW = 0x%x\n",
1197 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1198 ahd_inb(ahd, SG_CACHE_SHADOW));
1199 }
1200#endif
652 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
653 "SG_CACHE_SHADOW = 0x%x\n",
654 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
655 ahd_inb(ahd, SG_CACHE_SHADOW));
1201 ahd_reinitialize_dataptrs(ahd);
1202 break;
1203 }
1204 case HOST_MSG_LOOP:
1205 {
1206 struct ahd_devinfo devinfo;
1207
1208 /*

--- 12 unchanged lines hidden (view full) ---

1221 struct scb *scb;
1222 u_int scb_index;
1223 u_int bus_phase;
1224
1225 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1226 if (bus_phase != P_MESGIN
1227 && bus_phase != P_MESGOUT) {
1228 printf("ahd_intr: HOST_MSG_LOOP bad "
656 ahd_reinitialize_dataptrs(ahd);
657 break;
658 }
659 case HOST_MSG_LOOP:
660 {
661 struct ahd_devinfo devinfo;
662
663 /*

--- 12 unchanged lines hidden (view full) ---

676 struct scb *scb;
677 u_int scb_index;
678 u_int bus_phase;
679
680 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
681 if (bus_phase != P_MESGIN
682 && bus_phase != P_MESGOUT) {
683 printf("ahd_intr: HOST_MSG_LOOP bad "
1229 "phase 0x%x\n", bus_phase);
1230 AHD_CORRECTABLE_ERROR(ahd);
684 "phase 0x%x\n",
685 bus_phase);
1231 /*
1232 * Probably transitioned to bus free before
1233 * we got here. Just punt the message.
1234 */
1235 ahd_dump_card_state(ahd);
1236 ahd_clear_intstat(ahd);
1237 ahd_restart(ahd);
1238 return;

--- 7 unchanged lines hidden (view full) ---

1246 &devinfo,
1247 scb);
1248 else {
1249 ahd->msg_type =
1250 MSG_TYPE_INITIATOR_MSGIN;
1251 ahd->msgin_index = 0;
1252 }
1253 }
686 /*
687 * Probably transitioned to bus free before
688 * we got here. Just punt the message.
689 */
690 ahd_dump_card_state(ahd);
691 ahd_clear_intstat(ahd);
692 ahd_restart(ahd);
693 return;

--- 7 unchanged lines hidden (view full) ---

701 &devinfo,
702 scb);
703 else {
704 ahd->msg_type =
705 MSG_TYPE_INITIATOR_MSGIN;
706 ahd->msgin_index = 0;
707 }
708 }
1254#ifdef AHD_TARGET_MODE
709#if AHD_TARGET_MODE
1255 else {
1256 if (bus_phase == P_MESGOUT) {
1257 ahd->msg_type =
1258 MSG_TYPE_TARGET_MSGOUT;
1259 ahd->msgin_index = 0;
1260 }
1261 else
1262 ahd_setup_target_msgin(ahd,

--- 9 unchanged lines hidden (view full) ---

1272 case NO_MATCH:
1273 {
1274 /* Ensure we don't leave the selection hardware on */
1275 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1276 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1277
1278 printf("%s:%c:%d: no active SCB for reconnecting "
1279 "target - issuing BUS DEVICE RESET\n",
710 else {
711 if (bus_phase == P_MESGOUT) {
712 ahd->msg_type =
713 MSG_TYPE_TARGET_MSGOUT;
714 ahd->msgin_index = 0;
715 }
716 else
717 ahd_setup_target_msgin(ahd,

--- 9 unchanged lines hidden (view full) ---

727 case NO_MATCH:
728 {
729 /* Ensure we don't leave the selection hardware on */
730 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
731 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
732
733 printf("%s:%c:%d: no active SCB for reconnecting "
734 "target - issuing BUS DEVICE RESET\n",
1280 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
735 ahd_name(ahd), 'A', ahd_inb(ahd, SELID));
1281 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
736 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1282 "REG0 == 0x%x ACCUM = 0x%x\n",
737 "ARG_1 == 0x%x ACCUM = 0x%x\n",
1283 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
738 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1284 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
739 ahd_inb(ahd, ARG_1), ahd_inb(ahd, ACCUM));
1285 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1286 "SINDEX == 0x%x\n",
1287 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1288 ahd_find_busy_tcl(ahd,
740 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
741 "SINDEX == 0x%x\n",
742 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
743 ahd_find_busy_tcl(ahd,
1289 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1290 ahd_inb(ahd, SAVED_LUN))),
1291 ahd_inw(ahd, SINDEX));
744 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
745 ahd_inb(ahd, SAVED_LUN))),
746 ahd_inb(ahd, SINDEX));
1292 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1293 "SCB_CONTROL == 0x%x\n",
1294 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1295 ahd_inb_scbram(ahd, SCB_LUN),
1296 ahd_inb_scbram(ahd, SCB_CONTROL));
1297 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1298 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1299 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));

--- 4 unchanged lines hidden (view full) ---

1304 ahd->msgout_index = 0;
1305 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1306 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1307 ahd_assert_atn(ahd);
1308 break;
1309 }
1310 case PROTO_VIOLATION:
1311 {
747 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
748 "SCB_CONTROL == 0x%x\n",
749 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
750 ahd_inb_scbram(ahd, SCB_LUN),
751 ahd_inb_scbram(ahd, SCB_CONTROL));
752 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
753 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
754 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));

--- 4 unchanged lines hidden (view full) ---

759 ahd->msgout_index = 0;
760 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
761 ahd_outb(ahd, MSG_OUT, HOST_MSG);
762 ahd_assert_atn(ahd);
763 break;
764 }
765 case PROTO_VIOLATION:
766 {
1312 ahd_handle_proto_violation(ahd);
1313 break;
767 struct scb *scb;
768 u_int scbid;
769 u_int scsiid;
770 u_int target;
771 u_int seq_flags;
772 u_int curphase;
773 int found;
774
775 scbid = ahd_get_scbptr(ahd);
776 scb = ahd_lookup_scb(ahd, scbid);
777 scsiid = ahd_inb(ahd, SAVED_SCSIID);
778 target = SCSIID_TARGET(ahd, scsiid);
779 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
780 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
781 if ((seq_flags & NOT_IDENTIFIED) != 0) {
782
783 /*
784 * The reconnecting target either did not send an
785 * identify message, or did, but we didn't find an SCB
786 * to match.
787 */
788 printf("%s:%c:%d: Target did not send an "
789 "IDENTIFY message. LASTPHASE = 0x%x, "
790 "SAVED_SCSIID == 0x%x\n", ahd_name(ahd),
791 'A', target, ahd_inb(ahd, LASTPHASE),
792 scsiid);
793 } else if (scb == NULL) {
794 /*
795 * We don't seem to have an SCB active for this
796 * transaction. Print an error and reset the bus.
797 */
798 printf("%s:%c:%d: No SCB found during protocol "
799 "violation\n", ahd_name(ahd), 'A', target);
800 goto proto_violation_reset;
801 } else if ((seq_flags & NO_CDB_SENT) != 0) {
802 ahd_print_path(ahd, scb);
803 printf("No or incomplete CDB sent to device.\n");
804 } else if ((ahd_inb(ahd, SCB_CONTROL) & STATUS_RCVD) == 0) {
805 /*
806 * The target never bothered to provide status to
807 * us prior to completing the command. Since we don't
808 * know the disposition of this command, we must attempt
809 * to abort it. Assert ATN and prepare to send an abort
810 * message.
811 */
812 ahd_print_path(ahd, scb);
813 printf("Completed command without status.\n");
814 } else {
815 ahd_print_path(ahd, scb);
816 printf("Unknown protocol violation.\n");
817 ahd_dump_card_state(ahd);
818 }
819 if ((curphase & ~P_DATAIN_DT) == 0) {
820proto_violation_reset:
821 /*
822 * Target either went directly to data
823 * phase or didn't respond to our ATN.
824 * The only safe thing to do is to blow
825 * it away with a bus reset.
826 */
827 found = ahd_reset_channel(ahd, 'A', TRUE);
828 printf("%s: Issued Channel %c Bus Reset. "
829 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
830 } else {
831 /*
832 * Leave the selection hardware off in case
833 * this abort attempt will affect yet to
834 * be sent commands.
835 */
836 ahd_outb(ahd, SCSISEQ0,
837 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
838 ahd_print_path(ahd, scb);
839 printf("Protocol violation %s. Attempting to abort.\n",
840 ahd_lookup_phase_entry(curphase)->phasemsg);
841 scb->flags |= SCB_ABORT;
842 ahd_assert_atn(ahd);
843 ahd_outb(ahd, MSG_OUT, HOST_MSG);
844 }
845 return;
1314 }
1315 case IGN_WIDE_RES:
1316 {
1317 struct ahd_devinfo devinfo;
1318
1319 ahd_fetch_devinfo(ahd, &devinfo);
1320 ahd_handle_ign_wide_residue(ahd, &devinfo);
1321 break;
1322 }
1323 case BAD_PHASE:
1324 {
1325 u_int lastphase;
1326
1327 lastphase = ahd_inb(ahd, LASTPHASE);
1328 printf("%s:%c:%d: unknown scsi bus phase %x, "
1329 "lastphase = 0x%x. Attempting to continue\n",
1330 ahd_name(ahd), 'A',
1331 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1332 lastphase, ahd_inb(ahd, SCSISIGI));
846 }
847 case IGN_WIDE_RES:
848 {
849 struct ahd_devinfo devinfo;
850
851 ahd_fetch_devinfo(ahd, &devinfo);
852 ahd_handle_ign_wide_residue(ahd, &devinfo);
853 break;
854 }
855 case BAD_PHASE:
856 {
857 u_int lastphase;
858
859 lastphase = ahd_inb(ahd, LASTPHASE);
860 printf("%s:%c:%d: unknown scsi bus phase %x, "
861 "lastphase = 0x%x. Attempting to continue\n",
862 ahd_name(ahd), 'A',
863 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
864 lastphase, ahd_inb(ahd, SCSISIGI));
1333 AHD_CORRECTABLE_ERROR(ahd);
1334 break;
1335 }
1336 case MISSED_BUSFREE:
1337 {
1338 u_int lastphase;
1339
1340 lastphase = ahd_inb(ahd, LASTPHASE);
1341 printf("%s:%c:%d: Missed busfree. "
1342 "Lastphase = 0x%x, Curphase = 0x%x\n",
1343 ahd_name(ahd), 'A',
1344 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1345 lastphase, ahd_inb(ahd, SCSISIGI));
865 break;
866 }
867 case MISSED_BUSFREE:
868 {
869 u_int lastphase;
870
871 lastphase = ahd_inb(ahd, LASTPHASE);
872 printf("%s:%c:%d: Missed busfree. "
873 "Lastphase = 0x%x, Curphase = 0x%x\n",
874 ahd_name(ahd), 'A',
875 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
876 lastphase, ahd_inb(ahd, SCSISIGI));
1346 AHD_CORRECTABLE_ERROR(ahd);
1347 ahd_restart(ahd);
1348 return;
1349 }
1350 case DATA_OVERRUN:
1351 {
1352 /*
1353 * When the sequencer detects an overrun, it
1354 * places the controller in "BITBUCKET" mode
1355 * and allows the target to complete its transfer.
1356 * Unfortunately, none of the counters get updated
1357 * when the controller is in this mode, so we have
1358 * no way of knowing how large the overrun was.
1359 */
1360 struct scb *scb;
877 ahd_restart(ahd);
878 return;
879 }
880 case DATA_OVERRUN:
881 {
882 /*
883 * When the sequencer detects an overrun, it
884 * places the controller in "BITBUCKET" mode
885 * and allows the target to complete its transfer.
886 * Unfortunately, none of the counters get updated
887 * when the controller is in this mode, so we have
888 * no way of knowing how large the overrun was.
889 */
890 struct scb *scb;
1361 u_int scbindex;
1362#ifdef AHD_DEBUG
1363 u_int lastphase;
1364#endif
891 u_int scbindex = ahd_get_scbptr(ahd);
892 u_int lastphase = ahd_inb(ahd, LASTPHASE);
1365
893
1366 scbindex = ahd_get_scbptr(ahd);
1367 scb = ahd_lookup_scb(ahd, scbindex);
894 scb = ahd_lookup_scb(ahd, scbindex);
1368#ifdef AHD_DEBUG
1369 lastphase = ahd_inb(ahd, LASTPHASE);
1370 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1371 ahd_print_path(ahd, scb);
1372 printf("data overrun detected %s. Tag == 0x%x.\n",
1373 ahd_lookup_phase_entry(lastphase)->phasemsg,
1374 SCB_GET_TAG(scb));
1375 ahd_print_path(ahd, scb);
1376 printf("%s seen Data Phase. Length = %ld. "
1377 "NumSGs = %d.\n",
1378 ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1379 ? "Have" : "Haven't",
1380 aic_get_transfer_length(scb), scb->sg_count);
1381 ahd_dump_sglist(scb);
1382 }
1383#endif
895 ahd_print_path(ahd, scb);
896 printf("data overrun detected %s."
897 " Tag == 0x%x.\n",
898 ahd_lookup_phase_entry(lastphase)->phasemsg,
899 SCB_GET_TAG(scb));
900 ahd_print_path(ahd, scb);
901 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
902 ahd_inb(ahd, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
903 ahd_get_transfer_length(scb), scb->sg_count);
904 ahd_dump_sglist(scb);
1384
1385 /*
1386 * Set this and it will take effect when the
1387 * target does a command complete.
1388 */
1389 ahd_freeze_devq(ahd, scb);
905
906 /*
907 * Set this and it will take effect when the
908 * target does a command complete.
909 */
910 ahd_freeze_devq(ahd, scb);
1390 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1391 aic_freeze_scb(scb);
911 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
912 ahd_freeze_scb(scb);
1392 break;
1393 }
1394 case MKMSG_FAILED:
1395 {
1396 struct ahd_devinfo devinfo;
1397 struct scb *scb;
1398 u_int scbid;
1399
1400 ahd_fetch_devinfo(ahd, &devinfo);
1401 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1402 ahd_name(ahd), devinfo.channel, devinfo.target,
1403 devinfo.lun);
1404 scbid = ahd_get_scbptr(ahd);
1405 scb = ahd_lookup_scb(ahd, scbid);
913 break;
914 }
915 case MKMSG_FAILED:
916 {
917 struct ahd_devinfo devinfo;
918 struct scb *scb;
919 u_int scbid;
920
921 ahd_fetch_devinfo(ahd, &devinfo);
922 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
923 ahd_name(ahd), devinfo.channel, devinfo.target,
924 devinfo.lun);
925 scbid = ahd_get_scbptr(ahd);
926 scb = ahd_lookup_scb(ahd, scbid);
1406 AHD_CORRECTABLE_ERROR(ahd);
1407 if (scb != NULL
1408 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1409 /*
1410 * Ensure that we didn't put a second instance of this
1411 * SCB into the QINFIFO.
1412 */
1413 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1414 SCB_GET_CHANNEL(ahd, scb),
1415 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1416 ROLE_INITIATOR, /*status*/0,
1417 SEARCH_REMOVE);
1418 ahd_outb(ahd, SCB_CONTROL,
927 if (scb != NULL
928 && (scb->flags & SCB_RECOVERY_SCB) != 0)
929 /*
930 * Ensure that we didn't put a second instance of this
931 * SCB into the QINFIFO.
932 */
933 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
934 SCB_GET_CHANNEL(ahd, scb),
935 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
936 ROLE_INITIATOR, /*status*/0,
937 SEARCH_REMOVE);
938 ahd_outb(ahd, SCB_CONTROL,
1419 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
939 ahd_inb(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1420 break;
1421 }
940 break;
941 }
1422 case TASKMGMT_FUNC_COMPLETE:
1423 {
1424 u_int scbid;
1425 struct scb *scb;
1426
1427 scbid = ahd_get_scbptr(ahd);
1428 scb = ahd_lookup_scb(ahd, scbid);
1429 if (scb != NULL) {
1430 u_int lun;
1431 u_int tag;
1432 cam_status error;
1433
1434 ahd_print_path(ahd, scb);
1435 printf("Task Management Func 0x%x Complete\n",
1436 scb->hscb->task_management);
1437 lun = CAM_LUN_WILDCARD;
1438 tag = SCB_LIST_NULL;
1439
1440 switch (scb->hscb->task_management) {
1441 case SIU_TASKMGMT_ABORT_TASK:
1442 tag = SCB_GET_TAG(scb);
1443 case SIU_TASKMGMT_ABORT_TASK_SET:
1444 case SIU_TASKMGMT_CLEAR_TASK_SET:
1445 lun = scb->hscb->lun;
1446 error = CAM_REQ_ABORTED;
1447 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1448 'A', lun, tag, ROLE_INITIATOR,
1449 error);
1450 break;
1451 case SIU_TASKMGMT_LUN_RESET:
1452 lun = scb->hscb->lun;
1453 case SIU_TASKMGMT_TARGET_RESET:
1454 {
1455 struct ahd_devinfo devinfo;
1456
1457 ahd_scb_devinfo(ahd, &devinfo, scb);
1458 error = CAM_BDR_SENT;
1459 ahd_handle_devreset(ahd, &devinfo, lun,
1460 CAM_BDR_SENT,
1461 lun != CAM_LUN_WILDCARD
1462 ? "Lun Reset"
1463 : "Target Reset",
1464 /*verbose_level*/0);
1465 break;
1466 }
1467 default:
1468 panic("Unexpected TaskMgmt Func\n");
1469 break;
1470 }
1471 }
1472 break;
1473 }
942 }
1474 case TASKMGMT_CMD_CMPLT_OKAY:
1475 {
1476 u_int scbid;
1477 struct scb *scb;
1478
1479 /*
1480 * An ABORT TASK TMF failed to be delivered before
1481 * the targeted command completed normally.
1482 */
1483 scbid = ahd_get_scbptr(ahd);
1484 scb = ahd_lookup_scb(ahd, scbid);
1485 if (scb != NULL) {
1486 /*
1487 * Remove the second instance of this SCB from
1488 * the QINFIFO if it is still there.
1489 */
1490 ahd_print_path(ahd, scb);
1491 printf("SCB completes before TMF\n");
1492 /*
1493 * Handle losing the race. Wait until any
1494 * current selection completes. We will then
1495 * set the TMF back to zero in this SCB so that
1496 * the sequencer doesn't bother to issue another
1497 * sequencer interrupt for its completion.
1498 */
1499 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1500 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1501 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1502 ;
1503 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1504 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1505 SCB_GET_CHANNEL(ahd, scb),
1506 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1507 ROLE_INITIATOR, /*status*/0,
1508 SEARCH_REMOVE);
1509 }
1510 break;
1511 }
1512 case TRACEPOINT0:
1513 case TRACEPOINT1:
1514 case TRACEPOINT2:
1515 case TRACEPOINT3:
1516 printf("%s: Tracepoint %d\n", ahd_name(ahd),
1517 seqintcode - TRACEPOINT0);
1518 break;
1519 case NO_SEQINT:
1520 break;
1521 case SAW_HWERR:
1522 ahd_handle_hwerrint(ahd);
1523 break;
1524 default:
1525 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1526 seqintcode);
1527 break;
1528 }
1529 /*
1530 * The sequencer is paused immediately on
1531 * a SEQINT, so we should restart it when
1532 * we're done.
1533 */
1534 ahd_unpause(ahd);
1535}
1536
1537void
1538ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1539{
1540 struct scb *scb;
1541 u_int status0;
1542 u_int status3;
1543 u_int status;
1544 u_int lqistat1;
1545 u_int lqostat0;
1546 u_int scbid;
943 /*
944 * The sequencer is paused immediately on
945 * a SEQINT, so we should restart it when
946 * we're done.
947 */
948 ahd_unpause(ahd);
949}
950
951void
952ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
953{
954 struct scb *scb;
955 u_int status0;
956 u_int status3;
957 u_int status;
958 u_int lqistat1;
959 u_int lqostat0;
960 u_int scbid;
1547 u_int busfreetime;
1548
1549 ahd_update_modes(ahd);
1550 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1551
1552 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1553 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1554 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1555 lqistat1 = ahd_inb(ahd, LQISTAT1);
1556 lqostat0 = ahd_inb(ahd, LQOSTAT0);
961
962 ahd_update_modes(ahd);
963 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
964
965 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
966 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
967 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
968 lqistat1 = ahd_inb(ahd, LQISTAT1);
969 lqostat0 = ahd_inb(ahd, LQOSTAT0);
1557 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1558 if ((status0 & (SELDI|SELDO)) != 0) {
1559 u_int simode0;
1560
1561 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1562 simode0 = ahd_inb(ahd, SIMODE0);
970 if ((status0 & (SELDI|SELDO)) != 0) {
971 u_int simode0;
972
973 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
974 simode0 = ahd_inb(ahd, SIMODE0);
1563 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
975 status0 &= simode0 & (ENSELDO|ENSELDI|IOERR);
1564 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1565 }
1566 scbid = ahd_get_scbptr(ahd);
1567 scb = ahd_lookup_scb(ahd, scbid);
1568 if (scb != NULL
1569 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1570 scb = NULL;
1571
976 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
977 }
978 scbid = ahd_get_scbptr(ahd);
979 scb = ahd_lookup_scb(ahd, scbid);
980 if (scb != NULL
981 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
982 scb = NULL;
983
984 /* Make sure the sequencer is in a safe location. */
985 ahd_clear_critical_section(ahd);
986
1572 if ((status0 & IOERR) != 0) {
987 if ((status0 & IOERR) != 0) {
1573 u_int now_lvd;
988 int now_lvd;
1574
1575 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1576 printf("%s: Transceiver State Has Changed to %s mode\n",
1577 ahd_name(ahd), now_lvd ? "LVD" : "SE");
1578 ahd_outb(ahd, CLRSINT0, CLRIOERR);
989
990 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
991 printf("%s: Transceiver State Has Changed to %s mode\n",
992 ahd_name(ahd), now_lvd ? "LVD" : "SE");
993 ahd_outb(ahd, CLRSINT0, CLRIOERR);
994/* XXX Still True?? */
1579 /*
995 /*
1580 * A change in I/O mode is equivalent to a bus reset.
996 * When transitioning to SE mode, the reset line
997 * glitches, triggering an arbitration bug in some
998 * Ultra2 controllers. This bug is cleared when we
999 * assert the reset line. Since a reset glitch has
1000 * already occurred with this transition and a
1001 * transceiver state change is handled just like
1002 * a bus reset anyway, asserting the reset line
1003 * ourselves is safe.
1581 */
1004 */
1582 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1005 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/now_lvd == 0);
1006
1583 ahd_pause(ahd);
1584 ahd_setup_iocell_workaround(ahd);
1585 ahd_unpause(ahd);
1586 } else if ((status0 & OVERRUN) != 0) {
1007 ahd_pause(ahd);
1008 ahd_setup_iocell_workaround(ahd);
1009 ahd_unpause(ahd);
1010 } else if ((status0 & OVERRUN) != 0) {
1587
1588 printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1589 ahd_name(ahd));
1011 printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1012 ahd_name(ahd));
1590 AHD_CORRECTABLE_ERROR(ahd);
1591 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1592 } else if ((status & SCSIRSTI) != 0) {
1013 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1014 } else if ((status & SCSIRSTI) != 0) {
1593
1594 printf("%s: Someone reset channel A\n", ahd_name(ahd));
1595 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1015 printf("%s: Someone reset channel A\n", ahd_name(ahd));
1016 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1596 AHD_UNCORRECTABLE_ERROR(ahd);
1597 } else if ((status & SCSIPERR) != 0) {
1017 } else if ((status & SCSIPERR) != 0) {
1598
1599 /* Make sure the sequencer is in a safe location. */
1600 ahd_clear_critical_section(ahd);
1601
1602 ahd_handle_transmission_error(ahd);
1603 } else if (lqostat0 != 0) {
1018 ahd_handle_transmission_error(ahd);
1019 } else if (lqostat0 != 0) {
1604
1605 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1606 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1020 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1021 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1607 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1022 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1608 ahd_outb(ahd, CLRLQOINT1, 0);
1023 ahd_outb(ahd, CLRLQOINT1, 0);
1024 }
1609 } else if ((status & SELTO) != 0) {
1025 } else if ((status & SELTO) != 0) {
1610 u_int scbid;
1026 u_int scbid;
1611
1612 /* Stop the selection */
1613 ahd_outb(ahd, SCSISEQ0, 0);
1614
1027
1028 /* Stop the selection */
1029 ahd_outb(ahd, SCSISEQ0, 0);
1030
1615 /* Make sure the sequencer is in a safe location. */
1616 ahd_clear_critical_section(ahd);
1617
1618 /* No more pending messages */
1619 ahd_clear_msg_state(ahd);
1620
1621 /* Clear interrupt state */
1031 /* No more pending messages */
1032 ahd_clear_msg_state(ahd);
1033
1034 /* Clear interrupt state */
1035 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1622 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1623
1624 /*
1625 * Although the driver does not care about the
1626 * 'Selection in Progress' status bit, the busy
1627 * LED does. SELINGO is only cleared by a sucessfull
1628 * selection, so we must manually clear it to insure
1629 * the LED turns off just incase no future successful
1630 * selections occur (e.g. no devices on the bus).
1631 */
1632 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1633
1634 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1036 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1037
1038 /*
1039 * Although the driver does not care about the
1040 * 'Selection in Progress' status bit, the busy
1041 * LED does. SELINGO is only cleared by a sucessfull
1042 * selection, so we must manually clear it to insure
1043 * the LED turns off just incase no future successful
1044 * selections occur (e.g. no devices on the bus).
1045 */
1046 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1047
1048 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1049#ifdef AHD_DEBUG
1050 if ((ahd_debug & AHD_SHOW_SELTO) != 0)
1051 printf("%s: Saw Selection Timeout for SCB 0x%x\n",
1052 ahd_name(ahd), scbid);
1053#endif
1635 scb = ahd_lookup_scb(ahd, scbid);
1636 if (scb == NULL) {
1637 printf("%s: ahd_intr - referenced scb not "
1638 "valid during SELTO scb(0x%x)\n",
1639 ahd_name(ahd), scbid);
1640 ahd_dump_card_state(ahd);
1054 scb = ahd_lookup_scb(ahd, scbid);
1055 if (scb == NULL) {
1056 printf("%s: ahd_intr - referenced scb not "
1057 "valid during SELTO scb(0x%x)\n",
1058 ahd_name(ahd), scbid);
1059 ahd_dump_card_state(ahd);
1641 AHD_UNCORRECTABLE_ERROR(ahd);
1060 panic("For diagnostics");
1642 } else {
1061 } else {
1643 struct ahd_devinfo devinfo;
1644#ifdef AHD_DEBUG
1645 if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1646 ahd_print_path(ahd, scb);
1647 printf("Saw Selection Timeout for SCB 0x%x\n",
1648 scbid);
1649 }
1650#endif
1651 ahd_scb_devinfo(ahd, &devinfo, scb);
1652 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1062 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1653 ahd_freeze_devq(ahd, scb);
1063 ahd_freeze_devq(ahd, scb);
1654
1655 /*
1656 * Cancel any pending transactions on the device
1657 * now that it seems to be missing. This will
1658 * also revert us to async/narrow transfers until
1659 * we can renegotiate with the device.
1660 */
1661 ahd_handle_devreset(ahd, &devinfo,
1662 CAM_LUN_WILDCARD,
1663 CAM_SEL_TIMEOUT,
1664 "Selection Timeout",
1665 /*verbose_level*/1);
1666 }
1667 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1668 ahd_iocell_first_selection(ahd);
1064 }
1065 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1066 ahd_iocell_first_selection(ahd);
1669 ahd_unpause(ahd);
1067 ahd_restart(ahd);
1670 } else if ((status0 & (SELDI|SELDO)) != 0) {
1068 } else if ((status0 & (SELDI|SELDO)) != 0) {
1671
1672 ahd_iocell_first_selection(ahd);
1673 ahd_unpause(ahd);
1674 } else if (status3 != 0) {
1675 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1676 ahd_name(ahd), status3);
1069 ahd_iocell_first_selection(ahd);
1070 ahd_unpause(ahd);
1071 } else if (status3 != 0) {
1072 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1073 ahd_name(ahd), status3);
1677 AHD_CORRECTABLE_ERROR(ahd);
1678 ahd_outb(ahd, CLRSINT3, status3);
1679 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1074 ahd_outb(ahd, CLRSINT3, status3);
1075 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1680
1681 /* Make sure the sequencer is in a safe location. */
1682 ahd_clear_critical_section(ahd);
1683
1684 ahd_handle_lqiphase_error(ahd, lqistat1);
1076 ahd_handle_lqiphase_error(ahd, lqistat1);
1685 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1686 /*
1687 * This status can be delayed during some
1688 * streaming operations. The SCSIPHASE
1689 * handler has already dealt with this case
1690 * so just clear the error.
1691 */
1692 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1693 } else if ((status & BUSFREE) != 0
1694 || (lqistat1 & LQOBUSFREE) != 0) {
1077 } else if ((status & BUSFREE) != 0) {
1078 u_int busfreetime;
1695 u_int lqostat1;
1696 int restart;
1697 int clear_fifo;
1698 int packetized;
1699 u_int mode;
1700
1701 /*
1702 * Clear our selection hardware as soon as possible.
1703 * We may have an entry in the waiting Q for this target,
1704 * that is affected by this busfree and we don't want to
1705 * go about selecting the target while we handle the event.
1706 */
1707 ahd_outb(ahd, SCSISEQ0, 0);
1708
1079 u_int lqostat1;
1080 int restart;
1081 int clear_fifo;
1082 int packetized;
1083 u_int mode;
1084
1085 /*
1086 * Clear our selection hardware as soon as possible.
1087 * We may have an entry in the waiting Q for this target,
1088 * that is affected by this busfree and we don't want to
1089 * go about selecting the target while we handle the event.
1090 */
1091 ahd_outb(ahd, SCSISEQ0, 0);
1092
1709 /* Make sure the sequencer is in a safe location. */
1710 ahd_clear_critical_section(ahd);
1711
1712 /*
1713 * Determine what we were up to at the time of
1714 * the busfree.
1715 */
1716 mode = AHD_MODE_SCSI;
1093 /*
1094 * Determine what we were up to at the time of
1095 * the busfree.
1096 */
1097 mode = AHD_MODE_SCSI;
1098 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1717 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1718 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1719 switch (busfreetime) {
1720 case BUSFREE_DFF0:
1721 case BUSFREE_DFF1:
1722 {
1723 u_int scbid;
1724 struct scb *scb;
1725
1726 mode = busfreetime == BUSFREE_DFF0
1727 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1728 ahd_set_modes(ahd, mode, mode);
1729 scbid = ahd_get_scbptr(ahd);
1730 scb = ahd_lookup_scb(ahd, scbid);
1731 if (scb == NULL) {
1099 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1100 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1101 switch (busfreetime) {
1102 case BUSFREE_DFF0:
1103 case BUSFREE_DFF1:
1104 {
1105 u_int scbid;
1106 struct scb *scb;
1107
1108 mode = busfreetime == BUSFREE_DFF0
1109 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1110 ahd_set_modes(ahd, mode, mode);
1111 scbid = ahd_get_scbptr(ahd);
1112 scb = ahd_lookup_scb(ahd, scbid);
1113 if (scb == NULL) {
1732 printf("%s: Invalid SCB %d in DFF%d "
1114 printf("%s: Invalid SCB in DFF%d "
1733 "during unexpected busfree\n",
1115 "during unexpected busfree\n",
1734 ahd_name(ahd), scbid, mode);
1116 ahd_name(ahd), mode);
1735 packetized = 0;
1117 packetized = 0;
1736 AHD_CORRECTABLE_ERROR(ahd);
1737 } else
1738 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1739 clear_fifo = 1;
1740 break;
1741 }
1742 case BUSFREE_LQO:
1743 clear_fifo = 0;
1744 packetized = 1;
1745 break;
1746 default:
1747 clear_fifo = 0;
1748 packetized = (lqostat1 & LQOBUSFREE) != 0;
1749 if (!packetized
1118 } else
1119 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1120 clear_fifo = 1;
1121 break;
1122 }
1123 case BUSFREE_LQO:
1124 clear_fifo = 0;
1125 packetized = 1;
1126 break;
1127 default:
1128 clear_fifo = 0;
1129 packetized = (lqostat1 & LQOBUSFREE) != 0;
1130 if (!packetized
1750 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
1751 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
1752 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
1753 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
1754 /*
1755 * Assume packetized if we are not
1756 * on the bus in a non-packetized
1757 * capacity and any pending selection
1758 * was a packetized selection.
1759 */
1131 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE)
1760 packetized = 1;
1761 break;
1762 }
1763
1764#ifdef AHD_DEBUG
1765 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1766 printf("Saw Busfree. Busfreetime = 0x%x.\n",
1767 busfreetime);
1768#endif
1769 /*
1770 * Busfrees that occur in non-packetized phases are
1771 * handled by the nonpkt_busfree handler.
1772 */
1773 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1774 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1775 } else {
1132 packetized = 1;
1133 break;
1134 }
1135
1136#ifdef AHD_DEBUG
1137 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1138 printf("Saw Busfree. Busfreetime = 0x%x.\n",
1139 busfreetime);
1140#endif
1141 /*
1142 * Busfrees that occur in non-packetized phases are
1143 * handled by the nonpkt_busfree handler.
1144 */
1145 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1146 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1147 } else {
1776 packetized = 0;
1777 restart = ahd_handle_nonpkt_busfree(ahd);
1778 }
1779 /*
1780 * Clear the busfree interrupt status. The setting of
1148 restart = ahd_handle_nonpkt_busfree(ahd);
1149 }
1150 /*
1151 * Clear the busfree interrupt status. The setting of
1781 * the interrupt is a pulse, so in a perfect world, we
1782 * would not need to muck with the ENBUSFREE logic. This
1783 * would ensure that if the bus moves on to another
1784 * connection, busfree protection is still in force. If
1785 * BUSFREEREV is broken, however, we must manually clear
1786 * the ENBUSFREE if the busfree occurred during a non-pack
1787 * connection so that we don't get false positives during
1788 * future, packetized, connections.
1152 * the interrupt is a pulse, so we do not need to muck
1153 * with the ENBUSFREE logic. This also ensures that if
1154 * the bus has moved on to another connection, busfree
1155 * protection is still in force.
1789 */
1156 */
1790 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1791 if (packetized == 0
1792 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1793 ahd_outb(ahd, SIMODE1,
1794 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1157 ahd_outb(ahd, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1795
1796 if (clear_fifo)
1797 ahd_clear_fifo(ahd, mode);
1798
1799 ahd_clear_msg_state(ahd);
1800 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1158
1159 if (clear_fifo)
1160 ahd_clear_fifo(ahd, mode);
1161
1162 ahd_clear_msg_state(ahd);
1163 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1801 if (restart) {
1164 if (restart)
1802 ahd_restart(ahd);
1165 ahd_restart(ahd);
1803 } else {
1166 else {
1804 ahd_unpause(ahd);
1805 }
1806 } else {
1807 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1808 ahd_name(ahd), status);
1167 ahd_unpause(ahd);
1168 }
1169 } else {
1170 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1171 ahd_name(ahd), status);
1172 printf("%s: lqostat1 == 0x%x, SIMODE1 == 0x%x\n",
1173 ahd_name(ahd), ahd_inb(ahd, LQOSTAT1),
1174 ahd_inb(ahd, SIMODE1));
1175 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1809 ahd_dump_card_state(ahd);
1176 ahd_dump_card_state(ahd);
1810 ahd_clear_intstat(ahd);
1177 panic("Missing SCSIINT case");
1811 ahd_unpause(ahd);
1812 }
1813}
1814
1815static void
1816ahd_handle_transmission_error(struct ahd_softc *ahd)
1817{
1178 ahd_unpause(ahd);
1179 }
1180}
1181
1182static void
1183ahd_handle_transmission_error(struct ahd_softc *ahd)
1184{
1818 struct scb *scb;
1819 u_int scbid;
1820 u_int lqistat1;
1821 u_int lqistat2;
1822 u_int msg_out;
1823 u_int curphase;
1824 u_int lastphase;
1825 u_int perrdiag;
1826 u_int cur_col;
1827 int silent;
1185 u_int lqistat1;
1186 u_int lqistat2;
1187 u_int msg_out;
1188 u_int curphase;
1189 u_int lastphase;
1190 u_int perrdiag;
1828
1191
1829 scb = NULL;
1830 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1831 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1832 lqistat2 = ahd_inb(ahd, LQISTAT2);
1833 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1834 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1835 u_int lqistate;
1836
1837 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1838 lqistate = ahd_inb(ahd, LQISTATE);
1839 if ((lqistate >= 0x1E && lqistate <= 0x24)
1840 || (lqistate == 0x29)) {
1192 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1193 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1194 lqistat2 = ahd_inb(ahd, LQISTAT2);
1195 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1196 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1197 u_int lqistate;
1198
1199 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1200 lqistate = ahd_inb(ahd, LQISTATE);
1201 if ((lqistate >= 0x1E && lqistate <= 0x24)
1202 || (lqistate == 0x29)) {
1841#ifdef AHD_DEBUG
1842 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1843 printf("%s: NLQCRC found via LQISTATE\n",
1844 ahd_name(ahd));
1845 }
1846#endif
1203 printf("%s: NLQCRC found via LQISTATE\n",
1204 ahd_name(ahd));
1847 lqistat1 |= LQICRCI_NLQ;
1848 }
1849 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1850 }
1851
1852 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1853 lastphase = ahd_inb(ahd, LASTPHASE);
1854 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1855 perrdiag = ahd_inb(ahd, PERRDIAG);
1856 msg_out = MSG_INITIATOR_DET_ERR;
1857 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1205 lqistat1 |= LQICRCI_NLQ;
1206 }
1207 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1208 }
1209
1210 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1211 lastphase = ahd_inb(ahd, LASTPHASE);
1212 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1213 perrdiag = ahd_inb(ahd, PERRDIAG);
1214 msg_out = MSG_INITIATOR_DET_ERR;
1215 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1858
1859 /*
1860 * Try to find the SCB associated with this error.
1861 */
1862 silent = FALSE;
1863 if (lqistat1 == 0
1864 || (lqistat1 & LQICRCI_NLQ) != 0) {
1865 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1866 ahd_set_active_fifo(ahd);
1867 scbid = ahd_get_scbptr(ahd);
1868 scb = ahd_lookup_scb(ahd, scbid);
1869 if (scb != NULL && SCB_IS_SILENT(scb))
1870 silent = TRUE;
1871 }
1872
1873 cur_col = 0;
1874 if (silent == FALSE) {
1875 printf("%s: Transmission error detected\n", ahd_name(ahd));
1876 ahd_lqistat1_print(lqistat1, &cur_col, 50);
1877 ahd_lastphase_print(lastphase, &cur_col, 50);
1878 ahd_scsisigi_print(curphase, &cur_col, 50);
1879 ahd_perrdiag_print(perrdiag, &cur_col, 50);
1880 printf("\n");
1881 AHD_CORRECTABLE_ERROR(ahd);
1882 ahd_dump_card_state(ahd);
1883 }
1884
1216 printf("%s: Transmission error detected\n", ahd_name(ahd));
1217 printf("%s: lqistat1 == 0x%x, LASTPHASE == 0x0%x, "
1218 "curphase = 0x%x, perrdiag == 0x%x\n",
1219 ahd_name(ahd), lqistat1, lastphase, curphase, perrdiag);
1220 ahd_dump_card_state(ahd);
1885 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1221 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1886 if (silent == FALSE) {
1887 printf("%s: Gross protocol error during incoming "
1888 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1889 ahd_name(ahd), lqistat1);
1890 AHD_UNCORRECTABLE_ERROR(ahd);
1891 }
1222 printf("%s: Gross protocol error during incoming "
1223 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1224 ahd_name(ahd), lqistat1);
1892 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1893 return;
1894 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1895 /*
1896 * A CRC error has been detected on an incoming LQ.
1897 * The bus is currently hung on the last ACK.
1898 * Hit LQIRETRY to release the last ack, and
1899 * wait for the sequencer to determine that ATNO

--- 10 unchanged lines hidden (view full) ---

1910 * ignore a perfectly valid "unexected busfree"
1911 * after our "initiator detected error" message is
1912 * sent. A busfree is the expected response after
1913 * we tell the target that it's L_Q was corrupted.
1914 * (SPI4R09 10.7.3.3.3)
1915 */
1916 ahd_outb(ahd, LQCTL2, LQIRETRY);
1917 printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1225 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1226 return;
1227 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1228 /*
1229 * A CRC error has been detected on an incoming LQ.
1230 * The bus is currently hung on the last ACK.
1231 * Hit LQIRETRY to release the last ack, and
1232 * wait for the sequencer to determine that ATNO

--- 10 unchanged lines hidden (view full) ---

1243 * ignore a perfectly valid "unexected busfree"
1244 * after our "initiator detected error" message is
1245 * sent. A busfree is the expected response after
1246 * we tell the target that it's L_Q was corrupted.
1247 * (SPI4R09 10.7.3.3.3)
1248 */
1249 ahd_outb(ahd, LQCTL2, LQIRETRY);
1250 printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1918 AHD_CORRECTABLE_ERROR(ahd);
1919 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1251 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1252 u_int scbid;
1253 struct scb *scb;
1254
1920 /*
1921 * We detected a CRC error in a NON-LQ packet.
1922 * The hardware has varying behavior in this situation
1923 * depending on whether this packet was part of a
1924 * stream or not.
1925 *
1926 * PKT by PKT mode:
1927 * The hardware has already acked the complete packet.

--- 23 unchanged lines hidden (view full) ---

1951 * start another packet in response to our message.
1952 * Busfree detection is enabled.
1953 *
1954 * Read Streaming P0 not asserted:
1955 * If we raise ATN and the target transitions to
1956 * MSGOUT in or after a packet where P0 is not
1957 * asserted, the hardware will assert LQIPHASE_NLQ.
1958 * We should respond to the LQIPHASE_NLQ with an
1255 /*
1256 * We detected a CRC error in a NON-LQ packet.
1257 * The hardware has varying behavior in this situation
1258 * depending on whether this packet was part of a
1259 * stream or not.
1260 *
1261 * PKT by PKT mode:
1262 * The hardware has already acked the complete packet.

--- 23 unchanged lines hidden (view full) ---

1286 * start another packet in response to our message.
1287 * Busfree detection is enabled.
1288 *
1289 * Read Streaming P0 not asserted:
1290 * If we raise ATN and the target transitions to
1291 * MSGOUT in or after a packet where P0 is not
1292 * asserted, the hardware will assert LQIPHASE_NLQ.
1293 * We should respond to the LQIPHASE_NLQ with an
1959 * LQIRETRY. Should the target stay in a non-pkt
1294 * LQICONTINUE. Should the target stay in a non-pkt
1960 * phase after we send our message, the hardware
1961 * will assert LQIPHASE_LQ. Recovery is then just as
1962 * listed above for the read streaming with P0 asserted.
1963 * Busfree detection is enabled.
1964 */
1295 * phase after we send our message, the hardware
1296 * will assert LQIPHASE_LQ. Recovery is then just as
1297 * listed above for the read streaming with P0 asserted.
1298 * Busfree detection is enabled.
1299 */
1965 if (silent == FALSE)
1966 printf("LQICRC_NLQ\n");
1300 printf("LQICRC_NLQ\n");
1301 ahd_set_active_fifo(ahd);
1302 scbid = ahd_get_scbptr(ahd);
1303 scb = ahd_lookup_scb(ahd, scbid);
1967 if (scb == NULL) {
1968 printf("%s: No SCB valid for LQICRC_NLQ. "
1969 "Resetting bus\n", ahd_name(ahd));
1304 if (scb == NULL) {
1305 printf("%s: No SCB valid for LQICRC_NLQ. "
1306 "Resetting bus\n", ahd_name(ahd));
1970 AHD_UNCORRECTABLE_ERROR(ahd);
1971 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1972 return;
1973 }
1307 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1308 return;
1309 }
1310 scb->flags |= SCB_TRANSMISSION_ERROR;
1974 } else if ((lqistat1 & LQIBADLQI) != 0) {
1975 printf("Need to handle BADLQI!\n");
1976 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1977 return;
1311 } else if ((lqistat1 & LQIBADLQI) != 0) {
1312 printf("Need to handle BADLQI!\n");
1313 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1314 return;
1978 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1315 } else if ((perrdiag & (PARITYERR|LASTPHASE)) == PARITYERR) {
1979 if ((curphase & ~P_DATAIN_DT) != 0) {
1980 /* Ack the byte. So we can continue. */
1316 if ((curphase & ~P_DATAIN_DT) != 0) {
1317 /* Ack the byte. So we can continue. */
1981 if (silent == FALSE)
1982 printf("Acking %s to clear perror\n",
1983 ahd_lookup_phase_entry(curphase)->phasemsg);
1318 printf("Acking %s to clear perror\n",
1319 ahd_lookup_phase_entry(curphase)->phasemsg);
1984 ahd_inb(ahd, SCSIDAT);
1985 }
1986
1987 if (curphase == P_MESGIN)
1988 msg_out = MSG_PARITY_ERROR;
1989 }
1990
1991 /*
1992 * We've set the hardware to assert ATN if we
1993 * get a parity error on "in" phases, so all we
1994 * need to do is stuff the message buffer with
1995 * the appropriate message. "In" phases have set
1996 * mesg_out to something other than MSG_NOP.
1997 */
1998 ahd->send_msg_perror = msg_out;
1320 ahd_inb(ahd, SCSIDAT);
1321 }
1322
1323 if (curphase == P_MESGIN)
1324 msg_out = MSG_PARITY_ERROR;
1325 }
1326
1327 /*
1328 * We've set the hardware to assert ATN if we
1329 * get a parity error on "in" phases, so all we
1330 * need to do is stuff the message buffer with
1331 * the appropriate message. "In" phases have set
1332 * mesg_out to something other than MSG_NOP.
1333 */
1334 ahd->send_msg_perror = msg_out;
1999 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
2000 scb->flags |= SCB_TRANSMISSION_ERROR;
2001 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2002 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2003 ahd_unpause(ahd);
2004}
2005
2006static void
2007ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
2008{

--- 11 unchanged lines hidden (view full) ---

2020 * way toward sending the message. Otherwise, reset
2021 * the bus to clear the error.
2022 */
2023 ahd_set_active_fifo(ahd);
2024 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
2025 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
2026 if ((lqistat1 & LQIPHASE_LQ) != 0) {
2027 printf("LQIRETRY for LQIPHASE_LQ\n");
1335 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1336 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1337 ahd_unpause(ahd);
1338}
1339
1340static void
1341ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
1342{

--- 11 unchanged lines hidden (view full) ---

1354 * way toward sending the message. Otherwise, reset
1355 * the bus to clear the error.
1356 */
1357 ahd_set_active_fifo(ahd);
1358 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
1359 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
1360 if ((lqistat1 & LQIPHASE_LQ) != 0) {
1361 printf("LQIRETRY for LQIPHASE_LQ\n");
2028 AHD_CORRECTABLE_ERROR(ahd);
2029 ahd_outb(ahd, LQCTL2, LQIRETRY);
2030 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
1362 ahd_outb(ahd, LQCTL2, LQIRETRY);
1363 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
2031 printf("LQIRETRY for LQIPHASE_NLQ\n");
2032 AHD_CORRECTABLE_ERROR(ahd);
1364 printf("LQICONTINUE for LQIPHASE_NLQ\n");
2033 ahd_outb(ahd, LQCTL2, LQIRETRY);
2034 } else
2035 panic("ahd_handle_lqiphase_error: No phase errors\n");
2036 ahd_dump_card_state(ahd);
2037 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2038 ahd_unpause(ahd);
2039 } else {
2040 printf("Reseting Channel for LQI Phase error\n");
1365 ahd_outb(ahd, LQCTL2, LQIRETRY);
1366 } else
1367 panic("ahd_handle_lqiphase_error: No phase errors\n");
1368 ahd_dump_card_state(ahd);
1369 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1370 ahd_unpause(ahd);
1371 } else {
1372 printf("Reseting Channel for LQI Phase error\n");
2041 AHD_CORRECTABLE_ERROR(ahd);
2042 ahd_dump_card_state(ahd);
2043 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
2044 }
2045}
2046
2047/*
2048 * Packetized unexpected or expected busfree.
1373 ahd_dump_card_state(ahd);
1374 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1375 }
1376}
1377
1378/*
1379 * Packetized unexpected or expected busfree.
2049 * Entered in mode based on busfreetime.
1380 * Entered in MODE_SCSI.
2050 */
2051static int
2052ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
2053{
2054 u_int lqostat1;
2055
2056 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2057 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2058 lqostat1 = ahd_inb(ahd, LQOSTAT1);
2059 if ((lqostat1 & LQOBUSFREE) != 0) {
2060 struct scb *scb;
2061 u_int scbid;
1381 */
1382static int
1383ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
1384{
1385 u_int lqostat1;
1386
1387 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
1388 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
1389 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1390 if ((lqostat1 & LQOBUSFREE) != 0) {
1391 struct scb *scb;
1392 u_int scbid;
2062 u_int saved_scbptr;
2063 u_int waiting_h;
2064 u_int waiting_t;
2065 u_int next;
2066
1393 u_int waiting_h;
1394 u_int waiting_t;
1395 u_int next;
1396
1397 if ((busfreetime & BUSFREE_LQO) == 0)
1398 printf("%s: Warning, BUSFREE time is 0x%x. "
1399 "Expected BUSFREE_LQO.\n",
1400 ahd_name(ahd), busfreetime);
1401
1402 scbid = ahd_get_scbptr(ahd);
1403 scb = ahd_lookup_scb(ahd, scbid);
1404 if (scb == NULL)
1405 panic("SCB not valid during LQOBUSFREE");
1406 ahd_print_path(ahd, scb);
1407 printf("Probable outgoing LQ CRC error. Retrying command\n");
1408
2067 /*
1409 /*
1410 * Return the LQO manager to its idle loop. It will
1411 * not do this automatically if the busfree occurs
1412 * after the first REQ of either the LQ or command
1413 * packet or between the LQ and command packet.
1414 */
1415 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
1416
1417 /*
1418 * Clear the status.
1419 */
1420 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
1421 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1422 ahd_outb(ahd, CLRLQOINT1, 0);
1423 }
1424 /*
2068 * The LQO manager detected an unexpected busfree
2069 * either:
2070 *
2071 * 1) During an outgoing LQ.
2072 * 2) After an outgoing LQ but before the first
2073 * REQ of the command packet.
2074 * 3) During an outgoing command packet.
2075 *
2076 * In all cases, CURRSCB is pointing to the
2077 * SCB that encountered the failure. Clean
2078 * up the queue, clear SELDO and LQOBUSFREE,
2079 * and allow the sequencer to restart the select
2080 * out at its lesure.
2081 */
1425 * The LQO manager detected an unexpected busfree
1426 * either:
1427 *
1428 * 1) During an outgoing LQ.
1429 * 2) After an outgoing LQ but before the first
1430 * REQ of the command packet.
1431 * 3) During an outgoing command packet.
1432 *
1433 * In all cases, CURRSCB is pointing to the
1434 * SCB that encountered the failure. Clean
1435 * up the queue, clear SELDO and LQOBUSFREE,
1436 * and allow the sequencer to restart the select
1437 * out at its lesure.
1438 */
2082 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2083 scbid = ahd_inw(ahd, CURRSCB);
2084 scb = ahd_lookup_scb(ahd, scbid);
2085 if (scb == NULL)
2086 panic("SCB not valid during LQOBUSFREE");
2087 /*
2088 * Clear the status.
2089 */
2090 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
2091 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
2092 ahd_outb(ahd, CLRLQOINT1, 0);
2093 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1439 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2094 ahd_flush_device_writes(ahd);
2095 ahd_outb(ahd, CLRSINT0, CLRSELDO);
1440 ahd_outb(ahd, CLRSINT0, CLRSELDO);
2096
2097 /*
2098 * Return the LQO manager to its idle loop. It will
2099 * not do this automatically if the busfree occurs
2100 * after the first REQ of either the LQ or command
2101 * packet or between the LQ and command packet.
2102 */
2103 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2104
2105 /*
2106 * Update the waiting for selection queue so
2107 * we restart on the correct SCB.
2108 */
2109 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
1441 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2110 saved_scbptr = ahd_get_scbptr(ahd);
2111 if (waiting_h != scbid) {
2112
2113 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2114 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
1442 if (waiting_h != scbid) {
1443
1444 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
1445 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
1446 next = SCB_LIST_NULL;
2115 if (waiting_t == waiting_h) {
2116 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
1447 if (waiting_t == waiting_h) {
1448 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2117 next = SCB_LIST_NULL;
2118 } else {
2119 ahd_set_scbptr(ahd, waiting_h);
1449 } else {
1450 ahd_set_scbptr(ahd, waiting_h);
2120 next = ahd_inw_scbram(ahd, SCB_NEXT2);
1451 next = ahd_inw(ahd, SCB_NEXT2);
2121 }
2122 ahd_set_scbptr(ahd, scbid);
2123 ahd_outw(ahd, SCB_NEXT2, next);
2124 }
1452 }
1453 ahd_set_scbptr(ahd, scbid);
1454 ahd_outw(ahd, SCB_NEXT2, next);
1455 }
2125 ahd_set_scbptr(ahd, saved_scbptr);
2126 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2127 if (SCB_IS_SILENT(scb) == FALSE) {
2128 ahd_print_path(ahd, scb);
2129 printf("Probable outgoing LQ CRC error. "
2130 "Retrying command\n");
2131 AHD_CORRECTABLE_ERROR(ahd);
2132 }
2133 scb->crc_retry_count++;
2134 } else {
2135 aic_set_transaction_status(scb, CAM_UNCOR_PARITY);
2136 aic_freeze_scb(scb);
2137 ahd_freeze_devq(ahd, scb);
2138 }
1456
2139 /* Return unpausing the sequencer. */
2140 return (0);
1457 /* Return unpausing the sequencer. */
1458 return (0);
2141 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2142 /*
2143 * Ignore what are really parity errors that
2144 * occur on the last REQ of a free running
2145 * clock prior to going busfree. Some drives
2146 * do not properly active negate just before
2147 * going busfree resulting in a parity glitch.
2148 */
2149 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2150#ifdef AHD_DEBUG
2151 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2152 printf("%s: Parity on last REQ detected "
2153 "during busfree phase.\n",
2154 ahd_name(ahd));
2155#endif
2156 /* Return unpausing the sequencer. */
2157 return (0);
2158 }
2159 if (ahd->src_mode != AHD_MODE_SCSI) {
2160 u_int scbid;
2161 struct scb *scb;
2162
2163 scbid = ahd_get_scbptr(ahd);
2164 scb = ahd_lookup_scb(ahd, scbid);
2165 ahd_print_path(ahd, scb);
2166 printf("Unexpected PKT busfree condition\n");
1459 }
1460 if (ahd->src_mode != AHD_MODE_SCSI) {
1461 u_int scbid;
1462 struct scb *scb;
1463
1464 scbid = ahd_get_scbptr(ahd);
1465 scb = ahd_lookup_scb(ahd, scbid);
1466 ahd_print_path(ahd, scb);
1467 printf("Unexpected PKT busfree condition\n");
2167 AHD_UNCORRECTABLE_ERROR(ahd);
2168 ahd_dump_card_state(ahd);
2169 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2170 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2171 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2172
2173 /* Return restarting the sequencer. */
2174 return (1);
2175 }
2176 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
1468 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
1469 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1470 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
1471
1472 /* Return restarting the sequencer. */
1473 return (1);
1474 }
1475 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2177 AHD_UNCORRECTABLE_ERROR(ahd);
2178 ahd_dump_card_state(ahd);
2179 /* Restart the sequencer. */
2180 return (1);
2181}
2182
2183/*
2184 * Non-packetized unexpected or expected busfree.
2185 */
2186static int
2187ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2188{
2189 struct ahd_devinfo devinfo;
2190 struct scb *scb;
2191 u_int lastphase;
2192 u_int saved_scsiid;
2193 u_int saved_lun;
2194 u_int target;
2195 u_int initiator_role_id;
2196 u_int scbid;
1476 ahd_dump_card_state(ahd);
1477 /* Restart the sequencer. */
1478 return (1);
1479}
1480
1481/*
1482 * Non-packetized unexpected or expected busfree.
1483 */
1484static int
1485ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
1486{
1487 struct ahd_devinfo devinfo;
1488 struct scb *scb;
1489 u_int lastphase;
1490 u_int saved_scsiid;
1491 u_int saved_lun;
1492 u_int target;
1493 u_int initiator_role_id;
1494 u_int scbid;
2197 u_int ppr_busfree;
2198 int printerror;
2199
2200 /*
2201 * Look at what phase we were last in. If its message out,
2202 * chances are pretty good that the busfree was in response
2203 * to one of our abort requests.
2204 */
2205 lastphase = ahd_inb(ahd, LASTPHASE);

--- 6 unchanged lines hidden (view full) ---

2212 printerror = 1;
2213
2214 scbid = ahd_get_scbptr(ahd);
2215 scb = ahd_lookup_scb(ahd, scbid);
2216 if (scb != NULL
2217 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2218 scb = NULL;
2219
1495 int printerror;
1496
1497 /*
1498 * Look at what phase we were last in. If its message out,
1499 * chances are pretty good that the busfree was in response
1500 * to one of our abort requests.
1501 */
1502 lastphase = ahd_inb(ahd, LASTPHASE);

--- 6 unchanged lines hidden (view full) ---

1509 printerror = 1;
1510
1511 scbid = ahd_get_scbptr(ahd);
1512 scb = ahd_lookup_scb(ahd, scbid);
1513 if (scb != NULL
1514 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1515 scb = NULL;
1516
2220 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2221 if (lastphase == P_MESGOUT) {
2222 u_int tag;
2223
2224 tag = SCB_LIST_NULL;
2225 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2226 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2227 int found;
2228 int sent_msg;
2229
1517 if (lastphase == P_MESGOUT) {
1518 u_int tag;
1519
1520 tag = SCB_LIST_NULL;
1521 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
1522 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
1523 int found;
1524 int sent_msg;
1525
2230 if (scb == NULL) {
2231 ahd_print_devinfo(ahd, &devinfo);
2232 printf("Abort for unidentified "
2233 "connection completed.\n");
2234 /* restart the sequencer. */
2235 return (1);
2236 }
2237 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2238 ahd_print_path(ahd, scb);
2239 printf("SCB %d - Abort%s Completed.\n",
2240 SCB_GET_TAG(scb),
2241 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2242
2243 if (sent_msg == MSG_ABORT_TAG)
2244 tag = SCB_GET_TAG(scb);

--- 27 unchanged lines hidden (view full) ---

2272 * as completing with CAM_BDR_SENT. CAM3
2273 * specifies CAM_REQ_CMP.
2274 */
2275 if (scb != NULL
2276 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2277 && ahd_match_scb(ahd, scb, target, 'A',
2278 CAM_LUN_WILDCARD, SCB_LIST_NULL,
2279 ROLE_INITIATOR))
1526 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
1527 ahd_print_path(ahd, scb);
1528 printf("SCB %d - Abort%s Completed.\n",
1529 SCB_GET_TAG(scb),
1530 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
1531
1532 if (sent_msg == MSG_ABORT_TAG)
1533 tag = SCB_GET_TAG(scb);

--- 27 unchanged lines hidden (view full) ---

1561 * as completing with CAM_BDR_SENT. CAM3
1562 * specifies CAM_REQ_CMP.
1563 */
1564 if (scb != NULL
1565 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1566 && ahd_match_scb(ahd, scb, target, 'A',
1567 CAM_LUN_WILDCARD, SCB_LIST_NULL,
1568 ROLE_INITIATOR))
2280 aic_set_transaction_status(scb, CAM_REQ_CMP);
1569 ahd_set_transaction_status(scb, CAM_REQ_CMP);
2281#endif
1570#endif
2282 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2283 CAM_BDR_SENT, "Bus Device Reset",
1571 ahd_handle_devreset(ahd, &devinfo, CAM_BDR_SENT,
1572 "Bus Device Reset",
2284 /*verbose_level*/0);
2285 printerror = 0;
1573 /*verbose_level*/0);
1574 printerror = 0;
2286 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2287 && ppr_busfree == 0) {
1575 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)) {
2288 struct ahd_initiator_tinfo *tinfo;
2289 struct ahd_tmode_tstate *tstate;
2290
2291 /*
1576 struct ahd_initiator_tinfo *tinfo;
1577 struct ahd_tmode_tstate *tstate;
1578
1579 /*
2292 * PPR Rejected.
2293 *
2294 * If the previous negotiation was packetized,
2295 * this could be because the device has been
2296 * reset without our knowledge. Force our
2297 * current negotiation to async and retry the
2298 * negotiation. Otherwise retry the command
2299 * with non-ppr negotiation.
1580 * PPR Rejected. Try non-ppr negotiation
1581 * and retry command.
2300 */
1582 */
2301#ifdef AHD_DEBUG
2302 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2303 printf("PPR negotiation rejected busfree.\n");
2304#endif
2305 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2306 devinfo.our_scsiid,
2307 devinfo.target, &tstate);
1583 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
1584 devinfo.our_scsiid,
1585 devinfo.target, &tstate);
2308 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
2309 ahd_set_width(ahd, &devinfo,
2310 MSG_EXT_WDTR_BUS_8_BIT,
2311 AHD_TRANS_CUR,
2312 /*paused*/TRUE);
2313 ahd_set_syncrate(ahd, &devinfo,
2314 /*period*/0, /*offset*/0,
2315 /*ppr_options*/0,
2316 AHD_TRANS_CUR,
2317 /*paused*/TRUE);
2318 /*
2319 * The expect PPR busfree handler below
2320 * will effect the retry and necessary
2321 * abort.
2322 */
2323 } else {
2324 tinfo->curr.transport_version = 2;
2325 tinfo->goal.transport_version = 2;
2326 tinfo->goal.ppr_options = 0;
2327 /*
2328 * Remove any SCBs in the waiting for selection
2329 * queue that may also be for this target so
2330 * that command ordering is preserved.
2331 */
2332 ahd_freeze_devq(ahd, scb);
2333 ahd_qinfifo_requeue_tail(ahd, scb);
2334 printerror = 0;
2335 }
1586 tinfo->curr.transport_version = 2;
1587 tinfo->goal.transport_version = 2;
1588 tinfo->goal.ppr_options = 0;
1589 ahd_qinfifo_requeue_tail(ahd, scb);
1590 printerror = 0;
2336 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
1591 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2337 && ppr_busfree == 0) {
1592 || ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)) {
2338 /*
1593 /*
2339 * Negotiation Rejected. Go-narrow and
1594 * Negotiation Rejected. Go-async and
2340 * retry command.
2341 */
1595 * retry command.
1596 */
2342#ifdef AHD_DEBUG
2343 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2344 printf("WDTR negotiation rejected busfree.\n");
2345#endif
2346 ahd_set_width(ahd, &devinfo,
2347 MSG_EXT_WDTR_BUS_8_BIT,
2348 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2349 /*paused*/TRUE);
1597 ahd_set_width(ahd, &devinfo,
1598 MSG_EXT_WDTR_BUS_8_BIT,
1599 AHD_TRANS_CUR|AHD_TRANS_GOAL,
1600 /*paused*/TRUE);
2350 /*
2351 * Remove any SCBs in the waiting for selection
2352 * queue that may also be for this target so that
2353 * command ordering is preserved.
2354 */
2355 ahd_freeze_devq(ahd, scb);
2356 ahd_qinfifo_requeue_tail(ahd, scb);
2357 printerror = 0;
2358 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2359 && ppr_busfree == 0) {
2360 /*
2361 * Negotiation Rejected. Go-async and
2362 * retry command.
2363 */
2364#ifdef AHD_DEBUG
2365 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2366 printf("SDTR negotiation rejected busfree.\n");
2367#endif
2368 ahd_set_syncrate(ahd, &devinfo,
2369 /*period*/0, /*offset*/0,
2370 /*ppr_options*/0,
2371 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2372 /*paused*/TRUE);
1601 ahd_set_syncrate(ahd, &devinfo,
1602 /*period*/0, /*offset*/0,
1603 /*ppr_options*/0,
1604 AHD_TRANS_CUR|AHD_TRANS_GOAL,
1605 /*paused*/TRUE);
2373 /*
2374 * Remove any SCBs in the waiting for selection
2375 * queue that may also be for this target so that
2376 * command ordering is preserved.
2377 */
2378 ahd_freeze_devq(ahd, scb);
2379 ahd_qinfifo_requeue_tail(ahd, scb);
2380 printerror = 0;
2381 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2382 && ahd_sent_msg(ahd, AHDMSG_1B,
2383 MSG_INITIATOR_DET_ERR, TRUE)) {
2384
2385#ifdef AHD_DEBUG
2386 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2387 printf("Expected IDE Busfree\n");
2388#endif
2389 printerror = 0;
1606 ahd_qinfifo_requeue_tail(ahd, scb);
1607 printerror = 0;
1608 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
1609 && ahd_sent_msg(ahd, AHDMSG_1B,
1610 MSG_INITIATOR_DET_ERR, TRUE)) {
1611
1612#ifdef AHD_DEBUG
1613 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
1614 printf("Expected IDE Busfree\n");
1615#endif
1616 printerror = 0;
2390 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2391 && ahd_sent_msg(ahd, AHDMSG_1B,
2392 MSG_MESSAGE_REJECT, TRUE)) {
2393
2394#ifdef AHD_DEBUG
2395 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2396 printf("Expected QAS Reject Busfree\n");
2397#endif
2398 printerror = 0;
2399 }
1617 }
2400 }
1618 } else if (lastphase == P_MESGIN) {
2401
1619
2402 /*
2403 * The busfree required flag is honored at the end of
2404 * the message phases. We check it last in case we
2405 * had to send some other message that caused a busfree.
2406 */
2407 if (printerror != 0
2408 && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2409 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
1620 if ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0) {
2410
1621
2411 ahd_freeze_devq(ahd, scb);
2412 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
2413 aic_freeze_scb(scb);
2414 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2415 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2416 SCB_GET_CHANNEL(ahd, scb),
2417 SCB_GET_LUN(scb), SCB_LIST_NULL,
2418 ROLE_INITIATOR, CAM_REQ_ABORTED);
2419 } else {
1622 ahd_freeze_devq(ahd, scb);
1623 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
1624 ahd_freeze_scb(scb);
1625 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
1626 ahd_print_path(ahd, scb);
1627 printf("Now %spacketized.\n",
1628 (scb->flags & SCB_PACKETIZED) == 0
1629 ? "" : "non-");
1630 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1631 SCB_GET_CHANNEL(ahd, scb),
1632 SCB_GET_LUN(scb), SCB_LIST_NULL,
1633 ROLE_INITIATOR, CAM_REQ_ABORTED);
1634 } else {
2420#ifdef AHD_DEBUG
1635#ifdef AHD_DEBUG
2421 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2422 printf("PPR Negotiation Busfree.\n");
1636 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
1637 printf("PPR Negotiation Busfree.\n");
2423#endif
1638#endif
2424 ahd_done(ahd, scb);
1639 ahd_done(ahd, scb);
1640 }
1641 printerror = 0;
2425 }
1642 }
2426 printerror = 0;
2427 }
2428 if (printerror != 0) {
2429 int aborted;
2430
2431 aborted = 0;
2432 if (scb != NULL) {
2433 u_int tag;
2434

--- 8 unchanged lines hidden (view full) ---

2443 CAM_UNEXP_BUSFREE);
2444 } else {
2445 /*
2446 * We had not fully identified this connection,
2447 * so we cannot abort anything.
2448 */
2449 printf("%s: ", ahd_name(ahd));
2450 }
1643 }
1644 if (printerror != 0) {
1645 int aborted;
1646
1647 aborted = 0;
1648 if (scb != NULL) {
1649 u_int tag;
1650

--- 8 unchanged lines hidden (view full) ---

1659 CAM_UNEXP_BUSFREE);
1660 } else {
1661 /*
1662 * We had not fully identified this connection,
1663 * so we cannot abort anything.
1664 */
1665 printf("%s: ", ahd_name(ahd));
1666 }
1667 if (lastphase != P_BUSFREE)
1668 ahd_force_renegotiation(ahd, &devinfo);
2451 printf("Unexpected busfree %s, %d SCBs aborted, "
2452 "PRGMCNT == 0x%x\n",
2453 ahd_lookup_phase_entry(lastphase)->phasemsg,
2454 aborted,
1669 printf("Unexpected busfree %s, %d SCBs aborted, "
1670 "PRGMCNT == 0x%x\n",
1671 ahd_lookup_phase_entry(lastphase)->phasemsg,
1672 aborted,
2455 ahd_inw(ahd, PRGMCNT));
2456 AHD_UNCORRECTABLE_ERROR(ahd);
1673 ahd_inb(ahd, PRGMCNT)
1674 | (ahd_inb(ahd, PRGMCNT+1) << 8));
2457 ahd_dump_card_state(ahd);
1675 ahd_dump_card_state(ahd);
2458 if (lastphase != P_BUSFREE)
2459 ahd_force_renegotiation(ahd, &devinfo);
2460 }
2461 /* Always restart the sequencer. */
2462 return (1);
2463}
2464
1676 }
1677 /* Always restart the sequencer. */
1678 return (1);
1679}
1680
2465static void
2466ahd_handle_proto_violation(struct ahd_softc *ahd)
2467{
2468 struct ahd_devinfo devinfo;
2469 struct scb *scb;
2470 u_int scbid;
2471 u_int seq_flags;
2472 u_int curphase;
2473 u_int lastphase;
2474 int found;
2475
2476 ahd_fetch_devinfo(ahd, &devinfo);
2477 scbid = ahd_get_scbptr(ahd);
2478 scb = ahd_lookup_scb(ahd, scbid);
2479 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2480 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2481 lastphase = ahd_inb(ahd, LASTPHASE);
2482 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2483
2484 /*
2485 * The reconnecting target either did not send an
2486 * identify message, or did, but we didn't find an SCB
2487 * to match.
2488 */
2489 ahd_print_devinfo(ahd, &devinfo);
2490 printf("Target did not send an IDENTIFY message. "
2491 "LASTPHASE = 0x%x.\n", lastphase);
2492 AHD_UNCORRECTABLE_ERROR(ahd);
2493 scb = NULL;
2494 } else if (scb == NULL) {
2495 /*
2496 * We don't seem to have an SCB active for this
2497 * transaction. Print an error and reset the bus.
2498 */
2499 ahd_print_devinfo(ahd, &devinfo);
2500 printf("No SCB found during protocol violation\n");
2501 AHD_UNCORRECTABLE_ERROR(ahd);
2502 goto proto_violation_reset;
2503 } else {
2504 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2505 if ((seq_flags & NO_CDB_SENT) != 0) {
2506 ahd_print_path(ahd, scb);
2507 printf("No or incomplete CDB sent to device.\n");
2508 AHD_UNCORRECTABLE_ERROR(ahd);
2509 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2510 & STATUS_RCVD) == 0) {
2511 /*
2512 * The target never bothered to provide status to
2513 * us prior to completing the command. Since we don't
2514 * know the disposition of this command, we must attempt
2515 * to abort it. Assert ATN and prepare to send an abort
2516 * message.
2517 */
2518 ahd_print_path(ahd, scb);
2519 printf("Completed command without status.\n");
2520 } else {
2521 ahd_print_path(ahd, scb);
2522 printf("Unknown protocol violation.\n");
2523 AHD_UNCORRECTABLE_ERROR(ahd);
2524 ahd_dump_card_state(ahd);
2525 }
2526 }
2527 if ((lastphase & ~P_DATAIN_DT) == 0
2528 || lastphase == P_COMMAND) {
2529proto_violation_reset:
2530 /*
2531 * Target either went directly to data
2532 * phase or didn't respond to our ATN.
2533 * The only safe thing to do is to blow
2534 * it away with a bus reset.
2535 */
2536 found = ahd_reset_channel(ahd, 'A', TRUE);
2537 printf("%s: Issued Channel %c Bus Reset. "
2538 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2539 AHD_UNCORRECTABLE_ERROR(ahd);
2540 } else {
2541 /*
2542 * Leave the selection hardware off in case
2543 * this abort attempt will affect yet to
2544 * be sent commands.
2545 */
2546 ahd_outb(ahd, SCSISEQ0,
2547 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2548 ahd_assert_atn(ahd);
2549 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2550 if (scb == NULL) {
2551 ahd_print_devinfo(ahd, &devinfo);
2552 ahd->msgout_buf[0] = MSG_ABORT_TASK;
2553 ahd->msgout_len = 1;
2554 ahd->msgout_index = 0;
2555 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2556 } else {
2557 ahd_print_path(ahd, scb);
2558 scb->flags |= SCB_ABORT;
2559 }
2560 printf("Protocol violation %s. Attempting to abort.\n",
2561 ahd_lookup_phase_entry(curphase)->phasemsg);
2562 AHD_UNCORRECTABLE_ERROR(ahd);
2563 }
2564}
2565
2566/*
2567 * Force renegotiation to occur the next time we initiate
2568 * a command to the current device.
2569 */
2570static void
2571ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2572{
2573 struct ahd_initiator_tinfo *targ_info;
2574 struct ahd_tmode_tstate *tstate;
2575
1681/*
1682 * Force renegotiation to occur the next time we initiate
1683 * a command to the current device.
1684 */
1685static void
1686ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
1687{
1688 struct ahd_initiator_tinfo *targ_info;
1689 struct ahd_tmode_tstate *tstate;
1690
2576#ifdef AHD_DEBUG
2577 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2578 ahd_print_devinfo(ahd, devinfo);
2579 printf("Forcing renegotiation\n");
2580 }
2581#endif
1691 printf("Forcing renegotiation (%d:%c:%d)\n",
1692 devinfo->our_scsiid, devinfo->channel,
1693 devinfo->target);
2582 targ_info = ahd_fetch_transinfo(ahd,
2583 devinfo->channel,
2584 devinfo->our_scsiid,
2585 devinfo->target,
2586 &tstate);
2587 ahd_update_neg_request(ahd, devinfo, tstate,
1694 targ_info = ahd_fetch_transinfo(ahd,
1695 devinfo->channel,
1696 devinfo->our_scsiid,
1697 devinfo->target,
1698 &tstate);
1699 ahd_update_neg_request(ahd, devinfo, tstate,
2588 targ_info, AHD_NEG_IF_NON_ASYNC);
1700 targ_info, /*force*/TRUE);
2589}
2590
2591#define AHD_MAX_STEPS 2000
2592void
2593ahd_clear_critical_section(struct ahd_softc *ahd)
2594{
2595 ahd_mode_state saved_modes;
2596 int stepping;
2597 int steps;
1701}
1702
1703#define AHD_MAX_STEPS 2000
1704void
1705ahd_clear_critical_section(struct ahd_softc *ahd)
1706{
1707 ahd_mode_state saved_modes;
1708 int stepping;
1709 int steps;
2598 int first_instr;
2599 u_int simode0;
2600 u_int simode1;
2601 u_int simode3;
2602 u_int lqimode0;
2603 u_int lqimode1;
2604 u_int lqomode0;
2605 u_int lqomode1;
2606
2607 if (ahd->num_critical_sections == 0)
2608 return;
2609
2610 stepping = FALSE;
2611 steps = 0;
1710 u_int simode0;
1711 u_int simode1;
1712 u_int simode3;
1713 u_int lqimode0;
1714 u_int lqimode1;
1715 u_int lqomode0;
1716 u_int lqomode1;
1717
1718 if (ahd->num_critical_sections == 0)
1719 return;
1720
1721 stepping = FALSE;
1722 steps = 0;
2612 first_instr = 0;
2613 simode0 = 0;
2614 simode1 = 0;
2615 simode3 = 0;
2616 lqimode0 = 0;
2617 lqimode1 = 0;
2618 lqomode0 = 0;
2619 lqomode1 = 0;
2620 saved_modes = ahd_save_modes(ahd);
2621 for (;;) {
2622 struct cs *cs;
2623 u_int seqaddr;
2624 u_int i;
2625
2626 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1723 simode0 = 0;
1724 simode1 = 0;
1725 simode3 = 0;
1726 lqimode0 = 0;
1727 lqimode1 = 0;
1728 lqomode0 = 0;
1729 lqomode1 = 0;
1730 saved_modes = ahd_save_modes(ahd);
1731 for (;;) {
1732 struct cs *cs;
1733 u_int seqaddr;
1734 u_int i;
1735
1736 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2627 seqaddr = ahd_inw(ahd, CURADDR);
1737 seqaddr = ahd_inb(ahd, CURADDR)
1738 | (ahd_inb(ahd, CURADDR+1) << 8);
2628
2629 cs = ahd->critical_sections;
2630 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2631
2632 if (cs->begin < seqaddr && cs->end >= seqaddr)
2633 break;
2634 }
2635
2636 if (i == ahd->num_critical_sections)
2637 break;
2638
2639 if (steps > AHD_MAX_STEPS) {
1739
1740 cs = ahd->critical_sections;
1741 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
1742
1743 if (cs->begin < seqaddr && cs->end >= seqaddr)
1744 break;
1745 }
1746
1747 if (i == ahd->num_critical_sections)
1748 break;
1749
1750 if (steps > AHD_MAX_STEPS) {
2640 printf("%s: Infinite loop in critical section\n"
2641 "%s: First Instruction 0x%x now 0x%x\n",
2642 ahd_name(ahd), ahd_name(ahd), first_instr,
2643 seqaddr);
2644 AHD_FATAL_ERROR(ahd);
1751 printf("%s: Infinite loop in critical section\n",
1752 ahd_name(ahd));
2645 ahd_dump_card_state(ahd);
2646 panic("critical section loop");
2647 }
2648
2649 steps++;
1753 ahd_dump_card_state(ahd);
1754 panic("critical section loop");
1755 }
1756
1757 steps++;
2650#ifdef AHD_DEBUG
2651 if ((ahd_debug & AHD_SHOW_MISC) != 0)
2652 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2653 seqaddr);
2654#endif
2655 if (stepping == FALSE) {
2656
1758 if (stepping == FALSE) {
1759
2657 first_instr = seqaddr;
2658 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2659 simode0 = ahd_inb(ahd, SIMODE0);
1760 /*
1761 * Disable all interrupt sources so that the
1762 * sequencer will not be stuck by a pausing
1763 * interrupt condition while we attempt to
1764 * leave a critical section.
1765 */
1766 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1767 simode0 = ahd_inb(ahd, SIMODE0);
2660 simode3 = ahd_inb(ahd, SIMODE3);
2661 lqimode0 = ahd_inb(ahd, LQIMODE0);
2662 lqimode1 = ahd_inb(ahd, LQIMODE1);
2663 lqomode0 = ahd_inb(ahd, LQOMODE0);
2664 lqomode1 = ahd_inb(ahd, LQOMODE1);
2665 ahd_outb(ahd, SIMODE0, 0);
2666 ahd_outb(ahd, SIMODE3, 0);
2667 ahd_outb(ahd, LQIMODE0, 0);
2668 ahd_outb(ahd, LQIMODE1, 0);
2669 ahd_outb(ahd, LQOMODE0, 0);
2670 ahd_outb(ahd, LQOMODE1, 0);
2671 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2672 simode1 = ahd_inb(ahd, SIMODE1);
1768 simode3 = ahd_inb(ahd, SIMODE3);
1769 lqimode0 = ahd_inb(ahd, LQIMODE0);
1770 lqimode1 = ahd_inb(ahd, LQIMODE1);
1771 lqomode0 = ahd_inb(ahd, LQOMODE0);
1772 lqomode1 = ahd_inb(ahd, LQOMODE1);
1773 ahd_outb(ahd, SIMODE0, 0);
1774 ahd_outb(ahd, SIMODE3, 0);
1775 ahd_outb(ahd, LQIMODE0, 0);
1776 ahd_outb(ahd, LQIMODE1, 0);
1777 ahd_outb(ahd, LQOMODE0, 0);
1778 ahd_outb(ahd, LQOMODE1, 0);
1779 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1780 simode1 = ahd_inb(ahd, SIMODE1);
2673 /*
2674 * We don't clear ENBUSFREE. Unfortunately
2675 * we cannot re-enable busfree detection within
2676 * the current connection, so we must leave it
2677 * on while single stepping.
2678 */
2679 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
1781 ahd_outb(ahd, SIMODE1, 0);
1782 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2680 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2681 stepping = TRUE;
2682 }
1783 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
1784 stepping = TRUE;
1785 }
2683 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2684 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2685 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2686 ahd_outb(ahd, HCNTRL, ahd->unpause);
1786 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
1787 ahd_outb(ahd, HCNTRL, ahd->unpause);
2687 while (!ahd_is_paused(ahd))
2688 aic_delay(200);
1788 do {
1789 ahd_delay(200);
1790 } while (!ahd_is_paused(ahd));
2689 ahd_update_modes(ahd);
2690 }
2691 if (stepping) {
2692 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2693 ahd_outb(ahd, SIMODE0, simode0);
2694 ahd_outb(ahd, SIMODE3, simode3);
2695 ahd_outb(ahd, LQIMODE0, lqimode0);
2696 ahd_outb(ahd, LQIMODE1, lqimode1);
2697 ahd_outb(ahd, LQOMODE0, lqomode0);
2698 ahd_outb(ahd, LQOMODE1, lqomode1);
2699 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1791 ahd_update_modes(ahd);
1792 }
1793 if (stepping) {
1794 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1795 ahd_outb(ahd, SIMODE0, simode0);
1796 ahd_outb(ahd, SIMODE3, simode3);
1797 ahd_outb(ahd, LQIMODE0, lqimode0);
1798 ahd_outb(ahd, LQIMODE1, lqimode1);
1799 ahd_outb(ahd, LQOMODE0, lqomode0);
1800 ahd_outb(ahd, LQOMODE1, lqomode1);
1801 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1802 ahd_outb(ahd, SIMODE1, simode1);
2700 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
1803 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2701 ahd_outb(ahd, SIMODE1, simode1);
2702 /*
2703 * SCSIINT seems to glitch occassionally when
2704 * the interrupt masks are restored. Clear SCSIINT
2705 * one more time so that only persistent errors
2706 * are seen as a real interrupt.
2707 */
2708 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2709 }
2710 ahd_restore_modes(ahd, saved_modes);
2711}
2712
2713/*
2714 * Clear any pending interrupt status.
2715 */
2716void
2717ahd_clear_intstat(struct ahd_softc *ahd)
2718{
1804 }
1805 ahd_restore_modes(ahd, saved_modes);
1806}
1807
1808/*
1809 * Clear any pending interrupt status.
1810 */
1811void
1812ahd_clear_intstat(struct ahd_softc *ahd)
1813{
2719 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2720 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2721 /* Clear any interrupt conditions this may have caused */
1814 /* Clear any interrupt conditions this may have caused */
2722 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2723 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2724 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2725 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2726 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2727 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2728 |CLRLQOATNPKT|CLRLQOTCRC);
2729 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2730 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2731 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2732 ahd_outb(ahd, CLRLQOINT0, 0);
2733 ahd_outb(ahd, CLRLQOINT1, 0);
2734 }
2735 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2736 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2737 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
1815 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1816 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2738 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2739 |CLRIOERR|CLROVERRUN);
1817 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO|CLRIOERR);
2740 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2741}
2742
2743/**************************** Debugging Routines ******************************/
2744#ifdef AHD_DEBUG
2745uint32_t ahd_debug = AHD_DEBUG_OPTS;
2746#endif
2747void

--- 8 unchanged lines hidden (view full) ---

2756 hscb->control,
2757 hscb->scsiid,
2758 hscb->lun,
2759 hscb->cdb_len);
2760 printf("Shared Data: ");
2761 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2762 printf("%#02x", hscb->shared_data.idata.cdb[i]);
2763 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
1818 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1819}
1820
1821/**************************** Debugging Routines ******************************/
1822#ifdef AHD_DEBUG
1823uint32_t ahd_debug = AHD_DEBUG_OPTS;
1824#endif
1825void

--- 8 unchanged lines hidden (view full) ---

1834 hscb->control,
1835 hscb->scsiid,
1836 hscb->lun,
1837 hscb->cdb_len);
1838 printf("Shared Data: ");
1839 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
1840 printf("%#02x", hscb->shared_data.idata.cdb[i]);
1841 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2764 (uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2765 (uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2766 aic_le32toh(hscb->datacnt),
2767 aic_le32toh(hscb->sgptr),
1842 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
1843 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF),
1844 ahd_le32toh(hscb->datacnt),
1845 ahd_le32toh(hscb->sgptr),
2768 SCB_GET_TAG(scb));
2769 ahd_dump_sglist(scb);
2770}
2771
2772void
2773ahd_dump_sglist(struct scb *scb)
2774{
2775 int i;
2776
2777 if (scb->sg_count > 0) {
2778 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2779 struct ahd_dma64_seg *sg_list;
2780
2781 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2782 for (i = 0; i < scb->sg_count; i++) {
2783 uint64_t addr;
1846 SCB_GET_TAG(scb));
1847 ahd_dump_sglist(scb);
1848}
1849
1850void
1851ahd_dump_sglist(struct scb *scb)
1852{
1853 int i;
1854
1855 if (scb->sg_count > 0) {
1856 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
1857 struct ahd_dma64_seg *sg_list;
1858
1859 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
1860 for (i = 0; i < scb->sg_count; i++) {
1861 uint64_t addr;
2784 uint32_t len;
2785
1862
2786 addr = aic_le64toh(sg_list[i].addr);
2787 len = aic_le32toh(sg_list[i].len);
2788 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
1863 addr = ahd_le64toh(sg_list[i].addr);
1864 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
2789 i,
2790 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2791 (uint32_t)(addr & 0xFFFFFFFF),
1865 i,
1866 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
1867 (uint32_t)(addr & 0xFFFFFFFF),
2792 sg_list[i].len & AHD_SG_LEN_MASK,
2793 (sg_list[i].len & AHD_DMA_LAST_SEG)
2794 ? " Last" : "");
1868 ahd_le32toh(sg_list[i].len));
2795 }
2796 } else {
2797 struct ahd_dma_seg *sg_list;
2798
2799 sg_list = (struct ahd_dma_seg*)scb->sg_list;
2800 for (i = 0; i < scb->sg_count; i++) {
1869 }
1870 } else {
1871 struct ahd_dma_seg *sg_list;
1872
1873 sg_list = (struct ahd_dma_seg*)scb->sg_list;
1874 for (i = 0; i < scb->sg_count; i++) {
2801 uint32_t len;
2802
2803 len = aic_le32toh(sg_list[i].len);
2804 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
1875 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
2805 i,
1876 i,
2806 (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2807 aic_le32toh(sg_list[i].addr),
2808 len & AHD_SG_LEN_MASK,
2809 len & AHD_DMA_LAST_SEG ? " Last" : "");
1877 (ahd_le32toh(sg_list[i].len) >> 24
1878 & SG_HIGH_ADDR_BITS),
1879 ahd_le32toh(sg_list[i].addr),
1880 ahd_le32toh(sg_list[i].len)
1881 & AHD_SG_LEN_MASK);
2810 }
2811 }
2812 }
2813}
2814
2815/************************* Transfer Negotiation *******************************/
2816/*
2817 * Allocate per target mode instance (ID we respond to as a target)

--- 93 unchanged lines hidden (view full) ---

2911 * incoming negotiations even if target initiated
2912 * negotiation is not performed.
2913 */
2914 if (role == ROLE_TARGET)
2915 transinfo = &tinfo->user;
2916 else
2917 transinfo = &tinfo->goal;
2918 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
1882 }
1883 }
1884 }
1885}
1886
1887/************************* Transfer Negotiation *******************************/
1888/*
1889 * Allocate per target mode instance (ID we respond to as a target)

--- 93 unchanged lines hidden (view full) ---

1983 * incoming negotiations even if target initiated
1984 * negotiation is not performed.
1985 */
1986 if (role == ROLE_TARGET)
1987 transinfo = &tinfo->user;
1988 else
1989 transinfo = &tinfo->goal;
1990 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2919 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2920 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2921 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2922 }
2923 if (transinfo->period == 0) {
2924 *period = 0;
2925 *ppr_options = 0;
2926 } else {
2927 *period = MAX(*period, transinfo->period);
2928 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2929 }
2930}
2931
2932/*
2933 * Look up the valid period to SCSIRATE conversion in our table.
2934 * Return the period and offset that should be sent to the target
2935 * if this was the beginning of an SDTR.
2936 */
2937void
2938ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2939 u_int *ppr_options, u_int maxsync)
2940{
1991 if (transinfo->period == 0) {
1992 *period = 0;
1993 *ppr_options = 0;
1994 } else {
1995 *period = MAX(*period, transinfo->period);
1996 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
1997 }
1998}
1999
2000/*
2001 * Look up the valid period to SCSIRATE conversion in our table.
2002 * Return the period and offset that should be sent to the target
2003 * if this was the beginning of an SDTR.
2004 */
2005void
2006ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2007 u_int *ppr_options, u_int maxsync)
2008{
2009 /* Skip all PACED only entries if IU is not available */
2010 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2011 && maxsync < AHD_SYNCRATE_DT)
2012 maxsync = AHD_SYNCRATE_DT;
2013
2014 /* Skip all DT only entries if DT is not available */
2015 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2016 && maxsync < AHD_SYNCRATE_ULTRA2)
2017 maxsync = AHD_SYNCRATE_ULTRA2;
2018
2941 if (*period < maxsync)
2942 *period = maxsync;
2943
2944 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2945 && *period > AHD_SYNCRATE_MIN_DT)
2946 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2947
2948 if (*period > AHD_SYNCRATE_MIN)
2949 *period = 0;
2950
2951 /* Honor PPR option conformance rules. */
2019 if (*period < maxsync)
2020 *period = maxsync;
2021
2022 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2023 && *period > AHD_SYNCRATE_MIN_DT)
2024 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2025
2026 if (*period > AHD_SYNCRATE_MIN)
2027 *period = 0;
2028
2029 /* Honor PPR option conformance rules. */
2952 if (*period > AHD_SYNCRATE_PACED)
2953 *ppr_options &= ~MSG_EXT_PPR_RTI;
2954
2955 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2956 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2957
2958 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2959 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2030 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2031 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2032
2033 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2034 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2960
2961 /* Skip all PACED only entries if IU is not available */
2962 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2963 && *period < AHD_SYNCRATE_DT)
2964 *period = AHD_SYNCRATE_DT;
2965
2966 /* Skip all DT only entries if DT is not available */
2967 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2968 && *period < AHD_SYNCRATE_ULTRA2)
2969 *period = AHD_SYNCRATE_ULTRA2;
2970}
2971
2972/*
2973 * Truncate the given synchronous offset to a value the
2974 * current adapter type and syncrate are capable of.
2975 */
2976void
2977ahd_validate_offset(struct ahd_softc *ahd,
2978 struct ahd_initiator_tinfo *tinfo,
2979 u_int period, u_int *offset, int wide,
2980 role_t role)
2981{
2982 u_int maxoffset;
2983
2984 /* Limit offset to what we can do */
2985 if (period == 0)
2986 maxoffset = 0;
2035}
2036
2037/*
2038 * Truncate the given synchronous offset to a value the
2039 * current adapter type and syncrate are capable of.
2040 */
2041void
2042ahd_validate_offset(struct ahd_softc *ahd,
2043 struct ahd_initiator_tinfo *tinfo,
2044 u_int period, u_int *offset, int wide,
2045 role_t role)
2046{
2047 u_int maxoffset;
2048
2049 /* Limit offset to what we can do */
2050 if (period == 0)
2051 maxoffset = 0;
2987 else if (period <= AHD_SYNCRATE_PACED) {
2988 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2989 maxoffset = MAX_OFFSET_PACED_BUG;
2990 else
2991 maxoffset = MAX_OFFSET_PACED;
2992 } else
2993 maxoffset = MAX_OFFSET_NON_PACED;
2052 else if (period <= AHD_SYNCRATE_PACED)
2053 maxoffset = MAX_OFFSET_PACED;
2054 else
2055 maxoffset = MAX_OFFSET;
2994 *offset = MIN(*offset, maxoffset);
2995 if (tinfo != NULL) {
2996 if (role == ROLE_TARGET)
2997 *offset = MIN(*offset, tinfo->user.offset);
2998 else
2999 *offset = MIN(*offset, tinfo->goal.offset);
3000 }
3001}

--- 30 unchanged lines hidden (view full) ---

3032 * Update the bitmask of targets for which the controller should
3033 * negotiate with at the next convenient oportunity. This currently
3034 * means the next time we send the initial identify messages for
3035 * a new transaction.
3036 */
3037int
3038ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3039 struct ahd_tmode_tstate *tstate,
2056 *offset = MIN(*offset, maxoffset);
2057 if (tinfo != NULL) {
2058 if (role == ROLE_TARGET)
2059 *offset = MIN(*offset, tinfo->user.offset);
2060 else
2061 *offset = MIN(*offset, tinfo->goal.offset);
2062 }
2063}

--- 30 unchanged lines hidden (view full) ---

2094 * Update the bitmask of targets for which the controller should
2095 * negotiate with at the next convenient oportunity. This currently
2096 * means the next time we send the initial identify messages for
2097 * a new transaction.
2098 */
2099int
2100ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2101 struct ahd_tmode_tstate *tstate,
3040 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
2102 struct ahd_initiator_tinfo *tinfo, int force)
3041{
3042 u_int auto_negotiate_orig;
3043
3044 auto_negotiate_orig = tstate->auto_negotiate;
2103{
2104 u_int auto_negotiate_orig;
2105
2106 auto_negotiate_orig = tstate->auto_negotiate;
3045 if (neg_type == AHD_NEG_ALWAYS) {
3046 /*
3047 * Force our "current" settings to be
3048 * unknown so that unless a bus reset
3049 * occurs the need to renegotiate is
3050 * recorded persistently.
3051 */
3052 if ((ahd->features & AHD_WIDE) != 0)
3053 tinfo->curr.width = AHD_WIDTH_UNKNOWN;
3054 tinfo->curr.period = AHD_PERIOD_UNKNOWN;
3055 tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
3056 }
3057 if (tinfo->curr.period != tinfo->goal.period
3058 || tinfo->curr.width != tinfo->goal.width
3059 || tinfo->curr.offset != tinfo->goal.offset
3060 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
2107 if (tinfo->curr.period != tinfo->goal.period
2108 || tinfo->curr.width != tinfo->goal.width
2109 || tinfo->curr.offset != tinfo->goal.offset
2110 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
3061 || (neg_type == AHD_NEG_IF_NON_ASYNC
3062 && (tinfo->goal.offset != 0
2111 || (force
2112 && (tinfo->goal.period != 0
3063 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
3064 || tinfo->goal.ppr_options != 0)))
3065 tstate->auto_negotiate |= devinfo->target_mask;
3066 else
3067 tstate->auto_negotiate &= ~devinfo->target_mask;
3068
3069 return (auto_negotiate_orig != tstate->auto_negotiate);
3070}

--- 56 unchanged lines hidden (view full) ---

3127 tinfo->curr.period = period;
3128 tinfo->curr.offset = offset;
3129 tinfo->curr.ppr_options = ppr_options;
3130
3131 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3132 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3133 if (bootverbose) {
3134 if (offset != 0) {
2113 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
2114 || tinfo->goal.ppr_options != 0)))
2115 tstate->auto_negotiate |= devinfo->target_mask;
2116 else
2117 tstate->auto_negotiate &= ~devinfo->target_mask;
2118
2119 return (auto_negotiate_orig != tstate->auto_negotiate);
2120}

--- 56 unchanged lines hidden (view full) ---

2177 tinfo->curr.period = period;
2178 tinfo->curr.offset = offset;
2179 tinfo->curr.ppr_options = ppr_options;
2180
2181 ahd_send_async(ahd, devinfo->channel, devinfo->target,
2182 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2183 if (bootverbose) {
2184 if (offset != 0) {
3135 int options;
3136
3137 printf("%s: target %d synchronous with "
2185 printf("%s: target %d synchronous with "
3138 "period = 0x%x, offset = 0x%x",
2186 "period = 0x%x, offset = 0x%x%s\n",
3139 ahd_name(ahd), devinfo->target,
2187 ahd_name(ahd), devinfo->target,
3140 period, offset);
3141 options = 0;
3142 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
3143 printf("(RDSTRM");
3144 options++;
3145 }
3146 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
3147 printf("%s", options ? "|DT" : "(DT");
3148 options++;
3149 }
3150 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3151 printf("%s", options ? "|IU" : "(IU");
3152 options++;
3153 }
3154 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3155 printf("%s", options ? "|RTI" : "(RTI");
3156 options++;
3157 }
3158 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3159 printf("%s", options ? "|QAS" : "(QAS");
3160 options++;
3161 }
3162 if (options != 0)
3163 printf(")\n");
3164 else
3165 printf("\n");
2188 period, offset,
2189 (ppr_options & MSG_EXT_PPR_DT_REQ)
2190 ? " (DT)" : "");
3166 } else {
3167 printf("%s: target %d using "
2191 } else {
2192 printf("%s: target %d using "
3168 "asynchronous transfers%s\n",
3169 ahd_name(ahd), devinfo->target,
3170 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3171 ? "(QAS)" : "");
2193 "asynchronous transfers\n",
2194 ahd_name(ahd), devinfo->target);
3172 }
3173 }
3174 }
3175 /*
3176 * Always refresh the neg-table to handle the case of the
3177 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3178 * We will always renegotiate in that case if this is a
2195 }
2196 }
2197 }
2198 /*
2199 * Always refresh the neg-table to handle the case of the
2200 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
2201 * We will always renegotiate in that case if this is a
3179 * packetized request. Also manage the busfree expected flag
3180 * from this common routine so that we catch changes due to
3181 * WDTR or SDTR messages.
2202 * packetized request.
3182 */
2203 */
3183 if ((type & AHD_TRANS_CUR) != 0) {
3184 if (!paused)
3185 ahd_pause(ahd);
2204 if ((type & AHD_TRANS_CUR) != 0)
3186 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
2205 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3187 if (!paused)
3188 ahd_unpause(ahd);
3189 if (ahd->msg_type != MSG_TYPE_NONE) {
3190 if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3191 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3192#ifdef AHD_DEBUG
3193 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3194 ahd_print_devinfo(ahd, devinfo);
3195 printf("Expecting IU Change busfree\n");
3196 }
3197#endif
3198 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3199 | MSG_FLAG_IU_REQ_CHANGED;
3200 }
3201 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3202#ifdef AHD_DEBUG
3203 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3204 printf("PPR with IU_REQ outstanding\n");
3205#endif
3206 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3207 }
3208 }
3209 }
3210
3211 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
2206
2207 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3212 tinfo, AHD_NEG_TO_GOAL);
2208 tinfo, /*force*/FALSE);
3213
2209
3214 if (update_needed && active)
2210 if (update_needed)
3215 ahd_update_pending_scbs(ahd);
3216}
3217
3218/*
3219 * Update the user/goal/curr tables of wide negotiation
3220 * parameters as well as, in the case of a current or active update,
3221 * any data structures on the host controller. In the case of an
3222 * active update, the specified target is currently talking to us on

--- 30 unchanged lines hidden (view full) ---

3253 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3254 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3255 if (bootverbose) {
3256 printf("%s: target %d using %dbit transfers\n",
3257 ahd_name(ahd), devinfo->target,
3258 8 * (0x01 << width));
3259 }
3260 }
2211 ahd_update_pending_scbs(ahd);
2212}
2213
2214/*
2215 * Update the user/goal/curr tables of wide negotiation
2216 * parameters as well as, in the case of a current or active update,
2217 * any data structures on the host controller. In the case of an
2218 * active update, the specified target is currently talking to us on

--- 30 unchanged lines hidden (view full) ---

2249 ahd_send_async(ahd, devinfo->channel, devinfo->target,
2250 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2251 if (bootverbose) {
2252 printf("%s: target %d using %dbit transfers\n",
2253 ahd_name(ahd), devinfo->target,
2254 8 * (0x01 << width));
2255 }
2256 }
3261
3262 if ((type & AHD_TRANS_CUR) != 0) {
3263 if (!paused)
3264 ahd_pause(ahd);
2257 if ((type & AHD_TRANS_CUR) != 0)
3265 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
2258 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3266 if (!paused)
3267 ahd_unpause(ahd);
3268 }
3269
3270 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
2259
2260 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3271 tinfo, AHD_NEG_TO_GOAL);
3272 if (update_needed && active)
2261 tinfo, /*force*/FALSE);
2262 if (update_needed)
3273 ahd_update_pending_scbs(ahd);
2263 ahd_update_pending_scbs(ahd);
3274
3275}
3276
3277/*
3278 * Update the current state of tagged queuing for a given target.
3279 */
3280void
3281ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3282 ahd_queue_alg alg)
3283{
2264}
2265
2266/*
2267 * Update the current state of tagged queuing for a given target.
2268 */
2269void
2270ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2271 ahd_queue_alg alg)
2272{
3284 ahd_platform_set_tags(ahd, devinfo, alg);
3285 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3286 devinfo->lun, AC_TRANSFER_NEG, &alg);
2273 ahd_platform_set_tags(ahd, devinfo, alg);
2274 ahd_send_async(ahd, devinfo->channel, devinfo->target,
2275 devinfo->lun, AC_TRANSFER_NEG, &alg);
3287}
3288
3289static void
3290ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3291 struct ahd_transinfo *tinfo)
3292{
3293 ahd_mode_state saved_modes;
3294 u_int period;
3295 u_int ppr_opts;
3296 u_int con_opts;
3297 u_int offset;
2276}
2277
2278static void
2279ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2280 struct ahd_transinfo *tinfo)
2281{
2282 ahd_mode_state saved_modes;
2283 u_int period;
2284 u_int ppr_opts;
2285 u_int con_opts;
2286 u_int offset;
3298 u_int saved_negoaddr;
3299 uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
2287 u_int precomp;
3300
3301 saved_modes = ahd_save_modes(ahd);
3302 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3303
2288
2289 saved_modes = ahd_save_modes(ahd);
2290 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2291
3304 saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3305 ahd_outb(ahd, NEGOADDR, devinfo->target);
3306 period = tinfo->period;
3307 offset = tinfo->offset;
2292 ahd_outb(ahd, NEGOADDR, devinfo->target);
2293 period = tinfo->period;
2294 offset = tinfo->offset;
3308 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3309 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3310 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3311 con_opts = 0;
2295 precomp = 0;
3312 if (period == 0)
3313 period = AHD_SYNCRATE_ASYNC;
3314 if (period == AHD_SYNCRATE_160) {
2296 if (period == 0)
2297 period = AHD_SYNCRATE_ASYNC;
2298 if (period == AHD_SYNCRATE_160) {
3315
3316 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3317 /*
3318 * When the SPI4 spec was finalized, PACE transfers
3319 * was not made a configurable option in the PPR
3320 * message. Instead it is assumed to be enabled for
3321 * any syncrate faster than 80MHz. Nevertheless,
3322 * Harpoon2A4 allows this to be configurable.
3323 *
3324 * Harpoon2A4 also assumes at most 2 data bytes per
3325 * negotiated REQ/ACK offset. Paced transfers take
3326 * 4, so we must adjust our offset.
3327 */
3328 ppr_opts |= PPROPT_PACE;
3329 offset *= 2;
3330
3331 /*
3332 * Harpoon2A assumed that there would be a
3333 * fallback rate between 160MHz and 80Mhz,
3334 * so 7 is used as the period factor rather
3335 * than 8 for 160MHz.
3336 */
3337 period = AHD_SYNCRATE_REVA_160;
3338 }
3339 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3340 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3341 ~AHD_PRECOMP_MASK;
3342 } else {
3343 /*
3344 * Precomp should be disabled for non-paced transfers.
3345 */
3346 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3347
3348 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3349 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
3350 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
3351 /*
3352 * Slow down our CRC interval to be
3353 * compatible with non-packetized
3354 * U160 devices that can't handle a
3355 * CRC at full speed.
3356 */
3357 con_opts |= ENSLOWCRC;
3358 }
3359
3360 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3361 /*
3362 * On H2A4, revert to a slower slewrate
3363 * on non-paced transfers.
3364 */
3365 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3366 ~AHD_SLEWRATE_MASK;
3367 }
2299 period = AHD_SYNCRATE_REVA_160;
2300 precomp = 0;
2301 if ((ahd->flags & AHD_CPQ_BOARD) == 0)
2302 precomp |= AHD_PRECOMP_FASTSLEW;
2303 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) != 0)
2304 precomp |= AHD_PRECOMP_CUTBACK_29;
3368 }
2305 }
2306 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP);
2307 ahd_outb(ahd, ANNEXDAT, precomp);
3369
2308
3370 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3371 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3372 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3373 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3374
3375 ahd_outb(ahd, NEGPERIOD, period);
2309 ahd_outb(ahd, NEGPERIOD, period);
2310 ppr_opts = tinfo->ppr_options
2311 & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_IU_REQ);
2312 /*
2313 * When the SPI4 spec was finalized, PACE transfers
2314 * was not made a configurable option in the PPR message.
2315 * Instead it is assumed to be enabled for any
2316 * syncrate faster than 80MHz. Nevertheless, Harpoon
2317 * allows this to be configurable.
2318 *
2319 * Harpoon also assumes at most 2 data bytes per negotiated
2320 * REQ/ACK offset. Paced transfers take 4, so we must
2321 * adjust our offset.
2322 */
2323 if (period <= AHD_SYNCRATE_PACED) {
2324 ppr_opts |= PPROPT_PACE;
2325 offset *= 2;
2326 }
3376 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3377 ahd_outb(ahd, NEGOFFSET, offset);
3378
2327 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
2328 ahd_outb(ahd, NEGOFFSET, offset);
2329
2330 con_opts = 0;
3379 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3380 con_opts |= WIDEXFER;
3381
3382 /*
3383 * During packetized transfers, the target will
3384 * give us the oportunity to send command packets
3385 * without us asserting attention.
3386 */
3387 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3388 con_opts |= ENAUTOATNO;
3389 ahd_outb(ahd, NEGCONOPTS, con_opts);
2331 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
2332 con_opts |= WIDEXFER;
2333
2334 /*
2335 * During packetized transfers, the target will
2336 * give us the oportunity to send command packets
2337 * without us asserting attention.
2338 */
2339 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2340 con_opts |= ENAUTOATNO;
2341 ahd_outb(ahd, NEGCONOPTS, con_opts);
3390 ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3391 ahd_restore_modes(ahd, saved_modes);
3392}
3393
3394/*
2342 ahd_restore_modes(ahd, saved_modes);
2343}
2344
2345/*
3395 * When the transfer settings for a connection change, setup for
3396 * negotiation in pending SCBs to effect the change as quickly as
3397 * possible. We also cancel any negotiations that are scheduled
3398 * for inflight SCBs that have not been started yet.
2346 * When the transfer settings for a connection change, update any
2347 * in-transit SCBs to contain the new data so the hardware will
2348 * be set correctly during future (re)selections.
3399 */
3400static void
3401ahd_update_pending_scbs(struct ahd_softc *ahd)
3402{
3403 struct scb *pending_scb;
3404 int pending_scb_count;
2349 */
2350static void
2351ahd_update_pending_scbs(struct ahd_softc *ahd)
2352{
2353 struct scb *pending_scb;
2354 int pending_scb_count;
2355 int i;
3405 int paused;
3406 u_int saved_scbptr;
3407 ahd_mode_state saved_modes;
3408
3409 /*
3410 * Traverse the pending SCB list and ensure that all of the
2356 int paused;
2357 u_int saved_scbptr;
2358 ahd_mode_state saved_modes;
2359
2360 /*
2361 * Traverse the pending SCB list and ensure that all of the
3411 * SCBs there have the proper settings. We can only safely
3412 * clear the negotiation required flag (setting requires the
3413 * execution queue to be modified) and this is only possible
3414 * if we are not already attempting to select out for this
3415 * SCB. For this reason, all callers only call this routine
3416 * if we are changing the negotiation settings for the currently
3417 * active transaction on the bus.
2362 * SCBs there have the proper settings.
3418 */
3419 pending_scb_count = 0;
3420 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3421 struct ahd_devinfo devinfo;
2363 */
2364 pending_scb_count = 0;
2365 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
2366 struct ahd_devinfo devinfo;
2367 struct hardware_scb *pending_hscb;
3422 struct ahd_initiator_tinfo *tinfo;
3423 struct ahd_tmode_tstate *tstate;
3424
3425 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3426 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
3427 devinfo.our_scsiid,
3428 devinfo.target, &tstate);
2368 struct ahd_initiator_tinfo *tinfo;
2369 struct ahd_tmode_tstate *tstate;
2370
2371 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
2372 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2373 devinfo.our_scsiid,
2374 devinfo.target, &tstate);
2375 pending_hscb = pending_scb->hscb;
3429 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3430 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3431 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2376 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2377 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2378 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3432 pending_scb->hscb->control &= ~MK_MESSAGE;
2379 pending_hscb->control &= ~MK_MESSAGE;
3433 }
3434 ahd_sync_scb(ahd, pending_scb,
3435 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3436 pending_scb_count++;
3437 }
3438
3439 if (pending_scb_count == 0)
3440 return;
3441
3442 if (ahd_is_paused(ahd)) {
3443 paused = 1;
3444 } else {
3445 paused = 0;
3446 ahd_pause(ahd);
3447 }
3448
2380 }
2381 ahd_sync_scb(ahd, pending_scb,
2382 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2383 pending_scb_count++;
2384 }
2385
2386 if (pending_scb_count == 0)
2387 return;
2388
2389 if (ahd_is_paused(ahd)) {
2390 paused = 1;
2391 } else {
2392 paused = 0;
2393 ahd_pause(ahd);
2394 }
2395
3449 /*
3450 * Force the sequencer to reinitialize the selection for
3451 * the command at the head of the execution queue if it
3452 * has already been setup. The negotiation changes may
3453 * effect whether we select-out with ATN. It is only
3454 * safe to clear ENSELO when the bus is not free and no
3455 * selection is in progres or completed.
3456 */
3457 saved_modes = ahd_save_modes(ahd);
3458 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2396 saved_modes = ahd_save_modes(ahd);
2397 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3459 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
3460 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
3461 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3462 saved_scbptr = ahd_get_scbptr(ahd);
3463 /* Ensure that the hscbs down on the card match the new information */
2398 saved_scbptr = ahd_get_scbptr(ahd);
2399 /* Ensure that the hscbs down on the card match the new information */
3464 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3465 u_int scb_tag;
2400 for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
2401 struct hardware_scb *pending_hscb;
3466 u_int control;
2402 u_int control;
2403 u_int scb_tag;
3467
2404
3468 scb_tag = SCB_GET_TAG(pending_scb);
3469 ahd_set_scbptr(ahd, scb_tag);
2405 ahd_set_scbptr(ahd, i);
2406 scb_tag = i;
2407 pending_scb = ahd_lookup_scb(ahd, scb_tag);
2408 if (pending_scb == NULL)
2409 continue;
2410
2411 pending_hscb = pending_scb->hscb;
3470 control = ahd_inb_scbram(ahd, SCB_CONTROL);
3471 control &= ~MK_MESSAGE;
2412 control = ahd_inb_scbram(ahd, SCB_CONTROL);
2413 control &= ~MK_MESSAGE;
3472 control |= pending_scb->hscb->control & MK_MESSAGE;
2414 control |= pending_hscb->control & MK_MESSAGE;
3473 ahd_outb(ahd, SCB_CONTROL, control);
3474 }
2415 ahd_outb(ahd, SCB_CONTROL, control);
2416 }
3475 ahd_set_scbptr(ahd, saved_scbptr);
2417 ahd_set_scbptr(ahd,saved_scbptr);
3476 ahd_restore_modes(ahd, saved_modes);
3477
3478 if (paused == 0)
3479 ahd_unpause(ahd);
3480}
3481
3482/**************************** Pathing Information *****************************/
3483static void

--- 26 unchanged lines hidden (view full) ---

3510 our_id,
3511 SCSIID_TARGET(ahd, saved_scsiid),
3512 ahd_inb(ahd, SAVED_LUN),
3513 SCSIID_CHANNEL(ahd, saved_scsiid),
3514 role);
3515 ahd_restore_modes(ahd, saved_modes);
3516}
3517
2418 ahd_restore_modes(ahd, saved_modes);
2419
2420 if (paused == 0)
2421 ahd_unpause(ahd);
2422}
2423
2424/**************************** Pathing Information *****************************/
2425static void

--- 26 unchanged lines hidden (view full) ---

2452 our_id,
2453 SCSIID_TARGET(ahd, saved_scsiid),
2454 ahd_inb(ahd, SAVED_LUN),
2455 SCSIID_CHANNEL(ahd, saved_scsiid),
2456 role);
2457 ahd_restore_modes(ahd, saved_modes);
2458}
2459
3518void
3519ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3520{
3521 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3522 devinfo->target, devinfo->lun);
3523}
3524
3525struct ahd_phase_table_entry*
3526ahd_lookup_phase_entry(int phase)
3527{
3528 struct ahd_phase_table_entry *entry;
3529 struct ahd_phase_table_entry *last_entry;
3530
3531 /*
3532 * num_phases doesn't include the default entry which

--- 60 unchanged lines hidden (view full) ---

3593 if (ahd_currently_packetized(ahd))
3594 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3595
3596 if (ahd->send_msg_perror
3597 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3598 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3599 ahd->msgout_len++;
3600 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2460struct ahd_phase_table_entry*
2461ahd_lookup_phase_entry(int phase)
2462{
2463 struct ahd_phase_table_entry *entry;
2464 struct ahd_phase_table_entry *last_entry;
2465
2466 /*
2467 * num_phases doesn't include the default entry which

--- 60 unchanged lines hidden (view full) ---

2528 if (ahd_currently_packetized(ahd))
2529 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
2530
2531 if (ahd->send_msg_perror
2532 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
2533 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
2534 ahd->msgout_len++;
2535 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3601#ifdef AHD_DEBUG
3602 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3603 printf("Setting up for Parity Error delivery\n");
3604#endif
2536 printf("Setting up for Parity Error delivery\n");
3605 return;
3606 } else if (scb == NULL) {
3607 printf("%s: WARNING. No pending message for "
3608 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
2537 return;
2538 } else if (scb == NULL) {
2539 printf("%s: WARNING. No pending message for "
2540 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3609 AHD_CORRECTABLE_ERROR(ahd);
3610 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3611 ahd->msgout_len++;
3612 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3613 return;
3614 }
3615
3616 if ((scb->flags & SCB_DEVICE_RESET) == 0
3617 && (scb->flags & SCB_PACKETIZED) == 0

--- 14 unchanged lines hidden (view full) ---

3632 }
3633 }
3634
3635 if (scb->flags & SCB_DEVICE_RESET) {
3636 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3637 ahd->msgout_len++;
3638 ahd_print_path(ahd, scb);
3639 printf("Bus Device Reset Message Sent\n");
2541 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
2542 ahd->msgout_len++;
2543 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2544 return;
2545 }
2546
2547 if ((scb->flags & SCB_DEVICE_RESET) == 0
2548 && (scb->flags & SCB_PACKETIZED) == 0

--- 14 unchanged lines hidden (view full) ---

2563 }
2564 }
2565
2566 if (scb->flags & SCB_DEVICE_RESET) {
2567 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
2568 ahd->msgout_len++;
2569 ahd_print_path(ahd, scb);
2570 printf("Bus Device Reset Message Sent\n");
3640 AHD_CORRECTABLE_ERROR(ahd);
3641 /*
3642 * Clear our selection hardware in advance of
3643 * the busfree. We may have an entry in the waiting
3644 * Q for this target, and we don't want to go about
3645 * selecting while we handle the busfree and blow it
3646 * away.
3647 */
3648 ahd_outb(ahd, SCSISEQ0, 0);
3649 } else if ((scb->flags & SCB_ABORT) != 0) {
3650
3651 if ((scb->hscb->control & TAG_ENB) != 0) {
3652 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3653 } else {
3654 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3655 }
3656 ahd->msgout_len++;
3657 ahd_print_path(ahd, scb);
3658 printf("Abort%s Message Sent\n",
3659 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2571 /*
2572 * Clear our selection hardware in advance of
2573 * the busfree. We may have an entry in the waiting
2574 * Q for this target, and we don't want to go about
2575 * selecting while we handle the busfree and blow it
2576 * away.
2577 */
2578 ahd_outb(ahd, SCSISEQ0, 0);
2579 } else if ((scb->flags & SCB_ABORT) != 0) {
2580
2581 if ((scb->hscb->control & TAG_ENB) != 0) {
2582 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
2583 } else {
2584 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
2585 }
2586 ahd->msgout_len++;
2587 ahd_print_path(ahd, scb);
2588 printf("Abort%s Message Sent\n",
2589 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3660 AHD_CORRECTABLE_ERROR(ahd);
3661 /*
3662 * Clear our selection hardware in advance of
3663 * the busfree. We may have an entry in the waiting
3664 * Q for this target, and we don't want to go about
3665 * selecting while we handle the busfree and blow it
3666 * away.
3667 */
3668 ahd_outb(ahd, SCSISEQ0, 0);

--- 7 unchanged lines hidden (view full) ---

3676 * it away.
3677 */
3678 ahd_outb(ahd, SCSISEQ0, 0);
3679 } else {
3680 printf("ahd_intr: AWAITING_MSG for an SCB that "
3681 "does not have a waiting message\n");
3682 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3683 devinfo->target_mask);
2590 /*
2591 * Clear our selection hardware in advance of
2592 * the busfree. We may have an entry in the waiting
2593 * Q for this target, and we don't want to go about
2594 * selecting while we handle the busfree and blow it
2595 * away.
2596 */
2597 ahd_outb(ahd, SCSISEQ0, 0);

--- 7 unchanged lines hidden (view full) ---

2605 * it away.
2606 */
2607 ahd_outb(ahd, SCSISEQ0, 0);
2608 } else {
2609 printf("ahd_intr: AWAITING_MSG for an SCB that "
2610 "does not have a waiting message\n");
2611 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2612 devinfo->target_mask);
3684 AHD_FATAL_ERROR(ahd);
3685 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
2613 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
3686 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
2614 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3687 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3688 scb->flags);
2615 ahd_inb(ahd, MSG_OUT), scb->flags);
3689 }
3690
3691 /*
3692 * Clear the MK_MESSAGE flag from the SCB so we aren't
3693 * asked to send this message again.
3694 */
3695 ahd_outb(ahd, SCB_CONTROL,
3696 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);

--- 14 unchanged lines hidden (view full) ---

3711 * If our current and goal settings are identical,
3712 * we want to renegotiate due to a check condition.
3713 */
3714 struct ahd_initiator_tinfo *tinfo;
3715 struct ahd_tmode_tstate *tstate;
3716 int dowide;
3717 int dosync;
3718 int doppr;
2616 }
2617
2618 /*
2619 * Clear the MK_MESSAGE flag from the SCB so we aren't
2620 * asked to send this message again.
2621 */
2622 ahd_outb(ahd, SCB_CONTROL,
2623 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);

--- 14 unchanged lines hidden (view full) ---

2638 * If our current and goal settings are identical,
2639 * we want to renegotiate due to a check condition.
2640 */
2641 struct ahd_initiator_tinfo *tinfo;
2642 struct ahd_tmode_tstate *tstate;
2643 int dowide;
2644 int dosync;
2645 int doppr;
2646 int use_ppr;
3719 u_int period;
3720 u_int ppr_options;
3721 u_int offset;
3722
3723 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3724 devinfo->target, &tstate);
3725 /*
3726 * Filter our period based on the current connection.
3727 * If we can't perform DT transfers on this segment (not in LVD
3728 * mode for instance), then our decision to issue a PPR message
3729 * may change.
3730 */
3731 period = tinfo->goal.period;
2647 u_int period;
2648 u_int ppr_options;
2649 u_int offset;
2650
2651 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
2652 devinfo->target, &tstate);
2653 /*
2654 * Filter our period based on the current connection.
2655 * If we can't perform DT transfers on this segment (not in LVD
2656 * mode for instance), then our decision to issue a PPR message
2657 * may change.
2658 */
2659 period = tinfo->goal.period;
3732 offset = tinfo->goal.offset;
3733 ppr_options = tinfo->goal.ppr_options;
3734 /* Target initiated PPR is not allowed in the SCSI spec */
3735 if (devinfo->role == ROLE_TARGET)
3736 ppr_options = 0;
3737 ahd_devlimited_syncrate(ahd, tinfo, &period,
3738 &ppr_options, devinfo->role);
3739 dowide = tinfo->curr.width != tinfo->goal.width;
2660 ppr_options = tinfo->goal.ppr_options;
2661 /* Target initiated PPR is not allowed in the SCSI spec */
2662 if (devinfo->role == ROLE_TARGET)
2663 ppr_options = 0;
2664 ahd_devlimited_syncrate(ahd, tinfo, &period,
2665 &ppr_options, devinfo->role);
2666 dowide = tinfo->curr.width != tinfo->goal.width;
3740 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3741 /*
3742 * Only use PPR if we have options that need it, even if the device
3743 * claims to support it. There might be an expander in the way
3744 * that doesn't.
3745 */
3746 doppr = ppr_options != 0;
2667 dosync = tinfo->curr.period != period;
2668 doppr = tinfo->curr.ppr_options != ppr_options;
3747
3748 if (!dowide && !dosync && !doppr) {
3749 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2669
2670 if (!dowide && !dosync && !doppr) {
2671 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3750 dosync = tinfo->goal.offset != 0;
2672 dosync = tinfo->goal.period != 0;
2673 doppr = tinfo->goal.ppr_options != 0;
3751 }
3752
3753 if (!dowide && !dosync && !doppr) {
2674 }
2675
2676 if (!dowide && !dosync && !doppr) {
3754 /*
3755 * Force async with a WDTR message if we have a wide bus,
3756 * or just issue an SDTR with a 0 offset.
3757 */
3758 if ((ahd->features & AHD_WIDE) != 0)
3759 dowide = 1;
3760 else
3761 dosync = 1;
3762
3763 if (bootverbose) {
3764 ahd_print_devinfo(ahd, devinfo);
3765 printf("Ensuring async\n");
3766 }
2677 panic("ahd_intr: AWAITING_MSG for negotiation, "
2678 "but no negotiation needed\n");
3767 }
2679 }
2680
2681 use_ppr = (tinfo->curr.transport_version >= 3) || doppr;
3768 /* Target initiated PPR is not allowed in the SCSI spec */
3769 if (devinfo->role == ROLE_TARGET)
2682 /* Target initiated PPR is not allowed in the SCSI spec */
2683 if (devinfo->role == ROLE_TARGET)
3770 doppr = 0;
2684 use_ppr = 0;
3771
3772 /*
3773 * Both the PPR message and SDTR message require the
3774 * goal syncrate to be limited to what the target device
3775 * is capable of handling (based on whether an LVD->SE
3776 * expander is on the bus), so combine these two cases.
3777 * Regardless, guarantee that if we are using WDTR and SDTR
3778 * messages that WDTR comes first.
3779 */
2685
2686 /*
2687 * Both the PPR message and SDTR message require the
2688 * goal syncrate to be limited to what the target device
2689 * is capable of handling (based on whether an LVD->SE
2690 * expander is on the bus), so combine these two cases.
2691 * Regardless, guarantee that if we are using WDTR and SDTR
2692 * messages that WDTR comes first.
2693 */
3780 if (doppr || (dosync && !dowide)) {
2694 if (use_ppr || (dosync && !dowide)) {
3781
3782 offset = tinfo->goal.offset;
3783 ahd_validate_offset(ahd, tinfo, period, &offset,
2695
2696 offset = tinfo->goal.offset;
2697 ahd_validate_offset(ahd, tinfo, period, &offset,
3784 doppr ? tinfo->goal.width
3785 : tinfo->curr.width,
2698 use_ppr ? tinfo->goal.width
2699 : tinfo->curr.width,
3786 devinfo->role);
2700 devinfo->role);
3787 if (doppr) {
2701 if (use_ppr) {
3788 ahd_construct_ppr(ahd, devinfo, period, offset,
3789 tinfo->goal.width, ppr_options);
3790 } else {
3791 ahd_construct_sdtr(ahd, devinfo, period, offset);
3792 }
3793 } else {
3794 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3795 }
3796}
3797
3798/*
3799 * Build a synchronous negotiation message in our message
3800 * buffer based on the input parameters.
3801 */
3802static void
3803ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3804 u_int period, u_int offset)
3805{
2702 ahd_construct_ppr(ahd, devinfo, period, offset,
2703 tinfo->goal.width, ppr_options);
2704 } else {
2705 ahd_construct_sdtr(ahd, devinfo, period, offset);
2706 }
2707 } else {
2708 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
2709 }
2710}
2711
2712/*
2713 * Build a synchronous negotiation message in our message
2714 * buffer based on the input parameters.
2715 */
2716static void
2717ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2718 u_int period, u_int offset)
2719{
3806 if (offset == 0)
3807 period = AHD_ASYNC_XFER_PERIOD;
3808 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3809 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
3810 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
3811 ahd->msgout_buf[ahd->msgout_index++] = period;
3812 ahd->msgout_buf[ahd->msgout_index++] = offset;
3813 ahd->msgout_len += 5;
3814 if (bootverbose) {
3815 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",

--- 33 unchanged lines hidden (view full) ---

3849{
3850 /*
3851 * Always request precompensation from
3852 * the other target if we are running
3853 * at paced syncrates.
3854 */
3855 if (period <= AHD_SYNCRATE_PACED)
3856 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
2720 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
2721 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
2722 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
2723 ahd->msgout_buf[ahd->msgout_index++] = period;
2724 ahd->msgout_buf[ahd->msgout_index++] = offset;
2725 ahd->msgout_len += 5;
2726 if (bootverbose) {
2727 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",

--- 33 unchanged lines hidden (view full) ---

2761{
2762 /*
2763 * Always request precompensation from
2764 * the other target if we are running
2765 * at paced syncrates.
2766 */
2767 if (period <= AHD_SYNCRATE_PACED)
2768 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3857 if (offset == 0)
3858 period = AHD_ASYNC_XFER_PERIOD;
3859 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3860 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
3861 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
3862 ahd->msgout_buf[ahd->msgout_index++] = period;
3863 ahd->msgout_buf[ahd->msgout_index++] = 0;
3864 ahd->msgout_buf[ahd->msgout_index++] = offset;
3865 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3866 ahd->msgout_buf[ahd->msgout_index++] = ppr_options;

--- 59 unchanged lines hidden (view full) ---

3926 int lastbyte;
3927 int phasemis;
3928 int msgdone;
3929
3930 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3931 panic("HOST_MSG_LOOP interrupt with no active message");
3932
3933#ifdef AHD_DEBUG
2769 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
2770 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
2771 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
2772 ahd->msgout_buf[ahd->msgout_index++] = period;
2773 ahd->msgout_buf[ahd->msgout_index++] = 0;
2774 ahd->msgout_buf[ahd->msgout_index++] = offset;
2775 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
2776 ahd->msgout_buf[ahd->msgout_index++] = ppr_options;

--- 59 unchanged lines hidden (view full) ---

2836 int lastbyte;
2837 int phasemis;
2838 int msgdone;
2839
2840 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
2841 panic("HOST_MSG_LOOP interrupt with no active message");
2842
2843#ifdef AHD_DEBUG
3934 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3935 ahd_print_devinfo(ahd, &devinfo);
3936 printf("INITIATOR_MSG_OUT");
3937 }
2844 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2845 printf("%s: INITIATOR_MSG_OUT", ahd_name(ahd));
3938#endif
3939 phasemis = bus_phase != P_MESGOUT;
3940 if (phasemis) {
3941#ifdef AHD_DEBUG
3942 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2846#endif
2847 phasemis = bus_phase != P_MESGOUT;
2848 if (phasemis) {
2849#ifdef AHD_DEBUG
2850 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3943 printf(" PHASEMIS %s\n",
2851 printf(" PHASEMIS %s - %s\n",
3944 ahd_lookup_phase_entry(bus_phase)
2852 ahd_lookup_phase_entry(bus_phase)
2853 ->phasemsg,
2854 ahd_lookup_phase_entry(ahd_inb(ahd, SCSISIGI) & PHASE_MASK)
3945 ->phasemsg);
3946 }
3947#endif
3948 if (bus_phase == P_MESGIN) {
3949 /*
3950 * Change gears and see if
3951 * this messages is of interest to
3952 * us or should be passed back to

--- 63 unchanged lines hidden (view full) ---

4016 break;
4017 }
4018 case MSG_TYPE_INITIATOR_MSGIN:
4019 {
4020 int phasemis;
4021 int message_done;
4022
4023#ifdef AHD_DEBUG
2855 ->phasemsg);
2856 }
2857#endif
2858 if (bus_phase == P_MESGIN) {
2859 /*
2860 * Change gears and see if
2861 * this messages is of interest to
2862 * us or should be passed back to

--- 63 unchanged lines hidden (view full) ---

2926 break;
2927 }
2928 case MSG_TYPE_INITIATOR_MSGIN:
2929 {
2930 int phasemis;
2931 int message_done;
2932
2933#ifdef AHD_DEBUG
4024 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4025 ahd_print_devinfo(ahd, &devinfo);
4026 printf("INITIATOR_MSG_IN");
4027 }
2934 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2935 printf("%s: INITIATOR_MSG_IN", ahd_name(ahd));
4028#endif
4029 phasemis = bus_phase != P_MESGIN;
4030 if (phasemis) {
4031#ifdef AHD_DEBUG
4032 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4033 printf(" PHASEMIS %s\n",
4034 ahd_lookup_phase_entry(bus_phase)
4035 ->phasemsg);

--- 28 unchanged lines hidden (view full) ---

4064 */
4065 ahd->msgin_index = 0;
4066
4067 /*
4068 * If this message illicited a response,
4069 * assert ATN so the target takes us to the
4070 * message out phase.
4071 */
2936#endif
2937 phasemis = bus_phase != P_MESGIN;
2938 if (phasemis) {
2939#ifdef AHD_DEBUG
2940 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2941 printf(" PHASEMIS %s\n",
2942 ahd_lookup_phase_entry(bus_phase)
2943 ->phasemsg);

--- 28 unchanged lines hidden (view full) ---

2972 */
2973 ahd->msgin_index = 0;
2974
2975 /*
2976 * If this message illicited a response,
2977 * assert ATN so the target takes us to the
2978 * message out phase.
2979 */
4072 if (ahd->msgout_len != 0) {
4073#ifdef AHD_DEBUG
4074 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4075 ahd_print_devinfo(ahd, &devinfo);
4076 printf("Asserting ATN for response\n");
4077 }
4078#endif
2980 if (ahd->msgout_len != 0)
4079 ahd_assert_atn(ahd);
2981 ahd_assert_atn(ahd);
4080 }
4081 } else
4082 ahd->msgin_index++;
4083
4084 if (message_done == MSGLOOP_TERMINATED) {
4085 end_session = TRUE;
4086 } else {
4087 /* Ack the byte */
4088 ahd_outb(ahd, CLRSINT1, CLRREQINIT);

--- 129 unchanged lines hidden (view full) ---

4218 default:
4219 panic("Unknown REQINIT message type");
4220 }
4221
4222 if (end_session) {
4223 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4224 printf("%s: Returning to Idle Loop\n",
4225 ahd_name(ahd));
2982 } else
2983 ahd->msgin_index++;
2984
2985 if (message_done == MSGLOOP_TERMINATED) {
2986 end_session = TRUE;
2987 } else {
2988 /* Ack the byte */
2989 ahd_outb(ahd, CLRSINT1, CLRREQINIT);

--- 129 unchanged lines hidden (view full) ---

3119 default:
3120 panic("Unknown REQINIT message type");
3121 }
3122
3123 if (end_session) {
3124 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
3125 printf("%s: Returning to Idle Loop\n",
3126 ahd_name(ahd));
4226 ahd_clear_msg_state(ahd);
4227
4228 /*
4229 * Perform the equivalent of a clear_target_state.
4230 */
4231 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
3127 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4232 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
3128 ahd_clear_msg_state(ahd);
4233 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4234 } else {
4235 ahd_clear_msg_state(ahd);
4236 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4237 }
4238 }
4239}
4240

--- 30 unchanged lines hidden (view full) ---

4271 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4272 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4273
4274 /* Skip tag type and tag id or residue param*/
4275 index += 2;
4276 } else {
4277 /* Single byte message */
4278 if (type == AHDMSG_1B
3129 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
3130 } else {
3131 ahd_clear_msg_state(ahd);
3132 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
3133 }
3134 }
3135}
3136

--- 30 unchanged lines hidden (view full) ---

3167 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
3168 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3169
3170 /* Skip tag type and tag id or residue param*/
3171 index += 2;
3172 } else {
3173 /* Single byte message */
3174 if (type == AHDMSG_1B
4279 && ahd->msgout_index > index
4280 && (ahd->msgout_buf[index] == msgval
4281 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4282 && msgval == MSG_IDENTIFYFLAG)))
3175 && ahd->msgout_buf[index] == msgval
3176 && ahd->msgout_index > index)
4283 found = TRUE;
4284 index++;
4285 }
4286
4287 if (found)
4288 break;
4289 }
4290 return (found);

--- 13 unchanged lines hidden (view full) ---

4304
4305 done = MSGLOOP_IN_PROG;
4306 response = FALSE;
4307 reject = FALSE;
4308 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4309 devinfo->target, &tstate);
4310
4311 /*
3177 found = TRUE;
3178 index++;
3179 }
3180
3181 if (found)
3182 break;
3183 }
3184 return (found);

--- 13 unchanged lines hidden (view full) ---

3198
3199 done = MSGLOOP_IN_PROG;
3200 response = FALSE;
3201 reject = FALSE;
3202 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3203 devinfo->target, &tstate);
3204
3205 /*
4312 * Parse as much of the message as is available,
3206 * Parse as much of the message as is availible,
4313 * rejecting it if we don't support it. When
3207 * rejecting it if we don't support it. When
4314 * the entire message is available and has been
3208 * the entire message is availible and has been
4315 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4316 * that we have parsed an entire message.
4317 *
4318 * In the case of extended messages, we accept the length
4319 * byte outright and perform more checking once we know the
4320 * extended message type.
4321 */
4322 switch (ahd->msgin_buf[0]) {

--- 158 unchanged lines hidden (view full) ---

4481 }
4482 ahd->msgout_index = 0;
4483 ahd->msgout_len = 0;
4484 ahd_construct_wdtr(ahd, devinfo, bus_width);
4485 ahd->msgout_index = 0;
4486 response = TRUE;
4487 sending_reply = TRUE;
4488 }
3209 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3210 * that we have parsed an entire message.
3211 *
3212 * In the case of extended messages, we accept the length
3213 * byte outright and perform more checking once we know the
3214 * extended message type.
3215 */
3216 switch (ahd->msgin_buf[0]) {

--- 158 unchanged lines hidden (view full) ---

3375 }
3376 ahd->msgout_index = 0;
3377 ahd->msgout_len = 0;
3378 ahd_construct_wdtr(ahd, devinfo, bus_width);
3379 ahd->msgout_index = 0;
3380 response = TRUE;
3381 sending_reply = TRUE;
3382 }
4489 /*
4490 * After a wide message, we are async, but
4491 * some devices don't seem to honor this portion
4492 * of the spec. Force a renegotiation of the
4493 * sync component of our transfer agreement even
4494 * if our goal is async. By updating our width
4495 * after forcing the negotiation, we avoid
4496 * renegotiating for width.
4497 */
4498 ahd_update_neg_request(ahd, devinfo, tstate,
4499 tinfo, AHD_NEG_ALWAYS);
4500 ahd_set_width(ahd, devinfo, bus_width,
4501 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4502 /*paused*/TRUE);
3383 ahd_set_width(ahd, devinfo, bus_width,
3384 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
3385 /*paused*/TRUE);
3386 /* After a wide message, we are async */
3387 ahd_set_syncrate(ahd, devinfo, /*period*/0,
3388 /*offset*/0, /*ppr_options*/0,
3389 AHD_TRANS_ACTIVE, /*paused*/TRUE);
4503 if (sending_reply == FALSE && reject == FALSE) {
4504
3390 if (sending_reply == FALSE && reject == FALSE) {
3391
4505 /*
4506 * We will always have an SDTR to send.
4507 */
4508 ahd->msgout_index = 0;
4509 ahd->msgout_len = 0;
4510 ahd_build_transfer_msg(ahd, devinfo);
4511 ahd->msgout_index = 0;
4512 response = TRUE;
3392 if (tinfo->goal.period) {
3393 ahd->msgout_index = 0;
3394 ahd->msgout_len = 0;
3395 ahd_build_transfer_msg(ahd, devinfo);
3396 ahd->msgout_index = 0;
3397 response = TRUE;
3398 }
4513 }
4514 done = MSGLOOP_MSGCOMPLETE;
4515 break;
4516 }
4517 case MSG_EXT_PPR:
4518 {
4519 u_int period;
4520 u_int offset;

--- 90 unchanged lines hidden (view full) ---

4611 devinfo->target, devinfo->lun,
4612 saved_width, ahd->msgin_buf[3],
4613 saved_offset, saved_ppr_options,
4614 bus_width, period, offset, ppr_options);
4615 }
4616 ahd_set_width(ahd, devinfo, bus_width,
4617 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4618 /*paused*/TRUE);
3399 }
3400 done = MSGLOOP_MSGCOMPLETE;
3401 break;
3402 }
3403 case MSG_EXT_PPR:
3404 {
3405 u_int period;
3406 u_int offset;

--- 90 unchanged lines hidden (view full) ---

3497 devinfo->target, devinfo->lun,
3498 saved_width, ahd->msgin_buf[3],
3499 saved_offset, saved_ppr_options,
3500 bus_width, period, offset, ppr_options);
3501 }
3502 ahd_set_width(ahd, devinfo, bus_width,
3503 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
3504 /*paused*/TRUE);
3505 saved_ppr_options = tinfo->curr.ppr_options;
3506 if ((saved_ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3507#ifdef AHD_DEBUG
3508 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3509 printf("PPR with IU_REQ outstanding\n");
3510#endif
3511 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3512 }
3513 if ((saved_ppr_options & MSG_EXT_PPR_IU_REQ)
3514 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3515#ifdef AHD_DEBUG
3516 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3517 printf("Expecting IU Change busfree\n");
3518#endif
3519 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3520 | MSG_FLAG_IU_REQ_CHANGED;
3521 }
3522
4619 ahd_set_syncrate(ahd, devinfo, period,
4620 offset, ppr_options,
4621 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4622 /*paused*/TRUE);
4623
4624 done = MSGLOOP_MSGCOMPLETE;
4625 break;
4626 }
4627 default:
4628 /* Unknown extended message. Reject it. */
4629 reject = TRUE;
4630 break;
4631 }
4632 break;
4633 }
4634#ifdef AHD_TARGET_MODE
4635 case MSG_BUS_DEV_RESET:
3523 ahd_set_syncrate(ahd, devinfo, period,
3524 offset, ppr_options,
3525 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
3526 /*paused*/TRUE);
3527
3528 done = MSGLOOP_MSGCOMPLETE;
3529 break;
3530 }
3531 default:
3532 /* Unknown extended message. Reject it. */
3533 reject = TRUE;
3534 break;
3535 }
3536 break;
3537 }
3538#ifdef AHD_TARGET_MODE
3539 case MSG_BUS_DEV_RESET:
4636 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
3540 ahd_handle_devreset(ahd, devinfo,
4637 CAM_BDR_SENT,
4638 "Bus Device Reset Received",
4639 /*verbose_level*/0);
4640 ahd_restart(ahd);
4641 done = MSGLOOP_TERMINATED;
4642 break;
4643 case MSG_ABORT_TAG:
4644 case MSG_ABORT:

--- 27 unchanged lines hidden (view full) ---

4672 }
4673 }
4674 ahd_restart(ahd);
4675 done = MSGLOOP_TERMINATED;
4676 break;
4677 }
4678#endif
4679 case MSG_QAS_REQUEST:
3541 CAM_BDR_SENT,
3542 "Bus Device Reset Received",
3543 /*verbose_level*/0);
3544 ahd_restart(ahd);
3545 done = MSGLOOP_TERMINATED;
3546 break;
3547 case MSG_ABORT_TAG:
3548 case MSG_ABORT:

--- 27 unchanged lines hidden (view full) ---

3576 }
3577 }
3578 ahd_restart(ahd);
3579 done = MSGLOOP_TERMINATED;
3580 break;
3581 }
3582#endif
3583 case MSG_QAS_REQUEST:
4680#ifdef AHD_DEBUG
4681 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4682 printf("%s: QAS request. SCSISIGI == 0x%x\n",
4683 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4684#endif
4685 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
3584 printf("%s: QAS request. SCSISIGI == 0x%x\n",
3585 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4686 /* FALLTHROUGH */
4687 case MSG_TERM_IO_PROC:
4688 default:
4689 reject = TRUE;
4690 break;
4691 }
4692
4693 if (reject) {

--- 37 unchanged lines hidden (view full) ---

4731 scb = ahd_lookup_scb(ahd, scb_index);
4732 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4733 devinfo->our_scsiid,
4734 devinfo->target, &tstate);
4735 /* Might be necessary */
4736 last_msg = ahd_inb(ahd, LAST_MSG);
4737
4738 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3586 /* FALLTHROUGH */
3587 case MSG_TERM_IO_PROC:
3588 default:
3589 reject = TRUE;
3590 break;
3591 }
3592
3593 if (reject) {

--- 37 unchanged lines hidden (view full) ---

3631 scb = ahd_lookup_scb(ahd, scb_index);
3632 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
3633 devinfo->our_scsiid,
3634 devinfo->target, &tstate);
3635 /* Might be necessary */
3636 last_msg = ahd_inb(ahd, LAST_MSG);
3637
3638 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4739 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4740 && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4741 /*
4742 * Target may not like our SPI-4 PPR Options.
4743 * Attempt to negotiate 80MHz which will turn
4744 * off these options.
4745 */
4746 if (bootverbose) {
4747 printf("(%s:%c:%d:%d): PPR Rejected. "
4748 "Trying simple U160 PPR\n",
4749 ahd_name(ahd), devinfo->channel,
4750 devinfo->target, devinfo->lun);
4751 }
4752 tinfo->goal.period = AHD_SYNCRATE_DT;
4753 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4754 | MSG_EXT_PPR_QAS_REQ
4755 | MSG_EXT_PPR_DT_REQ;
4756 } else {
4757 /*
4758 * Target does not support the PPR message.
4759 * Attempt to negotiate SPI-2 style.
4760 */
4761 if (bootverbose) {
4762 printf("(%s:%c:%d:%d): PPR Rejected. "
4763 "Trying WDTR/SDTR\n",
4764 ahd_name(ahd), devinfo->channel,
4765 devinfo->target, devinfo->lun);
4766 }
4767 tinfo->goal.ppr_options = 0;
4768 tinfo->curr.transport_version = 2;
4769 tinfo->goal.transport_version = 2;
3639 /*
3640 * Target does not support the PPR message.
3641 * Attempt to negotiate SPI-2 style.
3642 */
3643 if (bootverbose) {
3644 printf("(%s:%c:%d:%d): PPR Rejected. "
3645 "Trying WDTR/SDTR\n",
3646 ahd_name(ahd), devinfo->channel,
3647 devinfo->target, devinfo->lun);
4770 }
3648 }
3649 tinfo->goal.ppr_options = 0;
3650 tinfo->curr.transport_version = 2;
3651 tinfo->goal.transport_version = 2;
4771 ahd->msgout_index = 0;
4772 ahd->msgout_len = 0;
4773 ahd_build_transfer_msg(ahd, devinfo);
4774 ahd->msgout_index = 0;
4775 response = 1;
4776 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4777
4778 /* note 8bit xfers */

--- 5 unchanged lines hidden (view full) ---

4784 /*paused*/TRUE);
4785 /*
4786 * No need to clear the sync rate. If the target
4787 * did not accept the command, our syncrate is
4788 * unaffected. If the target started the negotiation,
4789 * but rejected our response, we already cleared the
4790 * sync rate before sending our WDTR.
4791 */
3652 ahd->msgout_index = 0;
3653 ahd->msgout_len = 0;
3654 ahd_build_transfer_msg(ahd, devinfo);
3655 ahd->msgout_index = 0;
3656 response = 1;
3657 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3658
3659 /* note 8bit xfers */

--- 5 unchanged lines hidden (view full) ---

3665 /*paused*/TRUE);
3666 /*
3667 * No need to clear the sync rate. If the target
3668 * did not accept the command, our syncrate is
3669 * unaffected. If the target started the negotiation,
3670 * but rejected our response, we already cleared the
3671 * sync rate before sending our WDTR.
3672 */
4792 if (tinfo->goal.offset != tinfo->curr.offset) {
3673 if (tinfo->goal.period) {
4793
4794 /* Start the sync negotiation */
4795 ahd->msgout_index = 0;
4796 ahd->msgout_len = 0;
4797 ahd_build_transfer_msg(ahd, devinfo);
4798 ahd->msgout_index = 0;
4799 response = 1;
4800 }

--- 31 unchanged lines hidden (view full) ---

4832
4833 /*
4834 * Resend the identify for this CCB as the target
4835 * may believe that the selection is invalid otherwise.
4836 */
4837 ahd_outb(ahd, SCB_CONTROL,
4838 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4839 scb->hscb->control &= mask;
3674
3675 /* Start the sync negotiation */
3676 ahd->msgout_index = 0;
3677 ahd->msgout_len = 0;
3678 ahd_build_transfer_msg(ahd, devinfo);
3679 ahd->msgout_index = 0;
3680 response = 1;
3681 }

--- 31 unchanged lines hidden (view full) ---

3713
3714 /*
3715 * Resend the identify for this CCB as the target
3716 * may believe that the selection is invalid otherwise.
3717 */
3718 ahd_outb(ahd, SCB_CONTROL,
3719 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
3720 scb->hscb->control &= mask;
4840 aic_set_transaction_tag(scb, /*enabled*/FALSE,
3721 ahd_set_transaction_tag(scb, /*enabled*/FALSE,
4841 /*type*/MSG_SIMPLE_TASK);
4842 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4843 ahd_assert_atn(ahd);
4844 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4845 SCB_GET_TAG(scb));
4846
4847 /*
4848 * Requeue all tagged commands for this target
4849 * currently in our posession so they can be
4850 * converted to untagged commands.
4851 */
4852 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4853 SCB_GET_CHANNEL(ahd, scb),
4854 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4855 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4856 SEARCH_COMPLETE);
3722 /*type*/MSG_SIMPLE_TASK);
3723 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
3724 ahd_assert_atn(ahd);
3725 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3726 SCB_GET_TAG(scb));
3727
3728 /*
3729 * Requeue all tagged commands for this target
3730 * currently in our posession so they can be
3731 * converted to untagged commands.
3732 */
3733 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
3734 SCB_GET_CHANNEL(ahd, scb),
3735 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3736 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3737 SEARCH_COMPLETE);
4857 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4858 /*
4859 * Most likely the device believes that we had
4860 * previously negotiated packetized.
4861 */
4862 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4863 | MSG_FLAG_IU_REQ_CHANGED;
4864
4865 ahd_force_renegotiation(ahd, devinfo);
4866 ahd->msgout_index = 0;
4867 ahd->msgout_len = 0;
4868 ahd_build_transfer_msg(ahd, devinfo);
4869 ahd->msgout_index = 0;
4870 response = 1;
4871 } else {
4872 /*
4873 * Otherwise, we ignore it.
4874 */
4875 printf("%s:%c:%d: Message reject for %x -- ignored\n",
4876 ahd_name(ahd), devinfo->channel, devinfo->target,
4877 last_msg);
4878 }

--- 11 unchanged lines hidden (view full) ---

4890
4891 scb_index = ahd_get_scbptr(ahd);
4892 scb = ahd_lookup_scb(ahd, scb_index);
4893 /*
4894 * XXX Actually check data direction in the sequencer?
4895 * Perhaps add datadir to some spare bits in the hscb?
4896 */
4897 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
3738 } else {
3739 /*
3740 * Otherwise, we ignore it.
3741 */
3742 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3743 ahd_name(ahd), devinfo->channel, devinfo->target,
3744 last_msg);
3745 }

--- 11 unchanged lines hidden (view full) ---

3757
3758 scb_index = ahd_get_scbptr(ahd);
3759 scb = ahd_lookup_scb(ahd, scb_index);
3760 /*
3761 * XXX Actually check data direction in the sequencer?
3762 * Perhaps add datadir to some spare bits in the hscb?
3763 */
3764 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4898 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
3765 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) {
4899 /*
4900 * Ignore the message if we haven't
4901 * seen an appropriate data phase yet.
4902 */
4903 } else {
4904 /*
4905 * If the residual occurred on the last
4906 * transfer and the transfer request was
4907 * expected to end on an odd count, do
4908 * nothing. Otherwise, subtract a byte
4909 * and update the residual count accordingly.
4910 */
4911 uint32_t sgptr;
4912
4913 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4914 if ((sgptr & SG_LIST_NULL) != 0
3766 /*
3767 * Ignore the message if we haven't
3768 * seen an appropriate data phase yet.
3769 */
3770 } else {
3771 /*
3772 * If the residual occurred on the last
3773 * transfer and the transfer request was
3774 * expected to end on an odd count, do
3775 * nothing. Otherwise, subtract a byte
3776 * and update the residual count accordingly.
3777 */
3778 uint32_t sgptr;
3779
3780 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
3781 if ((sgptr & SG_LIST_NULL) != 0
4915 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4916 & SCB_XFERLEN_ODD) != 0) {
3782 && ahd_inb(ahd, DATA_COUNT_ODD) == 1) {
4917 /*
4918 * If the residual occurred on the last
4919 * transfer and the transfer request was
4920 * expected to end on an odd count, do
4921 * nothing.
4922 */
4923 } else {
4924 uint32_t data_cnt;
4925 uint64_t data_addr;
4926 uint32_t sglen;
4927
4928 /* Pull in the rest of the sgptr */
3783 /*
3784 * If the residual occurred on the last
3785 * transfer and the transfer request was
3786 * expected to end on an odd count, do
3787 * nothing.
3788 */
3789 } else {
3790 uint32_t data_cnt;
3791 uint64_t data_addr;
3792 uint32_t sglen;
3793
3794 /* Pull in the rest of the sgptr */
4929 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4930 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4931 if ((sgptr & SG_LIST_NULL) != 0) {
4932 /*
4933 * The residual data count is not updated
4934 * for the command run to completion case.
4935 * Explicitly zero the count.
4936 */
4937 data_cnt &= ~AHD_SG_LEN_MASK;
4938 }
4939 data_addr = ahd_inq(ahd, SHADDR);
3795 sgptr |=
3796 (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24)
3797 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16)
3798 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8);
3799 sgptr &= SG_PTR_MASK;
3800 data_cnt =
3801 (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24)
3802 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+2) << 16)
3803 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+1) << 8)
3804 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT));
3805
3806 data_addr = (((uint64_t)ahd_inb(ahd, SHADDR + 7)) << 56)
3807 | (((uint64_t)ahd_inb(ahd, SHADDR + 6)) << 48)
3808 | (((uint64_t)ahd_inb(ahd, SHADDR + 5)) << 40)
3809 | (((uint64_t)ahd_inb(ahd, SHADDR + 4)) << 32)
3810 | (ahd_inb(ahd, SHADDR + 3) << 24)
3811 | (ahd_inb(ahd, SHADDR + 2) << 16)
3812 | (ahd_inb(ahd, SHADDR + 1) << 8)
3813 | (ahd_inb(ahd, SHADDR));
3814
4940 data_cnt += 1;
4941 data_addr -= 1;
3815 data_cnt += 1;
3816 data_addr -= 1;
4942 sgptr &= SG_PTR_MASK;
3817
4943 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4944 struct ahd_dma64_seg *sg;
4945
4946 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4947
4948 /*
4949 * The residual sg ptr points to the next S/G
4950 * to load so we must go back one.
4951 */
4952 sg--;
3818 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
3819 struct ahd_dma64_seg *sg;
3820
3821 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
3822
3823 /*
3824 * The residual sg ptr points to the next S/G
3825 * to load so we must go back one.
3826 */
3827 sg--;
4953 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
3828 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
4954 if (sg != scb->sg_list
4955 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4956
4957 sg--;
3829 if (sg != scb->sg_list
3830 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
3831
3832 sg--;
4958 sglen = aic_le32toh(sg->len);
3833 sglen = ahd_le32toh(sg->len);
4959 /*
4960 * Preserve High Address and SG_LIST
4961 * bits while setting the count to 1.
4962 */
4963 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
3834 /*
3835 * Preserve High Address and SG_LIST
3836 * bits while setting the count to 1.
3837 */
3838 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4964 data_addr = aic_le64toh(sg->addr)
3839 data_addr = ahd_le64toh(sg->addr)
4965 + (sglen & AHD_SG_LEN_MASK)
4966 - 1;
4967
4968 /*
4969 * Increment sg so it points to the
4970 * "next" sg.
4971 */
4972 sg++;

--- 5 unchanged lines hidden (view full) ---

4978
4979 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4980
4981 /*
4982 * The residual sg ptr points to the next S/G
4983 * to load so we must go back one.
4984 */
4985 sg--;
3840 + (sglen & AHD_SG_LEN_MASK)
3841 - 1;
3842
3843 /*
3844 * Increment sg so it points to the
3845 * "next" sg.
3846 */
3847 sg++;

--- 5 unchanged lines hidden (view full) ---

3853
3854 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
3855
3856 /*
3857 * The residual sg ptr points to the next S/G
3858 * to load so we must go back one.
3859 */
3860 sg--;
4986 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
3861 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
4987 if (sg != scb->sg_list
4988 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4989
4990 sg--;
3862 if (sg != scb->sg_list
3863 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
3864
3865 sg--;
4991 sglen = aic_le32toh(sg->len);
3866 sglen = ahd_le32toh(sg->len);
4992 /*
4993 * Preserve High Address and SG_LIST
4994 * bits while setting the count to 1.
4995 */
4996 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
3867 /*
3868 * Preserve High Address and SG_LIST
3869 * bits while setting the count to 1.
3870 */
3871 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4997 data_addr = aic_le32toh(sg->addr)
3872 data_addr = ahd_le32toh(sg->addr)
4998 + (sglen & AHD_SG_LEN_MASK)
4999 - 1;
5000
5001 /*
5002 * Increment sg so it points to the
5003 * "next" sg.
5004 */
5005 sg++;
5006 sgptr = ahd_sg_virt_to_bus(ahd, scb,
5007 sg);
5008 }
5009 }
3873 + (sglen & AHD_SG_LEN_MASK)
3874 - 1;
3875
3876 /*
3877 * Increment sg so it points to the
3878 * "next" sg.
3879 */
3880 sg++;
3881 sgptr = ahd_sg_virt_to_bus(ahd, scb,
3882 sg);
3883 }
3884 }
5010 /*
5011 * Toggle the "oddness" of the transfer length
5012 * to handle this mid-transfer ignore wide
5013 * residue. This ensures that the oddness is
5014 * correct for subsequent data transfers.
5015 */
5016 ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
5017 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
5018 ^ SCB_XFERLEN_ODD);
3885 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 3, sgptr >> 24);
3886 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 2, sgptr >> 16);
3887 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 1, sgptr >> 8);
3888 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, sgptr);
5019
3889
5020 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
5021 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
3890 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24);
3891 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16);
3892 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8);
3893 ahd_outb(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
3894
5022 /*
5023 * The FIFO's pointers will be updated if/when the
5024 * sequencer re-enters a data phase.
5025 */
5026 }
5027 }
5028}
5029

--- 20 unchanged lines hidden (view full) ---

5050 scb = ahd_lookup_scb(ahd, scb_index);
5051
5052 /*
5053 * Release and reacquire the FIFO so we
5054 * have a clean slate.
5055 */
5056 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
5057 wait = 1000;
3895 /*
3896 * The FIFO's pointers will be updated if/when the
3897 * sequencer re-enters a data phase.
3898 */
3899 }
3900 }
3901}
3902

--- 20 unchanged lines hidden (view full) ---

3923 scb = ahd_lookup_scb(ahd, scb_index);
3924
3925 /*
3926 * Release and reacquire the FIFO so we
3927 * have a clean slate.
3928 */
3929 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
3930 wait = 1000;
5058 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
5059 aic_delay(100);
3931 do {
3932 ahd_delay(100);
3933 } while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE));
5060 if (wait == 0) {
5061 ahd_print_path(ahd, scb);
5062 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5063 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
5064 }
5065 saved_modes = ahd_save_modes(ahd);
5066 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5067 ahd_outb(ahd, DFFSTAT,
3934 if (wait == 0) {
3935 ahd_print_path(ahd, scb);
3936 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
3937 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
3938 }
3939 saved_modes = ahd_save_modes(ahd);
3940 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3941 ahd_outb(ahd, DFFSTAT,
5068 ahd_inb(ahd, DFFSTAT)
5069 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
3942 ahd_inb(ahd, DFFSTAT) | (saved_modes == 0x11 ? CURRFIFO : 0));
5070
5071 /*
5072 * Determine initial values for data_addr and data_cnt
5073 * for resuming the data phase.
5074 */
3943
3944 /*
3945 * Determine initial values for data_addr and data_cnt
3946 * for resuming the data phase.
3947 */
5075 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
3948 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24)
3949 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16)
3950 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8)
3951 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
5076 sgptr &= SG_PTR_MASK;
5077
5078 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
5079 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
5080 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
5081
5082 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
5083 struct ahd_dma64_seg *sg;
5084
5085 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5086
5087 /* The residual sg_ptr always points to the next sg */
5088 sg--;
5089
3952 sgptr &= SG_PTR_MASK;
3953
3954 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
3955 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
3956 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
3957
3958 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
3959 struct ahd_dma64_seg *sg;
3960
3961 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
3962
3963 /* The residual sg_ptr always points to the next sg */
3964 sg--;
3965
5090 dataptr = aic_le64toh(sg->addr)
5091 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
3966 dataptr = ahd_le64toh(sg->addr)
3967 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
5092 - resid;
3968 - resid;
5093 ahd_outl(ahd, HADDR + 4, dataptr >> 32);
3969 ahd_outb(ahd, HADDR + 7, dataptr >> 56);
3970 ahd_outb(ahd, HADDR + 6, dataptr >> 48);
3971 ahd_outb(ahd, HADDR + 5, dataptr >> 40);
3972 ahd_outb(ahd, HADDR + 4, dataptr >> 32);
5094 } else {
5095 struct ahd_dma_seg *sg;
5096
5097 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5098
5099 /* The residual sg_ptr always points to the next sg */
5100 sg--;
5101
3973 } else {
3974 struct ahd_dma_seg *sg;
3975
3976 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
3977
3978 /* The residual sg_ptr always points to the next sg */
3979 sg--;
3980
5102 dataptr = aic_le32toh(sg->addr)
5103 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
3981 dataptr = ahd_le32toh(sg->addr)
3982 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
5104 - resid;
5105 ahd_outb(ahd, HADDR + 4,
3983 - resid;
3984 ahd_outb(ahd, HADDR + 4,
5106 (aic_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
3985 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
5107 }
3986 }
5108 ahd_outl(ahd, HADDR, dataptr);
3987 ahd_outb(ahd, HADDR + 3, dataptr >> 24);
3988 ahd_outb(ahd, HADDR + 2, dataptr >> 16);
3989 ahd_outb(ahd, HADDR + 1, dataptr >> 8);
3990 ahd_outb(ahd, HADDR, dataptr);
5109 ahd_outb(ahd, HCNT + 2, resid >> 16);
5110 ahd_outb(ahd, HCNT + 1, resid >> 8);
5111 ahd_outb(ahd, HCNT, resid);
5112}
5113
5114/*
5115 * Handle the effects of issuing a bus device reset message.
5116 */
5117static void
5118ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3991 ahd_outb(ahd, HCNT + 2, resid >> 16);
3992 ahd_outb(ahd, HCNT + 1, resid >> 8);
3993 ahd_outb(ahd, HCNT, resid);
3994}
3995
3996/*
3997 * Handle the effects of issuing a bus device reset message.
3998 */
3999static void
4000ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5119 u_int lun, cam_status status, char *message,
5120 int verbose_level)
4001 cam_status status, char *message, int verbose_level)
5121{
5122#ifdef AHD_TARGET_MODE
5123 struct ahd_tmode_tstate* tstate;
4002{
4003#ifdef AHD_TARGET_MODE
4004 struct ahd_tmode_tstate* tstate;
4005 u_int lun;
5124#endif
5125 int found;
5126
5127 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4006#endif
4007 int found;
4008
4009 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
5128 lun, SCB_LIST_NULL, devinfo->role,
4010 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
5129 status);
5130
5131#ifdef AHD_TARGET_MODE
5132 /*
5133 * Send an immediate notify ccb to all target mord peripheral
5134 * drivers affected by this action.
5135 */
5136 tstate = ahd->enabled_targets[devinfo->our_scsiid];
5137 if (tstate != NULL) {
4011 status);
4012
4013#ifdef AHD_TARGET_MODE
4014 /*
4015 * Send an immediate notify ccb to all target mord peripheral
4016 * drivers affected by this action.
4017 */
4018 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4019 if (tstate != NULL) {
5138 u_int cur_lun;
5139 u_int max_lun;
5140
5141 if (lun != CAM_LUN_WILDCARD) {
5142 cur_lun = 0;
5143 max_lun = AHD_NUM_LUNS - 1;
5144 } else {
5145 cur_lun = lun;
5146 max_lun = lun;
5147 }
5148 for (cur_lun <= max_lun; cur_lun++) {
4020 for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
5149 struct ahd_tmode_lstate* lstate;
5150
4021 struct ahd_tmode_lstate* lstate;
4022
5151 lstate = tstate->enabled_luns[cur_lun];
4023 lstate = tstate->enabled_luns[lun];
5152 if (lstate == NULL)
5153 continue;
5154
5155 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
5156 MSG_BUS_DEV_RESET, /*arg*/0);
5157 ahd_send_lstate_events(ahd, lstate);
5158 }
5159 }
5160#endif
5161
5162 /*
5163 * Go back to async/narrow transfers and renegotiate.
5164 */
5165 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5166 AHD_TRANS_CUR, /*paused*/TRUE);
5167 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
4024 if (lstate == NULL)
4025 continue;
4026
4027 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
4028 MSG_BUS_DEV_RESET, /*arg*/0);
4029 ahd_send_lstate_events(ahd, lstate);
4030 }
4031 }
4032#endif
4033
4034 /*
4035 * Go back to async/narrow transfers and renegotiate.
4036 */
4037 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4038 AHD_TRANS_CUR, /*paused*/TRUE);
4039 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5168 /*ppr_options*/0, AHD_TRANS_CUR,
5169 /*paused*/TRUE);
4040 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE);
5170
4041
5171 if (status != CAM_SEL_TIMEOUT)
5172 ahd_send_async(ahd, devinfo->channel, devinfo->target,
5173 lun, AC_SENT_BDR, NULL);
4042 ahd_send_async(ahd, devinfo->channel, devinfo->target,
4043 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
5174
5175 if (message != NULL
4044
4045 if (message != NULL
5176 && (verbose_level <= bootverbose)) {
5177 AHD_CORRECTABLE_ERROR(ahd);
4046 && (verbose_level <= bootverbose))
5178 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5179 message, devinfo->channel, devinfo->target, found);
4047 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
4048 message, devinfo->channel, devinfo->target, found);
5180 }
5181}
5182
5183#ifdef AHD_TARGET_MODE
5184static void
5185ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5186 struct scb *scb)
5187{
5188

--- 10 unchanged lines hidden (view full) ---

5199 else
5200 panic("ahd_intr: AWAITING target message with no message");
5201
5202 ahd->msgout_index = 0;
5203 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5204}
5205#endif
5206/**************************** Initialization **********************************/
4049}
4050
4051#ifdef AHD_TARGET_MODE
4052static void
4053ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
4054 struct scb *scb)
4055{
4056

--- 10 unchanged lines hidden (view full) ---

4067 else
4068 panic("ahd_intr: AWAITING target message with no message");
4069
4070 ahd->msgout_index = 0;
4071 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4072}
4073#endif
4074/**************************** Initialization **********************************/
5207static u_int
4075static bus_size_t
5208ahd_sglist_size(struct ahd_softc *ahd)
5209{
5210 bus_size_t list_size;
5211
5212 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5213 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5214 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5215 return (list_size);
5216}
5217
5218/*
5219 * Calculate the optimum S/G List allocation size. S/G elements used
5220 * for a given transaction must be physically contiguous. Assume the
5221 * OS will allocate full pages to us, so it doesn't make sense to request
5222 * less than a page.
5223 */
4076ahd_sglist_size(struct ahd_softc *ahd)
4077{
4078 bus_size_t list_size;
4079
4080 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
4081 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
4082 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
4083 return (list_size);
4084}
4085
4086/*
4087 * Calculate the optimum S/G List allocation size. S/G elements used
4088 * for a given transaction must be physically contiguous. Assume the
4089 * OS will allocate full pages to us, so it doesn't make sense to request
4090 * less than a page.
4091 */
5224static u_int
4092static bus_size_t
5225ahd_sglist_allocsize(struct ahd_softc *ahd)
5226{
5227 bus_size_t sg_list_increment;
5228 bus_size_t sg_list_size;
5229 bus_size_t max_list_size;
5230 bus_size_t best_list_size;
5231
5232 /* Start out with the minimum required for AHD_NSEG. */

--- 54 unchanged lines hidden (view full) ---

5287 if (ahd->seep_config == NULL) {
5288#ifndef __FreeBSD__
5289 free(ahd, M_DEVBUF);
5290#endif
5291 free(name, M_DEVBUF);
5292 return (NULL);
5293 }
5294 LIST_INIT(&ahd->pending_scbs);
4093ahd_sglist_allocsize(struct ahd_softc *ahd)
4094{
4095 bus_size_t sg_list_increment;
4096 bus_size_t sg_list_size;
4097 bus_size_t max_list_size;
4098 bus_size_t best_list_size;
4099
4100 /* Start out with the minimum required for AHD_NSEG. */

--- 54 unchanged lines hidden (view full) ---

4155 if (ahd->seep_config == NULL) {
4156#ifndef __FreeBSD__
4157 free(ahd, M_DEVBUF);
4158#endif
4159 free(name, M_DEVBUF);
4160 return (NULL);
4161 }
4162 LIST_INIT(&ahd->pending_scbs);
5295 LIST_INIT(&ahd->timedout_scbs);
5296 /* We don't know our unit number until the OSM sets it */
5297 ahd->name = name;
5298 ahd->unit = -1;
5299 ahd->description = NULL;
5300 ahd->bus_description = NULL;
5301 ahd->channel = 'A';
5302 ahd->chip = AHD_NONE;
5303 ahd->features = AHD_FENONE;
5304 ahd->bugs = AHD_BUGNONE;
5305 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5306 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
4163 /* We don't know our unit number until the OSM sets it */
4164 ahd->name = name;
4165 ahd->unit = -1;
4166 ahd->description = NULL;
4167 ahd->bus_description = NULL;
4168 ahd->channel = 'A';
4169 ahd->chip = AHD_NONE;
4170 ahd->features = AHD_FENONE;
4171 ahd->bugs = AHD_BUGNONE;
4172 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
4173 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5307 aic_timer_init(&ahd->reset_timer);
5308 aic_timer_init(&ahd->stat_timer);
5309 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5310 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5311 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5312 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5313 ahd->int_coalescing_stop_threshold =
5314 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
4174 ahd_timer_init(&ahd->reset_timer);
5315
5316 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
5317 ahd_free(ahd);
5318 ahd = NULL;
5319 }
4175
4176 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
4177 ahd_free(ahd);
4178 ahd = NULL;
4179 }
5320 ahd_lockinit(ahd);
5321#ifdef AHD_DEBUG
5322 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5323 printf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5324 ahd_name(ahd), (u_int)sizeof(struct scb),
5325 (u_int)sizeof(struct hardware_scb));
5326 }
5327#endif
5328 return (ahd);
5329}
5330
5331int
5332ahd_softc_init(struct ahd_softc *ahd)
5333{
5334
5335 ahd->unpause = 0;
5336 ahd->pause = PAUSE;
5337 return (0);
5338}
5339
5340void
5341ahd_softc_insert(struct ahd_softc *ahd)
5342{
5343 struct ahd_softc *list_ahd;
5344
4180 return (ahd);
4181}
4182
4183int
4184ahd_softc_init(struct ahd_softc *ahd)
4185{
4186
4187 ahd->unpause = 0;
4188 ahd->pause = PAUSE;
4189 return (0);
4190}
4191
4192void
4193ahd_softc_insert(struct ahd_softc *ahd)
4194{
4195 struct ahd_softc *list_ahd;
4196
5345#if AIC_PCI_CONFIG > 0
4197#if AHD_PCI_CONFIG > 0
5346 /*
5347 * Second Function PCI devices need to inherit some
5348 * settings from function 0.
5349 */
5350 if ((ahd->features & AHD_MULTI_FUNC) != 0) {
5351 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
4198 /*
4199 * Second Function PCI devices need to inherit some
4200 * settings from function 0.
4201 */
4202 if ((ahd->features & AHD_MULTI_FUNC) != 0) {
4203 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5352 aic_dev_softc_t list_pci;
5353 aic_dev_softc_t pci;
4204 ahd_dev_softc_t list_pci;
4205 ahd_dev_softc_t pci;
5354
5355 list_pci = list_ahd->dev_softc;
5356 pci = ahd->dev_softc;
4206
4207 list_pci = list_ahd->dev_softc;
4208 pci = ahd->dev_softc;
5357 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
5358 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
4209 if (ahd_get_pci_slot(list_pci) == ahd_get_pci_slot(pci)
4210 && ahd_get_pci_bus(list_pci) == ahd_get_pci_bus(pci)) {
5359 struct ahd_softc *master;
5360 struct ahd_softc *slave;
5361
4211 struct ahd_softc *master;
4212 struct ahd_softc *slave;
4213
5362 if (aic_get_pci_function(list_pci) == 0) {
4214 if (ahd_get_pci_function(list_pci) == 0) {
5363 master = list_ahd;
5364 slave = ahd;
5365 } else {
5366 master = ahd;
5367 slave = list_ahd;
5368 }
5369 slave->flags &= ~AHD_BIOS_ENABLED;
5370 slave->flags |=
5371 master->flags & AHD_BIOS_ENABLED;
4215 master = list_ahd;
4216 slave = ahd;
4217 } else {
4218 master = ahd;
4219 slave = list_ahd;
4220 }
4221 slave->flags &= ~AHD_BIOS_ENABLED;
4222 slave->flags |=
4223 master->flags & AHD_BIOS_ENABLED;
4224 slave->flags &= ~AHD_PRIMARY_CHANNEL;
4225 slave->flags |=
4226 master->flags & AHD_PRIMARY_CHANNEL;
5372 break;
5373 }
5374 }
5375 }
5376#endif
5377
5378 /*
5379 * Insertion sort into our list of softcs.
5380 */
5381 list_ahd = TAILQ_FIRST(&ahd_tailq);
5382 while (list_ahd != NULL
4227 break;
4228 }
4229 }
4230 }
4231#endif
4232
4233 /*
4234 * Insertion sort into our list of softcs.
4235 */
4236 list_ahd = TAILQ_FIRST(&ahd_tailq);
4237 while (list_ahd != NULL
5383 && ahd_softc_comp(ahd, list_ahd) <= 0)
4238 && ahd_softc_comp(list_ahd, ahd) <= 0)
5384 list_ahd = TAILQ_NEXT(list_ahd, links);
5385 if (list_ahd != NULL)
5386 TAILQ_INSERT_BEFORE(list_ahd, ahd, links);
5387 else
5388 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links);
5389 ahd->init_level++;
5390}
5391
4239 list_ahd = TAILQ_NEXT(list_ahd, links);
4240 if (list_ahd != NULL)
4241 TAILQ_INSERT_BEFORE(list_ahd, ahd, links);
4242 else
4243 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links);
4244 ahd->init_level++;
4245}
4246
4247/*
4248 * Verify that the passed in softc pointer is for a
4249 * controller that is still configured.
4250 */
4251struct ahd_softc *
4252ahd_find_softc(struct ahd_softc *ahd)
4253{
4254 struct ahd_softc *list_ahd;
4255
4256 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
4257 if (list_ahd == ahd)
4258 return (ahd);
4259 }
4260 return (NULL);
4261}
4262
5392void
5393ahd_set_unit(struct ahd_softc *ahd, int unit)
5394{
5395 ahd->unit = unit;
5396}
5397
5398void
5399ahd_set_name(struct ahd_softc *ahd, char *name)
5400{
5401 if (ahd->name != NULL)
5402 free(ahd->name, M_DEVBUF);
5403 ahd->name = name;
5404}
5405
5406void
5407ahd_free(struct ahd_softc *ahd)
5408{
5409 int i;
5410
4263void
4264ahd_set_unit(struct ahd_softc *ahd, int unit)
4265{
4266 ahd->unit = unit;
4267}
4268
4269void
4270ahd_set_name(struct ahd_softc *ahd, char *name)
4271{
4272 if (ahd->name != NULL)
4273 free(ahd->name, M_DEVBUF);
4274 ahd->name = name;
4275}
4276
4277void
4278ahd_free(struct ahd_softc *ahd)
4279{
4280 int i;
4281
5411 ahd_terminate_recovery_thread(ahd);
4282 ahd_fini_scbdata(ahd);
5412 switch (ahd->init_level) {
5413 default:
5414 case 5:
5415 ahd_shutdown(ahd);
4283 switch (ahd->init_level) {
4284 default:
4285 case 5:
4286 ahd_shutdown(ahd);
4287 TAILQ_REMOVE(&ahd_tailq, ahd, links);
5416 /* FALLTHROUGH */
5417 case 4:
4288 /* FALLTHROUGH */
4289 case 4:
5418 aic_dmamap_unload(ahd, ahd->shared_data_dmat,
5419 ahd->shared_data_map.dmamap);
4290 ahd_dmamap_unload(ahd, ahd->shared_data_dmat,
4291 ahd->shared_data_dmamap);
5420 /* FALLTHROUGH */
5421 case 3:
4292 /* FALLTHROUGH */
4293 case 3:
5422 aic_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
5423 ahd->shared_data_map.dmamap);
5424 aic_dmamap_destroy(ahd, ahd->shared_data_dmat,
5425 ahd->shared_data_map.dmamap);
4294 ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
4295 ahd->shared_data_dmamap);
4296 ahd_dmamap_destroy(ahd, ahd->shared_data_dmat,
4297 ahd->shared_data_dmamap);
5426 /* FALLTHROUGH */
5427 case 2:
4298 /* FALLTHROUGH */
4299 case 2:
5428 aic_dma_tag_destroy(ahd, ahd->shared_data_dmat);
4300 ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat);
5429 case 1:
5430#ifndef __linux__
4301 case 1:
4302#ifndef __linux__
5431 aic_dma_tag_destroy(ahd, ahd->buffer_dmat);
4303 ahd_dma_tag_destroy(ahd, ahd->buffer_dmat);
5432#endif
5433 break;
5434 case 0:
5435 break;
5436 }
5437
5438#ifndef __linux__
4304#endif
4305 break;
4306 case 0:
4307 break;
4308 }
4309
4310#ifndef __linux__
5439 aic_dma_tag_destroy(ahd, ahd->parent_dmat);
4311 ahd_dma_tag_destroy(ahd, ahd->parent_dmat);
5440#endif
5441 ahd_platform_free(ahd);
4312#endif
4313 ahd_platform_free(ahd);
5442 ahd_fini_scbdata(ahd);
5443 for (i = 0; i < AHD_NUM_TARGETS; i++) {
5444 struct ahd_tmode_tstate *tstate;
5445
5446 tstate = ahd->enabled_targets[i];
5447 if (tstate != NULL) {
4314 for (i = 0; i < AHD_NUM_TARGETS; i++) {
4315 struct ahd_tmode_tstate *tstate;
4316
4317 tstate = ahd->enabled_targets[i];
4318 if (tstate != NULL) {
5448#ifdef AHD_TARGET_MODE
4319#if AHD_TARGET_MODE
5449 int j;
5450
5451 for (j = 0; j < AHD_NUM_LUNS; j++) {
5452 struct ahd_tmode_lstate *lstate;
5453
5454 lstate = tstate->enabled_luns[j];
5455 if (lstate != NULL) {
5456 xpt_free_path(lstate->path);
5457 free(lstate, M_DEVBUF);
5458 }
5459 }
5460#endif
5461 free(tstate, M_DEVBUF);
5462 }
5463 }
4320 int j;
4321
4322 for (j = 0; j < AHD_NUM_LUNS; j++) {
4323 struct ahd_tmode_lstate *lstate;
4324
4325 lstate = tstate->enabled_luns[j];
4326 if (lstate != NULL) {
4327 xpt_free_path(lstate->path);
4328 free(lstate, M_DEVBUF);
4329 }
4330 }
4331#endif
4332 free(tstate, M_DEVBUF);
4333 }
4334 }
5464#ifdef AHD_TARGET_MODE
4335#if AHD_TARGET_MODE
5465 if (ahd->black_hole != NULL) {
5466 xpt_free_path(ahd->black_hole->path);
5467 free(ahd->black_hole, M_DEVBUF);
5468 }
5469#endif
5470 if (ahd->name != NULL)
5471 free(ahd->name, M_DEVBUF);
5472 if (ahd->seep_config != NULL)
5473 free(ahd->seep_config, M_DEVBUF);
4336 if (ahd->black_hole != NULL) {
4337 xpt_free_path(ahd->black_hole->path);
4338 free(ahd->black_hole, M_DEVBUF);
4339 }
4340#endif
4341 if (ahd->name != NULL)
4342 free(ahd->name, M_DEVBUF);
4343 if (ahd->seep_config != NULL)
4344 free(ahd->seep_config, M_DEVBUF);
5474 if (ahd->saved_stack != NULL)
5475 free(ahd->saved_stack, M_DEVBUF);
5476#ifndef __FreeBSD__
5477 free(ahd, M_DEVBUF);
5478#endif
5479 return;
5480}
5481
5482void
5483ahd_shutdown(void *arg)
5484{
5485 struct ahd_softc *ahd;
5486
5487 ahd = (struct ahd_softc *)arg;
5488
4345#ifndef __FreeBSD__
4346 free(ahd, M_DEVBUF);
4347#endif
4348 return;
4349}
4350
4351void
4352ahd_shutdown(void *arg)
4353{
4354 struct ahd_softc *ahd;
4355
4356 ahd = (struct ahd_softc *)arg;
4357
5489 /*
5490 * Stop periodic timer callbacks.
5491 */
5492 aic_timer_stop(&ahd->reset_timer);
5493 aic_timer_stop(&ahd->stat_timer);
5494
5495 /* This will reset most registers to 0, but not all */
4358 /* This will reset most registers to 0, but not all */
5496 ahd_reset(ahd, /*reinit*/FALSE);
4359 ahd_reset(ahd);
5497}
5498
5499/*
5500 * Reset the controller and record some information about it
4360}
4361
4362/*
4363 * Reset the controller and record some information about it
5501 * that is only available just after a reset. If "reinit" is
5502 * non-zero, this reset occured after initial configuration
5503 * and the caller requests that the chip be fully reinitialized
5504 * to a runable state. Chip interrupts are *not* enabled after
5505 * a reinitialization. The caller must enable interrupts via
5506 * ahd_intr_enable().
4364 * that is only available just after a reset.
5507 */
5508int
4365 */
4366int
5509ahd_reset(struct ahd_softc *ahd, int reinit)
4367ahd_reset(struct ahd_softc *ahd)
5510{
5511 u_int sxfrctl1;
5512 int wait;
5513 uint32_t cmd;
5514
5515 /*
5516 * Preserve the value of the SXFRCTL1 register for all channels.
5517 * It contains settings that affect termination and we don't want
5518 * to disturb the integrity of the bus.
5519 */
5520 ahd_pause(ahd);
4368{
4369 u_int sxfrctl1;
4370 int wait;
4371 uint32_t cmd;
4372
4373 /*
4374 * Preserve the value of the SXFRCTL1 register for all channels.
4375 * It contains settings that affect termination and we don't want
4376 * to disturb the integrity of the bus.
4377 */
4378 ahd_pause(ahd);
5521 ahd_update_modes(ahd);
5522 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5523 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5524
4379 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
4380
5525 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
4381 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
5526 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5527 uint32_t mod_cmd;
5528
5529 /*
5530 * A4 Razor #632
5531 * During the assertion of CHIPRST, the chip
5532 * does not disable its parity logic prior to
5533 * the start of the reset. This may cause a
5534 * parity error to be detected and thus a
5535 * spurious SERR or PERR assertion. Disble
5536 * PERR and SERR responses during the CHIPRST.
5537 */
5538 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
4382 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
4383 uint32_t mod_cmd;
4384
4385 /*
4386 * A4 Razor #632
4387 * During the assertion of CHIPRST, the chip
4388 * does not disable its parity logic prior to
4389 * the start of the reset. This may cause a
4390 * parity error to be detected and thus a
4391 * spurious SERR or PERR assertion. Disble
4392 * PERR and SERR responses during the CHIPRST.
4393 */
4394 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
5539 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
4395 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5540 mod_cmd, /*bytes*/2);
5541 }
5542 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5543
5544 /*
5545 * Ensure that the reset has finished. We delay 1000us
5546 * prior to reading the register to make sure the chip
5547 * has sufficiently completed its reset to handle register
5548 * accesses.
5549 */
5550 wait = 1000;
5551 do {
4396 mod_cmd, /*bytes*/2);
4397 }
4398 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
4399
4400 /*
4401 * Ensure that the reset has finished. We delay 1000us
4402 * prior to reading the register to make sure the chip
4403 * has sufficiently completed its reset to handle register
4404 * accesses.
4405 */
4406 wait = 1000;
4407 do {
5552 aic_delay(1000);
4408 ahd_delay(1000);
5553 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5554
5555 if (wait == 0) {
5556 printf("%s: WARNING - Failed chip reset! "
5557 "Trying to initialize anyway.\n", ahd_name(ahd));
4409 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
4410
4411 if (wait == 0) {
4412 printf("%s: WARNING - Failed chip reset! "
4413 "Trying to initialize anyway.\n", ahd_name(ahd));
5558 AHD_FATAL_ERROR(ahd);
5559 }
5560 ahd_outb(ahd, HCNTRL, ahd->pause);
5561
5562 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5563 /*
5564 * Clear any latched PCI error status and restore
5565 * previous SERR and PERR response enables.
5566 */
4414 }
4415 ahd_outb(ahd, HCNTRL, ahd->pause);
4416
4417 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
4418 /*
4419 * Clear any latched PCI error status and restore
4420 * previous SERR and PERR response enables.
4421 */
5567 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
4422 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
5568 0xFF, /*bytes*/1);
4423 0xFF, /*bytes*/1);
5569 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
4424 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5570 cmd, /*bytes*/2);
5571 }
4425 cmd, /*bytes*/2);
4426 }
5572
5573 /*
5574 * Mode should be SCSI after a chip reset, but lets
5575 * set it just to be safe. We touch the MODE_PTR
5576 * register directly so as to bypass the lazy update
5577 * code in ahd_set_modes().
5578 */
4427 /* After a reset, we know the state of the mode register. */
5579 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
4428 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5580 ahd_outb(ahd, MODE_PTR,
5581 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5582
4429
4430 /* Determine chip configuration */
4431 ahd->features &= ~AHD_WIDE;
4432 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
4433 ahd->features |= AHD_WIDE;
4434
5583 /*
5584 * Restore SXFRCTL1.
5585 *
5586 * We must always initialize STPWEN to 1 before we
5587 * restore the saved values. STPWEN is initialized
5588 * to a tri-state condition which can only be cleared
5589 * by turning it on.
5590 */
5591 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5592 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5593
4435 /*
4436 * Restore SXFRCTL1.
4437 *
4438 * We must always initialize STPWEN to 1 before we
4439 * restore the saved values. STPWEN is initialized
4440 * to a tri-state condition which can only be cleared
4441 * by turning it on.
4442 */
4443 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
4444 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
4445
5594 /* Determine chip configuration */
5595 ahd->features &= ~AHD_WIDE;
5596 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5597 ahd->features |= AHD_WIDE;
5598
5599 /*
5600 * If a recovery action has forced a chip reset,
4446 /*
4447 * If a recovery action has forced a chip reset,
5601 * re-initialize the chip to our liking.
4448 * re-initialize the chip to our likeing.
5602 */
4449 */
5603 if (reinit != 0)
4450 if (ahd->init_level > 0)
5604 ahd_chip_init(ahd);
5605
5606 return (0);
5607}
5608
5609/*
5610 * Determine the number of SCBs available on the controller
5611 */

--- 44 unchanged lines hidden (view full) ---

5656 /* Set the next pointer */
5657 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5658 }
5659}
5660
5661static int
5662ahd_init_scbdata(struct ahd_softc *ahd)
5663{
4451 ahd_chip_init(ahd);
4452
4453 return (0);
4454}
4455
4456/*
4457 * Determine the number of SCBs available on the controller
4458 */

--- 44 unchanged lines hidden (view full) ---

4503 /* Set the next pointer */
4504 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
4505 }
4506}
4507
4508static int
4509ahd_init_scbdata(struct ahd_softc *ahd)
4510{
5664 struct scb_data *scb_data;
5665 int i;
4511 struct scb_data *scb_data;
5666
5667 scb_data = &ahd->scb_data;
4512
4513 scb_data = &ahd->scb_data;
5668 TAILQ_INIT(&scb_data->free_scbs);
5669 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
5670 LIST_INIT(&scb_data->free_scb_lists[i]);
5671 LIST_INIT(&scb_data->any_dev_free_scb_list);
4514 SLIST_INIT(&scb_data->free_scbs);
5672 SLIST_INIT(&scb_data->hscb_maps);
5673 SLIST_INIT(&scb_data->sg_maps);
5674 SLIST_INIT(&scb_data->sense_maps);
5675
5676 /* Determine the number of hardware SCBs and initialize them */
5677 scb_data->maxhscbs = ahd_probe_scbs(ahd);
5678 if (scb_data->maxhscbs == 0) {
5679 printf("%s: No SCB space found\n", ahd_name(ahd));
4515 SLIST_INIT(&scb_data->hscb_maps);
4516 SLIST_INIT(&scb_data->sg_maps);
4517 SLIST_INIT(&scb_data->sense_maps);
4518
4519 /* Determine the number of hardware SCBs and initialize them */
4520 scb_data->maxhscbs = ahd_probe_scbs(ahd);
4521 if (scb_data->maxhscbs == 0) {
4522 printf("%s: No SCB space found\n", ahd_name(ahd));
5680 AHD_FATAL_ERROR(ahd);
5681 return (ENXIO);
5682 }
5683
5684 ahd_initialize_hscbs(ahd);
5685
5686 /*
5687 * Create our DMA tags. These tags define the kinds of device
5688 * accessible memory allocations and memory mappings we will
5689 * need to perform during normal operation.
5690 *
5691 * Unless we need to further restrict the allocation, we rely
5692 * on the restrictions of the parent dmat, hence the common
5693 * use of MAXADDR and MAXSIZE.
5694 */
5695
5696 /* DMA tag for our hardware scb structures */
4523 return (ENXIO);
4524 }
4525
4526 ahd_initialize_hscbs(ahd);
4527
4528 /*
4529 * Create our DMA tags. These tags define the kinds of device
4530 * accessible memory allocations and memory mappings we will
4531 * need to perform during normal operation.
4532 *
4533 * Unless we need to further restrict the allocation, we rely
4534 * on the restrictions of the parent dmat, hence the common
4535 * use of MAXADDR and MAXSIZE.
4536 */
4537
4538 /* DMA tag for our hardware scb structures */
5697 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
4539 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5698 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5699 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5700 /*highaddr*/BUS_SPACE_MAXADDR,
5701 /*filter*/NULL, /*filterarg*/NULL,
5702 PAGE_SIZE, /*nsegments*/1,
5703 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5704 /*flags*/0, &scb_data->hscb_dmat) != 0) {
5705 goto error_exit;
5706 }
5707
5708 scb_data->init_level++;
5709
5710 /* DMA tag for our S/G structures. */
4540 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4541 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4542 /*highaddr*/BUS_SPACE_MAXADDR,
4543 /*filter*/NULL, /*filterarg*/NULL,
4544 PAGE_SIZE, /*nsegments*/1,
4545 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4546 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4547 goto error_exit;
4548 }
4549
4550 scb_data->init_level++;
4551
4552 /* DMA tag for our S/G structures. */
5711 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
4553 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5712 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5713 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5714 /*highaddr*/BUS_SPACE_MAXADDR,
5715 /*filter*/NULL, /*filterarg*/NULL,
5716 ahd_sglist_allocsize(ahd), /*nsegments*/1,
5717 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5718 /*flags*/0, &scb_data->sg_dmat) != 0) {
5719 goto error_exit;
5720 }
5721#ifdef AHD_DEBUG
5722 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
5723 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
5724 ahd_sglist_allocsize(ahd));
5725#endif
5726
5727 scb_data->init_level++;
5728
5729 /* DMA tag for our sense buffers. We allocate in page sized chunks */
4554 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4555 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4556 /*highaddr*/BUS_SPACE_MAXADDR,
4557 /*filter*/NULL, /*filterarg*/NULL,
4558 ahd_sglist_allocsize(ahd), /*nsegments*/1,
4559 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4560 /*flags*/0, &scb_data->sg_dmat) != 0) {
4561 goto error_exit;
4562 }
4563#ifdef AHD_DEBUG
4564 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
4565 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
4566 ahd_sglist_allocsize(ahd));
4567#endif
4568
4569 scb_data->init_level++;
4570
4571 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5730 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
4572 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5731 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5732 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5733 /*highaddr*/BUS_SPACE_MAXADDR,
5734 /*filter*/NULL, /*filterarg*/NULL,
5735 PAGE_SIZE, /*nsegments*/1,
5736 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5737 /*flags*/0, &scb_data->sense_dmat) != 0) {
5738 goto error_exit;
5739 }
5740
5741 scb_data->init_level++;
5742
5743 /* Perform initial CCB allocation */
4573 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4574 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4575 /*highaddr*/BUS_SPACE_MAXADDR,
4576 /*filter*/NULL, /*filterarg*/NULL,
4577 PAGE_SIZE, /*nsegments*/1,
4578 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4579 /*flags*/0, &scb_data->sense_dmat) != 0) {
4580 goto error_exit;
4581 }
4582
4583 scb_data->init_level++;
4584
4585 /* Perform initial CCB allocation */
5744 while (ahd_alloc_scbs(ahd) != 0)
5745 ;
4586 ahd_alloc_scbs(ahd);
5746
5747 if (scb_data->numscbs == 0) {
5748 printf("%s: ahd_init_scbdata - "
5749 "Unable to allocate initial scbs\n",
5750 ahd_name(ahd));
5751 goto error_exit;
5752 }
5753
5754 /*
4587
4588 if (scb_data->numscbs == 0) {
4589 printf("%s: ahd_init_scbdata - "
4590 "Unable to allocate initial scbs\n",
4591 ahd_name(ahd));
4592 goto error_exit;
4593 }
4594
4595 /*
4596 * Reserve an SCB as the initial "next SCB" to be
4597 * queued to the controller.
4598 */
4599 ahd->next_queued_scb = ahd_get_scb(ahd);
4600
4601 /*
5755 * Note that we were successfull
5756 */
5757 return (0);
5758
5759error_exit:
5760
5761 return (ENOMEM);
5762}
5763
4602 * Note that we were successfull
4603 */
4604 return (0);
4605
4606error_exit:
4607
4608 return (ENOMEM);
4609}
4610
5764static struct scb *
5765ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5766{
5767 struct scb *scb;
5768
5769 /*
5770 * Look on the pending list.
5771 */
5772 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
5773 if (SCB_GET_TAG(scb) == tag)
5774 return (scb);
5775 }
5776
5777 /*
5778 * Then on all of the collision free lists.
5779 */
5780 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5781 struct scb *list_scb;
5782
5783 list_scb = scb;
5784 do {
5785 if (SCB_GET_TAG(list_scb) == tag)
5786 return (list_scb);
5787 list_scb = LIST_NEXT(list_scb, collision_links);
5788 } while (list_scb);
5789 }
5790
5791 /*
5792 * And finally on the generic free list.
5793 */
5794 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
5795 if (SCB_GET_TAG(scb) == tag)
5796 return (scb);
5797 }
5798
5799 return (NULL);
5800}
5801
5802static void
5803ahd_fini_scbdata(struct ahd_softc *ahd)
5804{
5805 struct scb_data *scb_data;
5806
5807 scb_data = &ahd->scb_data;
5808 if (scb_data == NULL)
5809 return;
5810
5811 switch (scb_data->init_level) {
5812 default:
5813 case 7:
5814 {
5815 struct map_node *sns_map;
5816
5817 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5818 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
4611static void
4612ahd_fini_scbdata(struct ahd_softc *ahd)
4613{
4614 struct scb_data *scb_data;
4615
4616 scb_data = &ahd->scb_data;
4617 if (scb_data == NULL)
4618 return;
4619
4620 switch (scb_data->init_level) {
4621 default:
4622 case 7:
4623 {
4624 struct map_node *sns_map;
4625
4626 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
4627 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5819 aic_dmamap_unload(ahd, scb_data->sense_dmat,
4628 ahd_dmamap_unload(ahd, scb_data->sense_dmat,
5820 sns_map->dmamap);
4629 sns_map->dmamap);
5821 aic_dmamem_free(ahd, scb_data->sense_dmat,
4630 ahd_dmamem_free(ahd, scb_data->sense_dmat,
5822 sns_map->vaddr, sns_map->dmamap);
5823 free(sns_map, M_DEVBUF);
5824 }
4631 sns_map->vaddr, sns_map->dmamap);
4632 free(sns_map, M_DEVBUF);
4633 }
5825 aic_dma_tag_destroy(ahd, scb_data->sense_dmat);
4634 ahd_dma_tag_destroy(ahd, scb_data->sense_dmat);
5826 /* FALLTHROUGH */
5827 }
5828 case 6:
5829 {
5830 struct map_node *sg_map;
5831
5832 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5833 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4635 /* FALLTHROUGH */
4636 }
4637 case 6:
4638 {
4639 struct map_node *sg_map;
4640
4641 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
4642 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5834 aic_dmamap_unload(ahd, scb_data->sg_dmat,
4643 ahd_dmamap_unload(ahd, scb_data->sg_dmat,
5835 sg_map->dmamap);
4644 sg_map->dmamap);
5836 aic_dmamem_free(ahd, scb_data->sg_dmat,
4645 ahd_dmamem_free(ahd, scb_data->sg_dmat,
5837 sg_map->vaddr, sg_map->dmamap);
5838 free(sg_map, M_DEVBUF);
5839 }
4646 sg_map->vaddr, sg_map->dmamap);
4647 free(sg_map, M_DEVBUF);
4648 }
5840 aic_dma_tag_destroy(ahd, scb_data->sg_dmat);
4649 ahd_dma_tag_destroy(ahd, scb_data->sg_dmat);
5841 /* FALLTHROUGH */
5842 }
5843 case 5:
5844 {
5845 struct map_node *hscb_map;
5846
5847 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5848 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
4650 /* FALLTHROUGH */
4651 }
4652 case 5:
4653 {
4654 struct map_node *hscb_map;
4655
4656 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
4657 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5849 aic_dmamap_unload(ahd, scb_data->hscb_dmat,
4658 ahd_dmamap_unload(ahd, scb_data->hscb_dmat,
5850 hscb_map->dmamap);
4659 hscb_map->dmamap);
5851 aic_dmamem_free(ahd, scb_data->hscb_dmat,
4660 ahd_dmamem_free(ahd, scb_data->hscb_dmat,
5852 hscb_map->vaddr, hscb_map->dmamap);
5853 free(hscb_map, M_DEVBUF);
5854 }
4661 hscb_map->vaddr, hscb_map->dmamap);
4662 free(hscb_map, M_DEVBUF);
4663 }
5855 aic_dma_tag_destroy(ahd, scb_data->hscb_dmat);
4664 ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat);
5856 /* FALLTHROUGH */
5857 }
5858 case 4:
5859 case 3:
5860 case 2:
5861 case 1:
5862 case 0:
5863 break;

--- 9 unchanged lines hidden (view full) ---

5873{
5874 ahd_mode_state saved_modes;
5875
5876 saved_modes = ahd_save_modes(ahd);
5877 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5878 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5879 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5880 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
4665 /* FALLTHROUGH */
4666 }
4667 case 4:
4668 case 3:
4669 case 2:
4670 case 1:
4671 case 0:
4672 break;

--- 9 unchanged lines hidden (view full) ---

4682{
4683 ahd_mode_state saved_modes;
4684
4685 saved_modes = ahd_save_modes(ahd);
4686 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
4687 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
4688 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
4689 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5881#ifdef AHD_DEBUG
5882 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5883 printf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5884#endif
5885 ahd_restore_modes(ahd, saved_modes);
4690 ahd_restore_modes(ahd, saved_modes);
5886 ahd->flags &= ~AHD_HAD_FIRST_SEL;
5887}
5888
5889static void
5890ahd_iocell_first_selection(struct ahd_softc *ahd)
5891{
5892 ahd_mode_state saved_modes;
5893 u_int sblkctl;
5894
4691}
4692
4693static void
4694ahd_iocell_first_selection(struct ahd_softc *ahd)
4695{
4696 ahd_mode_state saved_modes;
4697 u_int sblkctl;
4698
5895 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5896 return;
5897 saved_modes = ahd_save_modes(ahd);
5898 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5899 sblkctl = ahd_inb(ahd, SBLKCTL);
5900 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
4699 saved_modes = ahd_save_modes(ahd);
4700 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
4701 sblkctl = ahd_inb(ahd, SBLKCTL);
4702 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5901#ifdef AHD_DEBUG
5902 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5903 printf("%s: iocell first selection\n", ahd_name(ahd));
5904#endif
5905 if ((sblkctl & ENAB40) != 0) {
5906 ahd_outb(ahd, DSPDATACTL,
5907 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
4703 if ((sblkctl & ENAB40) != 0) {
4704 ahd_outb(ahd, DSPDATACTL,
4705 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5908#ifdef AHD_DEBUG
5909 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5910 printf("%s: BYPASS now disabled\n", ahd_name(ahd));
5911#endif
5912 }
5913 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5914 ahd_outb(ahd, CLRINT, CLRSCSIINT);
5915 ahd_restore_modes(ahd, saved_modes);
4706 }
4707 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
4708 ahd_outb(ahd, CLRINT, CLRSCSIINT);
4709 ahd_restore_modes(ahd, saved_modes);
5916 ahd->flags |= AHD_HAD_FIRST_SEL;
5917}
5918
4710}
4711
5919/*************************** SCB Management ***********************************/
5920static void
5921ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
5922{
5923 struct scb_list *free_list;
5924 struct scb_tailq *free_tailq;
5925 struct scb *first_scb;
5926
5927 scb->flags |= SCB_ON_COL_LIST;
5928 AHD_SET_SCB_COL_IDX(scb, col_idx);
5929 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5930 free_tailq = &ahd->scb_data.free_scbs;
5931 first_scb = LIST_FIRST(free_list);
5932 if (first_scb != NULL) {
5933 LIST_INSERT_AFTER(first_scb, scb, collision_links);
5934 } else {
5935 LIST_INSERT_HEAD(free_list, scb, collision_links);
5936 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
5937 }
5938}
5939
5940static void
5941ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
5942{
5943 struct scb_list *free_list;
5944 struct scb_tailq *free_tailq;
5945 struct scb *first_scb;
5946 u_int col_idx;
5947
5948 scb->flags &= ~SCB_ON_COL_LIST;
5949 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
5950 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5951 free_tailq = &ahd->scb_data.free_scbs;
5952 first_scb = LIST_FIRST(free_list);
5953 if (first_scb == scb) {
5954 struct scb *next_scb;
5955
5956 /*
5957 * Maintain order in the collision free
5958 * lists for fairness if this device has
5959 * other colliding tags active.
5960 */
5961 next_scb = LIST_NEXT(scb, collision_links);
5962 if (next_scb != NULL) {
5963 TAILQ_INSERT_AFTER(free_tailq, scb,
5964 next_scb, links.tqe);
5965 }
5966 TAILQ_REMOVE(free_tailq, scb, links.tqe);
5967 }
5968 LIST_REMOVE(scb, collision_links);
5969}
5970
5971/*
5972 * Get a free scb. If there are none, see if we can allocate a new SCB.
5973 */
5974struct scb *
5975ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
5976{
5977 struct scb *scb;
5978 int tries;
5979
5980 tries = 0;
5981look_again:
5982 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5983 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
5984 ahd_rem_col_list(ahd, scb);
5985 goto found;
5986 }
5987 }
5988 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
5989
5990 if (tries++ != 0)
5991 return (NULL);
5992 if (ahd_alloc_scbs(ahd) == 0)
5993 return (NULL);
5994 goto look_again;
5995 }
5996 LIST_REMOVE(scb, links.le);
5997 if (col_idx != AHD_NEVER_COL_IDX
5998 && (scb->col_scb != NULL)
5999 && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
6000 LIST_REMOVE(scb->col_scb, links.le);
6001 ahd_add_col_list(ahd, scb->col_scb, col_idx);
6002 }
6003found:
6004 scb->flags |= SCB_ACTIVE;
6005 return (scb);
6006}
6007
6008/*
6009 * Return an SCB resource to the free list.
6010 */
6011void
4712void
6012ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
6013{
6014
6015 /* Clean up for the next user */
6016 scb->flags = SCB_FLAG_NONE;
6017 scb->hscb->control = 0;
6018 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
6019
6020 if (scb->col_scb == NULL) {
6021
6022 /*
6023 * No collision possible. Just free normally.
6024 */
6025 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6026 scb, links.le);
6027 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
6028
6029 /*
6030 * The SCB we might have collided with is on
6031 * a free collision list. Put both SCBs on
6032 * the generic list.
6033 */
6034 ahd_rem_col_list(ahd, scb->col_scb);
6035 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6036 scb, links.le);
6037 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6038 scb->col_scb, links.le);
6039 } else if ((scb->col_scb->flags
6040 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
6041 && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
6042
6043 /*
6044 * The SCB we might collide with on the next allocation
6045 * is still active in a non-packetized, tagged, context.
6046 * Put us on the SCB collision list.
6047 */
6048 ahd_add_col_list(ahd, scb,
6049 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
6050 } else {
6051 /*
6052 * The SCB we might collide with on the next allocation
6053 * is either active in a packetized context, or free.
6054 * Since we can't collide, put this SCB on the generic
6055 * free list.
6056 */
6057 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6058 scb, links.le);
6059 }
6060
6061 aic_platform_scb_free(ahd, scb);
6062}
6063
6064int
6065ahd_alloc_scbs(struct ahd_softc *ahd)
6066{
6067 struct scb_data *scb_data;
6068 struct scb *next_scb;
6069 struct hardware_scb *hscb;
6070 struct map_node *hscb_map;
6071 struct map_node *sg_map;
6072 struct map_node *sense_map;
6073 uint8_t *segs;
6074 uint8_t *sense_data;
6075 bus_addr_t hscb_busaddr;
6076 bus_addr_t sg_busaddr;
6077 bus_addr_t sense_busaddr;
6078 int newcount;
6079 int i;
6080
6081 scb_data = &ahd->scb_data;
6082 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
6083 /* Can't allocate any more */
4713ahd_alloc_scbs(struct ahd_softc *ahd)
4714{
4715 struct scb_data *scb_data;
4716 struct scb *next_scb;
4717 struct hardware_scb *hscb;
4718 struct map_node *hscb_map;
4719 struct map_node *sg_map;
4720 struct map_node *sense_map;
4721 uint8_t *segs;
4722 uint8_t *sense_data;
4723 bus_addr_t hscb_busaddr;
4724 bus_addr_t sg_busaddr;
4725 bus_addr_t sense_busaddr;
4726 int newcount;
4727 int i;
4728
4729 scb_data = &ahd->scb_data;
4730 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
4731 /* Can't allocate any more */
6084 return (0);
4732 return;
6085
6086 if (scb_data->scbs_left != 0) {
6087 int offset;
6088
6089 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
6090 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
6091 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
4733
4734 if (scb_data->scbs_left != 0) {
4735 int offset;
4736
4737 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
4738 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
4739 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
6092 hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb));
4740 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb));
6093 } else {
6094 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT);
6095
6096 if (hscb_map == NULL)
4741 } else {
4742 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT);
4743
4744 if (hscb_map == NULL)
6097 return (0);
4745 return;
6098
6099 /* Allocate the next batch of hardware SCBs */
4746
4747 /* Allocate the next batch of hardware SCBs */
6100 if (aic_dmamem_alloc(ahd, scb_data->hscb_dmat,
4748 if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat,
6101 (void **)&hscb_map->vaddr,
6102 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) {
6103 free(hscb_map, M_DEVBUF);
4749 (void **)&hscb_map->vaddr,
4750 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) {
4751 free(hscb_map, M_DEVBUF);
6104 return (0);
4752 return;
6105 }
6106
6107 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
6108
4753 }
4754
4755 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
4756
6109 aic_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
4757 ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
6110 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
4758 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6111 &hscb_map->busaddr, /*flags*/0);
4759 &hscb_map->physaddr, /*flags*/0);
6112
6113 hscb = (struct hardware_scb *)hscb_map->vaddr;
4760
4761 hscb = (struct hardware_scb *)hscb_map->vaddr;
6114 hscb_busaddr = hscb_map->busaddr;
4762 hscb_busaddr = hscb_map->physaddr;
6115 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
6116 }
6117
6118 if (scb_data->sgs_left != 0) {
6119 int offset;
6120
4763 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
4764 }
4765
4766 if (scb_data->sgs_left != 0) {
4767 int offset;
4768
6121 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
6122 - scb_data->sgs_left) * ahd_sglist_size(ahd);
4769 offset = ahd_sglist_allocsize(ahd)
4770 - (scb_data->sgs_left * ahd_sglist_size(ahd));
6123 sg_map = SLIST_FIRST(&scb_data->sg_maps);
6124 segs = sg_map->vaddr + offset;
4771 sg_map = SLIST_FIRST(&scb_data->sg_maps);
4772 segs = sg_map->vaddr + offset;
6125 sg_busaddr = sg_map->busaddr + offset;
4773 sg_busaddr = sg_map->physaddr + offset;
6126 } else {
6127 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
6128
6129 if (sg_map == NULL)
4774 } else {
4775 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4776
4777 if (sg_map == NULL)
6130 return (0);
4778 return;
6131
6132 /* Allocate the next batch of S/G lists */
4779
4780 /* Allocate the next batch of S/G lists */
6133 if (aic_dmamem_alloc(ahd, scb_data->sg_dmat,
4781 if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat,
6134 (void **)&sg_map->vaddr,
6135 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) {
6136 free(sg_map, M_DEVBUF);
4782 (void **)&sg_map->vaddr,
4783 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) {
4784 free(sg_map, M_DEVBUF);
6137 return (0);
4785 return;
6138 }
6139
6140 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
6141
4786 }
4787
4788 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4789
6142 aic_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
4790 ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
6143 sg_map->vaddr, ahd_sglist_allocsize(ahd),
4791 sg_map->vaddr, ahd_sglist_allocsize(ahd),
6144 ahd_dmamap_cb, &sg_map->busaddr, /*flags*/0);
4792 ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0);
6145
6146 segs = sg_map->vaddr;
4793
4794 segs = sg_map->vaddr;
6147 sg_busaddr = sg_map->busaddr;
4795 sg_busaddr = sg_map->physaddr;
6148 scb_data->sgs_left =
6149 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
6150#ifdef AHD_DEBUG
6151 if (ahd_debug & AHD_SHOW_MEMORY)
6152 printf("Mapped SG data\n");
6153#endif
6154 }
6155
6156 if (scb_data->sense_left != 0) {
6157 int offset;
6158
6159 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
6160 sense_map = SLIST_FIRST(&scb_data->sense_maps);
6161 sense_data = sense_map->vaddr + offset;
4796 scb_data->sgs_left =
4797 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
4798#ifdef AHD_DEBUG
4799 if (ahd_debug & AHD_SHOW_MEMORY)
4800 printf("Mapped SG data\n");
4801#endif
4802 }
4803
4804 if (scb_data->sense_left != 0) {
4805 int offset;
4806
4807 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
4808 sense_map = SLIST_FIRST(&scb_data->sense_maps);
4809 sense_data = sense_map->vaddr + offset;
6162 sense_busaddr = sense_map->busaddr + offset;
4810 sense_busaddr = sense_map->physaddr + offset;
6163 } else {
6164 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT);
6165
6166 if (sense_map == NULL)
4811 } else {
4812 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT);
4813
4814 if (sense_map == NULL)
6167 return (0);
4815 return;
6168
6169 /* Allocate the next batch of sense buffers */
4816
4817 /* Allocate the next batch of sense buffers */
6170 if (aic_dmamem_alloc(ahd, scb_data->sense_dmat,
4818 if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat,
6171 (void **)&sense_map->vaddr,
6172 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
6173 free(sense_map, M_DEVBUF);
4819 (void **)&sense_map->vaddr,
4820 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
4821 free(sense_map, M_DEVBUF);
6174 return (0);
4822 return;
6175 }
6176
6177 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
6178
4823 }
4824
4825 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
4826
6179 aic_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
4827 ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
6180 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
4828 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6181 &sense_map->busaddr, /*flags*/0);
4829 &sense_map->physaddr, /*flags*/0);
6182
6183 sense_data = sense_map->vaddr;
4830
4831 sense_data = sense_map->vaddr;
6184 sense_busaddr = sense_map->busaddr;
4832 sense_busaddr = sense_map->physaddr;
6185 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
6186#ifdef AHD_DEBUG
6187 if (ahd_debug & AHD_SHOW_MEMORY)
6188 printf("Mapped sense data\n");
6189#endif
6190 }
6191
6192 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
6193 newcount = MIN(newcount, scb_data->sgs_left);
6194 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
6195 scb_data->sense_left -= newcount;
6196 scb_data->scbs_left -= newcount;
6197 scb_data->sgs_left -= newcount;
6198 for (i = 0; i < newcount; i++) {
6199 struct scb_platform_data *pdata;
4833 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
4834#ifdef AHD_DEBUG
4835 if (ahd_debug & AHD_SHOW_MEMORY)
4836 printf("Mapped sense data\n");
4837#endif
4838 }
4839
4840 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
4841 newcount = MIN(newcount, scb_data->sgs_left);
4842 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
4843 scb_data->sense_left -= newcount;
4844 scb_data->scbs_left -= newcount;
4845 scb_data->sgs_left -= newcount;
4846 for (i = 0; i < newcount; i++) {
4847 struct scb_platform_data *pdata;
6200 u_int col_tag;
6201#ifndef __linux__
6202 int error;
6203#endif
4848#ifndef __linux__
4849 int error;
4850#endif
6204
6205 next_scb = (struct scb *)malloc(sizeof(*next_scb),
6206 M_DEVBUF, M_NOWAIT);
6207 if (next_scb == NULL)
6208 break;
6209
6210 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
6211 M_DEVBUF, M_NOWAIT);
6212 if (pdata == NULL) {
6213 free(next_scb, M_DEVBUF);
6214 break;
6215 }
6216 next_scb->platform_data = pdata;
6217 next_scb->hscb_map = hscb_map;
6218 next_scb->sg_map = sg_map;
6219 next_scb->sense_map = sense_map;
6220 next_scb->sg_list = segs;
6221 next_scb->sense_data = sense_data;
6222 next_scb->sense_busaddr = sense_busaddr;
4851 next_scb = (struct scb *)malloc(sizeof(*next_scb),
4852 M_DEVBUF, M_NOWAIT);
4853 if (next_scb == NULL)
4854 break;
4855
4856 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4857 M_DEVBUF, M_NOWAIT);
4858 if (pdata == NULL) {
4859 free(next_scb, M_DEVBUF);
4860 break;
4861 }
4862 next_scb->platform_data = pdata;
4863 next_scb->hscb_map = hscb_map;
4864 next_scb->sg_map = sg_map;
4865 next_scb->sense_map = sense_map;
4866 next_scb->sg_list = segs;
4867 next_scb->sense_data = sense_data;
4868 next_scb->sense_busaddr = sense_busaddr;
6223 memset(hscb, 0, sizeof(*hscb));
6224 next_scb->hscb = hscb;
4869 next_scb->hscb = hscb;
6225 hscb->hscb_busaddr = aic_htole32(hscb_busaddr);
4870 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr);
6226
6227 /*
6228 * The sequencer always starts with the second entry.
6229 * The first entry is embedded in the scb.
6230 */
6231 next_scb->sg_list_busaddr = sg_busaddr;
6232 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
6233 next_scb->sg_list_busaddr
6234 += sizeof(struct ahd_dma64_seg);
6235 else
6236 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
6237 next_scb->ahd_softc = ahd;
4871
4872 /*
4873 * The sequencer always starts with the second entry.
4874 * The first entry is embedded in the scb.
4875 */
4876 next_scb->sg_list_busaddr = sg_busaddr;
4877 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
4878 next_scb->sg_list_busaddr
4879 += sizeof(struct ahd_dma64_seg);
4880 else
4881 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
4882 next_scb->ahd_softc = ahd;
6238 next_scb->flags = SCB_FLAG_NONE;
4883 next_scb->flags = SCB_FREE;
6239#ifndef __linux__
4884#ifndef __linux__
6240 error = aic_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
4885 error = ahd_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
6241 &next_scb->dmamap);
6242 if (error != 0) {
6243 free(next_scb, M_DEVBUF);
6244 free(pdata, M_DEVBUF);
6245 break;
6246 }
6247#endif
4886 &next_scb->dmamap);
4887 if (error != 0) {
4888 free(next_scb, M_DEVBUF);
4889 free(pdata, M_DEVBUF);
4890 break;
4891 }
4892#endif
6248 next_scb->hscb->tag = aic_htole16(scb_data->numscbs);
6249 col_tag = scb_data->numscbs ^ 0x100;
6250 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
6251 if (next_scb->col_scb != NULL)
6252 next_scb->col_scb->col_scb = next_scb;
6253 aic_timer_init(&next_scb->io_timer);
6254 ahd_free_scb(ahd, next_scb);
4893 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs);
4894
4895 SLIST_INSERT_HEAD(&scb_data->free_scbs,
4896 next_scb, links.sle);
6255 hscb++;
6256 hscb_busaddr += sizeof(*hscb);
6257 segs += ahd_sglist_size(ahd);
6258 sg_busaddr += ahd_sglist_size(ahd);
6259 sense_data += AHD_SENSE_BUFSIZE;
6260 sense_busaddr += AHD_SENSE_BUFSIZE;
6261 scb_data->numscbs++;
6262 }
4897 hscb++;
4898 hscb_busaddr += sizeof(*hscb);
4899 segs += ahd_sglist_size(ahd);
4900 sg_busaddr += ahd_sglist_size(ahd);
4901 sense_data += AHD_SENSE_BUFSIZE;
4902 sense_busaddr += AHD_SENSE_BUFSIZE;
4903 scb_data->numscbs++;
4904 }
6263 return (i);
6264}
6265
6266void
6267ahd_controller_info(struct ahd_softc *ahd, char *buf)
6268{
6269 const char *speed;
6270 const char *type;
6271 int len;
6272
6273 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
6274 buf += len;
6275
6276 speed = "Ultra320 ";
6277 if ((ahd->features & AHD_WIDE) != 0) {
4905}
4906
4907void
4908ahd_controller_info(struct ahd_softc *ahd, char *buf)
4909{
4910 const char *speed;
4911 const char *type;
4912 int len;
4913
4914 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
4915 buf += len;
4916
4917 speed = "Ultra320 ";
4918 if ((ahd->features & AHD_WIDE) != 0) {
6278 type = "Wide ";
4919 type = "Wide";
6279 } else {
4920 } else {
6280 type = "Single ";
4921 type = "Single";
6281 }
6282 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
6283 speed, type, ahd->channel, ahd->our_id);
6284 buf += len;
6285
6286 sprintf(buf, "%s, %d SCBs", ahd->bus_description,
6287 ahd->scb_data.maxhscbs);
6288}

--- 13 unchanged lines hidden (view full) ---

6302};
6303
6304/*
6305 * Start the board, ready for normal operation
6306 */
6307int
6308ahd_init(struct ahd_softc *ahd)
6309{
4922 }
4923 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
4924 speed, type, ahd->channel, ahd->our_id);
4925 buf += len;
4926
4927 sprintf(buf, "%s, %d SCBs", ahd->bus_description,
4928 ahd->scb_data.maxhscbs);
4929}

--- 13 unchanged lines hidden (view full) ---

4943};
4944
4945/*
4946 * Start the board, ready for normal operation
4947 */
4948int
4949ahd_init(struct ahd_softc *ahd)
4950{
6310 uint8_t *next_vaddr;
6311 bus_addr_t next_baddr;
6312 size_t driver_data_size;
6313 int i;
6314 int error;
6315 u_int warn_user;
6316 uint8_t current_sensing;
6317 uint8_t fstat;
4951 size_t driver_data_size;
4952 int i;
4953 int error;
4954 int wait;
4955 u_int warn_user;
4956 uint8_t current_sensing;
4957 uint8_t fstat;
6318
6319 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6320
4958
4959 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
4960
6321 ahd->stack_size = ahd_probe_stack_size(ahd);
6322 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t),
6323 M_DEVBUF, M_NOWAIT);
6324 if (ahd->saved_stack == NULL)
6325 return (ENOMEM);
6326
6327 /*
6328 * Verify that the compiler hasn't over-agressively
6329 * padded important structures.
6330 */
6331 if (sizeof(struct hardware_scb) != 64)
6332 panic("Hardware SCB size is incorrect");
6333
6334#ifdef AHD_DEBUG

--- 9 unchanged lines hidden (view full) ---

6344 /*
6345 * Only allow target mode features if this unit has them enabled.
6346 */
6347 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6348 ahd->features &= ~AHD_TARGETMODE;
6349
6350#ifndef __linux__
6351 /* DMA tag for mapping buffers into device visible space. */
4961 /*
4962 * Verify that the compiler hasn't over-agressively
4963 * padded important structures.
4964 */
4965 if (sizeof(struct hardware_scb) != 64)
4966 panic("Hardware SCB size is incorrect");
4967
4968#ifdef AHD_DEBUG

--- 9 unchanged lines hidden (view full) ---

4978 /*
4979 * Only allow target mode features if this unit has them enabled.
4980 */
4981 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
4982 ahd->features &= ~AHD_TARGETMODE;
4983
4984#ifndef __linux__
4985 /* DMA tag for mapping buffers into device visible space. */
6352 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
4986 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6353 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4987 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6354 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
6355 ? (bus_addr_t)0x7FFFFFFFFFULL
6356 : BUS_SPACE_MAXADDR_32BIT,
4988 /*lowaddr*/BUS_SPACE_MAXADDR,
6357 /*highaddr*/BUS_SPACE_MAXADDR,
6358 /*filter*/NULL, /*filterarg*/NULL,
4989 /*highaddr*/BUS_SPACE_MAXADDR,
4990 /*filter*/NULL, /*filterarg*/NULL,
6359 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
6360 /*nsegments*/AHD_NSEG,
4991 /*maxsize*/MAXBSIZE, /*nsegments*/AHD_NSEG,
6361 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
6362 /*flags*/BUS_DMA_ALLOCNOW,
6363 &ahd->buffer_dmat) != 0) {
6364 return (ENOMEM);
6365 }
6366#endif
6367
6368 ahd->init_level++;
6369
6370 /*
6371 * DMA tag for our command fifos and other data in system memory
6372 * the card's sequencer must be able to access. For initiator
6373 * roles, we need to allocate space for the qoutfifo. When providing
6374 * for the target mode role, we must additionally provide space for
6375 * the incoming target command fifo.
6376 */
4992 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
4993 /*flags*/BUS_DMA_ALLOCNOW,
4994 &ahd->buffer_dmat) != 0) {
4995 return (ENOMEM);
4996 }
4997#endif
4998
4999 ahd->init_level++;
5000
5001 /*
5002 * DMA tag for our command fifos and other data in system memory
5003 * the card's sequencer must be able to access. For initiator
5004 * roles, we need to allocate space for the qoutfifo. When providing
5005 * for the target mode role, we must additionally provide space for
5006 * the incoming target command fifo.
5007 */
6377 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
6378 + sizeof(struct hardware_scb);
5008 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t);
6379 if ((ahd->features & AHD_TARGETMODE) != 0)
6380 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6381 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6382 driver_data_size += PKT_OVERRUN_BUFSIZE;
5009 if ((ahd->features & AHD_TARGETMODE) != 0)
5010 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
5011 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
5012 driver_data_size += PKT_OVERRUN_BUFSIZE;
6383 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5013 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6384 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6385 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
6386 /*highaddr*/BUS_SPACE_MAXADDR,
6387 /*filter*/NULL, /*filterarg*/NULL,
6388 driver_data_size,
6389 /*nsegments*/1,
6390 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
6391 /*flags*/0, &ahd->shared_data_dmat) != 0) {
6392 return (ENOMEM);
6393 }
6394
6395 ahd->init_level++;
6396
6397 /* Allocation of driver data */
5014 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5015 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5016 /*highaddr*/BUS_SPACE_MAXADDR,
5017 /*filter*/NULL, /*filterarg*/NULL,
5018 driver_data_size,
5019 /*nsegments*/1,
5020 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5021 /*flags*/0, &ahd->shared_data_dmat) != 0) {
5022 return (ENOMEM);
5023 }
5024
5025 ahd->init_level++;
5026
5027 /* Allocation of driver data */
6398 if (aic_dmamem_alloc(ahd, ahd->shared_data_dmat,
6399 (void **)&ahd->shared_data_map.vaddr,
6400 BUS_DMA_NOWAIT,
6401 &ahd->shared_data_map.dmamap) != 0) {
5028 if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat,
5029 (void **)&ahd->qoutfifo,
5030 BUS_DMA_NOWAIT, &ahd->shared_data_dmamap) != 0) {
6402 return (ENOMEM);
6403 }
6404
6405 ahd->init_level++;
6406
6407 /* And permanently map it in */
5031 return (ENOMEM);
5032 }
5033
5034 ahd->init_level++;
5035
5036 /* And permanently map it in */
6408 aic_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
6409 ahd->shared_data_map.vaddr, driver_data_size,
6410 ahd_dmamap_cb, &ahd->shared_data_map.busaddr,
6411 /*flags*/0);
6412 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
6413 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6414 next_baddr = ahd->shared_data_map.busaddr
6415 + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
5037 ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_dmamap,
5038 ahd->qoutfifo, driver_data_size, ahd_dmamap_cb,
5039 &ahd->shared_data_busaddr, /*flags*/0);
5040
6416 if ((ahd->features & AHD_TARGETMODE) != 0) {
5041 if ((ahd->features & AHD_TARGETMODE) != 0) {
6417 ahd->targetcmds = (struct target_cmd *)next_vaddr;
6418 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6419 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
5042 /* XXX sequencer assumes qoutfifo is first. */
5043 ahd->targetcmds = (struct target_cmd *)ahd->qoutfifo;
5044 ahd->qoutfifo = (uint16_t *)&ahd->targetcmds[AHD_TMODE_CMDS];
6420 }
6421
5045 }
5046
6422 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6423 ahd->overrun_buf = next_vaddr;
6424 next_vaddr += PKT_OVERRUN_BUFSIZE;
6425 next_baddr += PKT_OVERRUN_BUFSIZE;
6426 }
5047 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
5048 ahd->overrun_buf = (uint8_t *)&ahd->qoutfifo[AHD_SCB_MAX];
6427
5049
6428 /*
6429 * We need one SCB to serve as the "next SCB". Since the
6430 * tag identifier in this SCB will never be used, there is
6431 * no point in using a valid HSCB tag from an SCB pulled from
6432 * the standard free pool. So, we allocate this "sentinel"
6433 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6434 */
6435 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6436 ahd->next_queued_hscb_map = &ahd->shared_data_map;
6437 ahd->next_queued_hscb->hscb_busaddr = aic_htole32(next_baddr);
6438
6439 ahd->init_level++;
6440
6441 /* Allocate SCB data now that buffer_dmat is initialized */
6442 if (ahd_init_scbdata(ahd) != 0)
6443 return (ENOMEM);
6444
6445 if ((ahd->flags & AHD_INITIATORROLE) == 0)
6446 ahd->flags &= ~AHD_RESET_BUS_A;
6447
5050 ahd->init_level++;
5051
5052 /* Allocate SCB data now that buffer_dmat is initialized */
5053 if (ahd_init_scbdata(ahd) != 0)
5054 return (ENOMEM);
5055
5056 if ((ahd->flags & AHD_INITIATORROLE) == 0)
5057 ahd->flags &= ~AHD_RESET_BUS_A;
5058
6448 /*
6449 * Before committing these settings to the chip, give
6450 * the OSM one last chance to modify our configuration.
6451 */
6452 ahd_platform_init(ahd);
6453
6454 /* Bring up the chip. */
6455 ahd_chip_init(ahd);
6456
6457 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6458
5059 ahd_chip_init(ahd);
5060
5061 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
5062
5063 /*
5064 * Wait for up to 500ms for our transceivers
5065 * to settle. If the adapter does not have
5066 * a cable attached, the tranceivers may
5067 * never settle, so don't complain if we
5068 * fail here.
5069 */
5070 for (wait = 10000;
5071 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
5072 wait--)
5073 ahd_delay(100);
6459 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6460 goto init_done;
6461
6462 /*
6463 * Verify termination based on current draw and
6464 * warn user if the bus is over/under terminated.
6465 */
6466 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,

--- 50 unchanged lines hidden (view full) ---

6517 channel_strings[i], termstat_strings[term_stat]);
6518 break;
6519 }
6520 }
6521 if (warn_user) {
6522 printf("%s: WARNING. Termination is not configured correctly.\n"
6523 "%s: WARNING. SCSI bus operations may FAIL.\n",
6524 ahd_name(ahd), ahd_name(ahd));
5074 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
5075 goto init_done;
5076
5077 /*
5078 * Verify termination based on current draw and
5079 * warn user if the bus is over/under terminated.
5080 */
5081 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,

--- 50 unchanged lines hidden (view full) ---

5132 channel_strings[i], termstat_strings[term_stat]);
5133 break;
5134 }
5135 }
5136 if (warn_user) {
5137 printf("%s: WARNING. Termination is not configured correctly.\n"
5138 "%s: WARNING. SCSI bus operations may FAIL.\n",
5139 ahd_name(ahd), ahd_name(ahd));
6525 AHD_CORRECTABLE_ERROR(ahd);
6526 }
6527init_done:
6528 ahd_restart(ahd);
5140 }
5141init_done:
5142 ahd_restart(ahd);
6529 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
6530 ahd_stat_timer, ahd);
6531 return (0);
6532}
6533
6534/*
6535 * (Re)initialize chip state after a chip reset.
6536 */
6537static void
6538ahd_chip_init(struct ahd_softc *ahd)
6539{
6540 uint32_t busaddr;
6541 u_int sxfrctl1;
6542 u_int scsiseq_template;
5143 return (0);
5144}
5145
5146/*
5147 * (Re)initialize chip state after a chip reset.
5148 */
5149static void
5150ahd_chip_init(struct ahd_softc *ahd)
5151{
5152 uint32_t busaddr;
5153 u_int sxfrctl1;
5154 u_int scsiseq_template;
6543 u_int wait;
6544 u_int i;
6545 u_int target;
6546
6547 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6548 /*
6549 * Take the LED out of diagnostic mode
6550 */
6551 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6552
5155 u_int i;
5156 u_int target;
5157
5158 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5159 /*
5160 * Take the LED out of diagnostic mode
5161 */
5162 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
5163
6553 /*
6554 * Return HS_MAILBOX to its default value.
6555 */
6556 ahd->hs_mailbox = 0;
6557 ahd_outb(ahd, HS_MAILBOX, 0);
6558
6559 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6560 ahd_outb(ahd, IOWNID, ahd->our_id);
6561 ahd_outb(ahd, TOWNID, ahd->our_id);
6562 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6563 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6564 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6565 && (ahd->seltime != STIMESEL_MIN)) {
6566 /*

--- 5 unchanged lines hidden (view full) ---

6572 } else {
6573 sxfrctl1 |= ahd->seltime;
6574 }
6575
6576 ahd_outb(ahd, SXFRCTL0, DFON);
6577 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6578 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6579
5164 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
5165 ahd_outb(ahd, IOWNID, ahd->our_id);
5166 ahd_outb(ahd, TOWNID, ahd->our_id);
5167 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
5168 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
5169 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
5170 && (ahd->seltime != STIMESEL_MIN)) {
5171 /*

--- 5 unchanged lines hidden (view full) ---

5177 } else {
5178 sxfrctl1 |= ahd->seltime;
5179 }
5180
5181 ahd_outb(ahd, SXFRCTL0, DFON);
5182 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
5183 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5184
6580 /*
6581 * Now that termination is set, wait for up
6582 * to 500ms for our transceivers to settle. If
6583 * the adapter does not have a cable attached,
6584 * the transceivers may never settle, so don't
6585 * complain if we fail here.
6586 */
6587 for (wait = 10000;
6588 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6589 wait--)
6590 aic_delay(100);
6591
6592 /* Clear any false bus resets due to the transceivers settling */
6593 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6594 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6595
6596 /* Initialize mode specific S/G state. */
6597 for (i = 0; i < 2; i++) {
6598 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6599 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
5185 /* Initialize mode specific S/G state. */
5186 for (i = 0; i < 2; i++) {
5187 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
5188 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
5189 ahd_outw(ahd, LONGJMP_SCB, SCB_LIST_NULL);
6600 ahd_outb(ahd, SG_STATE, 0);
6601 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6602 ahd_outb(ahd, SEQIMODE,
6603 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6604 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6605 }
6606
6607 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6608 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6609 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6610 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6611 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
5190 ahd_outb(ahd, SG_STATE, 0);
5191 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
5192 ahd_outb(ahd, SEQIMODE,
5193 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
5194 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
5195 }
5196
5197 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5198 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
5199 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
5200 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
5201 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6612 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6613 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6614 } else {
6615 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6616 }
6617 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
5202 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6618 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6619 /*
6620 * Do not issue a target abort when a split completion
6621 * error occurs. Let our PCIX interrupt handler deal
6622 * with it instead. H2A4 Razor #625
6623 */
6624 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6625
5203 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
5204 /*
5205 * Do not issue a target abort when a split completion
5206 * error occurs. Let our PCIX interrupt handler deal
5207 * with it instead. H2A4 Razor #625
5208 */
5209 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
5210
6626 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6627 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6628
6629 /*
6630 * Tweak IOCELL settings.
6631 */
5211 /*
5212 * Tweak IOCELL settings.
5213 */
6632 if ((ahd->flags & AHD_HP_BOARD) != 0) {
5214 if ((ahd->flags & AHD_CPQ_BOARD) != 0) {
6633 for (i = 0; i < NUMDSPS; i++) {
6634 ahd_outb(ahd, DSPSELECT, i);
5215 for (i = 0; i < NUMDSPS; i++) {
5216 ahd_outb(ahd, DSPSELECT, i);
6635 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
5217 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_CPQ_DEFAULT);
6636 }
5218 }
6637#ifdef AHD_DEBUG
6638 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6639 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6640 WRTBIASCTL_HP_DEFAULT);
6641#endif
6642 }
6643 ahd_setup_iocell_workaround(ahd);
6644
6645 /*
6646 * Enable LQI Manager interrupts.
6647 */
6648 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6649 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6650 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6651 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6652 /*
5219 }
5220 ahd_setup_iocell_workaround(ahd);
5221
5222 /*
5223 * Enable LQI Manager interrupts.
5224 */
5225 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
5226 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
5227 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
5228 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
5229 /*
6653 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6654 * manually for the command phase at the start of a packetized
6655 * selection case. ENLQOBUSFREE should be made redundant by
6656 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6657 * events fail to assert the BUSFREE interrupt so we must
6658 * also enable LQOBUSFREE interrupts.
5230 * An interrupt from LQOBUSFREE is made redundant by the
5231 * BUSFREE interrupt. We choose to have the sequencer catch
5232 * LQOPHCHGINPKT errors manually for the command phase at the
5233 * start of a packetized selection case.
5234 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT);
6659 */
5235 */
6660 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
5236 ahd_outb(ahd, LQOMODE1, 0);
6661
6662 /*
5237
5238 /*
6663 * Setup sequencer interrupt handlers.
5239 * Setup sequencer interrupt handler.
6664 */
6665 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
5240 */
5241 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6666 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6667
6668 /*
6669 * Setup SCB Offset registers.
6670 */
5242
5243 /*
5244 * Setup SCB Offset registers.
5245 */
6671 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6672 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6673 pkt_long_lun));
6674 } else {
6675 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6676 }
5246 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6677 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
5247 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6678 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
5248 ahd_outb(ahd, ATTRPTR,
5249 offsetof(struct hardware_scb, task_attribute_nonpkt_tag));
6679 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6680 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6681 shared_data.idata.cdb));
6682 ahd_outb(ahd, QNEXTPTR,
6683 offsetof(struct hardware_scb, next_hscb_busaddr));
6684 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6685 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
5250 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
5251 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
5252 shared_data.idata.cdb));
5253 ahd_outb(ahd, QNEXTPTR,
5254 offsetof(struct hardware_scb, next_hscb_busaddr));
5255 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
5256 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6686 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6687 ahd_outb(ahd, LUNLEN,
6688 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6689 } else {
6690 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6691 }
5257 ahd_outb(ahd, LUNLEN, sizeof(ahd->next_queued_scb->hscb->lun) - 1);
6692 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6693 ahd_outb(ahd, MAXCMD, 0xFF);
6694 ahd_outb(ahd, SCBAUTOPTR,
6695 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6696
6697 /* We haven't been enabled for target mode yet. */
6698 ahd_outb(ahd, MULTARGID, 0);
6699 ahd_outb(ahd, MULTARGID + 1, 0);
6700
6701 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5258 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
5259 ahd_outb(ahd, MAXCMD, 0xFF);
5260 ahd_outb(ahd, SCBAUTOPTR,
5261 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
5262
5263 /* We haven't been enabled for target mode yet. */
5264 ahd_outb(ahd, MULTARGID, 0);
5265 ahd_outb(ahd, MULTARGID + 1, 0);
5266
5267 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6702 /* Initialize the negotiation table. */
6703 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6704 /*
6705 * Clear the spare bytes in the neg table to avoid
6706 * spurious parity errors.
6707 */
6708 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6709 ahd_outb(ahd, NEGOADDR, target);
6710 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6711 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6712 ahd_outb(ahd, ANNEXDAT, 0);
6713 }
6714 }
5268 /*
5269 * Clear the spare bytes in the neg table to avoid
5270 * spurious parity errors.
5271 */
6715 for (target = 0; target < AHD_NUM_TARGETS; target++) {
5272 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6716 struct ahd_devinfo devinfo;
6717 struct ahd_initiator_tinfo *tinfo;
6718 struct ahd_tmode_tstate *tstate;
6719
5273
6720 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6721 target, &tstate);
6722 ahd_compile_devinfo(&devinfo, ahd->our_id,
6723 target, CAM_LUN_WILDCARD,
6724 'A', ROLE_INITIATOR);
6725 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
5274 ahd_outb(ahd, NEGOADDR, target);
5275 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP);
5276 for (i = 0; i < AHD_NUM_ANNEXCOLS; i++)
5277 ahd_outb(ahd, ANNEXDAT, 0);
6726 }
5278 }
6727
6728 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
5279 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6729 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6730
5280
6731#ifdef NEEDS_MORE_TESTING
6732 /*
6733 * Always enable abort on incoming L_Qs if this feature is
6734 * supported. We use this to catch invalid SCB references.
6735 */
6736 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6737 ahd_outb(ahd, LQCTL1, ABORTPENDING);
6738 else
5281 /*
5282 * Always enable abort on incoming L_Qs if this feature is
5283 * supported. We use this to catch invalid SCB references.
5284 */
5285 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
5286 ahd_outb(ahd, LQCTL1, ABORTPENDING);
5287 else
6739#endif
6740 ahd_outb(ahd, LQCTL1, 0);
6741
6742 /* All of our queues are empty */
6743 ahd->qoutfifonext = 0;
5288 ahd_outb(ahd, LQCTL1, 0);
5289
5290 /* All of our queues are empty */
5291 ahd->qoutfifonext = 0;
6744 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
6745 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
6746 for (i = 0; i < AHD_QOUT_SIZE; i++)
5292 for (i = 0; i < AHD_QOUT_SIZE; i++)
6747 ahd->qoutfifo[i].valid_tag = 0;
5293 ahd->qoutfifo[i] = SCB_LIST_NULL_LE;
6748 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6749
6750 ahd->qinfifonext = 0;
6751 for (i = 0; i < AHD_QIN_SIZE; i++)
6752 ahd->qinfifo[i] = SCB_LIST_NULL;
6753
6754 if ((ahd->features & AHD_TARGETMODE) != 0) {
6755 /* All target command blocks start out invalid. */

--- 7 unchanged lines hidden (view full) ---

6763
6764 /* Initialize Scratch Ram. */
6765 ahd_outb(ahd, SEQ_FLAGS, 0);
6766 ahd_outb(ahd, SEQ_FLAGS2, 0);
6767
6768 /* We don't have any waiting selections */
6769 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6770 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
5294 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
5295
5296 ahd->qinfifonext = 0;
5297 for (i = 0; i < AHD_QIN_SIZE; i++)
5298 ahd->qinfifo[i] = SCB_LIST_NULL;
5299
5300 if ((ahd->features & AHD_TARGETMODE) != 0) {
5301 /* All target command blocks start out invalid. */

--- 7 unchanged lines hidden (view full) ---

5309
5310 /* Initialize Scratch Ram. */
5311 ahd_outb(ahd, SEQ_FLAGS, 0);
5312 ahd_outb(ahd, SEQ_FLAGS2, 0);
5313
5314 /* We don't have any waiting selections */
5315 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
5316 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6771 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
6772 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
6773 for (i = 0; i < AHD_NUM_TARGETS; i++)
6774 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6775
6776 /*
6777 * Nobody is waiting to be DMAed into the QOUTFIFO.
6778 */
6779 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6780 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6781 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
5317 for (i = 0; i < AHD_NUM_TARGETS; i++)
5318 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
5319
5320 /*
5321 * Nobody is waiting to be DMAed into the QOUTFIFO.
5322 */
5323 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
5324 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
5325 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6782 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
6783 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
6784
6785 /*
6786 * The Freeze Count is 0.
6787 */
5326
5327 /*
5328 * The Freeze Count is 0.
5329 */
6788 ahd->qfreeze_cnt = 0;
6789 ahd_outw(ahd, QFREEZE_COUNT, 0);
5330 ahd_outw(ahd, QFREEZE_COUNT, 0);
6790 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
6791
6792 /*
6793 * Tell the sequencer where it can find our arrays in memory.
6794 */
5331
5332 /*
5333 * Tell the sequencer where it can find our arrays in memory.
5334 */
6795 busaddr = ahd->shared_data_map.busaddr;
6796 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
6797 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
5335 busaddr = ahd->shared_data_busaddr;
5336 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF);
5337 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF);
5338 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF);
5339 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF);
5340 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF);
5341 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF);
5342 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF);
5343 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF);
6798
6799 /*
6800 * Setup the allowed SCSI Sequences based on operational mode.
6801 * If we are a target, we'll enable select in operations once
6802 * we've had a lun enabled.
6803 */
6804 scsiseq_template = ENAUTOATNP;
6805 if ((ahd->flags & AHD_INITIATORROLE) != 0)

--- 4 unchanged lines hidden (view full) ---

6810 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6811 int lun;
6812
6813 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6814 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6815 }
6816
6817 /*
5344
5345 /*
5346 * Setup the allowed SCSI Sequences based on operational mode.
5347 * If we are a target, we'll enable select in operations once
5348 * we've had a lun enabled.
5349 */
5350 scsiseq_template = ENAUTOATNP;
5351 if ((ahd->flags & AHD_INITIATORROLE) != 0)

--- 4 unchanged lines hidden (view full) ---

5356 for (target = 0; target < AHD_NUM_TARGETS; target++) {
5357 int lun;
5358
5359 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
5360 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
5361 }
5362
5363 /*
5364 * Always enable abort on incoming L_Qs if this feature is
5365 * supported. We use this to catch invalid SCB references.
5366 */
5367 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
5368 ahd_outb(ahd, LQCTL1, ABORTPENDING);
5369 else
5370 ahd_outb(ahd, LQCTL1, 0);
5371
5372 /*
6818 * Initialize the group code to command length table.
6819 * Vendor Unique codes are set to 0 so we only capture
6820 * the first byte of the cdb. These can be overridden
6821 * when target mode is enabled.
6822 */
6823 ahd_outb(ahd, CMDSIZE_TABLE, 5);
6824 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6825 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);

--- 11 unchanged lines hidden (view full) ---

6837 ahd_set_hescb_qoff(ahd, 0);
6838 ahd_set_snscb_qoff(ahd, 0);
6839 ahd_set_sescb_qoff(ahd, 0);
6840 ahd_set_sdscb_qoff(ahd, 0);
6841
6842 /*
6843 * Tell the sequencer which SCB will be the next one it receives.
6844 */
5373 * Initialize the group code to command length table.
5374 * Vendor Unique codes are set to 0 so we only capture
5375 * the first byte of the cdb. These can be overridden
5376 * when target mode is enabled.
5377 */
5378 ahd_outb(ahd, CMDSIZE_TABLE, 5);
5379 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
5380 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);

--- 11 unchanged lines hidden (view full) ---

5392 ahd_set_hescb_qoff(ahd, 0);
5393 ahd_set_snscb_qoff(ahd, 0);
5394 ahd_set_sescb_qoff(ahd, 0);
5395 ahd_set_sdscb_qoff(ahd, 0);
5396
5397 /*
5398 * Tell the sequencer which SCB will be the next one it receives.
5399 */
6845 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6846 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6847
6848 /*
6849 * Default to coalescing disabled.
6850 */
6851 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6852 ahd_outw(ahd, CMDS_PENDING, 0);
6853 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6854 ahd->int_coalescing_maxcmds,
6855 ahd->int_coalescing_mincmds);
6856 ahd_enable_coalescing(ahd, FALSE);
6857
5400 busaddr = ahd_le32toh(ahd->next_queued_scb->hscb->hscb_busaddr);
5401 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF);
5402 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF);
5403 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF);
5404 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF);
6858 ahd_loadseq(ahd);
6859 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6860}
6861
6862/*
6863 * Setup default device and controller settings.
6864 * This should only be called if our probe has
6865 * determined that no configuration data is available.

--- 8 unchanged lines hidden (view full) ---

6874 /*
6875 * Allocate a tstate to house information for our
6876 * initiator presence on the bus as well as the user
6877 * data for any target mode initiator.
6878 */
6879 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6880 printf("%s: unable to allocate ahd_tmode_tstate. "
6881 "Failing attach\n", ahd_name(ahd));
5405 ahd_loadseq(ahd);
5406 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5407}
5408
5409/*
5410 * Setup default device and controller settings.
5411 * This should only be called if our probe has
5412 * determined that no configuration data is available.

--- 8 unchanged lines hidden (view full) ---

5421 /*
5422 * Allocate a tstate to house information for our
5423 * initiator presence on the bus as well as the user
5424 * data for any target mode initiator.
5425 */
5426 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
5427 printf("%s: unable to allocate ahd_tmode_tstate. "
5428 "Failing attach\n", ahd_name(ahd));
6882 AHD_FATAL_ERROR(ahd);
6883 return (ENOMEM);
6884 }
6885
6886 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6887 struct ahd_devinfo devinfo;
6888 struct ahd_initiator_tinfo *tinfo;
6889 struct ahd_tmode_tstate *tstate;
6890 uint16_t target_mask;
6891
5429 return (ENOMEM);
5430 }
5431
5432 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
5433 struct ahd_devinfo devinfo;
5434 struct ahd_initiator_tinfo *tinfo;
5435 struct ahd_tmode_tstate *tstate;
5436 uint16_t target_mask;
5437
5438 TAILQ_INIT(&ahd->untagged_queues[targ]);
6892 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6893 targ, &tstate);
6894 /*
6895 * We support SPC2 and SPI4.
6896 */
6897 tinfo->user.protocol_version = 4;
6898 tinfo->user.transport_version = 4;
6899
6900 target_mask = 0x01 << targ;
6901 ahd->user_discenable |= target_mask;
6902 tstate->discenable |= target_mask;
6903 ahd->user_tagenable |= target_mask;
6904#ifdef AHD_FORCE_160
6905 tinfo->user.period = AHD_SYNCRATE_DT;
6906#else
6907 tinfo->user.period = AHD_SYNCRATE_160;
6908#endif
5439 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
5440 targ, &tstate);
5441 /*
5442 * We support SPC2 and SPI4.
5443 */
5444 tinfo->user.protocol_version = 4;
5445 tinfo->user.transport_version = 4;
5446
5447 target_mask = 0x01 << targ;
5448 ahd->user_discenable |= target_mask;
5449 tstate->discenable |= target_mask;
5450 ahd->user_tagenable |= target_mask;
5451#ifdef AHD_FORCE_160
5452 tinfo->user.period = AHD_SYNCRATE_DT;
5453#else
5454 tinfo->user.period = AHD_SYNCRATE_160;
5455#endif
6909 tinfo->user.offset = MAX_OFFSET;
5456 tinfo->user.offset= ~0;
6910 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6911 | MSG_EXT_PPR_WR_FLOW
5457 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
5458 | MSG_EXT_PPR_WR_FLOW
6912 | MSG_EXT_PPR_HOLD_MCS
6913 | MSG_EXT_PPR_IU_REQ
6914 | MSG_EXT_PPR_QAS_REQ
6915 | MSG_EXT_PPR_DT_REQ;
5459 | MSG_EXT_PPR_IU_REQ
5460 | MSG_EXT_PPR_QAS_REQ
5461 | MSG_EXT_PPR_DT_REQ;
6916 if ((ahd->features & AHD_RTI) != 0)
6917 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6918
6919 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6920
6921 /*
6922 * Start out Async/Narrow/Untagged and with
6923 * conservative protocol support.
6924 */
6925 tinfo->goal.protocol_version = 2;

--- 4 unchanged lines hidden (view full) ---

6930 targ, CAM_LUN_WILDCARD,
6931 'A', ROLE_INITIATOR);
6932 tstate->tagenable &= ~target_mask;
6933 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6934 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6935 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6936 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6937 /*paused*/TRUE);
5462
5463 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5464
5465 /*
5466 * Start out Async/Narrow/Untagged and with
5467 * conservative protocol support.
5468 */
5469 tinfo->goal.protocol_version = 2;

--- 4 unchanged lines hidden (view full) ---

5474 targ, CAM_LUN_WILDCARD,
5475 'A', ROLE_INITIATOR);
5476 tstate->tagenable &= ~target_mask;
5477 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5478 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
5479 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
5480 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
5481 /*paused*/TRUE);
5482 /*
5483 * The neg table must be initialized even if the
5484 * new settings above are the same as those from
5485 * when our xfer info data structures were allocated
5486 * and initialized.
5487 */
5488 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6938 }
6939 return (0);
6940}
6941
6942/*
6943 * Parse device configuration information.
6944 */
6945int

--- 8 unchanged lines hidden (view full) ---

6954 /*
6955 * Allocate a tstate to house information for our
6956 * initiator presence on the bus as well as the user
6957 * data for any target mode initiator.
6958 */
6959 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6960 printf("%s: unable to allocate ahd_tmode_tstate. "
6961 "Failing attach\n", ahd_name(ahd));
5489 }
5490 return (0);
5491}
5492
5493/*
5494 * Parse device configuration information.
5495 */
5496int

--- 8 unchanged lines hidden (view full) ---

5505 /*
5506 * Allocate a tstate to house information for our
5507 * initiator presence on the bus as well as the user
5508 * data for any target mode initiator.
5509 */
5510 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
5511 printf("%s: unable to allocate ahd_tmode_tstate. "
5512 "Failing attach\n", ahd_name(ahd));
6962 AHD_FATAL_ERROR(ahd);
6963 return (ENOMEM);
6964 }
6965
6966 for (targ = 0; targ < max_targ; targ++) {
6967 struct ahd_devinfo devinfo;
6968 struct ahd_initiator_tinfo *tinfo;
6969 struct ahd_transinfo *user_tinfo;
6970 struct ahd_tmode_tstate *tstate;

--- 27 unchanged lines hidden (view full) ---

6998 user_tinfo->ppr_options = 0;
6999 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
7000 if (user_tinfo->period < CFXFER_ASYNC) {
7001 if (user_tinfo->period <= AHD_PERIOD_10MHz)
7002 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
7003 user_tinfo->offset = MAX_OFFSET;
7004 } else {
7005 user_tinfo->offset = 0;
5513 return (ENOMEM);
5514 }
5515
5516 for (targ = 0; targ < max_targ; targ++) {
5517 struct ahd_devinfo devinfo;
5518 struct ahd_initiator_tinfo *tinfo;
5519 struct ahd_transinfo *user_tinfo;
5520 struct ahd_tmode_tstate *tstate;

--- 27 unchanged lines hidden (view full) ---

5548 user_tinfo->ppr_options = 0;
5549 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
5550 if (user_tinfo->period < CFXFER_ASYNC) {
5551 if (user_tinfo->period <= AHD_PERIOD_10MHz)
5552 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
5553 user_tinfo->offset = MAX_OFFSET;
5554 } else {
5555 user_tinfo->offset = 0;
7006 user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
5556 user_tinfo->period = AHD_PERIOD_ASYNC;
7007 }
7008#ifdef AHD_FORCE_160
7009 if (user_tinfo->period <= AHD_SYNCRATE_160)
7010 user_tinfo->period = AHD_SYNCRATE_DT;
7011#endif
7012
5557 }
5558#ifdef AHD_FORCE_160
5559 if (user_tinfo->period <= AHD_SYNCRATE_160)
5560 user_tinfo->period = AHD_SYNCRATE_DT;
5561#endif
5562
7013 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
5563 if ((sc->device_flags[targ] & CFPACKETIZED) != 0)
7014 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
7015 | MSG_EXT_PPR_WR_FLOW
5564 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
5565 | MSG_EXT_PPR_WR_FLOW
7016 | MSG_EXT_PPR_HOLD_MCS
7017 | MSG_EXT_PPR_IU_REQ;
5566 | MSG_EXT_PPR_IU_REQ;
7018 if ((ahd->features & AHD_RTI) != 0)
7019 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
7020 }
7021
7022 if ((sc->device_flags[targ] & CFQAS) != 0)
7023 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
7024
7025 if ((sc->device_flags[targ] & CFWIDEB) != 0)
7026 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
7027 else
7028 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;

--- 15 unchanged lines hidden (view full) ---

7044 ahd_compile_devinfo(&devinfo, ahd->our_id,
7045 targ, CAM_LUN_WILDCARD,
7046 'A', ROLE_INITIATOR);
7047 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7048 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
7049 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
7050 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
7051 /*paused*/TRUE);
5567
5568 if ((sc->device_flags[targ] & CFQAS) != 0)
5569 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
5570
5571 if ((sc->device_flags[targ] & CFWIDEB) != 0)
5572 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
5573 else
5574 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;

--- 15 unchanged lines hidden (view full) ---

5590 ahd_compile_devinfo(&devinfo, ahd->our_id,
5591 targ, CAM_LUN_WILDCARD,
5592 'A', ROLE_INITIATOR);
5593 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5594 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
5595 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
5596 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
5597 /*paused*/TRUE);
5598 /*
5599 * The neg table must be initialized even if the
5600 * new settings above are the same as those from
5601 * when our xfer info data structures were allocated
5602 * and initialized.
5603 */
5604 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
7052 }
7053
7054 ahd->flags &= ~AHD_SPCHK_ENB_A;
7055 if (sc->bios_control & CFSPARITY)
7056 ahd->flags |= AHD_SPCHK_ENB_A;
7057
7058 ahd->flags &= ~AHD_RESET_BUS_A;
7059 if (sc->bios_control & CFRESETB)

--- 9 unchanged lines hidden (view full) ---

7069
7070 ahd->flags &= ~AHD_STPWLEVEL_A;
7071 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
7072 ahd->flags |= AHD_STPWLEVEL_A;
7073
7074 return (0);
7075}
7076
5605 }
5606
5607 ahd->flags &= ~AHD_SPCHK_ENB_A;
5608 if (sc->bios_control & CFSPARITY)
5609 ahd->flags |= AHD_SPCHK_ENB_A;
5610
5611 ahd->flags &= ~AHD_RESET_BUS_A;
5612 if (sc->bios_control & CFRESETB)

--- 9 unchanged lines hidden (view full) ---

5622
5623 ahd->flags &= ~AHD_STPWLEVEL_A;
5624 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
5625 ahd->flags |= AHD_STPWLEVEL_A;
5626
5627 return (0);
5628}
5629
7077/*
7078 * Parse device configuration information.
7079 */
7080int
7081ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
7082{
7083 int error;
7084
7085 error = ahd_verify_vpd_cksum(vpd);
7086 if (error == 0)
7087 return (EINVAL);
7088 if ((vpd->bios_flags & VPDBOOTHOST) != 0)
7089 ahd->flags |= AHD_BOOT_CHANNEL;
7090 return (0);
7091}
7092
7093void
7094ahd_intr_enable(struct ahd_softc *ahd, int enable)
7095{
7096 u_int hcntrl;
7097
7098 hcntrl = ahd_inb(ahd, HCNTRL);
7099 hcntrl &= ~INTEN;
7100 ahd->pause &= ~INTEN;
7101 ahd->unpause &= ~INTEN;
7102 if (enable) {
7103 hcntrl |= INTEN;
7104 ahd->pause |= INTEN;
7105 ahd->unpause |= INTEN;
7106 }
7107 ahd_outb(ahd, HCNTRL, hcntrl);
7108}
7109
5630void
5631ahd_intr_enable(struct ahd_softc *ahd, int enable)
5632{
5633 u_int hcntrl;
5634
5635 hcntrl = ahd_inb(ahd, HCNTRL);
5636 hcntrl &= ~INTEN;
5637 ahd->pause &= ~INTEN;
5638 ahd->unpause &= ~INTEN;
5639 if (enable) {
5640 hcntrl |= INTEN;
5641 ahd->pause |= INTEN;
5642 ahd->unpause |= INTEN;
5643 }
5644 ahd_outb(ahd, HCNTRL, hcntrl);
5645}
5646
7110void
7111ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
7112 u_int mincmds)
7113{
7114 if (timer > AHD_TIMER_MAX_US)
7115 timer = AHD_TIMER_MAX_US;
7116 ahd->int_coalescing_timer = timer;
7117
7118 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
7119 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
7120 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
7121 mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
7122 ahd->int_coalescing_maxcmds = maxcmds;
7123 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
7124 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
7125 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
7126}
7127
7128void
7129ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
7130{
7131
7132 ahd->hs_mailbox &= ~ENINT_COALESCE;
7133 if (enable)
7134 ahd->hs_mailbox |= ENINT_COALESCE;
7135 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
7136 ahd_flush_device_writes(ahd);
7137 ahd_run_qoutfifo(ahd);
7138}
7139
7140/*
7141 * Ensure that the card is paused in a location
7142 * outside of all critical sections and that all
7143 * pending work is completed prior to returning.
7144 * This routine should only be called from outside
7145 * an interrupt context.
7146 */
7147void
7148ahd_pause_and_flushwork(struct ahd_softc *ahd)
7149{
5647/*
5648 * Ensure that the card is paused in a location
5649 * outside of all critical sections and that all
5650 * pending work is completed prior to returning.
5651 * This routine should only be called from outside
5652 * an interrupt context.
5653 */
5654void
5655ahd_pause_and_flushwork(struct ahd_softc *ahd)
5656{
7150 u_int intstat;
7151 u_int maxloops;
5657 int intstat;
5658 int maxloops;
7152
7153 maxloops = 1000;
7154 ahd->flags |= AHD_ALL_INTERRUPTS;
5659
5660 maxloops = 1000;
5661 ahd->flags |= AHD_ALL_INTERRUPTS;
7155 ahd_pause(ahd);
7156 /*
7157 * Freeze the outgoing selections. We do this only
7158 * until we are safely paused without further selections
7159 * pending.
7160 */
7161 ahd->qfreeze_cnt--;
7162 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7163 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
5662 intstat = 0;
7164 do {
5663 do {
7165
7166 ahd_unpause(ahd);
7167 /*
7168 * Give the sequencer some time to service
7169 * any active selections.
7170 */
7171 aic_delay(500);
7172
7173 ahd_intr(ahd);
7174 ahd_pause(ahd);
5664 ahd_intr(ahd);
5665 ahd_pause(ahd);
7175 intstat = ahd_inb(ahd, INTSTAT);
7176 if ((intstat & INT_PEND) == 0) {
7177 ahd_clear_critical_section(ahd);
7178 intstat = ahd_inb(ahd, INTSTAT);
7179 }
7180 } while (--maxloops
7181 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
7182 && ((intstat & INT_PEND) != 0
7183 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
7184 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
7185
5666 ahd_clear_critical_section(ahd);
5667 if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0)
5668 break;
5669 maxloops--;
5670 } while (((intstat = ahd_inb(ahd, INTSTAT)) & INT_PEND) && --maxloops);
7186 if (maxloops == 0) {
7187 printf("Infinite interrupt loop, INTSTAT = %x",
7188 ahd_inb(ahd, INTSTAT));
5671 if (maxloops == 0) {
5672 printf("Infinite interrupt loop, INTSTAT = %x",
5673 ahd_inb(ahd, INTSTAT));
7189 AHD_FATAL_ERROR(ahd);
7190 }
5674 }
7191 ahd->qfreeze_cnt++;
7192 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7193
7194 ahd_flush_qoutfifo(ahd);
7195
7196 ahd_platform_flushwork(ahd);
7197 ahd->flags &= ~AHD_ALL_INTERRUPTS;
7198}
7199
7200int
7201ahd_suspend(struct ahd_softc *ahd)
7202{
5675 ahd_platform_flushwork(ahd);
5676 ahd->flags &= ~AHD_ALL_INTERRUPTS;
5677}
5678
5679int
5680ahd_suspend(struct ahd_softc *ahd)
5681{
5682#if 0
5683 uint8_t *ptr;
5684 int i;
7203
7204 ahd_pause_and_flushwork(ahd);
7205
5685
5686 ahd_pause_and_flushwork(ahd);
5687
7206 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7207 ahd_unpause(ahd);
5688 if (LIST_FIRST(&ahd->pending_scbs) != NULL)
7208 return (EBUSY);
5689 return (EBUSY);
5690
5691#if AHD_TARGET_MODE
5692 /*
5693 * XXX What about ATIOs that have not yet been serviced?
5694 * Perhaps we should just refuse to be suspended if we
5695 * are acting in a target role.
5696 */
5697 if (ahd->pending_device != NULL)
5698 return (EBUSY);
5699#endif
5700
5701 /* Save volatile registers */
5702 ahd->suspend_state.channel[0].scsiseq = ahd_inb(ahd, SCSISEQ0);
5703 ahd->suspend_state.channel[0].sxfrctl0 = ahd_inb(ahd, SXFRCTL0);
5704 ahd->suspend_state.channel[0].sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5705 ahd->suspend_state.channel[0].simode0 = ahd_inb(ahd, SIMODE0);
5706 ahd->suspend_state.channel[0].simode1 = ahd_inb(ahd, SIMODE1);
5707 ahd->suspend_state.channel[0].seltimer = ahd_inb(ahd, SELTIMER);
5708 ahd->suspend_state.channel[0].seqctl = ahd_inb(ahd, SEQCTL0);
5709 ahd->suspend_state.dscommand0 = ahd_inb(ahd, DSCOMMAND0);
5710 ahd->suspend_state.dspcistatus = ahd_inb(ahd, DSPCISTATUS);
5711
5712 if ((ahd->features & AHD_DT) != 0) {
5713 u_int sfunct;
5714
5715 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE;
5716 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE);
5717 ahd->suspend_state.optionmode = ahd_inb(ahd, OPTIONMODE);
5718 ahd_outb(ahd, SFUNCT, sfunct);
5719 ahd->suspend_state.crccontrol1 = ahd_inb(ahd, CRCCONTROL1);
7209 }
5720 }
5721
5722 if ((ahd->features & AHD_MULTI_FUNC) != 0)
5723 ahd->suspend_state.scbbaddr = ahd_inb(ahd, SCBBADDR);
5724
5725 if ((ahd->features & AHD_ULTRA2) != 0)
5726 ahd->suspend_state.dff_thrsh = ahd_inb(ahd, DFF_THRSH);
5727
5728 ptr = ahd->suspend_state.scratch_ram;
5729 for (i = 0; i < 64; i++)
5730 *ptr++ = ahd_inb(ahd, SRAM_BASE + i);
5731
5732 if ((ahd->features & AHD_MORE_SRAM) != 0) {
5733 for (i = 0; i < 16; i++)
5734 *ptr++ = ahd_inb(ahd, TARG_OFFSET + i);
5735 }
5736
5737 ptr = ahd->suspend_state.btt;
5738 for (i = 0;i < AHD_NUM_TARGETS; i++) {
5739 int j;
5740
5741 for (j = 0;j < AHD_NUM_LUNS; j++) {
5742 u_int tcl;
5743
5744 tcl = BUILD_TCL(i << 4, j);
5745 *ptr = ahd_find_busy_tcl(ahd, tcl);
5746 }
5747 }
7210 ahd_shutdown(ahd);
5748 ahd_shutdown(ahd);
5749#endif
7211 return (0);
7212}
7213
7214int
7215ahd_resume(struct ahd_softc *ahd)
7216{
5750 return (0);
5751}
5752
5753int
5754ahd_resume(struct ahd_softc *ahd)
5755{
5756#if 0
5757 uint8_t *ptr;
5758 int i;
7217
5759
7218 ahd_reset(ahd, /*reinit*/TRUE);
7219 ahd_intr_enable(ahd, TRUE);
7220 ahd_restart(ahd);
5760 ahd_reset(ahd);
5761
5762 ahd_build_free_scb_list(ahd);
5763
5764 /* Restore volatile registers */
5765 ahd_outb(ahd, SCSISEQ0, ahd->suspend_state.channel[0].scsiseq);
5766 ahd_outb(ahd, SXFRCTL0, ahd->suspend_state.channel[0].sxfrctl0);
5767 ahd_outb(ahd, SXFRCTL1, ahd->suspend_state.channel[0].sxfrctl1);
5768 ahd_outb(ahd, SIMODE0, ahd->suspend_state.channel[0].simode0);
5769 ahd_outb(ahd, SIMODE1, ahd->suspend_state.channel[0].simode1);
5770 ahd_outb(ahd, SELTIMER, ahd->suspend_state.channel[0].seltimer);
5771 ahd_outb(ahd, SEQCTL0, ahd->suspend_state.channel[0].seqctl);
5772 if ((ahd->features & AHD_ULTRA2) != 0)
5773 ahd_outb(ahd, SCSIID_ULTRA2, ahd->our_id);
5774 else
5775 ahd_outb(ahd, SCSIID, ahd->our_id);
5776
5777 ahd_outb(ahd, DSCOMMAND0, ahd->suspend_state.dscommand0);
5778 ahd_outb(ahd, DSPCISTATUS, ahd->suspend_state.dspcistatus);
5779
5780 if ((ahd->features & AHD_DT) != 0) {
5781 u_int sfunct;
5782
5783 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE;
5784 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE);
5785 ahd_outb(ahd, OPTIONMODE, ahd->suspend_state.optionmode);
5786 ahd_outb(ahd, SFUNCT, sfunct);
5787 ahd_outb(ahd, CRCCONTROL1, ahd->suspend_state.crccontrol1);
5788 }
5789
5790 if ((ahd->features & AHD_MULTI_FUNC) != 0)
5791 ahd_outb(ahd, SCBBADDR, ahd->suspend_state.scbbaddr);
5792
5793 if ((ahd->features & AHD_ULTRA2) != 0)
5794 ahd_outb(ahd, DFF_THRSH, ahd->suspend_state.dff_thrsh);
5795
5796 ptr = ahd->suspend_state.scratch_ram;
5797 for (i = 0; i < 64; i++)
5798 ahd_outb(ahd, SRAM_BASE + i, *ptr++);
5799
5800 if ((ahd->features & AHD_MORE_SRAM) != 0) {
5801 for (i = 0; i < 16; i++)
5802 ahd_outb(ahd, TARG_OFFSET + i, *ptr++);
5803 }
5804
5805 ptr = ahd->suspend_state.btt;
5806 for (i = 0;i < AHD_NUM_TARGETS; i++) {
5807 int j;
5808
5809 for (j = 0;j < AHD_NUM_LUNS; j++) {
5810 u_int tcl;
5811
5812 tcl = BUILD_TCL(i << 4, j);
5813 ahd_busy_tcl(ahd, tcl, *ptr);
5814 }
5815 }
5816#endif
7221 return (0);
7222}
7223
7224/************************** Busy Target Table *********************************/
7225/*
7226 * Set SCBPTR to the SCB that contains the busy
7227 * table entry for TCL. Return the offset into
7228 * the SCB that contains the entry for TCL.
7229 * saved_scbid is dereferenced and set to the
7230 * scbid that should be restored once manipualtion
7231 * of the TCL entry is complete.
7232 */
7233static __inline u_int
7234ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
7235{
5817 return (0);
5818}
5819
5820/************************** Busy Target Table *********************************/
5821/*
5822 * Set SCBPTR to the SCB that contains the busy
5823 * table entry for TCL. Return the offset into
5824 * the SCB that contains the entry for TCL.
5825 * saved_scbid is dereferenced and set to the
5826 * scbid that should be restored once manipualtion
5827 * of the TCL entry is complete.
5828 */
5829static __inline u_int
5830ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
5831{
5832
5833 *saved_scbid = ahd_get_scbptr(ahd);
5834
7236 /*
7237 * Index to the SCB that contains the busy entry.
7238 */
5835 /*
5836 * Index to the SCB that contains the busy entry.
5837 */
7239 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7240 *saved_scbid = ahd_get_scbptr(ahd);
7241 ahd_set_scbptr(ahd, TCL_LUN(tcl)
5838 ahd_set_scbptr(ahd, TCL_LUN(tcl)
7242 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
5839 | ((TCL_TARGET_OFFSET(tcl) & ~0x7) << 5));
7243
7244 /*
7245 * And now calculate the SCB offset to the entry.
7246 * Each entry is 2 bytes wide, hence the
7247 * multiplication by 2.
7248 */
5840
5841 /*
5842 * And now calculate the SCB offset to the entry.
5843 * Each entry is 2 bytes wide, hence the
5844 * multiplication by 2.
5845 */
7249 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
5846 return (((TCL_TARGET_OFFSET(tcl) & 0x7) << 1) + SCB_DISCONNECTED_LISTS);
7250}
7251
7252/*
7253 * Return the untagged transaction id for a given target/channel lun.
5847}
5848
5849/*
5850 * Return the untagged transaction id for a given target/channel lun.
5851 * Optionally, clear the entry.
7254 */
7255u_int
7256ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
7257{
7258 u_int scbid;
7259 u_int scb_offset;
7260 u_int saved_scbptr;
7261

--- 9 unchanged lines hidden (view full) ---

7271 u_int scb_offset;
7272 u_int saved_scbptr;
7273
7274 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7275 ahd_outw(ahd, scb_offset, scbid);
7276 ahd_set_scbptr(ahd, saved_scbptr);
7277}
7278
5852 */
5853u_int
5854ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
5855{
5856 u_int scbid;
5857 u_int scb_offset;
5858 u_int saved_scbptr;
5859

--- 9 unchanged lines hidden (view full) ---

5869 u_int scb_offset;
5870 u_int saved_scbptr;
5871
5872 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
5873 ahd_outw(ahd, scb_offset, scbid);
5874 ahd_set_scbptr(ahd, saved_scbptr);
5875}
5876
5877void
5878ahd_set_disconnected_list(struct ahd_softc *ahd, u_int target,
5879 u_int lun, u_int scbid)
5880{
5881 u_int saved_scbptr;
5882
5883 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5884 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5885 saved_scbptr = ahd_get_scbptr(ahd);
5886 ahd_set_scbptr(ahd, lun | ((target & 0x8) << 5));
5887 ahd_outw(ahd, SCB_DISCONNECTED_LISTS + ((target & 0x7) << 1), scbid);
5888 ahd_set_scbptr(ahd, saved_scbptr);
5889}
5890
7279/************************** SCB and SCB queue management **********************/
7280int
7281ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
7282 char channel, int lun, u_int tag, role_t role)
7283{
7284 int targ = SCB_GET_TARGET(ahd, scb);
7285 char chan = SCB_GET_CHANNEL(ahd, scb);
7286 int slun = SCB_GET_LUN(scb);
7287 int match;
7288
7289 match = ((chan == channel) || (channel == ALL_CHANNELS));
7290 if (match != 0)
7291 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
7292 if (match != 0)
7293 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
7294 if (match != 0) {
5891/************************** SCB and SCB queue management **********************/
5892int
5893ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
5894 char channel, int lun, u_int tag, role_t role)
5895{
5896 int targ = SCB_GET_TARGET(ahd, scb);
5897 char chan = SCB_GET_CHANNEL(ahd, scb);
5898 int slun = SCB_GET_LUN(scb);
5899 int match;
5900
5901 match = ((chan == channel) || (channel == ALL_CHANNELS));
5902 if (match != 0)
5903 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5904 if (match != 0)
5905 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5906 if (match != 0) {
7295#ifdef AHD_TARGET_MODE
5907#if AHD_TARGET_MODE
7296 int group;
7297
7298 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
7299 if (role == ROLE_INITIATOR) {
7300 match = (group != XPT_FC_GROUP_TMODE)
7301 && ((tag == SCB_GET_TAG(scb))
7302 || (tag == SCB_LIST_NULL));
7303 } else if (role == ROLE_TARGET) {

--- 25 unchanged lines hidden (view full) ---

7329 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7330
7331 ahd_platform_freeze_devq(ahd, scb);
7332}
7333
7334void
7335ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
7336{
5908 int group;
5909
5910 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5911 if (role == ROLE_INITIATOR) {
5912 match = (group != XPT_FC_GROUP_TMODE)
5913 && ((tag == SCB_GET_TAG(scb))
5914 || (tag == SCB_LIST_NULL));
5915 } else if (role == ROLE_TARGET) {

--- 25 unchanged lines hidden (view full) ---

5941 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5942
5943 ahd_platform_freeze_devq(ahd, scb);
5944}
5945
5946void
5947ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
5948{
7337 struct scb *prev_scb;
7338 ahd_mode_state saved_modes;
5949 struct scb *prev_scb;
7339
5950
7340 saved_modes = ahd_save_modes(ahd);
7341 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7342 prev_scb = NULL;
7343 if (ahd_qinfifo_count(ahd) != 0) {
7344 u_int prev_tag;
7345 u_int prev_pos;
7346
7347 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7348 prev_tag = ahd->qinfifo[prev_pos];
7349 prev_scb = ahd_lookup_scb(ahd, prev_tag);
7350 }
7351 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7352 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
5951 prev_scb = NULL;
5952 if (ahd_qinfifo_count(ahd) != 0) {
5953 u_int prev_tag;
5954 u_int prev_pos;
5955
5956 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
5957 prev_tag = ahd->qinfifo[prev_pos];
5958 prev_scb = ahd_lookup_scb(ahd, prev_tag);
5959 }
5960 ahd_qinfifo_requeue(ahd, prev_scb, scb);
5961 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7353 ahd_restore_modes(ahd, saved_modes);
7354}
7355
7356static void
7357ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7358 struct scb *scb)
7359{
7360 if (prev_scb == NULL) {
7361 uint32_t busaddr;
7362
5962}
5963
5964static void
5965ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
5966 struct scb *scb)
5967{
5968 if (prev_scb == NULL) {
5969 uint32_t busaddr;
5970
7363 busaddr = aic_le32toh(scb->hscb->hscb_busaddr);
7364 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
5971 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr);
5972 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF);
5973 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF);
5974 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF);
5975 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF);
7365 } else {
7366 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7367 ahd_sync_scb(ahd, prev_scb,
7368 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7369 }
7370 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7371 ahd->qinfifonext++;
5976 } else {
5977 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
5978 ahd_sync_scb(ahd, prev_scb,
5979 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5980 }
5981 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
5982 ahd->qinfifonext++;
7372 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
5983 scb->hscb->next_hscb_busaddr = ahd->next_queued_scb->hscb->hscb_busaddr;
7373 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7374}
7375
7376static int
7377ahd_qinfifo_count(struct ahd_softc *ahd)
7378{
7379 u_int qinpos;
7380 u_int wrap_qinpos;
7381 u_int wrap_qinfifonext;
7382
7383 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7384 qinpos = ahd_get_snscb_qoff(ahd);
7385 wrap_qinpos = AHD_QIN_WRAP(qinpos);
7386 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
5984 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5985}
5986
5987static int
5988ahd_qinfifo_count(struct ahd_softc *ahd)
5989{
5990 u_int qinpos;
5991 u_int wrap_qinpos;
5992 u_int wrap_qinfifonext;
5993
5994 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
5995 qinpos = ahd_get_snscb_qoff(ahd);
5996 wrap_qinpos = AHD_QIN_WRAP(qinpos);
5997 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7387 if (wrap_qinfifonext >= wrap_qinpos)
5998 if (wrap_qinfifonext > wrap_qinpos)
7388 return (wrap_qinfifonext - wrap_qinpos);
7389 else
7390 return (wrap_qinfifonext
7391 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7392}
7393
5999 return (wrap_qinfifonext - wrap_qinpos);
6000 else
6001 return (wrap_qinfifonext
6002 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
6003}
6004
7394void
7395ahd_reset_cmds_pending(struct ahd_softc *ahd)
7396{
7397 struct scb *scb;
7398 ahd_mode_state saved_modes;
7399 u_int pending_cmds;
7400
7401 saved_modes = ahd_save_modes(ahd);
7402 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7403
7404 /*
7405 * Don't count any commands as outstanding that the
7406 * sequencer has already marked for completion.
7407 */
7408 ahd_flush_qoutfifo(ahd);
7409
7410 pending_cmds = 0;
7411 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7412 pending_cmds++;
7413 }
7414 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7415 ahd_restore_modes(ahd, saved_modes);
7416 ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7417}
7418
7419void
7420ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
7421{
7422 cam_status ostat;
7423 cam_status cstat;
7424
7425 ostat = aic_get_transaction_status(scb);
7426 if (ostat == CAM_REQ_INPROG)
7427 aic_set_transaction_status(scb, status);
7428 cstat = aic_get_transaction_status(scb);
7429 if (cstat != CAM_REQ_CMP)
7430 aic_freeze_scb(scb);
7431 ahd_done(ahd, scb);
7432}
7433
7434int
7435ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7436 int lun, u_int tag, role_t role, uint32_t status,
7437 ahd_search_action action)
7438{
7439 struct scb *scb;
6005int
6006ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
6007 int lun, u_int tag, role_t role, uint32_t status,
6008 ahd_search_action action)
6009{
6010 struct scb *scb;
7440 struct scb *mk_msg_scb;
7441 struct scb *prev_scb;
7442 ahd_mode_state saved_modes;
7443 u_int qinstart;
7444 u_int qinpos;
7445 u_int qintail;
7446 u_int tid_next;
7447 u_int tid_prev;
7448 u_int scbid;
6011 struct scb *prev_scb;
6012 ahd_mode_state saved_modes;
6013 u_int qinstart;
6014 u_int qinpos;
6015 u_int qintail;
6016 u_int tid_next;
6017 u_int tid_prev;
6018 u_int scbid;
7449 u_int seq_flags2;
7450 u_int savedscbptr;
7451 uint32_t busaddr;
7452 int found;
7453 int targets;
7454
7455 /* Must be in CCHAN mode */
7456 saved_modes = ahd_save_modes(ahd);
7457 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);

--- 11 unchanged lines hidden (view full) ---

7469 }
7470 /* Determine sequencer's position in the qinfifo. */
7471 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7472 qinstart = ahd_get_snscb_qoff(ahd);
7473 qinpos = AHD_QIN_WRAP(qinstart);
7474 found = 0;
7475 prev_scb = NULL;
7476
6019 u_int savedscbptr;
6020 uint32_t busaddr;
6021 int found;
6022 int targets;
6023
6024 /* Must be in CCHAN mode */
6025 saved_modes = ahd_save_modes(ahd);
6026 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);

--- 11 unchanged lines hidden (view full) ---

6038 }
6039 /* Determine sequencer's position in the qinfifo. */
6040 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
6041 qinstart = ahd_get_snscb_qoff(ahd);
6042 qinpos = AHD_QIN_WRAP(qinstart);
6043 found = 0;
6044 prev_scb = NULL;
6045
6046 if (action == SEARCH_COMPLETE) {
6047 /*
6048 * Don't attempt to run any queued untagged transactions
6049 * until we are done with the abort process.
6050 */
6051 ahd_freeze_untagged_queues(ahd);
6052 }
6053
7477 if (action == SEARCH_PRINT) {
7478 printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7479 qinstart, ahd->qinfifonext);
7480 }
7481
7482 /*
7483 * Start with an empty queue. Entries that are not chosen
7484 * for removal will be re-added to the queue as we go.
7485 */
7486 ahd->qinfifonext = qinstart;
6054 if (action == SEARCH_PRINT) {
6055 printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
6056 qinstart, ahd->qinfifonext);
6057 }
6058
6059 /*
6060 * Start with an empty queue. Entries that are not chosen
6061 * for removal will be re-added to the queue as we go.
6062 */
6063 ahd->qinfifonext = qinstart;
7487 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7488 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6064 busaddr = ahd_le32toh(ahd->next_queued_scb->hscb->hscb_busaddr);
6065 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF);
6066 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF);
6067 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF);
6068 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF);
7489
7490 while (qinpos != qintail) {
7491 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7492 if (scb == NULL) {
7493 printf("qinpos = %d, SCB index = %d\n",
7494 qinpos, ahd->qinfifo[qinpos]);
6069
6070 while (qinpos != qintail) {
6071 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
6072 if (scb == NULL) {
6073 printf("qinpos = %d, SCB index = %d\n",
6074 qinpos, ahd->qinfifo[qinpos]);
7495 AHD_FATAL_ERROR(ahd);
7496 panic("Loop 1\n");
7497 }
7498
7499 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7500 /*
7501 * We found an scb that needs to be acted on.
7502 */
7503 found++;
7504 switch (action) {
7505 case SEARCH_COMPLETE:
6075 panic("Loop 1\n");
6076 }
6077
6078 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
6079 /*
6080 * We found an scb that needs to be acted on.
6081 */
6082 found++;
6083 switch (action) {
6084 case SEARCH_COMPLETE:
6085 {
6086 cam_status ostat;
6087 cam_status cstat;
6088
6089 ostat = ahd_get_transaction_status(scb);
6090 if (ostat == CAM_REQ_INPROG)
6091 ahd_set_transaction_status(scb,
6092 status);
6093 cstat = ahd_get_transaction_status(scb);
6094 if (cstat != CAM_REQ_CMP)
6095 ahd_freeze_scb(scb);
7506 if ((scb->flags & SCB_ACTIVE) == 0)
7507 printf("Inactive SCB in qinfifo\n");
6096 if ((scb->flags & SCB_ACTIVE) == 0)
6097 printf("Inactive SCB in qinfifo\n");
7508 ahd_done_with_status(ahd, scb, status);
6098 ahd_done(ahd, scb);
6099
7509 /* FALLTHROUGH */
6100 /* FALLTHROUGH */
6101 }
7510 case SEARCH_REMOVE:
7511 break;
7512 case SEARCH_PRINT:
7513 printf(" 0x%x", ahd->qinfifo[qinpos]);
7514 /* FALLTHROUGH */
7515 case SEARCH_COUNT:
7516 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7517 prev_scb = scb;

--- 12 unchanged lines hidden (view full) ---

7530 printf("\nWAITING_TID_QUEUES:\n");
7531
7532 /*
7533 * Search waiting for selection lists. We traverse the
7534 * list of "their ids" waiting for selection and, if
7535 * appropriate, traverse the SCBs of each "their id"
7536 * looking for matches.
7537 */
6102 case SEARCH_REMOVE:
6103 break;
6104 case SEARCH_PRINT:
6105 printf(" 0x%x", ahd->qinfifo[qinpos]);
6106 /* FALLTHROUGH */
6107 case SEARCH_COUNT:
6108 ahd_qinfifo_requeue(ahd, prev_scb, scb);
6109 prev_scb = scb;

--- 12 unchanged lines hidden (view full) ---

6122 printf("\nWAITING_TID_QUEUES:\n");
6123
6124 /*
6125 * Search waiting for selection lists. We traverse the
6126 * list of "their ids" waiting for selection and, if
6127 * appropriate, traverse the SCBs of each "their id"
6128 * looking for matches.
6129 */
7538 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7539 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
7540 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
7541 scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
7542 mk_msg_scb = ahd_lookup_scb(ahd, scbid);
7543 } else
7544 mk_msg_scb = NULL;
7545 savedscbptr = ahd_get_scbptr(ahd);
7546 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7547 tid_prev = SCB_LIST_NULL;
7548 targets = 0;
7549 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7550 u_int tid_head;
6130 savedscbptr = ahd_get_scbptr(ahd);
6131 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
6132 tid_prev = SCB_LIST_NULL;
6133 targets = 0;
6134 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
6135 u_int tid_head;
7551 u_int tid_tail;
7552
6136
6137 /*
6138 * We limit based on the number of SCBs since
6139 * MK_MESSAGE SCBs are not in the per-tid lists.
6140 */
7553 targets++;
6141 targets++;
7554 if (targets > AHD_NUM_TARGETS)
6142 if (targets > AHD_SCB_MAX) {
7555 panic("TID LIST LOOP");
6143 panic("TID LIST LOOP");
7556
6144 }
7557 if (scbid >= ahd->scb_data.numscbs) {
7558 printf("%s: Waiting TID List inconsistency. "
7559 "SCB index == 0x%x, yet numscbs == 0x%x.",
7560 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7561 ahd_dump_card_state(ahd);
7562 panic("for safety");
7563 }
7564 scb = ahd_lookup_scb(ahd, scbid);

--- 13 unchanged lines hidden (view full) ---

7578 /*
7579 * We found a list of scbs that needs to be searched.
7580 */
7581 if (action == SEARCH_PRINT)
7582 printf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7583 tid_head = scbid;
7584 found += ahd_search_scb_list(ahd, target, channel,
7585 lun, tag, role, status,
6145 if (scbid >= ahd->scb_data.numscbs) {
6146 printf("%s: Waiting TID List inconsistency. "
6147 "SCB index == 0x%x, yet numscbs == 0x%x.",
6148 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
6149 ahd_dump_card_state(ahd);
6150 panic("for safety");
6151 }
6152 scb = ahd_lookup_scb(ahd, scbid);

--- 13 unchanged lines hidden (view full) ---

6166 /*
6167 * We found a list of scbs that needs to be searched.
6168 */
6169 if (action == SEARCH_PRINT)
6170 printf(" %d ( ", SCB_GET_TARGET(ahd, scb));
6171 tid_head = scbid;
6172 found += ahd_search_scb_list(ahd, target, channel,
6173 lun, tag, role, status,
7586 action, &tid_head, &tid_tail,
6174 action, &tid_head,
7587 SCB_GET_TARGET(ahd, scb));
6175 SCB_GET_TARGET(ahd, scb));
7588 /*
7589 * Check any MK_MESSAGE SCB that is still waiting to
7590 * enter this target's waiting for selection queue.
7591 */
7592 if (mk_msg_scb != NULL
7593 && ahd_match_scb(ahd, mk_msg_scb, target, channel,
7594 lun, tag, role)) {
7595
7596 /*
7597 * We found an scb that needs to be acted on.
7598 */
7599 found++;
7600 switch (action) {
7601 case SEARCH_COMPLETE:
7602 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
7603 printf("Inactive SCB pending MK_MSG\n");
7604 ahd_done_with_status(ahd, mk_msg_scb, status);
7605 /* FALLTHROUGH */
7606 case SEARCH_REMOVE:
7607 {
7608 u_int tail_offset;
7609
7610 printf("Removing MK_MSG scb\n");
7611
7612 /*
7613 * Reset our tail to the tail of the
7614 * main per-target list.
7615 */
7616 tail_offset = WAITING_SCB_TAILS
7617 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
7618 ahd_outw(ahd, tail_offset, tid_tail);
7619
7620 seq_flags2 &= ~PENDING_MK_MESSAGE;
7621 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7622 ahd_outw(ahd, CMDS_PENDING,
7623 ahd_inw(ahd, CMDS_PENDING)-1);
7624 mk_msg_scb = NULL;
7625 break;
7626 }
7627 case SEARCH_PRINT:
7628 printf(" 0x%x", SCB_GET_TAG(scb));
7629 /* FALLTHROUGH */
7630 case SEARCH_COUNT:
7631 break;
7632 }
7633 }
7634
7635 if (mk_msg_scb != NULL
7636 && SCBID_IS_NULL(tid_head)
7637 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7638 SCB_LIST_NULL, ROLE_UNKNOWN)) {
7639
7640 /*
7641 * When removing the last SCB for a target
7642 * queue with a pending MK_MESSAGE scb, we
7643 * must queue the MK_MESSAGE scb.
7644 */
7645 printf("Queueing mk_msg_scb\n");
7646 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
7647 seq_flags2 &= ~PENDING_MK_MESSAGE;
7648 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7649 mk_msg_scb = NULL;
7650 }
7651 if (tid_head != scbid)
7652 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7653 if (!SCBID_IS_NULL(tid_head))
7654 tid_prev = tid_head;
7655 if (action == SEARCH_PRINT)
7656 printf(")\n");
7657 }
6176 if (tid_head != scbid)
6177 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
6178 if (!SCBID_IS_NULL(tid_head))
6179 tid_prev = tid_head;
6180 if (action == SEARCH_PRINT)
6181 printf(")\n");
6182 }
7658
7659 /* Restore saved state. */
7660 ahd_set_scbptr(ahd, savedscbptr);
6183 ahd_set_scbptr(ahd, savedscbptr);
6184
6185 if (action == SEARCH_COMPLETE)
6186 ahd_release_untagged_queues(ahd);
7661 ahd_restore_modes(ahd, saved_modes);
7662 return (found);
7663}
7664
7665static int
7666ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7667 int lun, u_int tag, role_t role, uint32_t status,
6187 ahd_restore_modes(ahd, saved_modes);
6188 return (found);
6189}
6190
6191static int
6192ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
6193 int lun, u_int tag, role_t role, uint32_t status,
7668 ahd_search_action action, u_int *list_head,
7669 u_int *list_tail, u_int tid)
6194 ahd_search_action action, u_int *list_head, u_int tid)
7670{
7671 struct scb *scb;
7672 u_int scbid;
7673 u_int next;
7674 u_int prev;
7675 int found;
7676
6195{
6196 struct scb *scb;
6197 u_int scbid;
6198 u_int next;
6199 u_int prev;
6200 int found;
6201
7677 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6202 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7678 found = 0;
7679 prev = SCB_LIST_NULL;
7680 next = *list_head;
6203 found = 0;
6204 prev = SCB_LIST_NULL;
6205 next = *list_head;
7681 *list_tail = SCB_LIST_NULL;
7682 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7683 if (scbid >= ahd->scb_data.numscbs) {
7684 printf("%s:SCB List inconsistency. "
7685 "SCB == 0x%x, yet numscbs == 0x%x.",
7686 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7687 ahd_dump_card_state(ahd);
7688 panic("for safety");
7689 }
7690 scb = ahd_lookup_scb(ahd, scbid);
7691 if (scb == NULL) {
7692 printf("%s: SCB = %d Not Active!\n",
7693 ahd_name(ahd), scbid);
7694 panic("Waiting List traversal\n");
7695 }
7696 ahd_set_scbptr(ahd, scbid);
6206 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
6207 if (scbid >= ahd->scb_data.numscbs) {
6208 printf("%s:SCB List inconsistency. "
6209 "SCB == 0x%x, yet numscbs == 0x%x.",
6210 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
6211 ahd_dump_card_state(ahd);
6212 panic("for safety");
6213 }
6214 scb = ahd_lookup_scb(ahd, scbid);
6215 if (scb == NULL) {
6216 printf("%s: SCB = %d Not Active!\n",
6217 ahd_name(ahd), scbid);
6218 panic("Waiting List traversal\n");
6219 }
6220 ahd_set_scbptr(ahd, scbid);
7697 *list_tail = scbid;
7698 next = ahd_inw_scbram(ahd, SCB_NEXT);
7699 if (ahd_match_scb(ahd, scb, target, channel,
7700 lun, SCB_LIST_NULL, role) == 0) {
7701 prev = scbid;
7702 continue;
7703 }
7704 found++;
7705 switch (action) {
7706 case SEARCH_COMPLETE:
6221 next = ahd_inw_scbram(ahd, SCB_NEXT);
6222 if (ahd_match_scb(ahd, scb, target, channel,
6223 lun, SCB_LIST_NULL, role) == 0) {
6224 prev = scbid;
6225 continue;
6226 }
6227 found++;
6228 switch (action) {
6229 case SEARCH_COMPLETE:
6230 {
6231 cam_status ostat;
6232 cam_status cstat;
6233
6234 ostat = ahd_get_transaction_status(scb);
6235 if (ostat == CAM_REQ_INPROG)
6236 ahd_set_transaction_status(scb, status);
6237 cstat = ahd_get_transaction_status(scb);
6238 if (cstat != CAM_REQ_CMP)
6239 ahd_freeze_scb(scb);
7707 if ((scb->flags & SCB_ACTIVE) == 0)
7708 printf("Inactive SCB in Waiting List\n");
6240 if ((scb->flags & SCB_ACTIVE) == 0)
6241 printf("Inactive SCB in Waiting List\n");
7709 ahd_done_with_status(ahd, scb, status);
6242 ahd_done(ahd, scb);
7710 /* FALLTHROUGH */
6243 /* FALLTHROUGH */
6244 }
7711 case SEARCH_REMOVE:
7712 ahd_rem_wscb(ahd, scbid, prev, next, tid);
6245 case SEARCH_REMOVE:
6246 ahd_rem_wscb(ahd, scbid, prev, next, tid);
7713 *list_tail = prev;
7714 if (SCBID_IS_NULL(prev))
6247 if (prev == SCB_LIST_NULL)
7715 *list_head = next;
7716 break;
7717 case SEARCH_PRINT:
7718 printf("0x%x ", scbid);
7719 case SEARCH_COUNT:
7720 prev = scbid;
7721 break;
7722 }
7723 if (found > AHD_SCB_MAX)
7724 panic("SCB LIST LOOP");
7725 }
6248 *list_head = next;
6249 break;
6250 case SEARCH_PRINT:
6251 printf("0x%x ", scbid);
6252 case SEARCH_COUNT:
6253 prev = scbid;
6254 break;
6255 }
6256 if (found > AHD_SCB_MAX)
6257 panic("SCB LIST LOOP");
6258 }
7726 if (action == SEARCH_COMPLETE
7727 || action == SEARCH_REMOVE)
7728 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7729 return (found);
7730}
7731
7732static void
7733ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7734 u_int tid_cur, u_int tid_next)
7735{
6259 return (found);
6260}
6261
6262static void
6263ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
6264 u_int tid_cur, u_int tid_next)
6265{
7736 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6266 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7737
7738 if (SCBID_IS_NULL(tid_cur)) {
7739
7740 /* Bypass current TID list */
7741 if (SCBID_IS_NULL(tid_prev)) {
7742 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7743 } else {
7744 ahd_set_scbptr(ahd, tid_prev);

--- 23 unchanged lines hidden (view full) ---

7768 * scb that follows the one that we remove.
7769 */
7770static u_int
7771ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7772 u_int prev, u_int next, u_int tid)
7773{
7774 u_int tail_offset;
7775
6267
6268 if (SCBID_IS_NULL(tid_cur)) {
6269
6270 /* Bypass current TID list */
6271 if (SCBID_IS_NULL(tid_prev)) {
6272 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
6273 } else {
6274 ahd_set_scbptr(ahd, tid_prev);

--- 23 unchanged lines hidden (view full) ---

6298 * scb that follows the one that we remove.
6299 */
6300static u_int
6301ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
6302 u_int prev, u_int next, u_int tid)
6303{
6304 u_int tail_offset;
6305
7776 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6306 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7777 if (!SCBID_IS_NULL(prev)) {
7778 ahd_set_scbptr(ahd, prev);
7779 ahd_outw(ahd, SCB_NEXT, next);
7780 }
7781
7782 /*
6307 if (!SCBID_IS_NULL(prev)) {
6308 ahd_set_scbptr(ahd, prev);
6309 ahd_outw(ahd, SCB_NEXT, next);
6310 }
6311
6312 /*
7783 * SCBs that have MK_MESSAGE set in them may
7784 * cause the tail pointer to be updated without
7785 * setting the next pointer of the previous tail.
7786 * Only clear the tail if the removed SCB was
7787 * the tail.
6313 * SCBs that had MK_MESSAGE set in them will not
6314 * be queued to the per-target lists, so don't
6315 * blindly clear the tail pointer.
7788 */
7789 tail_offset = WAITING_SCB_TAILS + (2 * tid);
7790 if (SCBID_IS_NULL(next)
7791 && ahd_inw(ahd, tail_offset) == scbid)
7792 ahd_outw(ahd, tail_offset, prev);
6316 */
6317 tail_offset = WAITING_SCB_TAILS + (2 * tid);
6318 if (SCBID_IS_NULL(next)
6319 && ahd_inw(ahd, tail_offset) == scbid)
6320 ahd_outw(ahd, tail_offset, prev);
7793
7794 ahd_add_scb_to_free_list(ahd, scbid);
7795 return (next);
7796}
7797
7798/*
7799 * Add the SCB as selected by SCBPTR onto the on chip list of
7800 * free hardware SCBs. This list is empty/unused if we are not
7801 * performing SCB paging.

--- 15 unchanged lines hidden (view full) ---

7817 * setting their status to the passed in status if the status has not already
7818 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7819 * is paused before it is called.
7820 */
7821int
7822ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7823 int lun, u_int tag, role_t role, uint32_t status)
7824{
6321 ahd_add_scb_to_free_list(ahd, scbid);
6322 return (next);
6323}
6324
6325/*
6326 * Add the SCB as selected by SCBPTR onto the on chip list of
6327 * free hardware SCBs. This list is empty/unused if we are not
6328 * performing SCB paging.

--- 15 unchanged lines hidden (view full) ---

6344 * setting their status to the passed in status if the status has not already
6345 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
6346 * is paused before it is called.
6347 */
6348int
6349ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
6350 int lun, u_int tag, role_t role, uint32_t status)
6351{
7825 struct scb *scbp;
7826 struct scb *scbp_next;
7827 u_int i, j;
7828 u_int maxtarget;
7829 u_int minlun;
7830 u_int maxlun;
7831 int found;
7832 ahd_mode_state saved_modes;
6352 struct scb *scbp;
6353 struct scb *scbp_next;
6354 u_int active_scb;
6355 u_int i, j;
6356 u_int maxtarget;
6357 u_int minlun;
6358 u_int maxlun;
7833
6359
6360 int found;
6361
6362 /*
6363 * Don't attempt to run any queued untagged transactions
6364 * until we are done with the abort process.
6365 */
6366 ahd_freeze_untagged_queues(ahd);
6367
7834 /* restore this when we're done */
6368 /* restore this when we're done */
7835 saved_modes = ahd_save_modes(ahd);
7836 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6369 active_scb = ahd_get_scbptr(ahd);
7837
7838 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7839 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7840
7841 /*
7842 * Clean out the busy target table for any untagged commands.
7843 */
7844 i = 0;

--- 16 unchanged lines hidden (view full) ---

7861 }
7862
7863 if (role != ROLE_TARGET) {
7864 for (;i < maxtarget; i++) {
7865 for (j = minlun;j < maxlun; j++) {
7866 u_int scbid;
7867 u_int tcl;
7868
6370
6371 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
6372 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
6373
6374 /*
6375 * Clean out the busy target table for any untagged commands.
6376 */
6377 i = 0;

--- 16 unchanged lines hidden (view full) ---

6394 }
6395
6396 if (role != ROLE_TARGET) {
6397 for (;i < maxtarget; i++) {
6398 for (j = minlun;j < maxlun; j++) {
6399 u_int scbid;
6400 u_int tcl;
6401
7869 tcl = BUILD_TCL_RAW(i, 'A', j);
6402 tcl = BUILD_TCL(i << 4, j);
7870 scbid = ahd_find_busy_tcl(ahd, tcl);
7871 scbp = ahd_lookup_scb(ahd, scbid);
7872 if (scbp == NULL
7873 || ahd_match_scb(ahd, scbp, target, channel,
7874 lun, tag, role) == 0)
7875 continue;
7876 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7877 }
7878 }
7879 }
7880
7881 /*
6403 scbid = ahd_find_busy_tcl(ahd, tcl);
6404 scbp = ahd_lookup_scb(ahd, scbid);
6405 if (scbp == NULL
6406 || ahd_match_scb(ahd, scbp, target, channel,
6407 lun, tag, role) == 0)
6408 continue;
6409 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
6410 }
6411 }
6412 }
6413
6414 /*
7882 * Don't abort commands that have already completed,
7883 * but haven't quite made it up to the host yet.
7884 */
7885 ahd_flush_qoutfifo(ahd);
7886
7887 /*
7888 * Go through the pending CCB list and look for
7889 * commands for this target that are still active.
7890 * These are other tagged commands that were
7891 * disconnected when the reset occurred.
7892 */
7893 scbp_next = LIST_FIRST(&ahd->pending_scbs);
7894 while (scbp_next != NULL) {
7895 scbp = scbp_next;
7896 scbp_next = LIST_NEXT(scbp, pending_links);
7897 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7898 cam_status ostat;
7899
6415 * Go through the pending CCB list and look for
6416 * commands for this target that are still active.
6417 * These are other tagged commands that were
6418 * disconnected when the reset occurred.
6419 */
6420 scbp_next = LIST_FIRST(&ahd->pending_scbs);
6421 while (scbp_next != NULL) {
6422 scbp = scbp_next;
6423 scbp_next = LIST_NEXT(scbp, pending_links);
6424 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
6425 cam_status ostat;
6426
7900 ostat = aic_get_transaction_status(scbp);
6427 ostat = ahd_get_transaction_status(scbp);
7901 if (ostat == CAM_REQ_INPROG)
6428 if (ostat == CAM_REQ_INPROG)
7902 aic_set_transaction_status(scbp, status);
7903 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
7904 aic_freeze_scb(scbp);
6429 ahd_set_transaction_status(scbp, status);
6430 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP)
6431 ahd_freeze_scb(scbp);
7905 if ((scbp->flags & SCB_ACTIVE) == 0)
7906 printf("Inactive SCB on pending list\n");
7907 ahd_done(ahd, scbp);
7908 found++;
7909 }
7910 }
6432 if ((scbp->flags & SCB_ACTIVE) == 0)
6433 printf("Inactive SCB on pending list\n");
6434 ahd_done(ahd, scbp);
6435 found++;
6436 }
6437 }
7911 ahd_restore_modes(ahd, saved_modes);
6438 ahd_set_scbptr(ahd, active_scb);
7912 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
6439 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
7913 ahd->flags |= AHD_UPDATE_PEND_CMDS;
6440 ahd_release_untagged_queues(ahd);
7914 return found;
7915}
7916
7917static void
7918ahd_reset_current_bus(struct ahd_softc *ahd)
7919{
7920 uint8_t scsiseq;
7921
7922 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7923 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
6441 return found;
6442}
6443
6444static void
6445ahd_reset_current_bus(struct ahd_softc *ahd)
6446{
6447 uint8_t scsiseq;
6448
6449 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6450 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7924 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
6451 scsiseq = ahd_inb(ahd, SCSISEQ0);
7925 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
6452 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7926 ahd_flush_device_writes(ahd);
7927 aic_delay(AHD_BUSRESET_DELAY);
6453 ahd_delay(AHD_BUSRESET_DELAY);
7928 /* Turn off the bus reset */
6454 /* Turn off the bus reset */
7929 ahd_outb(ahd, SCSISEQ0, scsiseq);
7930 ahd_flush_device_writes(ahd);
7931 aic_delay(AHD_BUSRESET_DELAY);
6455 ahd_outb(ahd, SCSISEQ0, scsiseq & ~SCSIRSTO);
7932 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7933 /*
7934 * 2A Razor #474
7935 * Certain chip state is not cleared for
7936 * SCSI bus resets that we initiate, so
7937 * we must reset the chip.
7938 */
6456 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
6457 /*
6458 * 2A Razor #474
6459 * Certain chip state is not cleared for
6460 * SCSI bus resets that we initiate, so
6461 * we must reset the chip.
6462 */
7939 ahd_reset(ahd, /*reinit*/TRUE);
6463 ahd_reset(ahd);
7940 ahd_intr_enable(ahd, /*enable*/TRUE);
7941 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7942 }
7943
7944 ahd_clear_intstat(ahd);
6464 ahd_intr_enable(ahd, /*enable*/TRUE);
6465 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6466 }
6467
6468 ahd_clear_intstat(ahd);
6469
6470 /* Re-enable reset interrupts */
6471 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
7945}
7946
7947int
7948ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7949{
7950 struct ahd_devinfo devinfo;
6472}
6473
6474int
6475ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
6476{
6477 struct ahd_devinfo devinfo;
7951 u_int initiator;
6478#if AHD_TARGET_MODE
7952 u_int target;
7953 u_int max_scsiid;
6479 u_int target;
6480 u_int max_scsiid;
6481#endif
7954 int found;
6482 int found;
7955 u_int fifo;
7956 u_int next_fifo;
7957
7958 ahd->pending_device = NULL;
7959
7960 ahd_compile_devinfo(&devinfo,
7961 CAM_TARGET_WILDCARD,
7962 CAM_TARGET_WILDCARD,
7963 CAM_LUN_WILDCARD,
7964 channel, ROLE_UNKNOWN);
7965 ahd_pause(ahd);
7966
7967 /* Make sure the sequencer is in a safe location. */
7968 ahd_clear_critical_section(ahd);
7969
6483
6484 ahd->pending_device = NULL;
6485
6486 ahd_compile_devinfo(&devinfo,
6487 CAM_TARGET_WILDCARD,
6488 CAM_TARGET_WILDCARD,
6489 CAM_LUN_WILDCARD,
6490 channel, ROLE_UNKNOWN);
6491 ahd_pause(ahd);
6492
6493 /* Make sure the sequencer is in a safe location. */
6494 ahd_clear_critical_section(ahd);
6495
7970#ifdef AHD_TARGET_MODE
6496 /*
6497 * Run our command complete fifos to ensure that we perform
6498 * completion processing on any commands that 'completed'
6499 * before the reset occurred.
6500 */
6501 ahd_run_qoutfifo(ahd);
6502#if AHD_TARGET_MODE
7971 if ((ahd->flags & AHD_TARGETROLE) != 0) {
7972 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7973 }
7974#endif
7975 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7976
7977 /*
6503 if ((ahd->flags & AHD_TARGETROLE) != 0) {
6504 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
6505 }
6506#endif
6507 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6508
6509 /*
7978 * Disable selections so no automatic hardware
7979 * functions will modify chip state.
7980 */
7981 ahd_outb(ahd, SCSISEQ0, 0);
7982 ahd_outb(ahd, SCSISEQ1, 0);
7983
7984 /*
7985 * Safely shut down our DMA engines. Always start with
7986 * the FIFO that is not currently active (if any are
7987 * actively connected).
7988 */
7989 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7990 if (next_fifo > CURRFIFO_1)
7991 /* If disconneced, arbitrarily start with FIFO1. */
7992 next_fifo = fifo = 0;
7993 do {
7994 next_fifo ^= CURRFIFO_1;
7995 ahd_set_modes(ahd, next_fifo, next_fifo);
7996 ahd_outb(ahd, DFCNTRL,
7997 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7998 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7999 aic_delay(10);
8000 /*
8001 * Set CURRFIFO to the now inactive channel.
8002 */
8003 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8004 ahd_outb(ahd, DFFSTAT, next_fifo);
8005 } while (next_fifo != fifo);
8006
8007 /*
8008 * Reset the bus if we are initiating this reset
8009 */
8010 ahd_clear_msg_state(ahd);
6510 * Reset the bus if we are initiating this reset
6511 */
6512 ahd_clear_msg_state(ahd);
8011 ahd_outb(ahd, SIMODE1,
8012 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
8013
6513 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
8014 if (initiate_reset)
8015 ahd_reset_current_bus(ahd);
6514 if (initiate_reset)
6515 ahd_reset_current_bus(ahd);
8016
8017 ahd_clear_intstat(ahd);
8018
8019 /*
8020 * Clean up all the state information for the
8021 * pending transactions on this bus.
8022 */
8023 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
8024 CAM_LUN_WILDCARD, SCB_LIST_NULL,
8025 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
8026
6516 ahd_clear_intstat(ahd);
6517
6518 /*
6519 * Clean up all the state information for the
6520 * pending transactions on this bus.
6521 */
6522 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
6523 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6524 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6525
8027 /*
8028 * Cleanup anything left in the FIFOs.
8029 */
8030 ahd_clear_fifo(ahd, 0);
8031 ahd_clear_fifo(ahd, 1);
8032
8033 /*
8034 * Revert to async/narrow transfers until we renegotiate.
8035 */
8036 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
8037 for (target = 0; target <= max_scsiid; target++) {
8038
8039 if (ahd->enabled_targets[target] == NULL)
8040 continue;
8041 for (initiator = 0; initiator <= max_scsiid; initiator++) {
8042 struct ahd_devinfo devinfo;
8043
8044 ahd_compile_devinfo(&devinfo, target, initiator,
8045 CAM_LUN_WILDCARD,
8046 'A', ROLE_UNKNOWN);
8047 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
8048 AHD_TRANS_CUR, /*paused*/TRUE);
8049 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
8050 /*offset*/0, /*ppr_options*/0,
8051 AHD_TRANS_CUR, /*paused*/TRUE);
8052 }
8053 }
8054
8055#ifdef AHD_TARGET_MODE
8056 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
8057
8058 /*
8059 * Send an immediate notify ccb to all target more peripheral
8060 * drivers affected by this action.
8061 */
8062 for (target = 0; target <= max_scsiid; target++) {

--- 14 unchanged lines hidden (view full) ---

8077 EVENT_TYPE_BUS_RESET, /*arg*/0);
8078 ahd_send_lstate_events(ahd, lstate);
8079 }
8080 }
8081#endif
8082 /* Notify the XPT that a bus reset occurred */
8083 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
8084 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6526#ifdef AHD_TARGET_MODE
6527 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
6528
6529 /*
6530 * Send an immediate notify ccb to all target more peripheral
6531 * drivers affected by this action.
6532 */
6533 for (target = 0; target <= max_scsiid; target++) {

--- 14 unchanged lines hidden (view full) ---

6548 EVENT_TYPE_BUS_RESET, /*arg*/0);
6549 ahd_send_lstate_events(ahd, lstate);
6550 }
6551 }
6552#endif
6553 /* Notify the XPT that a bus reset occurred */
6554 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
6555 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
8085 ahd_restart(ahd);
6556
8086 /*
8087 * Freeze the SIMQ until our poller can determine that
8088 * the bus reset has really gone away. We set the initial
8089 * timer to 0 to have the check performed as soon as possible
8090 * from the timer context.
8091 */
6557 /*
6558 * Freeze the SIMQ until our poller can determine that
6559 * the bus reset has really gone away. We set the initial
6560 * timer to 0 to have the check performed as soon as possible
6561 * from the timer context.
6562 */
8092 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
8093 ahd->flags |= AHD_RESET_POLL_ACTIVE;
8094 aic_freeze_simq(ahd);
8095 aic_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
8096 }
6563 ahd_freeze_simq(ahd);
6564 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
8097 return (found);
8098}
8099
8100
6565 return (found);
6566}
6567
6568
8101#define AHD_RESET_POLL_MS 1
6569#define AHD_RESET_POLL_US 1000
8102static void
8103ahd_reset_poll(void *arg)
8104{
6570static void
6571ahd_reset_poll(void *arg)
6572{
8105 struct ahd_softc *ahd = (struct ahd_softc *)arg;
6573 struct ahd_softc *ahd;
8106 u_int scsiseq1;
6574 u_int scsiseq1;
6575 u_int initiator, target, max_scsiid;
6576 u_long l;
6577 u_long s;
8107
6578
8108 ahd_lock(ahd);
8109 ahd_pause(ahd);
8110 ahd_update_modes(ahd);
8111 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8112 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
8113 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
8114 aic_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_MS,
8115 ahd_reset_poll, ahd);
8116 ahd_unpause(ahd);
8117 ahd_unlock(ahd);
6579 ahd_list_lock(&l);
6580 ahd = ahd_find_softc((struct ahd_softc *)arg);
6581 if (ahd == NULL) {
6582 printf("ahd_reset_poll: Instance %p no longer exists\n", arg);
6583 ahd_list_unlock(&l);
8118 return;
8119 }
6584 return;
6585 }
6586 ahd_lock(ahd, &s);
6587 if (ahd_is_paused(ahd) == 0)
6588 panic("Someone unpaused the sequencer!\n");
8120
6589
6590 ahd_clear_intstat(ahd);
6591 if ((ahd_inb(ahd, SSTAT0) & SCSIRSTI) != 0) {
6592 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US,
6593 ahd_reset_poll, ahd);
6594 ahd_unlock(ahd, &s);
6595 }
6596
8121 /* Reset is now low. Complete chip reinitialization. */
8122 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
8123 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
8124 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
6597 /* Reset is now low. Complete chip reinitialization. */
6598 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
6599 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
6600 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
8125 ahd_unpause(ahd);
8126 ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
8127 aic_release_simq(ahd);
8128 ahd_unlock(ahd);
8129}
8130
6601
8131/**************************** Statistics Processing ***************************/
8132static void
8133ahd_stat_timer(void *arg)
8134{
8135 struct ahd_softc *ahd = (struct ahd_softc *)arg;
8136 int enint_coal;
8137
8138 ahd_lock(ahd);
8139 enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
8140 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
8141 enint_coal |= ENINT_COALESCE;
8142 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
8143 enint_coal &= ~ENINT_COALESCE;
6602 /*
6603 * Revert to async/narrow transfers until we renegotiate.
6604 */
6605 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
6606 for (target = 0; target <= max_scsiid; target++) {
8144
6607
8145 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
8146 ahd_enable_coalescing(ahd, enint_coal);
8147#ifdef AHD_DEBUG
8148 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
8149 printf("%s: Interrupt coalescing "
8150 "now %sabled. Cmds %d\n",
8151 ahd_name(ahd),
8152 (enint_coal & ENINT_COALESCE) ? "en" : "dis",
8153 ahd->cmdcmplt_total);
8154#endif
6608 if (ahd->enabled_targets[target] == NULL)
6609 continue;
6610 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6611 struct ahd_devinfo devinfo;
6612
6613 ahd_compile_devinfo(&devinfo, target, initiator,
6614 CAM_LUN_WILDCARD,
6615 'A', ROLE_UNKNOWN);
6616 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6617 AHD_TRANS_CUR, /*paused*/TRUE);
6618 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
6619 /*offset*/0, /*ppr_options*/0,
6620 AHD_TRANS_CUR, /*paused*/TRUE);
6621 }
8155 }
8156
6622 }
6623
8157 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
8158 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
8159 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
8160 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
8161 ahd_stat_timer, ahd);
8162 ahd_unlock(ahd);
6624 ahd_clear_fifo(ahd, 0);
6625 ahd_clear_fifo(ahd, 1);
6626 ahd_restart(ahd);
6627 ahd_unlock(ahd, &s);
6628 ahd_release_simq(ahd);
6629 ahd_list_unlock(&l);
8163}
8164
6630}
6631
6632
8165/****************************** Status Processing *****************************/
8166void
8167ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
8168{
8169 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
8170 ahd_handle_scsi_status(ahd, scb);
8171 } else {
8172 ahd_calc_residual(ahd, scb);
8173 ahd_done(ahd, scb);
8174 }
8175}
8176
8177void
8178ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
8179{
6633/****************************** Status Processing *****************************/
6634void
6635ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
6636{
6637 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
6638 ahd_handle_scsi_status(ahd, scb);
6639 } else {
6640 ahd_calc_residual(ahd, scb);
6641 ahd_done(ahd, scb);
6642 }
6643}
6644
6645void
6646ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
6647{
8180 struct hardware_scb *hscb;
8181 int paused;
6648 struct hardware_scb *hscb;
6649 u_int qfreeze_cnt;
6650 ahd_mode_state saved_modes;
8182
8183 /*
8184 * The sequencer freezes its select-out queue
8185 * anytime a SCSI status error occurs. We must
6651
6652 /*
6653 * The sequencer freezes its select-out queue
6654 * anytime a SCSI status error occurs. We must
8186 * handle the error and increment our qfreeze count
8187 * to allow the sequencer to continue. We don't
8188 * bother clearing critical sections here since all
8189 * operations are on data structures that the sequencer
8190 * is not touching once the queue is frozen.
6655 * handle the error and decrement the QFREEZE count
6656 * to allow the sequencer to continue.
8191 */
8192 hscb = scb->hscb;
8193
6657 */
6658 hscb = scb->hscb;
6659
8194 if (ahd_is_paused(ahd)) {
8195 paused = 1;
8196 } else {
8197 paused = 0;
8198 ahd_pause(ahd);
8199 }
8200
8201 /* Freeze the queue until the client sees the error. */
8202 ahd_freeze_devq(ahd, scb);
8203 aic_freeze_scb(scb);
8204 ahd->qfreeze_cnt++;
8205 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
8206
8207 if (paused == 0)
8208 ahd_unpause(ahd);
8209
8210 /* Don't want to clobber the original sense code */
8211 if ((scb->flags & SCB_SENSE) != 0) {
8212 /*
8213 * Clear the SCB_SENSE Flag and perform
8214 * a normal command completion.
8215 */
8216 scb->flags &= ~SCB_SENSE;
6660 /* Don't want to clobber the original sense code */
6661 if ((scb->flags & SCB_SENSE) != 0) {
6662 /*
6663 * Clear the SCB_SENSE Flag and perform
6664 * a normal command completion.
6665 */
6666 scb->flags &= ~SCB_SENSE;
8217 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
6667 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
8218 ahd_done(ahd, scb);
8219 return;
8220 }
6668 ahd_done(ahd, scb);
6669 return;
6670 }
8221 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
8222 aic_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
6671 ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
6672 /* Freeze the queue until the client sees the error. */
6673 ahd_pause(ahd);
6674 saved_modes = ahd_save_modes(ahd);
6675 ahd_clear_critical_section(ahd);
6676 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6677 ahd_freeze_devq(ahd, scb);
6678 ahd_freeze_scb(scb);
6679 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT);
6680 if (qfreeze_cnt == 0) {
6681 printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd));
6682 } else {
6683 qfreeze_cnt--;
6684 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt);
6685 }
6686 if (qfreeze_cnt == 0)
6687 ahd_outb(ahd, SEQ_FLAGS2,
6688 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN);
6689 ahd_unpause(ahd);
6690 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
8223 switch (hscb->shared_data.istatus.scsi_status) {
8224 case STATUS_PKT_SENSE:
8225 {
8226 struct scsi_status_iu_header *siu;
8227
8228 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
8229 siu = (struct scsi_status_iu_header *)scb->sense_data;
6691 switch (hscb->shared_data.istatus.scsi_status) {
6692 case STATUS_PKT_SENSE:
6693 {
6694 struct scsi_status_iu_header *siu;
6695
6696 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
6697 siu = (struct scsi_status_iu_header *)scb->sense_data;
8230 aic_set_scsi_status(scb, siu->status);
6698 ahd_set_scsi_status(scb, siu->status);
8231#ifdef AHD_DEBUG
6699#ifdef AHD_DEBUG
8232 if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
6700 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8233 ahd_print_path(ahd, scb);
8234 printf("SCB 0x%x Received PKT Status of 0x%x\n",
8235 SCB_GET_TAG(scb), siu->status);
8236 printf("\tflags = 0x%x, sense len = 0x%x, "
8237 "pktfail = 0x%x\n",
8238 siu->flags, scsi_4btoul(siu->sense_length),
8239 scsi_4btoul(siu->pkt_failures_length));
6701 ahd_print_path(ahd, scb);
6702 printf("SCB 0x%x Received PKT Status of 0x%x\n",
6703 SCB_GET_TAG(scb), siu->status);
6704 printf("\tflags = 0x%x, sense len = 0x%x, "
6705 "pktfail = 0x%x\n",
6706 siu->flags, scsi_4btoul(siu->sense_length),
6707 scsi_4btoul(siu->pkt_failures_length));
8240 }
8241#endif
8242 if ((siu->flags & SIU_RSPVALID) != 0) {
8243 ahd_print_path(ahd, scb);
8244 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
8245 printf("Unable to parse pkt_failures\n");
8246 } else {
8247
8248 switch (SIU_PKTFAIL_CODE(siu)) {
8249 case SIU_PFC_NONE:
8250 printf("No packet failure found\n");
6708#endif
6709 if ((siu->flags & SIU_RSPVALID) != 0) {
6710 ahd_print_path(ahd, scb);
6711 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
6712 printf("Unable to parse pkt_failures\n");
6713 } else {
6714
6715 switch (SIU_PKTFAIL_CODE(siu)) {
6716 case SIU_PFC_NONE:
6717 printf("No packet failure found\n");
8251 AHD_UNCORRECTABLE_ERROR(ahd);
8252 break;
8253 case SIU_PFC_CIU_FIELDS_INVALID:
8254 printf("Invalid Command IU Field\n");
6718 break;
6719 case SIU_PFC_CIU_FIELDS_INVALID:
6720 printf("Invalid Command IU Field\n");
8255 AHD_UNCORRECTABLE_ERROR(ahd);
8256 break;
8257 case SIU_PFC_TMF_NOT_SUPPORTED:
8258 printf("TMF not supportd\n");
6721 break;
6722 case SIU_PFC_TMF_NOT_SUPPORTED:
6723 printf("TMF not supportd\n");
8259 AHD_UNCORRECTABLE_ERROR(ahd);
8260 break;
8261 case SIU_PFC_TMF_FAILED:
8262 printf("TMF failed\n");
6724 break;
6725 case SIU_PFC_TMF_FAILED:
6726 printf("TMF failed\n");
8263 AHD_UNCORRECTABLE_ERROR(ahd);
8264 break;
8265 case SIU_PFC_INVALID_TYPE_CODE:
8266 printf("Invalid L_Q Type code\n");
6727 break;
6728 case SIU_PFC_INVALID_TYPE_CODE:
6729 printf("Invalid L_Q Type code\n");
8267 AHD_UNCORRECTABLE_ERROR(ahd);
8268 break;
8269 case SIU_PFC_ILLEGAL_REQUEST:
6730 break;
6731 case SIU_PFC_ILLEGAL_REQUEST:
8270 AHD_UNCORRECTABLE_ERROR(ahd);
8271 printf("Illegal request\n");
8272 default:
8273 break;
8274 }
8275 }
8276 if (siu->status == SCSI_STATUS_OK)
6732 printf("Illegal request\n");
6733 default:
6734 break;
6735 }
6736 }
6737 if (siu->status == SCSI_STATUS_OK)
8277 aic_set_transaction_status(scb,
6738 ahd_set_transaction_status(scb,
8278 CAM_REQ_CMP_ERR);
8279 }
8280 if ((siu->flags & SIU_SNSVALID) != 0) {
8281 scb->flags |= SCB_PKT_SENSE;
8282#ifdef AHD_DEBUG
8283 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8284 printf("Sense data available\n");
8285#endif

--- 13 unchanged lines hidden (view full) ---

8299#ifdef AHD_DEBUG
8300 if (ahd_debug & AHD_SHOW_SENSE) {
8301 ahd_print_path(ahd, scb);
8302 printf("SCB %d: requests Check Status\n",
8303 SCB_GET_TAG(scb));
8304 }
8305#endif
8306
6739 CAM_REQ_CMP_ERR);
6740 }
6741 if ((siu->flags & SIU_SNSVALID) != 0) {
6742 scb->flags |= SCB_PKT_SENSE;
6743#ifdef AHD_DEBUG
6744 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
6745 printf("Sense data available\n");
6746#endif

--- 13 unchanged lines hidden (view full) ---

6760#ifdef AHD_DEBUG
6761 if (ahd_debug & AHD_SHOW_SENSE) {
6762 ahd_print_path(ahd, scb);
6763 printf("SCB %d: requests Check Status\n",
6764 SCB_GET_TAG(scb));
6765 }
6766#endif
6767
8307 if (aic_perform_autosense(scb) == 0)
6768 if (ahd_perform_autosense(scb) == 0)
8308 break;
8309
8310 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
8311 SCB_GET_TARGET(ahd, scb),
8312 SCB_GET_LUN(scb),
8313 SCB_GET_CHANNEL(ahd, scb),
8314 ROLE_INITIATOR);
8315 targ_info = ahd_fetch_transinfo(ahd,

--- 11 unchanged lines hidden (view full) ---

8327#ifdef AHD_DEBUG
8328 if (ahd_debug & AHD_SHOW_SENSE) {
8329 ahd_print_path(ahd, scb);
8330 printf("Sending Sense\n");
8331 }
8332#endif
8333 scb->sg_count = 0;
8334 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
6769 break;
6770
6771 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
6772 SCB_GET_TARGET(ahd, scb),
6773 SCB_GET_LUN(scb),
6774 SCB_GET_CHANNEL(ahd, scb),
6775 ROLE_INITIATOR);
6776 targ_info = ahd_fetch_transinfo(ahd,

--- 11 unchanged lines hidden (view full) ---

6788#ifdef AHD_DEBUG
6789 if (ahd_debug & AHD_SHOW_SENSE) {
6790 ahd_print_path(ahd, scb);
6791 printf("Sending Sense\n");
6792 }
6793#endif
6794 scb->sg_count = 0;
6795 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8335 aic_get_sense_bufsize(ahd, scb),
6796 ahd_get_sense_bufsize(ahd, scb),
8336 /*last*/TRUE);
8337 sc->opcode = REQUEST_SENSE;
8338 sc->byte2 = 0;
8339 if (tinfo->protocol_version <= SCSI_REV_2
8340 && SCB_GET_LUN(scb) < 8)
8341 sc->byte2 = SCB_GET_LUN(scb) << 5;
8342 sc->unused[0] = 0;
8343 sc->unused[1] = 0;
6797 /*last*/TRUE);
6798 sc->opcode = REQUEST_SENSE;
6799 sc->byte2 = 0;
6800 if (tinfo->protocol_version <= SCSI_REV_2
6801 && SCB_GET_LUN(scb) < 8)
6802 sc->byte2 = SCB_GET_LUN(scb) << 5;
6803 sc->unused[0] = 0;
6804 sc->unused[1] = 0;
8344 sc->length = aic_get_sense_bufsize(ahd, scb);
6805 sc->length = ahd_get_sense_bufsize(ahd, scb);
8345 sc->control = 0;
8346
8347 /*
8348 * We can't allow the target to disconnect.
8349 * This will be an untagged transaction and
8350 * having the target disconnect will make this
8351 * transaction indestinguishable from outstanding
8352 * tagged transactions.
8353 */
8354 hscb->control = 0;
8355
8356 /*
8357 * This request sense could be because the
8358 * the device lost power or in some other
8359 * way has lost our transfer negotiations.
8360 * Renegotiate if appropriate. Unit attention
8361 * errors will be reported before any data
8362 * phases occur.
8363 */
6806 sc->control = 0;
6807
6808 /*
6809 * We can't allow the target to disconnect.
6810 * This will be an untagged transaction and
6811 * having the target disconnect will make this
6812 * transaction indestinguishable from outstanding
6813 * tagged transactions.
6814 */
6815 hscb->control = 0;
6816
6817 /*
6818 * This request sense could be because the
6819 * the device lost power or in some other
6820 * way has lost our transfer negotiations.
6821 * Renegotiate if appropriate. Unit attention
6822 * errors will be reported before any data
6823 * phases occur.
6824 */
8364 if (aic_get_residual(scb) == aic_get_transfer_length(scb)) {
6825 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) {
8365 ahd_update_neg_request(ahd, &devinfo,
8366 tstate, targ_info,
6826 ahd_update_neg_request(ahd, &devinfo,
6827 tstate, targ_info,
8367 AHD_NEG_IF_NON_ASYNC);
6828 /*force*/TRUE);
8368 }
8369 if (tstate->auto_negotiate & devinfo.target_mask) {
8370 hscb->control |= MK_MESSAGE;
8371 scb->flags &=
8372 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8373 scb->flags |= SCB_AUTO_NEGOTIATE;
8374 }
8375 hscb->cdb_len = sizeof(*sc);
8376 ahd_setup_data_scb(ahd, scb);
8377 scb->flags |= SCB_SENSE;
8378 ahd_queue_scb(ahd, scb);
6829 }
6830 if (tstate->auto_negotiate & devinfo.target_mask) {
6831 hscb->control |= MK_MESSAGE;
6832 scb->flags &=
6833 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
6834 scb->flags |= SCB_AUTO_NEGOTIATE;
6835 }
6836 hscb->cdb_len = sizeof(*sc);
6837 ahd_setup_data_scb(ahd, scb);
6838 scb->flags |= SCB_SENSE;
6839 ahd_queue_scb(ahd, scb);
6840#ifdef __FreeBSD__
8379 /*
8380 * Ensure we have enough time to actually
6841 /*
6842 * Ensure we have enough time to actually
8381 * retrieve the sense, but only schedule
8382 * the timer if we are not in recovery or
8383 * this is a recovery SCB that is allowed
8384 * to have an active timer.
6843 * retrieve the sense.
8385 */
6844 */
8386 if (ahd->scb_data.recovery_scbs == 0
8387 || (scb->flags & SCB_RECOVERY_SCB) != 0)
8388 aic_scb_timer_reset(scb, 5 * 1000);
6845 untimeout(ahd_timeout, (caddr_t)scb,
6846 scb->io_ctx->ccb_h.timeout_ch);
6847 scb->io_ctx->ccb_h.timeout_ch =
6848 timeout(ahd_timeout, (caddr_t)scb, 5 * hz);
6849#endif
8389 break;
8390 }
8391 case SCSI_STATUS_OK:
8392 printf("%s: Interrupted for staus of 0???\n",
8393 ahd_name(ahd));
8394 /* FALLTHROUGH */
8395 default:
8396 ahd_done(ahd, scb);

--- 25 unchanged lines hidden (view full) ---

8422 * last transfer, so sgptr was
8423 * never updated.
8424 * 5) We have a partial residual.
8425 * Use residual_sgptr to determine
8426 * where we are.
8427 */
8428
8429 hscb = scb->hscb;
6850 break;
6851 }
6852 case SCSI_STATUS_OK:
6853 printf("%s: Interrupted for staus of 0???\n",
6854 ahd_name(ahd));
6855 /* FALLTHROUGH */
6856 default:
6857 ahd_done(ahd, scb);

--- 25 unchanged lines hidden (view full) ---

6883 * last transfer, so sgptr was
6884 * never updated.
6885 * 5) We have a partial residual.
6886 * Use residual_sgptr to determine
6887 * where we are.
6888 */
6889
6890 hscb = scb->hscb;
8430 sgptr = aic_le32toh(hscb->sgptr);
6891 sgptr = ahd_le32toh(hscb->sgptr);
8431 if ((sgptr & SG_STATUS_VALID) == 0)
8432 /* Case 1 */
8433 return;
8434 sgptr &= ~SG_STATUS_VALID;
8435
8436 if ((sgptr & SG_LIST_NULL) != 0)
8437 /* Case 2 */
8438 return;
8439
8440 /*
8441 * Residual fields are the same in both
8442 * target and initiator status packets,
8443 * so we can always use the initiator fields
8444 * regardless of the role for this SCB.
8445 */
8446 spkt = &hscb->shared_data.istatus;
6892 if ((sgptr & SG_STATUS_VALID) == 0)
6893 /* Case 1 */
6894 return;
6895 sgptr &= ~SG_STATUS_VALID;
6896
6897 if ((sgptr & SG_LIST_NULL) != 0)
6898 /* Case 2 */
6899 return;
6900
6901 /*
6902 * Residual fields are the same in both
6903 * target and initiator status packets,
6904 * so we can always use the initiator fields
6905 * regardless of the role for this SCB.
6906 */
6907 spkt = &hscb->shared_data.istatus;
8447 resid_sgptr = aic_le32toh(spkt->residual_sgptr);
6908 resid_sgptr = ahd_le32toh(spkt->residual_sgptr);
8448 if ((sgptr & SG_FULL_RESID) != 0) {
8449 /* Case 3 */
6909 if ((sgptr & SG_FULL_RESID) != 0) {
6910 /* Case 3 */
8450 resid = aic_get_transfer_length(scb);
6911 resid = ahd_get_transfer_length(scb);
8451 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8452 /* Case 4 */
8453 return;
8454 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8455 ahd_print_path(ahd, scb);
8456 printf("data overrun detected Tag == 0x%x.\n",
8457 SCB_GET_TAG(scb));
8458 ahd_freeze_devq(ahd, scb);
6912 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6913 /* Case 4 */
6914 return;
6915 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
6916 ahd_print_path(ahd, scb);
6917 printf("data overrun detected Tag == 0x%x.\n",
6918 SCB_GET_TAG(scb));
6919 ahd_freeze_devq(ahd, scb);
8459 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8460 aic_freeze_scb(scb);
6920 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
6921 ahd_freeze_scb(scb);
8461 return;
8462 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8463 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
8464 /* NOTREACHED */
8465 } else {
8466 struct ahd_dma_seg *sg;
8467
8468 /*
8469 * Remainder of the SG where the transfer
8470 * stopped.
8471 */
6922 return;
6923 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6924 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6925 /* NOTREACHED */
6926 } else {
6927 struct ahd_dma_seg *sg;
6928
6929 /*
6930 * Remainder of the SG where the transfer
6931 * stopped.
6932 */
8472 resid = aic_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
6933 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8473 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8474
8475 /* The residual sg_ptr always points to the next sg */
8476 sg--;
8477
8478 /*
8479 * Add up the contents of all residual
8480 * SG segments that are after the SG where
8481 * the transfer stopped.
8482 */
6934 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
6935
6936 /* The residual sg_ptr always points to the next sg */
6937 sg--;
6938
6939 /*
6940 * Add up the contents of all residual
6941 * SG segments that are after the SG where
6942 * the transfer stopped.
6943 */
8483 while ((aic_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
6944 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8484 sg++;
6945 sg++;
8485 resid += aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
6946 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
8486 }
8487 }
8488 if ((scb->flags & SCB_SENSE) == 0)
6947 }
6948 }
6949 if ((scb->flags & SCB_SENSE) == 0)
8489 aic_set_residual(scb, resid);
6950 ahd_set_residual(scb, resid);
8490 else
6951 else
8491 aic_set_sense_residual(scb, resid);
6952 ahd_set_sense_residual(scb, resid);
8492
8493#ifdef AHD_DEBUG
8494 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8495 ahd_print_path(ahd, scb);
6953
6954#ifdef AHD_DEBUG
6955 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
6956 ahd_print_path(ahd, scb);
8496 printf("Handled %sResidual of %d bytes\n",
8497 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6957 printf("Handled Residual of %d bytes\n", resid);
8498 }
8499#endif
8500}
8501
8502/******************************* Target Mode **********************************/
8503#ifdef AHD_TARGET_MODE
8504/*
8505 * Add a target mode event to this lun's queue

--- 89 unchanged lines hidden (view full) ---

8595ahd_dumpseq(struct ahd_softc* ahd)
8596{
8597 int i;
8598 int max_prog;
8599
8600 max_prog = 2048;
8601
8602 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6958 }
6959#endif
6960}
6961
6962/******************************* Target Mode **********************************/
6963#ifdef AHD_TARGET_MODE
6964/*
6965 * Add a target mode event to this lun's queue

--- 89 unchanged lines hidden (view full) ---

7055ahd_dumpseq(struct ahd_softc* ahd)
7056{
7057 int i;
7058 int max_prog;
7059
7060 max_prog = 2048;
7061
7062 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8603 ahd_outw(ahd, PRGMCNT, 0);
7063 ahd_outb(ahd, PRGMCNT, 0);
7064 ahd_outb(ahd, PRGMCNT+1, 0);
8604 for (i = 0; i < max_prog; i++) {
8605 uint8_t ins_bytes[4];
8606
8607 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8608 printf("0x%08x\n", ins_bytes[0] << 24
8609 | ins_bytes[1] << 16
8610 | ins_bytes[2] << 8
8611 | ins_bytes[3]);

--- 12 unchanged lines hidden (view full) ---

8624 u_int cur_cs;
8625 u_int i;
8626 int downloaded;
8627 u_int skip_addr;
8628 u_int sg_prefetch_cnt;
8629 u_int sg_prefetch_cnt_limit;
8630 u_int sg_prefetch_align;
8631 u_int sg_size;
7065 for (i = 0; i < max_prog; i++) {
7066 uint8_t ins_bytes[4];
7067
7068 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
7069 printf("0x%08x\n", ins_bytes[0] << 24
7070 | ins_bytes[1] << 16
7071 | ins_bytes[2] << 8
7072 | ins_bytes[3]);

--- 12 unchanged lines hidden (view full) ---

7085 u_int cur_cs;
7086 u_int i;
7087 int downloaded;
7088 u_int skip_addr;
7089 u_int sg_prefetch_cnt;
7090 u_int sg_prefetch_cnt_limit;
7091 u_int sg_prefetch_align;
7092 u_int sg_size;
8632 u_int cacheline_mask;
8633 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8634
8635 if (bootverbose)
8636 printf("%s: Downloading Sequencer Program...",
8637 ahd_name(ahd));
8638
7093 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
7094
7095 if (bootverbose)
7096 printf("%s: Downloading Sequencer Program...",
7097 ahd_name(ahd));
7098
8639#if DOWNLOAD_CONST_COUNT != 8
7099#if DOWNLOAD_CONST_COUNT != 6
8640#error "Download Const Mismatch"
8641#endif
8642 /*
8643 * Start out with 0 critical sections
8644 * that apply to this firmware load.
8645 */
8646 cs_count = 0;
8647 cur_cs = 0;

--- 15 unchanged lines hidden (view full) ---

8663 * that doesn't contain any or all of the S/G of interest
8664 * within the bounds of our S/G ram. Provide variables to
8665 * the sequencer that will allow it to handle these edge
8666 * cases.
8667 */
8668 /* Start by aligning to the nearest cacheline. */
8669 sg_prefetch_align = ahd->pci_cachesize;
8670 if (sg_prefetch_align == 0)
7100#error "Download Const Mismatch"
7101#endif
7102 /*
7103 * Start out with 0 critical sections
7104 * that apply to this firmware load.
7105 */
7106 cs_count = 0;
7107 cur_cs = 0;

--- 15 unchanged lines hidden (view full) ---

7123 * that doesn't contain any or all of the S/G of interest
7124 * within the bounds of our S/G ram. Provide variables to
7125 * the sequencer that will allow it to handle these edge
7126 * cases.
7127 */
7128 /* Start by aligning to the nearest cacheline. */
7129 sg_prefetch_align = ahd->pci_cachesize;
7130 if (sg_prefetch_align == 0)
8671 sg_prefetch_align = 8;
7131 sg_prefetch_cnt = 8;
8672 /* Round down to the nearest power of 2. */
8673 while (powerof2(sg_prefetch_align) == 0)
8674 sg_prefetch_align--;
7132 /* Round down to the nearest power of 2. */
7133 while (powerof2(sg_prefetch_align) == 0)
7134 sg_prefetch_align--;
8675
8676 cacheline_mask = sg_prefetch_align - 1;
8677
8678 /*
8679 * If the cacheline boundary is greater than half our prefetch RAM
8680 * we risk not being able to fetch even a single complete S/G
8681 * segment if we align to that boundary.
8682 */
8683 if (sg_prefetch_align > CCSGADDR_MAX/2)
8684 sg_prefetch_align = CCSGADDR_MAX/2;
8685 /* Start by fetching a single cacheline. */

--- 22 unchanged lines hidden (view full) ---

8708 */
8709 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8710 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8711 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8712 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8713 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8714 download_consts[SG_SIZEOF] = sg_size;
8715 download_consts[PKT_OVERRUN_BUFOFFSET] =
7135 /*
7136 * If the cacheline boundary is greater than half our prefetch RAM
7137 * we risk not being able to fetch even a single complete S/G
7138 * segment if we align to that boundary.
7139 */
7140 if (sg_prefetch_align > CCSGADDR_MAX/2)
7141 sg_prefetch_align = CCSGADDR_MAX/2;
7142 /* Start by fetching a single cacheline. */

--- 22 unchanged lines hidden (view full) ---

7165 */
7166 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
7167 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
7168 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
7169 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
7170 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
7171 download_consts[SG_SIZEOF] = sg_size;
7172 download_consts[PKT_OVERRUN_BUFOFFSET] =
8716 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8717 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8718 download_consts[CACHELINE_MASK] = cacheline_mask;
7173 (AHD_SCB_MAX * sizeof(uint16_t)) / 256;
7174 if ((ahd->features & AHD_TARGETMODE) != 0)
7175 download_consts[PKT_OVERRUN_BUFOFFSET] +=
7176 (AHD_TMODE_CMDS * sizeof(struct target_cmd)) / 256;
7177
8719 cur_patch = patches;
8720 downloaded = 0;
8721 skip_addr = 0;
8722 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
7178 cur_patch = patches;
7179 downloaded = 0;
7180 skip_addr = 0;
7181 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8723 ahd_outw(ahd, PRGMCNT, 0);
7182 ahd_outb(ahd, PRGMCNT, 0);
7183 ahd_outb(ahd, PRGMCNT+1, 0);
8724
8725 for (i = 0; i < sizeof(seqprog)/4; i++) {
8726 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8727 /*
8728 * Don't download this instruction as it
8729 * is in a patch that was removed.
8730 */
8731 continue;

--- 29 unchanged lines hidden (view full) ---

8761 cs_count *= sizeof(struct cs);
8762 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
8763 if (ahd->critical_sections == NULL)
8764 panic("ahd_loadseq: Could not malloc");
8765 memcpy(ahd->critical_sections, cs_table, cs_count);
8766 }
8767 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8768
7184
7185 for (i = 0; i < sizeof(seqprog)/4; i++) {
7186 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
7187 /*
7188 * Don't download this instruction as it
7189 * is in a patch that was removed.
7190 */
7191 continue;

--- 29 unchanged lines hidden (view full) ---

7221 cs_count *= sizeof(struct cs);
7222 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
7223 if (ahd->critical_sections == NULL)
7224 panic("ahd_loadseq: Could not malloc");
7225 memcpy(ahd->critical_sections, cs_table, cs_count);
7226 }
7227 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
7228
8769 if (bootverbose) {
7229 if (bootverbose)
8770 printf(" %d instructions downloaded\n", downloaded);
7230 printf(" %d instructions downloaded\n", downloaded);
8771 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8772 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8773 }
8774}
8775
8776static int
8777ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8778 u_int start_instr, u_int *skip_addr)
8779{
8780 struct patch *cur_patch;
8781 struct patch *last_patch;

--- 62 unchanged lines hidden (view full) ---

8844 union ins_formats instr;
8845 struct ins_format1 *fmt1_ins;
8846 struct ins_format3 *fmt3_ins;
8847 u_int opcode;
8848
8849 /*
8850 * The firmware is always compiled into a little endian format.
8851 */
7231}
7232
7233static int
7234ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
7235 u_int start_instr, u_int *skip_addr)
7236{
7237 struct patch *cur_patch;
7238 struct patch *last_patch;

--- 62 unchanged lines hidden (view full) ---

7301 union ins_formats instr;
7302 struct ins_format1 *fmt1_ins;
7303 struct ins_format3 *fmt3_ins;
7304 u_int opcode;
7305
7306 /*
7307 * The firmware is always compiled into a little endian format.
7308 */
8852 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
7309 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8853
8854 fmt1_ins = &instr.format1;
8855 fmt3_ins = NULL;
8856
8857 /* Pull the opcode */
8858 opcode = instr.format1.opcode;
8859 switch (opcode) {
8860 case AIC_OP_JMP:

--- 31 unchanged lines hidden (view full) ---

8892 mask = 0x01 << i;
8893 if ((instr.integer & mask) != 0)
8894 count++;
8895 }
8896 if ((count & 0x01) == 0)
8897 instr.format1.parity = 1;
8898
8899 /* The sequencer is a little endian cpu */
7310
7311 fmt1_ins = &instr.format1;
7312 fmt3_ins = NULL;
7313
7314 /* Pull the opcode */
7315 opcode = instr.format1.opcode;
7316 switch (opcode) {
7317 case AIC_OP_JMP:

--- 31 unchanged lines hidden (view full) ---

7349 mask = 0x01 << i;
7350 if ((instr.integer & mask) != 0)
7351 count++;
7352 }
7353 if ((count & 0x01) == 0)
7354 instr.format1.parity = 1;
7355
7356 /* The sequencer is a little endian cpu */
8900 instr.integer = aic_htole32(instr.integer);
7357 instr.integer = ahd_htole32(instr.integer);
8901 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8902 break;
8903 }
8904 default:
8905 panic("Unknown opcode encountered in seq program");
8906 break;
8907 }
8908}
8909
7358 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
7359 break;
7360 }
7361 default:
7362 panic("Unknown opcode encountered in seq program");
7363 break;
7364 }
7365}
7366
8910static int
8911ahd_probe_stack_size(struct ahd_softc *ahd)
8912{
8913 int last_probe;
8914
8915 last_probe = 0;
8916 while (1) {
8917 int i;
8918
8919 /*
8920 * We avoid using 0 as a pattern to avoid
8921 * confusion if the stack implementation
8922 * "back-fills" with zeros when "poping'
8923 * entries.
8924 */
8925 for (i = 1; i <= last_probe+1; i++) {
8926 ahd_outb(ahd, STACK, i & 0xFF);
8927 ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8928 }
8929
8930 /* Verify */
8931 for (i = last_probe+1; i > 0; i--) {
8932 u_int stack_entry;
8933
8934 stack_entry = ahd_inb(ahd, STACK)
8935 |(ahd_inb(ahd, STACK) << 8);
8936 if (stack_entry != i)
8937 goto sized;
8938 }
8939 last_probe++;
8940 }
8941sized:
8942 return (last_probe);
8943}
8944
8945void
7367void
8946ahd_dump_all_cards_state(void)
7368ahd_dump_all_cards_state()
8947{
8948 struct ahd_softc *list_ahd;
8949
8950 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
8951 ahd_dump_card_state(list_ahd);
8952 }
8953}
8954
7369{
7370 struct ahd_softc *list_ahd;
7371
7372 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
7373 ahd_dump_card_state(list_ahd);
7374 }
7375}
7376
8955int
8956ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8957 const char *name, u_int address, u_int value,
8958 u_int *cur_column, u_int wrap_point)
8959{
8960 int printed;
8961 u_int printed_mask;
8962 u_int dummy_column;
8963
8964 if (cur_column == NULL) {
8965 dummy_column = 0;
8966 cur_column = &dummy_column;
8967 }
8968
8969 if (cur_column != NULL && *cur_column >= wrap_point) {
8970 printf("\n");
8971 *cur_column = 0;
8972 }
8973 printed = printf("%s[0x%x]", name, value);
8974 if (table == NULL) {
8975 printed += printf(" ");
8976 *cur_column += printed;
8977 return (printed);
8978 }
8979 printed_mask = 0;
8980 while (printed_mask != 0xFF) {
8981 int entry;
8982
8983 for (entry = 0; entry < num_entries; entry++) {
8984 if (((value & table[entry].mask)
8985 != table[entry].value)
8986 || ((printed_mask & table[entry].mask)
8987 == table[entry].mask))
8988 continue;
8989
8990 printed += printf("%s%s",
8991 printed_mask == 0 ? ":(" : "|",
8992 table[entry].name);
8993 printed_mask |= table[entry].mask;
8994
8995 break;
8996 }
8997 if (entry >= num_entries)
8998 break;
8999 }
9000 if (printed_mask != 0)
9001 printed += printf(") ");
9002 else
9003 printed += printf(" ");
9004 *cur_column += printed;
9005 return (printed);
9006}
9007
9008void
9009ahd_dump_card_state(struct ahd_softc *ahd)
9010{
9011 struct scb *scb;
9012 ahd_mode_state saved_modes;
9013 u_int dffstat;
9014 int paused;
9015 u_int scb_index;
7377void
7378ahd_dump_card_state(struct ahd_softc *ahd)
7379{
7380 struct scb *scb;
7381 ahd_mode_state saved_modes;
7382 u_int dffstat;
7383 int paused;
7384 u_int scb_index;
9016 u_int saved_scb_index;
9017 u_int cur_col;
9018 int i;
7385 u_int i;
9019
9020 if (ahd_is_paused(ahd)) {
9021 paused = 1;
9022 } else {
9023 paused = 0;
9024 ahd_pause(ahd);
9025 }
9026 saved_modes = ahd_save_modes(ahd);
9027 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7386
7387 if (ahd_is_paused(ahd)) {
7388 paused = 1;
7389 } else {
7390 paused = 0;
7391 ahd_pause(ahd);
7392 }
7393 saved_modes = ahd_save_modes(ahd);
7394 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9028 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
9029 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
7395 printf("%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
9030 ahd_name(ahd),
7396 ahd_name(ahd),
9031 ahd_inw(ahd, CURADDR),
7397 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8),
9032 ahd_build_mode_state(ahd, ahd->saved_src_mode,
9033 ahd->saved_dst_mode));
7398 ahd_build_mode_state(ahd, ahd->saved_src_mode,
7399 ahd->saved_dst_mode));
7400 printf("Softc pointer is %p\n", ahd);
7401 printf("IOWNID == 0x%x, TOWNID == 0x%x, SCSISEQ1 == 0x%x\n",
7402 ahd_inb(ahd, IOWNID), ahd_inb(ahd, TOWNID),
7403 ahd_inb(ahd, SCSISEQ1));
7404 printf("SCSISIGI == 0x%x\n", ahd_inb(ahd, SCSISIGI));
7405 printf("QFREEZE_COUNT == %d, SEQ_FLAGS2 == 0x%x\n",
7406 ahd_inw(ahd, QFREEZE_COUNT), ahd_inb(ahd, SEQ_FLAGS2));
9034 if (paused)
9035 printf("Card was paused\n");
7407 if (paused)
7408 printf("Card was paused\n");
9036
9037 if (ahd_check_cmdcmpltqueues(ahd))
9038 printf("Completions are pending\n");
9039
9040 /*
9041 * Mode independent registers.
9042 */
9043 cur_col = 0;
9044 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
9045 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
9046 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
9047 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
9048 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
9049 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
9050 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
9051 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
9052 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
9053 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
9054 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
9055 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
9056 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
9057 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
9058 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
9059 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
9060 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
9061 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
9062 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
9063 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
9064 &cur_col, 50);
9065 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
9066 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
9067 &cur_col, 50);
9068 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
9069 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
9070 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
9071 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
9072 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
9073 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
9074 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
9075 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
9076 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
9077 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
9078 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
9079 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
7409 printf("%s: LASTSCB 0x%x CURRSCB 0x%x NEXTSCB 0x%x SEQINTCTL 0x%x\n",
7410 ahd_name(ahd), ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
7411 ahd_inw(ahd, NEXTSCB), ahd_inb(ahd, SEQINTCTL));
7412 printf("SCSISEQ = 0x%x\n", ahd_inb(ahd, SCSISEQ0));
7413 printf("SCB count = %d\n", ahd->scb_data.numscbs);
7414 printf("Kernel NEXTQSCB = %d\n", SCB_GET_TAG(ahd->next_queued_scb));
7415 printf("%s: LQCTL1 = 0x%x\n",
7416 ahd_name(ahd), ahd_inb(ahd, LQCTL1));
7417 printf("%s: WAITING_TID_LIST == 0x%x:0x%x\n",
7418 ahd_name(ahd), ahd_inw(ahd, WAITING_TID_HEAD),
7419 ahd_inw(ahd, WAITING_TID_TAIL));
7420 printf("%s: WAITING_SCB_TAILS: ", ahd_name(ahd));
7421 for (i = 0; i < AHD_NUM_TARGETS; i++) {
7422 printf("%d(0x%x) ", i,
7423 ahd_inw(ahd, WAITING_SCB_TAILS + (2 * i)));
7424 }
9080 printf("\n");
7425 printf("\n");
9081 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
9082 "CURRSCB 0x%x NEXTSCB 0x%x\n",
9083 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
9084 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
9085 ahd_inw(ahd, NEXTSCB));
9086 cur_col = 0;
9087 /* QINFIFO */
9088 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
9089 CAM_LUN_WILDCARD, SCB_LIST_NULL,
9090 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
7426 /* QINFIFO */
7427 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
7428 CAM_LUN_WILDCARD, SCB_LIST_NULL,
7429 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
9091 saved_scb_index = ahd_get_scbptr(ahd);
9092 printf("Pending list:");
7430 printf("Pending list:\n");
9093 i = 0;
9094 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
9095 if (i++ > AHD_SCB_MAX)
9096 break;
7431 i = 0;
7432 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7433 if (i++ > AHD_SCB_MAX)
7434 break;
9097 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
9098 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
7435 if (scb != LIST_FIRST(&ahd->pending_scbs))
7436 printf(", ");
7437 printf("%3d", SCB_GET_TAG(scb));
9099 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
7438 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9100 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
9101 &cur_col, 60);
9102 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
9103 &cur_col, 60);
7439 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x,"
7440 " RSG 0x%x, KSG 0x%x)\n",
7441 ahd_inb(ahd, SCB_CONTROL),
7442 ahd_inb(ahd, SCB_SCSIID), ahd_inw(ahd, SCB_NEXT),
7443 ahd_inw(ahd, SCB_NEXT2), ahd_inl(ahd, SCB_SGPTR),
7444 ahd_inl(ahd, SCB_RESIDUAL_SGPTR),
7445 ahd_le32toh(scb->hscb->sgptr));
9104 }
7446 }
9105 printf("\nTotal %d\n", i);
7447 printf("\n");
9106
7448
9107 printf("Kernel Free SCB lists: ");
7449 printf("Kernel Free SCB list: ");
9108 i = 0;
7450 i = 0;
9109 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
9110 struct scb *list_scb;
9111
9112 printf("\n COLIDX[%d]: ", AHD_GET_SCB_COL_IDX(ahd, scb));
9113 list_scb = scb;
9114 do {
9115 printf("%d ", SCB_GET_TAG(list_scb));
9116 list_scb = LIST_NEXT(list_scb, collision_links);
9117 } while (list_scb && i++ < AHD_SCB_MAX);
9118 }
9119
9120 printf("\n Any Device: ");
9121 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
7451 SLIST_FOREACH(scb, &ahd->scb_data.free_scbs, links.sle) {
9122 if (i++ > AHD_SCB_MAX)
9123 break;
9124 printf("%d ", SCB_GET_TAG(scb));
9125 }
9126 printf("\n");
9127
9128 printf("Sequencer Complete DMA-inprog list: ");
9129 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
9130 i = 0;
9131 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9132 ahd_set_scbptr(ahd, scb_index);
9133 printf("%d ", scb_index);
7452 if (i++ > AHD_SCB_MAX)
7453 break;
7454 printf("%d ", SCB_GET_TAG(scb));
7455 }
7456 printf("\n");
7457
7458 printf("Sequencer Complete DMA-inprog list: ");
7459 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
7460 i = 0;
7461 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
7462 ahd_set_scbptr(ahd, scb_index);
7463 printf("%d ", scb_index);
9134 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
7464 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE);
9135 }
9136 printf("\n");
9137
9138 printf("Sequencer Complete list: ");
9139 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
9140 i = 0;
9141 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9142 ahd_set_scbptr(ahd, scb_index);
9143 printf("%d ", scb_index);
7465 }
7466 printf("\n");
7467
7468 printf("Sequencer Complete list: ");
7469 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
7470 i = 0;
7471 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
7472 ahd_set_scbptr(ahd, scb_index);
7473 printf("%d ", scb_index);
9144 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
7474 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE);
9145 }
9146 printf("\n");
9147
9148
9149 printf("Sequencer DMA-Up and Complete list: ");
9150 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
9151 i = 0;
9152 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9153 ahd_set_scbptr(ahd, scb_index);
9154 printf("%d ", scb_index);
7475 }
7476 printf("\n");
7477
7478
7479 printf("Sequencer DMA-Up and Complete list: ");
7480 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
7481 i = 0;
7482 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
7483 ahd_set_scbptr(ahd, scb_index);
7484 printf("%d ", scb_index);
9155 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
7485 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE);
9156 }
9157 printf("\n");
7486 }
7487 printf("\n");
9158 printf("Sequencer On QFreeze and Complete list: ");
9159 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
9160 i = 0;
9161 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9162 ahd_set_scbptr(ahd, scb_index);
9163 printf("%d ", scb_index);
9164 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9165 }
9166 printf("\n");
9167 ahd_set_scbptr(ahd, saved_scb_index);
7488 printf("%s: SIMODE1 = 0x%x\n",
7489 ahd_name(ahd), ahd_inb(ahd, SIMODE1));
7490 printf("%s: LQISTAT0 = 0x%x, LQISTAT1 = 0x%x, LQISTAT2 = 0x%x\n",
7491 ahd_name(ahd), ahd_inb(ahd, LQISTAT0), ahd_inb(ahd, LQISTAT1),
7492 ahd_inb(ahd, LQISTAT2));
7493 printf("%s: LQOSTAT0 = 0x%x, LQOSTAT1 = 0x%x, LQOSTAT2 = 0x%x\n",
7494 ahd_name(ahd), ahd_inb(ahd, LQOSTAT0), ahd_inb(ahd, LQOSTAT1),
7495 ahd_inb(ahd, LQOSTAT2));
9168 dffstat = ahd_inb(ahd, DFFSTAT);
9169 for (i = 0; i < 2; i++) {
7496 dffstat = ahd_inb(ahd, DFFSTAT);
7497 for (i = 0; i < 2; i++) {
9170#ifdef AHD_DEBUG
9171 struct scb *fifo_scb;
7498 struct scb *fifo_scb;
9172#endif
9173 u_int fifo_scbptr;
9174
9175 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
7499 u_int fifo_scbptr;
7500
7501 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
9176 fifo_scbptr = ahd_get_scbptr(ahd);
9177 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
7502 fifo_scbptr = ahd_inb(ahd, SCBPTR);
7503 printf("%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x, LJSCB 0x%x\n",
9178 ahd_name(ahd), i,
9179 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
7504 ahd_name(ahd), i,
7505 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
9180 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
9181 cur_col = 0;
9182 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
9183 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
9184 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
9185 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
9186 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
9187 &cur_col, 50);
9188 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
9189 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
9190 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
9191 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
9192 if (cur_col > 50) {
9193 printf("\n");
9194 cur_col = 0;
9195 }
9196 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9197 ahd_inl(ahd, SHADDR+4),
9198 ahd_inl(ahd, SHADDR),
9199 (ahd_inb(ahd, SHCNT)
9200 | (ahd_inb(ahd, SHCNT + 1) << 8)
9201 | (ahd_inb(ahd, SHCNT + 2) << 16)));
9202 if (cur_col > 50) {
9203 printf("\n");
9204 cur_col = 0;
9205 }
9206 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ",
9207 ahd_inl(ahd, HADDR+4),
9208 ahd_inl(ahd, HADDR),
9209 (ahd_inb(ahd, HCNT)
9210 | (ahd_inb(ahd, HCNT + 1) << 8)
9211 | (ahd_inb(ahd, HCNT + 2) << 16)));
9212 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
9213#ifdef AHD_DEBUG
9214 if ((ahd_debug & AHD_SHOW_SG) != 0) {
9215 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
9216 if (fifo_scb != NULL)
9217 ahd_dump_sglist(fifo_scb);
9218 }
9219#endif
7506 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr,
7507 ahd_inw(ahd, LONGJMP_SCB));
7508 printf("%s: SEQIMODE == 0x%x, SEQINTSRC == 0x%x\n",
7509 ahd_name(ahd), ahd_inb(ahd, SEQIMODE),
7510 ahd_inb(ahd, SEQINTSRC));
7511 printf("%s: DFCNTRL == 0x%x, DFSTATUS == 0x%x, "
7512 "SG_CACHE_SHADOW = 0x%x, SG_STATE = 0x%x\n",
7513 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
7514 ahd_inb(ahd, DFSTATUS), ahd_inb(ahd, SG_CACHE_SHADOW),
7515 ahd_inb(ahd, SG_STATE));
7516 printf("SSTAT0 = 0x%x, SSTAT1 = 0x%x, SSTAT2 = 0x%x\n",
7517 ahd_inb(ahd, SSTAT0), ahd_inb(ahd, SSTAT1),
7518 ahd_inb(ahd, SSTAT2));
7519 printf("DFFSXFRCTL = 0x%x, SOFFCNT = 0x%x\n",
7520 ahd_inb(ahd, DFFSXFRCTL), ahd_inb(ahd, SOFFCNT));
7521 printf("MDFFSTAT = 0x%x, SHADDR = 0x%x, SHCNT = 0x%x\n",
7522 ahd_inb(ahd, MDFFSTAT), ahd_inl(ahd, SHADDR),
7523 (ahd_inb(ahd, SHCNT)
7524 | (ahd_inb(ahd, SHCNT + 1) << 8)
7525 | (ahd_inb(ahd, SHCNT + 2) << 16)));
7526 printf("HADDR = 0x%x, HCNT = 0x%x\n",
7527 ahd_inl(ahd, HADDR),
7528 (ahd_inb(ahd, HCNT)
7529 | (ahd_inb(ahd, HCNT + 1) << 8)
7530 | (ahd_inb(ahd, HCNT + 2) << 16)));
7531 printf("CCSGCTL = 0x%x\n", ahd_inb(ahd, CCSGCTL));
7532 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
7533 if (fifo_scb != NULL)
7534 ahd_dump_sglist(fifo_scb);
9220 }
7535 }
9221 printf("\nLQIN: ");
7536 printf("LQIN: ");
9222 for (i = 0; i < 20; i++)
9223 printf("0x%x ", ahd_inb(ahd, LQIN + i));
9224 printf("\n");
7537 for (i = 0; i < 20; i++)
7538 printf("0x%x ", ahd_inb(ahd, LQIN + i));
7539 printf("\n");
7540 printf("%s: SSTAT3 == 0x%x\n", ahd_name(ahd), ahd_inb(ahd, SSTAT3));
9225 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
9226 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9227 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
9228 ahd_inb(ahd, OPTIONMODE));
9229 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9230 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
9231 ahd_inb(ahd, MAXCMDCNT));
7541 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
7542 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
7543 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
7544 ahd_inb(ahd, OPTIONMODE));
7545 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
7546 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
7547 ahd_inb(ahd, MAXCMDCNT));
9232 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9233 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
9234 ahd_inb(ahd, SAVED_LUN));
9235 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
9236 printf("\n");
9237 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
9238 cur_col = 0;
9239 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
9240 printf("\n");
9241 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
9242 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9243 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
9244 ahd_inw(ahd, DINDEX));
9245 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
7548 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
7549 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
7550 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
7551 ahd_inw(ahd, DINDEX));
7552 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9246 ahd_name(ahd), ahd_get_scbptr(ahd),
9247 ahd_inw_scbram(ahd, SCB_NEXT),
9248 ahd_inw_scbram(ahd, SCB_NEXT2));
7553 ahd_name(ahd), ahd_get_scbptr(ahd), ahd_inw(ahd, SCB_NEXT),
7554 ahd_inw(ahd, SCB_NEXT2));
9249 printf("CDB %x %x %x %x %x %x\n",
7555 printf("CDB %x %x %x %x %x %x\n",
9250 ahd_inb_scbram(ahd, SCB_CDB_STORE),
9251 ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
9252 ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
9253 ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
9254 ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
9255 ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
7556 ahd_inb(ahd, SCB_CDB_STORE),
7557 ahd_inb(ahd, SCB_CDB_STORE+1),
7558 ahd_inb(ahd, SCB_CDB_STORE+2),
7559 ahd_inb(ahd, SCB_CDB_STORE+3),
7560 ahd_inb(ahd, SCB_CDB_STORE+4),
7561 ahd_inb(ahd, SCB_CDB_STORE+5));
9256 printf("STACK:");
7562 printf("STACK:");
9257 for (i = 0; i < ahd->stack_size; i++) {
9258 ahd->saved_stack[i] =
9259 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
9260 printf(" 0x%x", ahd->saved_stack[i]);
9261 }
9262 for (i = ahd->stack_size-1; i >= 0; i--) {
9263 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
9264 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
9265 }
9266 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
7563 for(i = 0; i < SEQ_STACK_SIZE; i++)
7564 printf(" 0x%x", ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8));
7565 printf("\n");
9267 ahd_platform_dump_card_state(ahd);
9268 ahd_restore_modes(ahd, saved_modes);
9269 if (paused == 0)
9270 ahd_unpause(ahd);
9271}
9272
9273void
9274ahd_dump_scbs(struct ahd_softc *ahd)
9275{
9276 ahd_mode_state saved_modes;
7566 ahd_platform_dump_card_state(ahd);
7567 ahd_restore_modes(ahd, saved_modes);
7568 if (paused == 0)
7569 ahd_unpause(ahd);
7570}
7571
7572void
7573ahd_dump_scbs(struct ahd_softc *ahd)
7574{
7575 ahd_mode_state saved_modes;
9277 u_int saved_scb_index;
9278 int i;
9279
9280 saved_modes = ahd_save_modes(ahd);
9281 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7576 int i;
7577
7578 saved_modes = ahd_save_modes(ahd);
7579 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9282 saved_scb_index = ahd_get_scbptr(ahd);
9283 for (i = 0; i < AHD_SCB_MAX; i++) {
9284 ahd_set_scbptr(ahd, i);
9285 printf("%3d", i);
9286 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
7580 for (i = 0; i < AHD_SCB_MAX; i++) {
7581 ahd_set_scbptr(ahd, i);
7582 printf("%3d", i);
7583 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9287 ahd_inb_scbram(ahd, SCB_CONTROL),
9288 ahd_inb_scbram(ahd, SCB_SCSIID),
9289 ahd_inw_scbram(ahd, SCB_NEXT),
9290 ahd_inw_scbram(ahd, SCB_NEXT2),
9291 ahd_inl_scbram(ahd, SCB_SGPTR),
9292 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
7584 ahd_inb(ahd, SCB_CONTROL),
7585 ahd_inb(ahd, SCB_SCSIID), ahd_inw(ahd, SCB_NEXT),
7586 ahd_inw(ahd, SCB_NEXT2), ahd_inl(ahd, SCB_SGPTR),
7587 ahd_inl(ahd, SCB_RESIDUAL_SGPTR));
9293 }
9294 printf("\n");
7588 }
7589 printf("\n");
9295 ahd_set_scbptr(ahd, saved_scb_index);
9296 ahd_restore_modes(ahd, saved_modes);
9297}
9298
7590 ahd_restore_modes(ahd, saved_modes);
7591}
7592
9299
9300/*************************** Timeout Handling *********************************/
9301void
9302ahd_timeout(struct scb *scb)
9303{
9304 struct ahd_softc *ahd;
9305
9306 ahd = scb->ahd_softc;
9307 if ((scb->flags & SCB_ACTIVE) != 0) {
9308 if ((scb->flags & SCB_TIMEDOUT) == 0) {
9309 LIST_INSERT_HEAD(&ahd->timedout_scbs, scb,
9310 timedout_links);
9311 scb->flags |= SCB_TIMEDOUT;
9312 }
9313 ahd_wakeup_recovery_thread(ahd);
9314 }
9315}
9316
9317/*
9318 * ahd_recover_commands determines if any of the commands that have currently
9319 * timedout are the root cause for this timeout. Innocent commands are given
9320 * a new timeout while we wait for the command executing on the bus to timeout.
9321 * This routine is invoked from a thread context so we are allowed to sleep.
9322 * Our lock is not held on entry.
9323 */
9324void
9325ahd_recover_commands(struct ahd_softc *ahd)
9326{
9327 struct scb *scb;
9328 struct scb *active_scb;
9329 int found;
9330 int was_paused;
9331 u_int active_scbptr;
9332 u_int last_phase;
9333
9334 /*
9335 * Pause the controller and manually flush any
9336 * commands that have just completed but that our
9337 * interrupt handler has yet to see.
9338 */
9339 was_paused = ahd_is_paused(ahd);
9340
9341 printf("%s: Recovery Initiated - Card was %spaused\n", ahd_name(ahd),
9342 was_paused ? "" : "not ");
9343 AHD_CORRECTABLE_ERROR(ahd);
9344 ahd_dump_card_state(ahd);
9345
9346 ahd_pause_and_flushwork(ahd);
9347
9348 if (LIST_EMPTY(&ahd->timedout_scbs) != 0) {
9349 /*
9350 * The timedout commands have already
9351 * completed. This typically means
9352 * that either the timeout value was on
9353 * the hairy edge of what the device
9354 * requires or - more likely - interrupts
9355 * are not happening.
9356 */
9357 printf("%s: Timedout SCBs already complete. "
9358 "Interrupts may not be functioning.\n", ahd_name(ahd));
9359 ahd_unpause(ahd);
9360 return;
9361 }
9362
9363 /*
9364 * Determine identity of SCB acting on the bus.
9365 * This test only catches non-packetized transactions.
9366 * Due to the fleeting nature of packetized operations,
9367 * we can't easily determine that a packetized operation
9368 * is on the bus.
9369 */
9370 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9371 last_phase = ahd_inb(ahd, LASTPHASE);
9372 active_scbptr = ahd_get_scbptr(ahd);
9373 active_scb = NULL;
9374 if (last_phase != P_BUSFREE
9375 || (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0)
9376 active_scb = ahd_lookup_scb(ahd, active_scbptr);
9377
9378 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9379 int target;
9380 int lun;
9381 char channel;
9382
9383 target = SCB_GET_TARGET(ahd, scb);
9384 channel = SCB_GET_CHANNEL(ahd, scb);
9385 lun = SCB_GET_LUN(scb);
9386
9387 ahd_print_path(ahd, scb);
9388 printf("SCB %d - timed out\n", SCB_GET_TAG(scb));
9389
9390 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
9391 /*
9392 * Been down this road before.
9393 * Do a full bus reset.
9394 */
9395 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
9396bus_reset:
9397 found = ahd_reset_channel(ahd, channel,
9398 /*Initiate Reset*/TRUE);
9399 printf("%s: Issued Channel %c Bus Reset. "
9400 "%d SCBs aborted\n", ahd_name(ahd), channel,
9401 found);
9402 continue;
9403 }
9404
9405 /*
9406 * Remove the command from the timedout list in
9407 * preparation for requeing it.
9408 */
9409 LIST_REMOVE(scb, timedout_links);
9410 scb->flags &= ~SCB_TIMEDOUT;
9411
9412 if (active_scb != NULL) {
9413
9414 if (active_scb != scb) {
9415
9416 /*
9417 * If the active SCB is not us, assume that
9418 * the active SCB has a longer timeout than
9419 * the timedout SCB, and wait for the active
9420 * SCB to timeout. As a safeguard, only
9421 * allow this deferral to continue if some
9422 * untimed-out command is outstanding.
9423 */
9424 if (ahd_other_scb_timeout(ahd, scb,
9425 active_scb) == 0)
9426 goto bus_reset;
9427 continue;
9428 }
9429
9430 /*
9431 * We're active on the bus, so assert ATN
9432 * and hope that the target responds.
9433 */
9434 ahd_set_recoveryscb(ahd, active_scb);
9435 active_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET;
9436 ahd_outb(ahd, MSG_OUT, HOST_MSG);
9437 ahd_outb(ahd, SCSISIGO, last_phase|ATNO);
9438 ahd_print_path(ahd, active_scb);
9439 printf("BDR message in message buffer\n");
9440 aic_scb_timer_reset(scb, 2 * 1000);
9441 break;
9442 } else if (last_phase != P_BUSFREE
9443 && ahd_inb(ahd, SCSIPHASE) == 0) {
9444 /*
9445 * SCB is not identified, there
9446 * is no pending REQ, and the sequencer
9447 * has not seen a busfree. Looks like
9448 * a stuck connection waiting to
9449 * go busfree. Reset the bus.
9450 */
9451 printf("%s: Connection stuck awaiting busfree or "
9452 "Identify Msg.\n", ahd_name(ahd));
9453 goto bus_reset;
9454 } else if (ahd_search_qinfifo(ahd, target, channel, lun,
9455 SCB_GET_TAG(scb),
9456 ROLE_INITIATOR, /*status*/0,
9457 SEARCH_COUNT) > 0) {
9458
9459 /*
9460 * We haven't even gone out on the bus
9461 * yet, so the timeout must be due to
9462 * some other command. Reset the timer
9463 * and go on.
9464 */
9465 if (ahd_other_scb_timeout(ahd, scb, NULL) == 0)
9466 goto bus_reset;
9467 } else {
9468 /*
9469 * This SCB is for a disconnected transaction
9470 * and we haven't found a better candidate on
9471 * the bus to explain this timeout.
9472 */
9473 ahd_set_recoveryscb(ahd, scb);
9474
9475 /*
9476 * Actually re-queue this SCB in an attempt
9477 * to select the device before it reconnects.
9478 * In either case (selection or reselection),
9479 * we will now issue a target reset to the
9480 * timed-out device.
9481 */
9482 scb->flags |= SCB_DEVICE_RESET;
9483 scb->hscb->cdb_len = 0;
9484 scb->hscb->task_attribute = 0;
9485 scb->hscb->task_management = SIU_TASKMGMT_ABORT_TASK;
9486
9487 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9488 if ((scb->flags & SCB_PACKETIZED) != 0) {
9489 /*
9490 * Mark the SCB has having an outstanding
9491 * task management function. Should the command
9492 * complete normally before the task management
9493 * function can be sent, the host will be
9494 * notified to abort our requeued SCB.
9495 */
9496 ahd_outb(ahd, SCB_TASK_MANAGEMENT,
9497 scb->hscb->task_management);
9498 } else {
9499 /*
9500 * If non-packetized, set the MK_MESSAGE control
9501 * bit indicating that we desire to send a
9502 * message. We also set the disconnected flag
9503 * since there is no guarantee that our SCB
9504 * control byte matches the version on the
9505 * card. We don't want the sequencer to abort
9506 * the command thinking an unsolicited
9507 * reselection occurred.
9508 */
9509 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
9510
9511 /*
9512 * The sequencer will never re-reference the
9513 * in-core SCB. To make sure we are notified
9514 * during reslection, set the MK_MESSAGE flag in
9515 * the card's copy of the SCB.
9516 */
9517 ahd_outb(ahd, SCB_CONTROL,
9518 ahd_inb(ahd, SCB_CONTROL)|MK_MESSAGE);
9519 }
9520
9521 /*
9522 * Clear out any entries in the QINFIFO first
9523 * so we are the next SCB for this target
9524 * to run.
9525 */
9526 ahd_search_qinfifo(ahd, target, channel, lun,
9527 SCB_LIST_NULL, ROLE_INITIATOR,
9528 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
9529 ahd_qinfifo_requeue_tail(ahd, scb);
9530 ahd_set_scbptr(ahd, active_scbptr);
9531 ahd_print_path(ahd, scb);
9532 printf("Queuing a BDR SCB\n");
9533 aic_scb_timer_reset(scb, 2 * 1000);
9534 break;
9535 }
9536 }
9537
9538 /*
9539 * Any remaining SCBs were not the "culprit", so remove
9540 * them from the timeout list. The timer for these commands
9541 * will be reset once the recovery SCB completes.
9542 */
9543 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9544
9545 LIST_REMOVE(scb, timedout_links);
9546 scb->flags &= ~SCB_TIMEDOUT;
9547 }
9548
9549 ahd_unpause(ahd);
9550}
9551
9552/*
9553 * Re-schedule a timeout for the passed in SCB if we determine that some
9554 * other SCB is in the process of recovery or an SCB with a longer
9555 * timeout is still pending. Limit our search to just "other_scb"
9556 * if it is non-NULL.
9557 */
9558static int
9559ahd_other_scb_timeout(struct ahd_softc *ahd, struct scb *scb,
9560 struct scb *other_scb)
9561{
9562 u_int newtimeout;
9563 int found;
9564
9565 ahd_print_path(ahd, scb);
9566 printf("Other SCB Timeout%s",
9567 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
9568 ? " again\n" : "\n");
9569
9570 AHD_UNCORRECTABLE_ERROR(ahd);
9571 newtimeout = aic_get_timeout(scb);
9572 scb->flags |= SCB_OTHERTCL_TIMEOUT;
9573 found = 0;
9574 if (other_scb != NULL) {
9575 if ((other_scb->flags
9576 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9577 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9578 found++;
9579 newtimeout = MAX(aic_get_timeout(other_scb),
9580 newtimeout);
9581 }
9582 } else {
9583 LIST_FOREACH(other_scb, &ahd->pending_scbs, pending_links) {
9584 if ((other_scb->flags
9585 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9586 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9587 found++;
9588 newtimeout = MAX(aic_get_timeout(other_scb),
9589 newtimeout);
9590 }
9591 }
9592 }
9593
9594 if (found != 0)
9595 aic_scb_timer_reset(scb, newtimeout);
9596 else {
9597 ahd_print_path(ahd, scb);
9598 printf("No other SCB worth waiting for...\n");
9599 }
9600
9601 return (found != 0);
9602}
9603
9604/**************************** Flexport Logic **********************************/
9605/*
9606 * Read count 16bit words from 16bit word address start_addr from the
9607 * SEEPROM attached to the controller, into buf, using the controller's
7593/**************************** Flexport Logic **********************************/
7594/*
7595 * Read count 16bit words from 16bit word address start_addr from the
7596 * SEEPROM attached to the controller, into buf, using the controller's
9608 * SEEPROM reading state machine. Optionally treat the data as a byte
9609 * stream in terms of byte order.
7597 * SEEPROM reading state machine.
9610 */
9611int
9612ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
7598 */
7599int
7600ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9613 u_int start_addr, u_int count, int bytestream)
7601 u_int start_addr, u_int count)
9614{
9615 u_int cur_addr;
9616 u_int end_addr;
9617 int error;
9618
9619 /*
9620 * If we never make it through the loop even once,
9621 * we were passed invalid arguments.
9622 */
9623 error = EINVAL;
9624 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9625 end_addr = start_addr + count;
9626 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
7602{
7603 u_int cur_addr;
7604 u_int end_addr;
7605 int error;
7606
7607 /*
7608 * If we never make it through the loop even once,
7609 * we were passed invalid arguments.
7610 */
7611 error = EINVAL;
7612 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7613 end_addr = start_addr + count;
7614 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9627
9628 ahd_outb(ahd, SEEADR, cur_addr);
9629 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9630
9631 error = ahd_wait_seeprom(ahd);
9632 if (error)
9633 break;
7615 ahd_outb(ahd, SEEADR, cur_addr);
7616 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
7617
7618 error = ahd_wait_seeprom(ahd);
7619 if (error)
7620 break;
9634 if (bytestream != 0) {
9635 uint8_t *bytestream_ptr;
9636
9637 bytestream_ptr = (uint8_t *)buf;
9638 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9639 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9640 } else {
9641 /*
9642 * ahd_inw() already handles machine byte order.
9643 */
9644 *buf = ahd_inw(ahd, SEEDAT);
9645 }
9646 buf++;
7621 *buf++ = ahd_inw(ahd, SEEDAT);
9647 }
9648 return (error);
9649}
9650
9651/*
9652 * Write count 16bit words from buf, into SEEPROM attache to the
9653 * controller starting at 16bit word address start_addr, using the
9654 * controller's SEEPROM writing state machine.

--- 47 unchanged lines hidden (view full) ---

9702/*
9703 * Wait ~100us for the serial eeprom to satisfy our request.
9704 */
9705int
9706ahd_wait_seeprom(struct ahd_softc *ahd)
9707{
9708 int cnt;
9709
7622 }
7623 return (error);
7624}
7625
7626/*
7627 * Write count 16bit words from buf, into SEEPROM attache to the
7628 * controller starting at 16bit word address start_addr, using the
7629 * controller's SEEPROM writing state machine.

--- 47 unchanged lines hidden (view full) ---

7677/*
7678 * Wait ~100us for the serial eeprom to satisfy our request.
7679 */
7680int
7681ahd_wait_seeprom(struct ahd_softc *ahd)
7682{
7683 int cnt;
7684
9710 cnt = 5000;
7685 cnt = 20;
9711 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
7686 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9712 aic_delay(5);
7687 ahd_delay(5);
9713
9714 if (cnt == 0)
9715 return (ETIMEDOUT);
9716 return (0);
9717}
9718
7688
7689 if (cnt == 0)
7690 return (ETIMEDOUT);
7691 return (0);
7692}
7693
9719/*
9720 * Validate the two checksums in the per_channel
9721 * vital product data struct.
9722 */
9723int
7694int
9724ahd_verify_vpd_cksum(struct vpd_config *vpd)
9725{
9726 int i;
9727 int maxaddr;
9728 uint32_t checksum;
9729 uint8_t *vpdarray;
9730
9731 vpdarray = (uint8_t *)vpd;
9732 maxaddr = offsetof(struct vpd_config, vpd_checksum);
9733 checksum = 0;
9734 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9735 checksum = checksum + vpdarray[i];
9736 if (checksum == 0
9737 || (-checksum & 0xFF) != vpd->vpd_checksum)
9738 return (0);
9739
9740 checksum = 0;
9741 maxaddr = offsetof(struct vpd_config, checksum);
9742 for (i = offsetof(struct vpd_config, default_target_flags);
9743 i < maxaddr; i++)
9744 checksum = checksum + vpdarray[i];
9745 if (checksum == 0
9746 || (-checksum & 0xFF) != vpd->checksum)
9747 return (0);
9748 return (1);
9749}
9750
9751int
9752ahd_verify_cksum(struct seeprom_config *sc)
9753{
9754 int i;
9755 int maxaddr;
9756 uint32_t checksum;
9757 uint16_t *scarray;
9758
9759 maxaddr = (sizeof(*sc)/2) - 1;

--- 8 unchanged lines hidden (view full) ---

9768 } else {
9769 return (1);
9770 }
9771}
9772
9773int
9774ahd_acquire_seeprom(struct ahd_softc *ahd)
9775{
7695ahd_verify_cksum(struct seeprom_config *sc)
7696{
7697 int i;
7698 int maxaddr;
7699 uint32_t checksum;
7700 uint16_t *scarray;
7701
7702 maxaddr = (sizeof(*sc)/2) - 1;

--- 8 unchanged lines hidden (view full) ---

7711 } else {
7712 return (1);
7713 }
7714}
7715
7716int
7717ahd_acquire_seeprom(struct ahd_softc *ahd)
7718{
9776 /*
9777 * We should be able to determine the SEEPROM type
9778 * from the flexport logic, but unfortunately not
9779 * all implementations have this logic and there is
9780 * no programatic method for determining if the logic
9781 * is present.
9782 */
9783 return (1);
9784#if 0
9785 uint8_t seetype;
9786 int error;
9787
9788 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9789 if (error != 0
9790 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9791 return (0);
9792 return (1);
7719 uint8_t seetype;
7720 int error;
7721
7722 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
7723 if (error != 0
7724 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
7725 return (0);
7726 return (1);
9793#endif
9794}
9795
9796void
9797ahd_release_seeprom(struct ahd_softc *ahd)
9798{
9799 /* Currently a no-op */
9800}
9801

--- 44 unchanged lines hidden (view full) ---

9846int
9847ahd_wait_flexport(struct ahd_softc *ahd)
9848{
9849 int cnt;
9850
9851 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9852 cnt = 1000000 * 2 / 5;
9853 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
7727}
7728
7729void
7730ahd_release_seeprom(struct ahd_softc *ahd)
7731{
7732 /* Currently a no-op */
7733}
7734

--- 44 unchanged lines hidden (view full) ---

7779int
7780ahd_wait_flexport(struct ahd_softc *ahd)
7781{
7782 int cnt;
7783
7784 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7785 cnt = 1000000 * 2 / 5;
7786 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9854 aic_delay(5);
7787 ahd_delay(5);
9855
9856 if (cnt == 0)
9857 return (ETIMEDOUT);
9858 return (0);
9859}
9860
9861/************************* Target Mode ****************************************/
9862#ifdef AHD_TARGET_MODE

--- 95 unchanged lines hidden (view full) ---

9958 }
9959
9960 /*
9961 * We now have an id that is valid.
9962 * If we aren't in target mode, switch modes.
9963 */
9964 if ((ahd->flags & AHD_TARGETROLE) == 0
9965 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7788
7789 if (cnt == 0)
7790 return (ETIMEDOUT);
7791 return (0);
7792}
7793
7794/************************* Target Mode ****************************************/
7795#ifdef AHD_TARGET_MODE

--- 95 unchanged lines hidden (view full) ---

7891 }
7892
7893 /*
7894 * We now have an id that is valid.
7895 * If we aren't in target mode, switch modes.
7896 */
7897 if ((ahd->flags & AHD_TARGETROLE) == 0
7898 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7899 u_long s;
7900
9966 printf("Configuring Target Mode\n");
7901 printf("Configuring Target Mode\n");
7902 ahd_lock(ahd, &s);
9967 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9968 ccb->ccb_h.status = CAM_BUSY;
7903 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7904 ccb->ccb_h.status = CAM_BUSY;
7905 ahd_unlock(ahd, &s);
9969 return;
9970 }
9971 ahd->flags |= AHD_TARGETROLE;
9972 if ((ahd->features & AHD_MULTIROLE) == 0)
9973 ahd->flags &= ~AHD_INITIATORROLE;
9974 ahd_pause(ahd);
9975 ahd_loadseq(ahd);
7906 return;
7907 }
7908 ahd->flags |= AHD_TARGETROLE;
7909 if ((ahd->features & AHD_MULTIROLE) == 0)
7910 ahd->flags &= ~AHD_INITIATORROLE;
7911 ahd_pause(ahd);
7912 ahd_loadseq(ahd);
9976 ahd_restart(ahd);
7913 ahd_unlock(ahd, &s);
9977 }
9978 cel = &ccb->cel;
9979 target = ccb->ccb_h.target_id;
9980 lun = ccb->ccb_h.target_lun;
9981 channel = SIM_CHANNEL(ahd, sim);
9982 target_mask = 0x01 << target;
9983 if (channel == 'B')
9984 target_mask <<= 8;
9985
9986 if (cel->enable != 0) {
9987 u_int scsiseq1;
9988
9989 /* Are we already enabled?? */
9990 if (lstate != NULL) {
9991 xpt_print_path(ccb->ccb_h.path);
9992 printf("Lun already enabled\n");
7914 }
7915 cel = &ccb->cel;
7916 target = ccb->ccb_h.target_id;
7917 lun = ccb->ccb_h.target_lun;
7918 channel = SIM_CHANNEL(ahd, sim);
7919 target_mask = 0x01 << target;
7920 if (channel == 'B')
7921 target_mask <<= 8;
7922
7923 if (cel->enable != 0) {
7924 u_int scsiseq1;
7925
7926 /* Are we already enabled?? */
7927 if (lstate != NULL) {
7928 xpt_print_path(ccb->ccb_h.path);
7929 printf("Lun already enabled\n");
9993 AHD_CORRECTABLE_ERROR(ahd);
9994 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9995 return;
9996 }
9997
9998 if (cel->grp6_len != 0
9999 || cel->grp7_len != 0) {
10000 /*
10001 * Don't (yet?) support vendor

--- 33 unchanged lines hidden (view full) ---

10035 free(lstate, M_DEVBUF);
10036 xpt_print_path(ccb->ccb_h.path);
10037 printf("Couldn't allocate path\n");
10038 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
10039 return;
10040 }
10041 SLIST_INIT(&lstate->accept_tios);
10042 SLIST_INIT(&lstate->immed_notifies);
7930 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7931 return;
7932 }
7933
7934 if (cel->grp6_len != 0
7935 || cel->grp7_len != 0) {
7936 /*
7937 * Don't (yet?) support vendor

--- 33 unchanged lines hidden (view full) ---

7971 free(lstate, M_DEVBUF);
7972 xpt_print_path(ccb->ccb_h.path);
7973 printf("Couldn't allocate path\n");
7974 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7975 return;
7976 }
7977 SLIST_INIT(&lstate->accept_tios);
7978 SLIST_INIT(&lstate->immed_notifies);
7979 ahd_lock(ahd, &s);
10043 ahd_pause(ahd);
10044 if (target != CAM_TARGET_WILDCARD) {
10045 tstate->enabled_luns[lun] = lstate;
10046 ahd->enabled_luns++;
10047
10048 if ((ahd->features & AHD_MULTI_TID) != 0) {
10049 u_int targid_mask;
10050
7980 ahd_pause(ahd);
7981 if (target != CAM_TARGET_WILDCARD) {
7982 tstate->enabled_luns[lun] = lstate;
7983 ahd->enabled_luns++;
7984
7985 if ((ahd->features & AHD_MULTI_TID) != 0) {
7986 u_int targid_mask;
7987
10051 targid_mask = ahd_inw(ahd, TARGID);
7988 targid_mask = ahd_inb(ahd, TARGID)
7989 | (ahd_inb(ahd, TARGID + 1) << 8);
7990
10052 targid_mask |= target_mask;
7991 targid_mask |= target_mask;
10053 ahd_outw(ahd, TARGID, targid_mask);
7992 ahd_outb(ahd, TARGID, targid_mask);
7993 ahd_outb(ahd, TARGID+1, (targid_mask >> 8));
7994
10054 ahd_update_scsiid(ahd, targid_mask);
10055 } else {
10056 u_int our_id;
10057 char channel;
10058
10059 channel = SIM_CHANNEL(ahd, sim);
10060 our_id = SIM_SCSI_ID(ahd, sim);
10061

--- 31 unchanged lines hidden (view full) ---

10093 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10094 scsiseq1 |= ENSELI;
10095 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10096 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10097 scsiseq1 |= ENSELI;
10098 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10099 }
10100 ahd_unpause(ahd);
7995 ahd_update_scsiid(ahd, targid_mask);
7996 } else {
7997 u_int our_id;
7998 char channel;
7999
8000 channel = SIM_CHANNEL(ahd, sim);
8001 our_id = SIM_SCSI_ID(ahd, sim);
8002

--- 31 unchanged lines hidden (view full) ---

8034 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
8035 scsiseq1 |= ENSELI;
8036 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
8037 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
8038 scsiseq1 |= ENSELI;
8039 ahd_outb(ahd, SCSISEQ1, scsiseq1);
8040 }
8041 ahd_unpause(ahd);
8042 ahd_unlock(ahd, &s);
10101 ccb->ccb_h.status = CAM_REQ_CMP;
10102 xpt_print_path(ccb->ccb_h.path);
10103 printf("Lun now enabled for target mode\n");
10104 } else {
10105 struct scb *scb;
10106 int i, empty;
10107
10108 if (lstate == NULL) {
10109 ccb->ccb_h.status = CAM_LUN_INVALID;
10110 return;
10111 }
10112
8043 ccb->ccb_h.status = CAM_REQ_CMP;
8044 xpt_print_path(ccb->ccb_h.path);
8045 printf("Lun now enabled for target mode\n");
8046 } else {
8047 struct scb *scb;
8048 int i, empty;
8049
8050 if (lstate == NULL) {
8051 ccb->ccb_h.status = CAM_LUN_INVALID;
8052 return;
8053 }
8054
8055 ahd_lock(ahd, &s);
8056
10113 ccb->ccb_h.status = CAM_REQ_CMP;
10114 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
10115 struct ccb_hdr *ccbh;
10116
10117 ccbh = &scb->io_ctx->ccb_h;
10118 if (ccbh->func_code == XPT_CONT_TARGET_IO
10119 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
10120 printf("CTIO pending\n");
10121 ccb->ccb_h.status = CAM_REQ_INVALID;
8057 ccb->ccb_h.status = CAM_REQ_CMP;
8058 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
8059 struct ccb_hdr *ccbh;
8060
8061 ccbh = &scb->io_ctx->ccb_h;
8062 if (ccbh->func_code == XPT_CONT_TARGET_IO
8063 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
8064 printf("CTIO pending\n");
8065 ccb->ccb_h.status = CAM_REQ_INVALID;
8066 ahd_unlock(ahd, &s);
10122 return;
10123 }
10124 }
10125
10126 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
10127 printf("ATIOs pending\n");
10128 ccb->ccb_h.status = CAM_REQ_INVALID;
10129 }
10130
10131 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
10132 printf("INOTs pending\n");
10133 ccb->ccb_h.status = CAM_REQ_INVALID;
10134 }
10135
10136 if (ccb->ccb_h.status != CAM_REQ_CMP) {
8067 return;
8068 }
8069 }
8070
8071 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
8072 printf("ATIOs pending\n");
8073 ccb->ccb_h.status = CAM_REQ_INVALID;
8074 }
8075
8076 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
8077 printf("INOTs pending\n");
8078 ccb->ccb_h.status = CAM_REQ_INVALID;
8079 }
8080
8081 if (ccb->ccb_h.status != CAM_REQ_CMP) {
8082 ahd_unlock(ahd, &s);
10137 return;
10138 }
10139
10140 xpt_print_path(ccb->ccb_h.path);
10141 printf("Target mode disabled\n");
10142 xpt_free_path(lstate->path);
10143 free(lstate, M_DEVBUF);
10144

--- 9 unchanged lines hidden (view full) ---

10154 }
10155
10156 if (empty) {
10157 ahd_free_tstate(ahd, target, channel,
10158 /*force*/FALSE);
10159 if (ahd->features & AHD_MULTI_TID) {
10160 u_int targid_mask;
10161
8083 return;
8084 }
8085
8086 xpt_print_path(ccb->ccb_h.path);
8087 printf("Target mode disabled\n");
8088 xpt_free_path(lstate->path);
8089 free(lstate, M_DEVBUF);
8090

--- 9 unchanged lines hidden (view full) ---

8100 }
8101
8102 if (empty) {
8103 ahd_free_tstate(ahd, target, channel,
8104 /*force*/FALSE);
8105 if (ahd->features & AHD_MULTI_TID) {
8106 u_int targid_mask;
8107
10162 targid_mask = ahd_inw(ahd, TARGID);
8108 targid_mask = ahd_inb(ahd, TARGID)
8109 | (ahd_inb(ahd, TARGID + 1)
8110 << 8);
8111
10163 targid_mask &= ~target_mask;
8112 targid_mask &= ~target_mask;
10164 ahd_outw(ahd, TARGID, targid_mask);
8113 ahd_outb(ahd, TARGID, targid_mask);
8114 ahd_outb(ahd, TARGID+1,
8115 (targid_mask >> 8));
10165 ahd_update_scsiid(ahd, targid_mask);
10166 }
10167 }
10168 } else {
10169
10170 ahd->black_hole = NULL;
10171
10172 /*

--- 14 unchanged lines hidden (view full) ---

10187 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10188
10189 if ((ahd->features & AHD_MULTIROLE) == 0) {
10190 printf("Configuring Initiator Mode\n");
10191 ahd->flags &= ~AHD_TARGETROLE;
10192 ahd->flags |= AHD_INITIATORROLE;
10193 ahd_pause(ahd);
10194 ahd_loadseq(ahd);
8116 ahd_update_scsiid(ahd, targid_mask);
8117 }
8118 }
8119 } else {
8120
8121 ahd->black_hole = NULL;
8122
8123 /*

--- 14 unchanged lines hidden (view full) ---

8138 ahd_outb(ahd, SCSISEQ1, scsiseq1);
8139
8140 if ((ahd->features & AHD_MULTIROLE) == 0) {
8141 printf("Configuring Initiator Mode\n");
8142 ahd->flags &= ~AHD_TARGETROLE;
8143 ahd->flags |= AHD_INITIATORROLE;
8144 ahd_pause(ahd);
8145 ahd_loadseq(ahd);
10195 ahd_restart(ahd);
10196 /*
10197 * Unpaused. The extra unpause
10198 * that follows is harmless.
10199 */
10200 }
10201 }
10202 ahd_unpause(ahd);
8146 }
8147 }
8148 ahd_unpause(ahd);
8149 ahd_unlock(ahd, &s);
10203 }
10204#endif
10205}
10206
10207static void
10208ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
10209{
10210#if NOT_YET
10211 u_int scsiid_mask;
10212 u_int scsiid;
10213
10214 if ((ahd->features & AHD_MULTI_TID) == 0)
10215 panic("ahd_update_scsiid called on non-multitid unit\n");
10216
10217 /*
8150 }
8151#endif
8152}
8153
8154static void
8155ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
8156{
8157#if NOT_YET
8158 u_int scsiid_mask;
8159 u_int scsiid;
8160
8161 if ((ahd->features & AHD_MULTI_TID) == 0)
8162 panic("ahd_update_scsiid called on non-multitid unit\n");
8163
8164 /*
10218 * Since we will rely on the TARGID mask
8165 * Since we will rely on the the TARGID mask
10219 * for selection enables, ensure that OID
10220 * in SCSIID is not set to some other ID
10221 * that we don't want to allow selections on.
10222 */
10223 if ((ahd->features & AHD_ULTRA2) != 0)
10224 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
10225 else
10226 scsiid = ahd_inb(ahd, SCSIID);

--- 172 unchanged lines hidden --- 		8166 * for selection enables, ensure that OID
8167 * in SCSIID is not set to some other ID
8168 * that we don't want to allow selections on.
8169 */
8170 if ((ahd->features & AHD_ULTRA2) != 0)
8171 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
8172 else
8173 scsiid = ahd_inb(ahd, SCSIID);

--- 172 unchanged lines hidden ---