ahci.h (3b8f08459569bf0faa21473e5cec2491e95c9349) ahci.h (802df3ace64925cb23b020c9cf9b06118b7b7d5d)
1/*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 401 unchanged lines hidden (view full) ---

410 void *ih; /* Interrupt handle */
411 struct ata_dma dma; /* DMA data */
412 struct cam_sim *sim;
413 struct cam_path *path;
414 uint32_t caps; /* Controller capabilities */
415 uint32_t caps2; /* Controller capabilities */
416 uint32_t chcaps; /* Channel capabilities */
417 uint32_t chscaps; /* Channel sleep capabilities */
1/*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 401 unchanged lines hidden (view full) ---

410 void *ih; /* Interrupt handle */
411 struct ata_dma dma; /* DMA data */
412 struct cam_sim *sim;
413 struct cam_path *path;
414 uint32_t caps; /* Controller capabilities */
415 uint32_t caps2; /* Controller capabilities */
416 uint32_t chcaps; /* Channel capabilities */
417 uint32_t chscaps; /* Channel sleep capabilities */
418 uint16_t vendorid; /* Vendor ID from the bus */
419 uint16_t deviceid; /* Device ID from the bus */
420 uint16_t subvendorid; /* Subvendor ID from the bus */
421 uint16_t subdeviceid; /* Subdevice ID from the bus */
418 int quirks;
419 int numslots; /* Number of present slots */
420 int pm_level; /* power management level */
421
422 struct ahci_slot slot[AHCI_MAX_SLOTS];
423 union ccb *hold[AHCI_MAX_SLOTS];
424 struct mtx mtx; /* state lock */
425 STAILQ_HEAD(, ccb_hdr) doneq; /* queue of completed CCBs */

--- 43 unchanged lines hidden (view full) ---

469 int ichannels;
470};
471
472/* structure describing a AHCI controller */
473struct ahci_controller {
474 device_t dev;
475 bus_dma_tag_t dma_tag;
476 int r_rid;
422 int quirks;
423 int numslots; /* Number of present slots */
424 int pm_level; /* power management level */
425
426 struct ahci_slot slot[AHCI_MAX_SLOTS];
427 union ccb *hold[AHCI_MAX_SLOTS];
428 struct mtx mtx; /* state lock */
429 STAILQ_HEAD(, ccb_hdr) doneq; /* queue of completed CCBs */

--- 43 unchanged lines hidden (view full) ---

473 int ichannels;
474};
475
476/* structure describing a AHCI controller */
477struct ahci_controller {
478 device_t dev;
479 bus_dma_tag_t dma_tag;
480 int r_rid;
481 uint16_t vendorid; /* Vendor ID from the bus */
482 uint16_t deviceid; /* Device ID from the bus */
483 uint16_t subvendorid; /* Subvendor ID from the bus */
484 uint16_t subdeviceid; /* Subdevice ID from the bus */
477 struct resource *r_mem;
478 struct rman sc_iomem;
479 struct ahci_controller_irq {
480 struct ahci_controller *ctlr;
481 struct resource *r_irq;
482 void *handle;
483 int r_irq_rid;
484 int mode;

--- 54 unchanged lines hidden (view full) ---

539#define ATA_OUTSW(res, offset, addr, count) \
540 bus_write_multi_2((res), (offset), (addr), (count))
541#define ATA_OUTSW_STRM(res, offset, addr, count) \
542 bus_write_multi_stream_2((res), (offset), (addr), (count))
543#define ATA_OUTSL(res, offset, addr, count) \
544 bus_write_multi_4((res), (offset), (addr), (count))
545#define ATA_OUTSL_STRM(res, offset, addr, count) \
546 bus_write_multi_stream_4((res), (offset), (addr), (count))
485 struct resource *r_mem;
486 struct rman sc_iomem;
487 struct ahci_controller_irq {
488 struct ahci_controller *ctlr;
489 struct resource *r_irq;
490 void *handle;
491 int r_irq_rid;
492 int mode;

--- 54 unchanged lines hidden (view full) ---

547#define ATA_OUTSW(res, offset, addr, count) \
548 bus_write_multi_2((res), (offset), (addr), (count))
549#define ATA_OUTSW_STRM(res, offset, addr, count) \
550 bus_write_multi_stream_2((res), (offset), (addr), (count))
551#define ATA_OUTSL(res, offset, addr, count) \
552 bus_write_multi_4((res), (offset), (addr), (count))
553#define ATA_OUTSL_STRM(res, offset, addr, count) \
554 bus_write_multi_stream_4((res), (offset), (addr), (count))
555
556
557#define AHCI_Q_NOFORCE 1
558#define AHCI_Q_NOPMP 2
559#define AHCI_Q_NONCQ 4
560#define AHCI_Q_1CH 8
561#define AHCI_Q_2CH 0x10
562#define AHCI_Q_4CH 0x20
563#define AHCI_Q_EDGEIS 0x40
564#define AHCI_Q_SATA2 0x80
565#define AHCI_Q_NOBSYRES 0x100
566#define AHCI_Q_NOAA 0x200
567#define AHCI_Q_NOCOUNT 0x400
568#define AHCI_Q_ALTSIG 0x800
569#define AHCI_Q_NOMSI 0x1000
570#define AHCI_Q_ATI_PMP_BUG 0x2000
571#define AHCI_Q_MAXIO_64K 0x4000
572#define AHCI_Q_SATA1_UNIT0 0x8000 /* need better method for this */
573
574#define AHCI_Q_BIT_STRING \
575 "\020" \
576 "\001NOFORCE" \
577 "\002NOPMP" \
578 "\003NONCQ" \
579 "\0041CH" \
580 "\0052CH" \
581 "\0064CH" \
582 "\007EDGEIS" \
583 "\010SATA2" \
584 "\011NOBSYRES" \
585 "\012NOAA" \
586 "\013NOCOUNT" \
587 "\014ALTSIG" \
588 "\015NOMSI" \
589 "\016ATI_PMP_BUG" \
590 "\017MAXIO_64K" \
591 "\020SATA1_UNIT0"
592
593int ahci_attach(device_t dev);
594int ahci_detach(device_t dev);
595int ahci_setup_interrupt(device_t dev);
596int ahci_print_child(device_t dev, device_t child);
597struct resource *ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
598 u_long start, u_long end, u_long count, u_int flags);
599int ahci_release_resource(device_t dev, device_t child, int type, int rid,
600 struct resource *r);
601int ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
602 int flags, driver_filter_t *filter, driver_intr_t *function,
603 void *argument, void **cookiep);
604int ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
605 void *cookie);
606int ahci_child_location_str(device_t dev, device_t child, char *buf,
607 size_t buflen);
608bus_dma_tag_t ahci_get_dma_tag(device_t dev, device_t child);
609int ahci_ctlr_reset(device_t dev);
610int ahci_ctlr_setup(device_t dev);