ahci.c (246e7a2b6494cd991b08ac669ed761ecea0cc98c) ahci.c (802df3ace64925cb23b020c9cf9b06118b7b7d5d)
1/*-
2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 27 unchanged lines hidden (view full) ---

36#include <sys/endian.h>
37#include <sys/malloc.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <machine/stdarg.h>
41#include <machine/resource.h>
42#include <machine/bus.h>
43#include <sys/rman.h>
1/*-
2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 27 unchanged lines hidden (view full) ---

36#include <sys/endian.h>
37#include <sys/malloc.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <machine/stdarg.h>
41#include <machine/resource.h>
42#include <machine/bus.h>
43#include <sys/rman.h>
44#include <dev/pci/pcivar.h>
45#include <dev/pci/pcireg.h>
46#include "ahci.h"
47
48#include <cam/cam.h>
49#include <cam/cam_ccb.h>
50#include <cam/cam_sim.h>
51#include <cam/cam_xpt_sim.h>
52#include <cam/cam_debug.h>
53
54/* local prototypes */
44#include "ahci.h"
45
46#include <cam/cam.h>
47#include <cam/cam_ccb.h>
48#include <cam/cam_sim.h>
49#include <cam/cam_xpt_sim.h>
50#include <cam/cam_debug.h>
51
52/* local prototypes */
55static int ahci_setup_interrupt(device_t dev);
56static void ahci_intr(void *data);
57static void ahci_intr_one(void *data);
58static void ahci_intr_one_edge(void *data);
53static void ahci_intr(void *data);
54static void ahci_intr_one(void *data);
55static void ahci_intr_one_edge(void *data);
59static int ahci_suspend(device_t dev);
60static int ahci_resume(device_t dev);
61static int ahci_ch_init(device_t dev);
62static int ahci_ch_deinit(device_t dev);
63static int ahci_ch_suspend(device_t dev);
64static int ahci_ch_resume(device_t dev);
65static void ahci_ch_pm(void *arg);
66static void ahci_ch_intr(void *arg);
67static void ahci_ch_intr_direct(void *arg);
68static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
56static int ahci_ch_init(device_t dev);
57static int ahci_ch_deinit(device_t dev);
58static int ahci_ch_suspend(device_t dev);
59static int ahci_ch_resume(device_t dev);
60static void ahci_ch_pm(void *arg);
61static void ahci_ch_intr(void *arg);
62static void ahci_ch_intr_direct(void *arg);
63static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
69static int ahci_ctlr_reset(device_t dev);
70static int ahci_ctlr_setup(device_t dev);
71static void ahci_begin_transaction(device_t dev, union ccb *ccb);
72static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
73static void ahci_execute_transaction(struct ahci_slot *slot);
74static void ahci_timeout(struct ahci_slot *slot);
75static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
76static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
77static void ahci_dmainit(device_t dev);
78static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);

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94static void ahci_process_read_log(device_t dev, union ccb *ccb);
95static void ahci_process_request_sense(device_t dev, union ccb *ccb);
96
97static void ahciaction(struct cam_sim *sim, union ccb *ccb);
98static void ahcipoll(struct cam_sim *sim);
99
100static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
101
64static void ahci_begin_transaction(device_t dev, union ccb *ccb);
65static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
66static void ahci_execute_transaction(struct ahci_slot *slot);
67static void ahci_timeout(struct ahci_slot *slot);
68static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
69static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
70static void ahci_dmainit(device_t dev);
71static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);

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87static void ahci_process_read_log(device_t dev, union ccb *ccb);
88static void ahci_process_request_sense(device_t dev, union ccb *ccb);
89
90static void ahciaction(struct cam_sim *sim, union ccb *ccb);
91static void ahcipoll(struct cam_sim *sim);
92
93static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
94
102static struct {
103 uint32_t id;
104 uint8_t rev;
105 const char *name;
106 int quirks;
107#define AHCI_Q_NOFORCE 1
108#define AHCI_Q_NOPMP 2
109#define AHCI_Q_NONCQ 4
110#define AHCI_Q_1CH 8
111#define AHCI_Q_2CH 16
112#define AHCI_Q_4CH 32
113#define AHCI_Q_EDGEIS 64
114#define AHCI_Q_SATA2 128
115#define AHCI_Q_NOBSYRES 256
116#define AHCI_Q_NOAA 512
117#define AHCI_Q_NOCOUNT 1024
118#define AHCI_Q_ALTSIG 2048
119#define AHCI_Q_NOMSI 4096
120
121#define AHCI_Q_BIT_STRING \
122 "\020" \
123 "\001NOFORCE" \
124 "\002NOPMP" \
125 "\003NONCQ" \
126 "\0041CH" \
127 "\0052CH" \
128 "\0064CH" \
129 "\007EDGEIS" \
130 "\010SATA2" \
131 "\011NOBSYRES" \
132 "\012NOAA" \
133 "\013NOCOUNT" \
134 "\014ALTSIG" \
135 "\015NOMSI"
136} ahci_ids[] = {
137 {0x43801002, 0x00, "AMD SB600", AHCI_Q_NOMSI},
138 {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
139 {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
140 {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
141 {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
142 {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
143 {0x43951002, 0x00, "AMD SB8x0/SB9x0", 0},
144 {0x78001022, 0x00, "AMD Hudson-2", 0},
145 {0x78011022, 0x00, "AMD Hudson-2", 0},
146 {0x78021022, 0x00, "AMD Hudson-2", 0},
147 {0x78031022, 0x00, "AMD Hudson-2", 0},
148 {0x78041022, 0x00, "AMD Hudson-2", 0},
149 {0x06111b21, 0x00, "ASMedia ASM2106", 0},
150 {0x06121b21, 0x00, "ASMedia ASM1061", 0},
151 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
152 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
153 {0x26818086, 0x00, "Intel ESB2", 0},
154 {0x26828086, 0x00, "Intel ESB2", 0},
155 {0x26838086, 0x00, "Intel ESB2", 0},
156 {0x27c18086, 0x00, "Intel ICH7", 0},
157 {0x27c38086, 0x00, "Intel ICH7", 0},
158 {0x27c58086, 0x00, "Intel ICH7M", 0},
159 {0x27c68086, 0x00, "Intel ICH7M", 0},
160 {0x28218086, 0x00, "Intel ICH8", 0},
161 {0x28228086, 0x00, "Intel ICH8", 0},
162 {0x28248086, 0x00, "Intel ICH8", 0},
163 {0x28298086, 0x00, "Intel ICH8M", 0},
164 {0x282a8086, 0x00, "Intel ICH8M", 0},
165 {0x29228086, 0x00, "Intel ICH9", 0},
166 {0x29238086, 0x00, "Intel ICH9", 0},
167 {0x29248086, 0x00, "Intel ICH9", 0},
168 {0x29258086, 0x00, "Intel ICH9", 0},
169 {0x29278086, 0x00, "Intel ICH9", 0},
170 {0x29298086, 0x00, "Intel ICH9M", 0},
171 {0x292a8086, 0x00, "Intel ICH9M", 0},
172 {0x292b8086, 0x00, "Intel ICH9M", 0},
173 {0x292c8086, 0x00, "Intel ICH9M", 0},
174 {0x292f8086, 0x00, "Intel ICH9M", 0},
175 {0x294d8086, 0x00, "Intel ICH9", 0},
176 {0x294e8086, 0x00, "Intel ICH9M", 0},
177 {0x3a058086, 0x00, "Intel ICH10", 0},
178 {0x3a228086, 0x00, "Intel ICH10", 0},
179 {0x3a258086, 0x00, "Intel ICH10", 0},
180 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
181 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
182 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
183 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
184 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
185 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
186 {0x1c028086, 0x00, "Intel Cougar Point", 0},
187 {0x1c038086, 0x00, "Intel Cougar Point", 0},
188 {0x1c048086, 0x00, "Intel Cougar Point", 0},
189 {0x1c058086, 0x00, "Intel Cougar Point", 0},
190 {0x1d028086, 0x00, "Intel Patsburg", 0},
191 {0x1d048086, 0x00, "Intel Patsburg", 0},
192 {0x1d068086, 0x00, "Intel Patsburg", 0},
193 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
194 {0x1e028086, 0x00, "Intel Panther Point", 0},
195 {0x1e038086, 0x00, "Intel Panther Point", 0},
196 {0x1e048086, 0x00, "Intel Panther Point (RAID)", 0},
197 {0x1e058086, 0x00, "Intel Panther Point (RAID)", 0},
198 {0x1e068086, 0x00, "Intel Panther Point (RAID)", 0},
199 {0x1e078086, 0x00, "Intel Panther Point (RAID)", 0},
200 {0x1e0e8086, 0x00, "Intel Panther Point (RAID)", 0},
201 {0x1e0f8086, 0x00, "Intel Panther Point (RAID)", 0},
202 {0x1f228086, 0x00, "Intel Avoton", 0},
203 {0x1f238086, 0x00, "Intel Avoton", 0},
204 {0x1f248086, 0x00, "Intel Avoton (RAID)", 0},
205 {0x1f258086, 0x00, "Intel Avoton (RAID)", 0},
206 {0x1f268086, 0x00, "Intel Avoton (RAID)", 0},
207 {0x1f278086, 0x00, "Intel Avoton (RAID)", 0},
208 {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0},
209 {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0},
210 {0x1f328086, 0x00, "Intel Avoton", 0},
211 {0x1f338086, 0x00, "Intel Avoton", 0},
212 {0x1f348086, 0x00, "Intel Avoton (RAID)", 0},
213 {0x1f358086, 0x00, "Intel Avoton (RAID)", 0},
214 {0x1f368086, 0x00, "Intel Avoton (RAID)", 0},
215 {0x1f378086, 0x00, "Intel Avoton (RAID)", 0},
216 {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0},
217 {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0},
218 {0x23a38086, 0x00, "Intel Coleto Creek", 0},
219 {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0},
220 {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0},
221 {0x8c028086, 0x00, "Intel Lynx Point", 0},
222 {0x8c038086, 0x00, "Intel Lynx Point", 0},
223 {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0},
224 {0x8c058086, 0x00, "Intel Lynx Point (RAID)", 0},
225 {0x8c068086, 0x00, "Intel Lynx Point (RAID)", 0},
226 {0x8c078086, 0x00, "Intel Lynx Point (RAID)", 0},
227 {0x8c0e8086, 0x00, "Intel Lynx Point (RAID)", 0},
228 {0x8c0f8086, 0x00, "Intel Lynx Point (RAID)", 0},
229 {0x8d028086, 0x00, "Intel Wellsburg", 0},
230 {0x8d048086, 0x00, "Intel Wellsburg (RAID)", 0},
231 {0x8d068086, 0x00, "Intel Wellsburg (RAID)", 0},
232 {0x8d628086, 0x00, "Intel Wellsburg", 0},
233 {0x8d648086, 0x00, "Intel Wellsburg (RAID)", 0},
234 {0x8d668086, 0x00, "Intel Wellsburg (RAID)", 0},
235 {0x8d6e8086, 0x00, "Intel Wellsburg (RAID)", 0},
236 {0x9c028086, 0x00, "Intel Lynx Point-LP", 0},
237 {0x9c038086, 0x00, "Intel Lynx Point-LP", 0},
238 {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
239 {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
240 {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
241 {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
242 {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
243 {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
244 {0x23238086, 0x00, "Intel DH89xxCC", 0},
245 {0x2360197b, 0x00, "JMicron JMB360", 0},
246 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
247 {0x2362197b, 0x00, "JMicron JMB362", 0},
248 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
249 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
250 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
251 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
252 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH |
253 AHCI_Q_EDGEIS},
254 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH |
255 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
256 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH |
257 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
258 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH |
259 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
260 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES},
261 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
262 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES},
263 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES},
264 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
265 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
266 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES},
267 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES},
268 {0x91831b4b, 0x00, "Marvell 88SS9183", AHCI_Q_NOBSYRES},
269 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", AHCI_Q_NOBSYRES},
270 {0x92151b4b, 0x00, "Marvell 88SE9215", AHCI_Q_NOBSYRES},
271 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
272 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
273 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES},
274 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
275 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
276 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
277 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
278 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
279 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
280 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
281 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
282 {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES},
283 {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES},
284 {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES},
285 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
286 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
287 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
288 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
289 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
290 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
291 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
292 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
293 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
294 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
295 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
296 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
297 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
298 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
299 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
300 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
301 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
302 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
303 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
304 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
305 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
306 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
307 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
308 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
309 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
310 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
311 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
312 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
313 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
314 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
315 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
316 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
317 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
318 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
319 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
320 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
321 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
322 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
323 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
324 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
325 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
326 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
327 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
328 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
329 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
330 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
331 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
332 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
333 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
334 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
335 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
336 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
337 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
338 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
339 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
340 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
341 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
342 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
343 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
344 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
345 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
346 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
347 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
348 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
349 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
350 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
351 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
352 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
353 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
354 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
355 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
356 {0x11841039, 0x00, "SiS 966", 0},
357 {0x11851039, 0x00, "SiS 968", 0},
358 {0x01861039, 0x00, "SiS 968", 0},
359 {0x00000000, 0x00, NULL, 0}
360};
361
362#define recovery_type spriv_field0
363#define RECOVERY_NONE 0
364#define RECOVERY_READ_LOG 1
365#define RECOVERY_REQUEST_SENSE 2
366#define recovery_slot spriv_field1
367
95#define recovery_type spriv_field0
96#define RECOVERY_NONE 0
97#define RECOVERY_READ_LOG 1
98#define RECOVERY_REQUEST_SENSE 2
99#define recovery_slot spriv_field1
100
368static int force_ahci = 1;
369TUNABLE_INT("hw.ahci.force", &force_ahci);
370
371static int
372ahci_probe(device_t dev)
101int
102ahci_ctlr_setup(device_t dev)
373{
103{
374 char buf[64];
375 int i, valid = 0;
376 uint32_t devid = pci_get_devid(dev);
377 uint8_t revid = pci_get_revid(dev);
378
379 /*
380 * Ensure it is not a PCI bridge (some vendors use
381 * the same PID and VID in PCI bridge and AHCI cards).
382 */
383 if (pci_get_class(dev) == PCIC_BRIDGE)
384 return (ENXIO);
385
386 /* Is this a possible AHCI candidate? */
387 if (pci_get_class(dev) == PCIC_STORAGE &&
388 pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
389 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
390 valid = 1;
391 /* Is this a known AHCI chip? */
392 for (i = 0; ahci_ids[i].id != 0; i++) {
393 if (ahci_ids[i].id == devid &&
394 ahci_ids[i].rev <= revid &&
395 (valid || (force_ahci == 1 &&
396 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
397 /* Do not attach JMicrons with single PCI function. */
398 if (pci_get_vendor(dev) == 0x197b &&
399 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
400 return (ENXIO);
401 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
402 ahci_ids[i].name);
403 device_set_desc_copy(dev, buf);
404 return (BUS_PROBE_VENDOR);
104 struct ahci_controller *ctlr = device_get_softc(dev);
105 /* Clear interrupts */
106 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
107 /* Configure CCC */
108 if (ctlr->ccc) {
109 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
110 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
111 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
112 (4 << AHCI_CCCC_CC_SHIFT) |
113 AHCI_CCCC_EN);
114 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
115 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
116 if (bootverbose) {
117 device_printf(dev,
118 "CCC with %dms/4cmd enabled on vector %d\n",
119 ctlr->ccc, ctlr->cccv);
405 }
406 }
120 }
121 }
407 if (!valid)
408 return (ENXIO);
409 device_set_desc_copy(dev, "AHCI SATA controller");
410 return (BUS_PROBE_VENDOR);
122 /* Enable AHCI interrupts */
123 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
124 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
125 return (0);
411}
412
126}
127
413static int
414ahci_ata_probe(device_t dev)
128int
129ahci_ctlr_reset(device_t dev)
415{
130{
416 char buf[64];
417 int i;
418 uint32_t devid = pci_get_devid(dev);
419 uint8_t revid = pci_get_revid(dev);
131 struct ahci_controller *ctlr = device_get_softc(dev);
132 int timeout;
420
133
421 if ((intptr_t)device_get_ivars(dev) >= 0)
422 return (ENXIO);
423 /* Is this a known AHCI chip? */
424 for (i = 0; ahci_ids[i].id != 0; i++) {
425 if (ahci_ids[i].id == devid &&
426 ahci_ids[i].rev <= revid) {
427 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
428 ahci_ids[i].name);
429 device_set_desc_copy(dev, buf);
430 return (BUS_PROBE_VENDOR);
431 }
134 /* Enable AHCI mode */
135 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
136 /* Reset AHCI controller */
137 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
138 for (timeout = 1000; timeout > 0; timeout--) {
139 DELAY(1000);
140 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
141 break;
432 }
142 }
433 device_set_desc_copy(dev, "AHCI SATA controller");
434 return (BUS_PROBE_VENDOR);
143 if (timeout == 0) {
144 device_printf(dev, "AHCI controller reset failure\n");
145 return ENXIO;
146 }
147 /* Reenable AHCI mode */
148 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
149 return (0);
435}
436
150}
151
437static int
152
153int
438ahci_attach(device_t dev)
439{
440 struct ahci_controller *ctlr = device_get_softc(dev);
154ahci_attach(device_t dev)
155{
156 struct ahci_controller *ctlr = device_get_softc(dev);
441 device_t child;
442 int error, unit, speed, i;
443 u_int u;
444 uint32_t devid = pci_get_devid(dev);
445 uint8_t revid = pci_get_revid(dev);
157 int error, i, u, speed, unit;
446 u_int32_t version;
158 u_int32_t version;
159 device_t child;
447
448 ctlr->dev = dev;
160
161 ctlr->dev = dev;
449 i = 0;
450 while (ahci_ids[i].id != 0 &&
451 (ahci_ids[i].id != devid ||
452 ahci_ids[i].rev > revid))
453 i++;
454 ctlr->quirks = ahci_ids[i].quirks;
455 resource_int_value(device_get_name(dev),
456 device_get_unit(dev), "ccc", &ctlr->ccc);
162 resource_int_value(device_get_name(dev),
163 device_get_unit(dev), "ccc", &ctlr->ccc);
457 /* if we have a memory BAR(5) we are likely on an AHCI part */
458 ctlr->r_rid = PCIR_BAR(5);
459 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
460 &ctlr->r_rid, RF_ACTIVE)))
461 return ENXIO;
164
462 /* Setup our own memory management for channels. */
463 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
464 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
465 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
466 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
467 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
468 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
469 return (error);
470 }
471 if ((error = rman_manage_region(&ctlr->sc_iomem,
472 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
473 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
474 rman_fini(&ctlr->sc_iomem);
475 return (error);
476 }
165 /* Setup our own memory management for channels. */
166 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
167 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
168 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
169 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
170 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
171 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
172 return (error);
173 }
174 if ((error = rman_manage_region(&ctlr->sc_iomem,
175 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
176 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
177 rman_fini(&ctlr->sc_iomem);
178 return (error);
179 }
477 pci_enable_busmaster(dev);
478 /* Reset controller */
479 if ((error = ahci_ctlr_reset(dev)) != 0) {
480 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
481 rman_fini(&ctlr->sc_iomem);
482 return (error);
483 };
484 /* Get the HW capabilities */
485 version = ATA_INL(ctlr->r_mem, AHCI_VS);
486 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
487 if (version >= 0x00010200)
488 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
489 if (ctlr->caps & AHCI_CAP_EMS)
490 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
491 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);

--- 36 unchanged lines hidden (view full) ---

528 0, NULL, NULL, &ctlr->dma_tag)) {
529 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
530 ctlr->r_mem);
531 rman_fini(&ctlr->sc_iomem);
532 return ENXIO;
533 }
534
535 ahci_ctlr_setup(dev);
180 /* Get the HW capabilities */
181 version = ATA_INL(ctlr->r_mem, AHCI_VS);
182 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
183 if (version >= 0x00010200)
184 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
185 if (ctlr->caps & AHCI_CAP_EMS)
186 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
187 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);

--- 36 unchanged lines hidden (view full) ---

224 0, NULL, NULL, &ctlr->dma_tag)) {
225 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
226 ctlr->r_mem);
227 rman_fini(&ctlr->sc_iomem);
228 return ENXIO;
229 }
230
231 ahci_ctlr_setup(dev);
536 /* Setup interrupts. */
537 if (ahci_setup_interrupt(dev)) {
538 bus_dma_tag_destroy(ctlr->dma_tag);
539 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
540 rman_fini(&ctlr->sc_iomem);
541 return ENXIO;
542 }
232
543 i = 0;
544 for (u = ctlr->ichannels; u != 0; u >>= 1)
545 i += (u & 1);
546 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
547 resource_int_value(device_get_name(dev), device_get_unit(dev),
548 "direct", &ctlr->direct);
549 /* Announce HW capabilities. */
550 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;

--- 63 unchanged lines hidden (view full) ---

614 device_printf(dev, "failed to add enclosure device\n");
615 else
616 device_set_ivars(child, (void *)(intptr_t)-1);
617 }
618 bus_generic_attach(dev);
619 return 0;
620}
621
233 i = 0;
234 for (u = ctlr->ichannels; u != 0; u >>= 1)
235 i += (u & 1);
236 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
237 resource_int_value(device_get_name(dev), device_get_unit(dev),
238 "direct", &ctlr->direct);
239 /* Announce HW capabilities. */
240 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;

--- 63 unchanged lines hidden (view full) ---

304 device_printf(dev, "failed to add enclosure device\n");
305 else
306 device_set_ivars(child, (void *)(intptr_t)-1);
307 }
308 bus_generic_attach(dev);
309 return 0;
310}
311
622static int
312int
623ahci_detach(device_t dev)
624{
625 struct ahci_controller *ctlr = device_get_softc(dev);
626 int i;
627
628 /* Detach & delete all children */
629 device_delete_children(dev);
630
631 /* Free interrupts. */
632 for (i = 0; i < ctlr->numirqs; i++) {
633 if (ctlr->irqs[i].r_irq) {
634 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
635 ctlr->irqs[i].handle);
636 bus_release_resource(dev, SYS_RES_IRQ,
637 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
638 }
639 }
313ahci_detach(device_t dev)
314{
315 struct ahci_controller *ctlr = device_get_softc(dev);
316 int i;
317
318 /* Detach & delete all children */
319 device_delete_children(dev);
320
321 /* Free interrupts. */
322 for (i = 0; i < ctlr->numirqs; i++) {
323 if (ctlr->irqs[i].r_irq) {
324 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
325 ctlr->irqs[i].handle);
326 bus_release_resource(dev, SYS_RES_IRQ,
327 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
328 }
329 }
640 pci_release_msi(dev);
641 bus_dma_tag_destroy(ctlr->dma_tag);
642 /* Free memory. */
643 rman_fini(&ctlr->sc_iomem);
644 if (ctlr->r_mem)
645 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
646 return (0);
647}
648
330 bus_dma_tag_destroy(ctlr->dma_tag);
331 /* Free memory. */
332 rman_fini(&ctlr->sc_iomem);
333 if (ctlr->r_mem)
334 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
335 return (0);
336}
337
649static int
650ahci_ctlr_reset(device_t dev)
651{
652 struct ahci_controller *ctlr = device_get_softc(dev);
653 int timeout;
654
655 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 &&
656 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
657 pci_write_config(dev, 0x92, 0x01, 1);
658 /* Enable AHCI mode */
659 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
660 /* Reset AHCI controller */
661 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
662 for (timeout = 1000; timeout > 0; timeout--) {
663 DELAY(1000);
664 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
665 break;
666 }
667 if (timeout == 0) {
668 device_printf(dev, "AHCI controller reset failure\n");
669 return ENXIO;
670 }
671 /* Reenable AHCI mode */
672 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
673 return (0);
674}
675
676static int
677ahci_ctlr_setup(device_t dev)
678{
679 struct ahci_controller *ctlr = device_get_softc(dev);
680 /* Clear interrupts */
681 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
682 /* Configure CCC */
683 if (ctlr->ccc) {
684 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
685 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
686 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
687 (4 << AHCI_CCCC_CC_SHIFT) |
688 AHCI_CCCC_EN);
689 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
690 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
691 if (bootverbose) {
692 device_printf(dev,
693 "CCC with %dms/4cmd enabled on vector %d\n",
694 ctlr->ccc, ctlr->cccv);
695 }
696 }
697 /* Enable AHCI interrupts */
698 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
699 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
700 return (0);
701}
702
703static int
704ahci_suspend(device_t dev)
705{
706 struct ahci_controller *ctlr = device_get_softc(dev);
707
708 bus_generic_suspend(dev);
709 /* Disable interupts, so the state change(s) doesn't trigger */
710 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
711 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
712 return 0;
713}
714
715static int
716ahci_resume(device_t dev)
717{
718 int res;
719
720 if ((res = ahci_ctlr_reset(dev)) != 0)
721 return (res);
722 ahci_ctlr_setup(dev);
723 return (bus_generic_resume(dev));
724}
725
726static int
338int
727ahci_setup_interrupt(device_t dev)
728{
729 struct ahci_controller *ctlr = device_get_softc(dev);
730 int i;
731
339ahci_setup_interrupt(device_t dev)
340{
341 struct ahci_controller *ctlr = device_get_softc(dev);
342 int i;
343
732 ctlr->msi = 2;
733 /* Process hints. */
734 if (ctlr->quirks & AHCI_Q_NOMSI)
735 ctlr->msi = 0;
736 resource_int_value(device_get_name(dev),
737 device_get_unit(dev), "msi", &ctlr->msi);
738 ctlr->numirqs = 1;
739 if (ctlr->msi < 0)
740 ctlr->msi = 0;
741 else if (ctlr->msi == 1)
742 ctlr->msi = min(1, pci_msi_count(dev));
743 else if (ctlr->msi > 1) {
744 ctlr->msi = 2;
745 ctlr->numirqs = pci_msi_count(dev);
746 }
747 /* Allocate MSI if needed/present. */
748 if (ctlr->msi && pci_alloc_msi(dev, &ctlr->numirqs) != 0) {
749 ctlr->msi = 0;
750 ctlr->numirqs = 1;
751 }
752 /* Check for single MSI vector fallback. */
753 if (ctlr->numirqs > 1 &&
754 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
755 device_printf(dev, "Falling back to one MSI\n");
756 ctlr->numirqs = 1;
757 }
758 /* Allocate all IRQs. */
759 for (i = 0; i < ctlr->numirqs; i++) {

--- 99 unchanged lines hidden (view full) ---

859
860 unit = irq->r_irq_rid - 1;
861 /* Some controllers have edge triggered IS. */
862 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
863 if ((arg = ctlr->interrupt[unit].argument))
864 ctlr->interrupt[unit].function(arg);
865}
866
344 /* Check for single MSI vector fallback. */
345 if (ctlr->numirqs > 1 &&
346 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
347 device_printf(dev, "Falling back to one MSI\n");
348 ctlr->numirqs = 1;
349 }
350 /* Allocate all IRQs. */
351 for (i = 0; i < ctlr->numirqs; i++) {

--- 99 unchanged lines hidden (view full) ---

451
452 unit = irq->r_irq_rid - 1;
453 /* Some controllers have edge triggered IS. */
454 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
455 if ((arg = ctlr->interrupt[unit].argument))
456 ctlr->interrupt[unit].function(arg);
457}
458
867static struct resource *
459struct resource *
868ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
460ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
869 u_long start, u_long end, u_long count, u_int flags)
461 u_long start, u_long end, u_long count, u_int flags)
870{
871 struct ahci_controller *ctlr = device_get_softc(dev);
872 struct resource *res;
873 long st;
874 int offset, size, unit;
875
876 unit = (intptr_t)device_get_ivars(child);
877 res = NULL;

--- 32 unchanged lines hidden (view full) ---

910 case SYS_RES_IRQ:
911 if (*rid == ATA_IRQ_RID)
912 res = ctlr->irqs[0].r_irq;
913 break;
914 }
915 return (res);
916}
917
462{
463 struct ahci_controller *ctlr = device_get_softc(dev);
464 struct resource *res;
465 long st;
466 int offset, size, unit;
467
468 unit = (intptr_t)device_get_ivars(child);
469 res = NULL;

--- 32 unchanged lines hidden (view full) ---

502 case SYS_RES_IRQ:
503 if (*rid == ATA_IRQ_RID)
504 res = ctlr->irqs[0].r_irq;
505 break;
506 }
507 return (res);
508}
509
918static int
510int
919ahci_release_resource(device_t dev, device_t child, int type, int rid,
511ahci_release_resource(device_t dev, device_t child, int type, int rid,
920 struct resource *r)
512 struct resource *r)
921{
922
923 switch (type) {
924 case SYS_RES_MEMORY:
925 rman_release_resource(r);
926 return (0);
927 case SYS_RES_IRQ:
928 if (rid != ATA_IRQ_RID)
929 return ENOENT;
930 return (0);
931 }
932 return (EINVAL);
933}
934
513{
514
515 switch (type) {
516 case SYS_RES_MEMORY:
517 rman_release_resource(r);
518 return (0);
519 case SYS_RES_IRQ:
520 if (rid != ATA_IRQ_RID)
521 return ENOENT;
522 return (0);
523 }
524 return (EINVAL);
525}
526
935static int
527int
936ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
528ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
937 int flags, driver_filter_t *filter, driver_intr_t *function,
938 void *argument, void **cookiep)
529 int flags, driver_filter_t *filter, driver_intr_t *function,
530 void *argument, void **cookiep)
939{
940 struct ahci_controller *ctlr = device_get_softc(dev);
941 int unit = (intptr_t)device_get_ivars(child);
942
943 if (filter != NULL) {
944 printf("ahci.c: we cannot use a filter here\n");
945 return (EINVAL);
946 }
947 ctlr->interrupt[unit].function = function;
948 ctlr->interrupt[unit].argument = argument;
949 return (0);
950}
951
531{
532 struct ahci_controller *ctlr = device_get_softc(dev);
533 int unit = (intptr_t)device_get_ivars(child);
534
535 if (filter != NULL) {
536 printf("ahci.c: we cannot use a filter here\n");
537 return (EINVAL);
538 }
539 ctlr->interrupt[unit].function = function;
540 ctlr->interrupt[unit].argument = argument;
541 return (0);
542}
543
952static int
544int
953ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
545ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
954 void *cookie)
546 void *cookie)
955{
956 struct ahci_controller *ctlr = device_get_softc(dev);
957 int unit = (intptr_t)device_get_ivars(child);
958
959 ctlr->interrupt[unit].function = NULL;
960 ctlr->interrupt[unit].argument = NULL;
961 return (0);
962}
963
547{
548 struct ahci_controller *ctlr = device_get_softc(dev);
549 int unit = (intptr_t)device_get_ivars(child);
550
551 ctlr->interrupt[unit].function = NULL;
552 ctlr->interrupt[unit].argument = NULL;
553 return (0);
554}
555
964static int
556int
965ahci_print_child(device_t dev, device_t child)
966{
967 int retval, channel;
968
969 retval = bus_print_child_header(dev, child);
970 channel = (int)(intptr_t)device_get_ivars(child);
971 if (channel >= 0)
972 retval += printf(" at channel %d", channel);
973 retval += bus_print_child_footer(dev, child);
974 return (retval);
975}
976
557ahci_print_child(device_t dev, device_t child)
558{
559 int retval, channel;
560
561 retval = bus_print_child_header(dev, child);
562 channel = (int)(intptr_t)device_get_ivars(child);
563 if (channel >= 0)
564 retval += printf(" at channel %d", channel);
565 retval += bus_print_child_footer(dev, child);
566 return (retval);
567}
568
977static int
569int
978ahci_child_location_str(device_t dev, device_t child, char *buf,
979 size_t buflen)
980{
981 int channel;
982
983 channel = (int)(intptr_t)device_get_ivars(child);
984 if (channel >= 0)
985 snprintf(buf, buflen, "channel=%d", channel);
986 return (0);
987}
988
570ahci_child_location_str(device_t dev, device_t child, char *buf,
571 size_t buflen)
572{
573 int channel;
574
575 channel = (int)(intptr_t)device_get_ivars(child);
576 if (channel >= 0)
577 snprintf(buf, buflen, "channel=%d", channel);
578 return (0);
579}
580
989static bus_dma_tag_t
581bus_dma_tag_t
990ahci_get_dma_tag(device_t dev, device_t child)
991{
992 struct ahci_controller *ctlr = device_get_softc(dev);
993
994 return (ctlr->dma_tag);
995}
996
582ahci_get_dma_tag(device_t dev, device_t child)
583{
584 struct ahci_controller *ctlr = device_get_softc(dev);
585
586 return (ctlr->dma_tag);
587}
588
997devclass_t ahci_devclass;
998static device_method_t ahci_methods[] = {
999 DEVMETHOD(device_probe, ahci_probe),
1000 DEVMETHOD(device_attach, ahci_attach),
1001 DEVMETHOD(device_detach, ahci_detach),
1002 DEVMETHOD(device_suspend, ahci_suspend),
1003 DEVMETHOD(device_resume, ahci_resume),
1004 DEVMETHOD(bus_print_child, ahci_print_child),
1005 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
1006 DEVMETHOD(bus_release_resource, ahci_release_resource),
1007 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
1008 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
1009 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
1010 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
1011 { 0, 0 }
1012};
1013static driver_t ahci_driver = {
1014 "ahci",
1015 ahci_methods,
1016 sizeof(struct ahci_controller)
1017};
1018DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0);
1019static device_method_t ahci_ata_methods[] = {
1020 DEVMETHOD(device_probe, ahci_ata_probe),
1021 DEVMETHOD(device_attach, ahci_attach),
1022 DEVMETHOD(device_detach, ahci_detach),
1023 DEVMETHOD(device_suspend, ahci_suspend),
1024 DEVMETHOD(device_resume, ahci_resume),
1025 DEVMETHOD(bus_print_child, ahci_print_child),
1026 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
1027 DEVMETHOD(bus_release_resource, ahci_release_resource),
1028 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
1029 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
1030 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
1031 { 0, 0 }
1032};
1033static driver_t ahci_ata_driver = {
1034 "ahci",
1035 ahci_ata_methods,
1036 sizeof(struct ahci_controller)
1037};
1038DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0);
1039MODULE_VERSION(ahci, 1);
1040MODULE_DEPEND(ahci, cam, 1, 1, 1);
1041
1042static int
1043ahci_ch_probe(device_t dev)
1044{
1045
1046 device_set_desc_copy(dev, "AHCI channel");
1047 return (0);
1048}
1049

--- 6 unchanged lines hidden (view full) ---

1056 int rid, error, i, sata_rev = 0;
1057 u_int32_t version;
1058
1059 ch->dev = dev;
1060 ch->unit = (intptr_t)device_get_ivars(dev);
1061 ch->caps = ctlr->caps;
1062 ch->caps2 = ctlr->caps2;
1063 ch->quirks = ctlr->quirks;
589static int
590ahci_ch_probe(device_t dev)
591{
592
593 device_set_desc_copy(dev, "AHCI channel");
594 return (0);
595}
596

--- 6 unchanged lines hidden (view full) ---

603 int rid, error, i, sata_rev = 0;
604 u_int32_t version;
605
606 ch->dev = dev;
607 ch->unit = (intptr_t)device_get_ivars(dev);
608 ch->caps = ctlr->caps;
609 ch->caps2 = ctlr->caps2;
610 ch->quirks = ctlr->quirks;
611 ch->vendorid = ctlr->vendorid;
612 ch->deviceid = ctlr->deviceid;
613 ch->subvendorid = ctlr->subvendorid;
614 ch->subdeviceid = ctlr->subdeviceid;
1064 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
1065 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
1066 resource_int_value(device_get_name(dev),
1067 device_get_unit(dev), "pm_level", &ch->pm_level);
1068 STAILQ_INIT(&ch->doneq);
1069 if (ch->pm_level > 3)
1070 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
1071 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
615 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
616 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
617 resource_int_value(device_get_name(dev),
618 device_get_unit(dev), "pm_level", &ch->pm_level);
619 STAILQ_INIT(&ch->doneq);
620 if (ch->pm_level > 3)
621 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
622 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
1072 /* Limit speed for my onboard JMicron external port.
1073 * It is not eSATA really. */
1074 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
1075 pci_get_subvendor(ctlr->dev) == 0x1043 &&
1076 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
1077 ch->unit == 0)
623 /* JMicron external ports (0) sometimes limited */
624 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
1078 sata_rev = 1;
1079 if (ch->quirks & AHCI_Q_SATA2)
1080 sata_rev = 2;
1081 resource_int_value(device_get_name(dev),
1082 device_get_unit(dev), "sata_rev", &sata_rev);
1083 for (i = 0; i < 16; i++) {
1084 ch->user[i].revision = sata_rev;
1085 ch->user[i].mode = 0;

--- 888 unchanged lines hidden (view full) ---

1974 "Poll error on slot %d, TFD: %04x\n",
1975 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1976#endif
1977 et = AHCI_ERR_TFE;
1978 break;
1979 }
1980 /* Workaround for ATI SB600/SB700 chipsets. */
1981 if (ccb->ccb_h.target_id == 15 &&
625 sata_rev = 1;
626 if (ch->quirks & AHCI_Q_SATA2)
627 sata_rev = 2;
628 resource_int_value(device_get_name(dev),
629 device_get_unit(dev), "sata_rev", &sata_rev);
630 for (i = 0; i < 16; i++) {
631 ch->user[i].revision = sata_rev;
632 ch->user[i].mode = 0;

--- 888 unchanged lines hidden (view full) ---

1521 "Poll error on slot %d, TFD: %04x\n",
1522 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1523#endif
1524 et = AHCI_ERR_TFE;
1525 break;
1526 }
1527 /* Workaround for ATI SB600/SB700 chipsets. */
1528 if (ccb->ccb_h.target_id == 15 &&
1982 pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
1529 (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1983 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1984 et = AHCI_ERR_TIMEOUT;
1985 break;
1986 }
1987 }
1988
1989 /* Marvell controllers do not wait for readyness. */
1990 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 &&

--- 768 unchanged lines hidden (view full) ---

2759}
2760
2761static int
2762ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2763{
2764 struct ahci_channel *ch = device_get_softc(dev);
2765 u_int8_t *fis = &ctp->cfis[0];
2766
1530 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1531 et = AHCI_ERR_TIMEOUT;
1532 break;
1533 }
1534 }
1535
1536 /* Marvell controllers do not wait for readyness. */
1537 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 &&

--- 768 unchanged lines hidden (view full) ---

2306}
2307
2308static int
2309ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2310{
2311 struct ahci_channel *ch = device_get_softc(dev);
2312 u_int8_t *fis = &ctp->cfis[0];
2313
2767 bzero(ctp->cfis, 16);
2314 bzero(fis, 20);
2768 fis[0] = 0x27; /* host to device */
2769 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2770 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2771 fis[1] |= 0x80;
2772 fis[2] = ATA_PACKET_CMD;
2773 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2774 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2775 fis[3] = ATA_F_DMA;

--- 304 unchanged lines hidden (view full) ---

3080 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
3081 cpi->unit_number = cam_sim_unit(sim);
3082 cpi->transport = XPORT_SATA;
3083 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
3084 cpi->protocol = PROTO_ATA;
3085 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
3086 cpi->maxio = MAXPHYS;
3087 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2315 fis[0] = 0x27; /* host to device */
2316 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2317 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2318 fis[1] |= 0x80;
2319 fis[2] = ATA_PACKET_CMD;
2320 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2321 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2322 fis[3] = ATA_F_DMA;

--- 304 unchanged lines hidden (view full) ---

2627 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2628 cpi->unit_number = cam_sim_unit(sim);
2629 cpi->transport = XPORT_SATA;
2630 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2631 cpi->protocol = PROTO_ATA;
2632 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2633 cpi->maxio = MAXPHYS;
2634 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
3088 if (pci_get_devid(parent) == 0x43801002)
2635 if (ch->quirks & AHCI_Q_MAXIO_64K)
3089 cpi->maxio = min(cpi->maxio, 128 * 512);
2636 cpi->maxio = min(cpi->maxio, 128 * 512);
3090 cpi->hba_vendor = pci_get_vendor(parent);
3091 cpi->hba_device = pci_get_device(parent);
3092 cpi->hba_subvendor = pci_get_subvendor(parent);
3093 cpi->hba_subdevice = pci_get_subdevice(parent);
2637 cpi->hba_vendor = ch->vendorid;
2638 cpi->hba_device = ch->deviceid;
2639 cpi->hba_subvendor = ch->subvendorid;
2640 cpi->hba_subdevice = ch->subdeviceid;
3094 cpi->ccb_h.status = CAM_REQ_CMP;
3095 break;
3096 }
3097 default:
3098 ccb->ccb_h.status = CAM_REQ_INVALID;
3099 break;
3100 }
3101 ahci_done(ch, ccb);

--- 10 unchanged lines hidden (view full) ---

3112 if (istatus != 0)
3113 ahci_ch_intr_main(ch, istatus);
3114 if (ch->resetting != 0 &&
3115 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
3116 ch->resetpolldiv = 1000;
3117 ahci_reset_to(ch->dev);
3118 }
3119}
2641 cpi->ccb_h.status = CAM_REQ_CMP;
2642 break;
2643 }
2644 default:
2645 ccb->ccb_h.status = CAM_REQ_INVALID;
2646 break;
2647 }
2648 ahci_done(ch, ccb);

--- 10 unchanged lines hidden (view full) ---

2659 if (istatus != 0)
2660 ahci_ch_intr_main(ch, istatus);
2661 if (ch->resetting != 0 &&
2662 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2663 ch->resetpolldiv = 1000;
2664 ahci_reset_to(ch->dev);
2665 }
2666}
2667MODULE_VERSION(ahci, 1);
2668MODULE_DEPEND(ahci, cam, 1, 1, 1);