agp_amd64.c (71ac18a84df2771fb9bd91e2349eae91602c4e46) agp_amd64.c (1587a9db92c03c738bb3f0fc5874b43c961e7c99)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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113
114 return (NULL);
115}
116
117static int
118agp_amd64_nvidia_match(uint16_t devid)
119{
120 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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113
114 return (NULL);
115}
116
117static int
118agp_amd64_nvidia_match(uint16_t devid)
119{
120 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
121 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
122 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
123 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
124 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
121 if (pci_cfgregread(0, 0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
122 pci_cfgregread(0, 0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
123 pci_cfgregread(0, 0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
124 pci_cfgregread(0, 0, 11, 0, PCIR_DEVICE, 2) != devid)
125 return (ENXIO);
126
127 return (0);
128}
129
130static int
131agp_amd64_via_match(void)
132{
133 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
125 return (ENXIO);
126
127 return (0);
128}
129
130static int
131agp_amd64_via_match(void)
132{
133 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
134 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
135 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
136 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
137 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
138 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
134 if (pci_cfgregread(0, 0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
135 pci_cfgregread(0, 0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
136 pci_cfgregread(0, 0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
137 pci_cfgregread(0, 0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
138 (pci_cfgregread(0, 0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
139 return (0);
140
141 return (1);
142}
143
144static int
145agp_amd64_probe(device_t dev)
146{

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160agp_amd64_attach(device_t dev)
161{
162 struct agp_amd64_softc *sc = device_get_softc(dev);
163 struct agp_gatt *gatt;
164 uint32_t devid;
165 int i, n, error;
166
167 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
139 return (0);
140
141 return (1);
142}
143
144static int
145agp_amd64_probe(device_t dev)
146{

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160agp_amd64_attach(device_t dev)
161{
162 struct agp_amd64_softc *sc = device_get_softc(dev);
163 struct agp_gatt *gatt;
164 uint32_t devid;
165 int i, n, error;
166
167 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
168 devid = pci_cfgregread(0, i, 3, 0, 4);
168 devid = pci_cfgregread(0, 0, i, 3, 0, 4);
169 if (devid == 0x11031022 || devid == 0x12031022) {
170 sc->mctrl[n] = i;
171 n++;
172 }
173 }
174 if (n == 0)
175 return (ENXIO);
176

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222 sc->initial_aperture))
223 return (ENXIO);
224 }
225 break;
226 }
227
228 /* Install the gatt and enable aperture. */
229 for (i = 0; i < sc->n_mctrl; i++) {
169 if (devid == 0x11031022 || devid == 0x12031022) {
170 sc->mctrl[n] = i;
171 n++;
172 }
173 }
174 if (n == 0)
175 return (ENXIO);
176

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222 sc->initial_aperture))
223 return (ENXIO);
224 }
225 break;
226 }
227
228 /* Install the gatt and enable aperture. */
229 for (i = 0; i < sc->n_mctrl; i++) {
230 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
230 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
231 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
232 4);
231 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
232 4);
233 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
234 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
233 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
234 (pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
235 AGP_AMD64_APCTRL_GARTEN) &
236 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
237 4);
238 }
239
240 return (0);
241}
242
243static int
244agp_amd64_detach(device_t dev)
245{
246 struct agp_amd64_softc *sc = device_get_softc(dev);
247 int i;
248
249 agp_free_cdev(dev);
250
251 for (i = 0; i < sc->n_mctrl; i++)
235 AGP_AMD64_APCTRL_GARTEN) &
236 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
237 4);
238 }
239
240 return (0);
241}
242
243static int
244agp_amd64_detach(device_t dev)
245{
246 struct agp_amd64_softc *sc = device_get_softc(dev);
247 int i;
248
249 agp_free_cdev(dev);
250
251 for (i = 0; i < sc->n_mctrl; i++)
252 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
253 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
252 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
253 pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
254 ~AGP_AMD64_APCTRL_GARTEN, 4);
255
256 AGP_SET_APERTURE(dev, sc->initial_aperture);
257 agp_free_gatt(sc->gatt);
258 agp_free_res(dev);
259
260 return (0);
261}

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273#define AGP_AMD64_TABLE_SIZE nitems(agp_amd64_table)
274
275static uint32_t
276agp_amd64_get_aperture(device_t dev)
277{
278 struct agp_amd64_softc *sc = device_get_softc(dev);
279 uint32_t i;
280
254 ~AGP_AMD64_APCTRL_GARTEN, 4);
255
256 AGP_SET_APERTURE(dev, sc->initial_aperture);
257 agp_free_gatt(sc->gatt);
258 agp_free_res(dev);
259
260 return (0);
261}

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273#define AGP_AMD64_TABLE_SIZE nitems(agp_amd64_table)
274
275static uint32_t
276agp_amd64_get_aperture(device_t dev)
277{
278 struct agp_amd64_softc *sc = device_get_softc(dev);
279 uint32_t i;
280
281 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
281 i = (pci_cfgregread(0, 0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
282 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
283
284 if (i >= AGP_AMD64_TABLE_SIZE)
285 return (0);
286
287 return (agp_amd64_table[i]);
288}
289

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296
297 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
298 if (agp_amd64_table[i] == aperture)
299 break;
300 if (i >= AGP_AMD64_TABLE_SIZE)
301 return (EINVAL);
302
303 for (j = 0; j < sc->n_mctrl; j++)
282 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
283
284 if (i >= AGP_AMD64_TABLE_SIZE)
285 return (0);
286
287 return (agp_amd64_table[i]);
288}
289

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296
297 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
298 if (agp_amd64_table[i] == aperture)
299 break;
300 if (i >= AGP_AMD64_TABLE_SIZE)
301 return (EINVAL);
302
303 for (j = 0; j < sc->n_mctrl; j++)
304 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
305 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
304 pci_cfgregwrite(0, 0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
305 (pci_cfgregread(0, 0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
306 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
307
308 switch (pci_get_vendor(dev)) {
309 case 0x10b9: /* ULi */
310 return (agp_amd64_uli_set_aperture(dev, aperture));
311 break;
312
313 case 0x10de: /* nVidia */

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351}
352
353static void
354agp_amd64_flush_tlb(device_t dev)
355{
356 struct agp_amd64_softc *sc = device_get_softc(dev);
357 int i;
358
306 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
307
308 switch (pci_get_vendor(dev)) {
309 case 0x10b9: /* ULi */
310 return (agp_amd64_uli_set_aperture(dev, aperture));
311 break;
312
313 case 0x10de: /* nVidia */

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351}
352
353static void
354agp_amd64_flush_tlb(device_t dev)
355{
356 struct agp_amd64_softc *sc = device_get_softc(dev);
357 int i;
358
359 for (i = 0; i < sc->n_mctrl; i++)
360 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
361 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
362 AGP_AMD64_CACHECTRL_INVGART, 4);
359 for (i = 0; i < sc->n_mctrl; i++) {
360 uint32_t val;
361
362 val = pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
363 4);
364 val |= AGP_AMD64_CACHECTRL_INVGART;
365 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, val,
366 4);
367 }
363}
364
365static void
366agp_amd64_apbase_fixup(device_t dev)
367{
368 struct agp_amd64_softc *sc = device_get_softc(dev);
369 uint32_t apbase;
370 int i;
371
372 sc->apbase = rman_get_start(sc->agp.as_aperture);
373 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
374 for (i = 0; i < sc->n_mctrl; i++)
368}
369
370static void
371agp_amd64_apbase_fixup(device_t dev)
372{
373 struct agp_amd64_softc *sc = device_get_softc(dev);
374 uint32_t apbase;
375 int i;
376
377 sc->apbase = rman_get_start(sc->agp.as_aperture);
378 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
379 for (i = 0; i < sc->n_mctrl; i++)
375 pci_cfgregwrite(0, sc->mctrl[i], 3,
380 pci_cfgregwrite(0, 0, sc->mctrl[i], 3,
376 AGP_AMD64_APBASE, apbase, 4);
377}
378
379static void
380agp_amd64_uli_init(device_t dev)
381{
382 struct agp_amd64_softc *sc = device_get_softc(dev);
383

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413agp_amd64_nvidia_init(device_t dev)
414{
415 struct agp_amd64_softc *sc = device_get_softc(dev);
416
417 agp_amd64_apbase_fixup(dev);
418 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
419 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
420 sc->apbase, 4);
381 AGP_AMD64_APBASE, apbase, 4);
382}
383
384static void
385agp_amd64_uli_init(device_t dev)
386{
387 struct agp_amd64_softc *sc = device_get_softc(dev);
388

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418agp_amd64_nvidia_init(device_t dev)
419{
420 struct agp_amd64_softc *sc = device_get_softc(dev);
421
422 agp_amd64_apbase_fixup(dev);
423 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
424 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
425 sc->apbase, 4);
421 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
422 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
426 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
427 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
423}
424
425static int
426agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
427{
428 struct agp_amd64_softc *sc = device_get_softc(dev);
429 uint32_t apsize;
430
431 switch (aperture) {
432 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
433 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
434 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
435 case 0x10000000: apsize = 0x08; break; /* 256 MB */
436 case 0x20000000: apsize = 0x00; break; /* 512 MB */
437 default:
438 return (EINVAL);
439 }
440
428}
429
430static int
431agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
432{
433 struct agp_amd64_softc *sc = device_get_softc(dev);
434 uint32_t apsize;
435
436 switch (aperture) {
437 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
438 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
439 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
440 case 0x10000000: apsize = 0x08; break; /* 256 MB */
441 case 0x20000000: apsize = 0x00; break; /* 512 MB */
442 default:
443 return (EINVAL);
444 }
445
441 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
442 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
446 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
447 (pci_cfgregread(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
443 0xfffffff0) | apsize, 4);
448 0xfffffff0) | apsize, 4);
444 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
449 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
445 sc->apbase + aperture - 1, 4);
450 sc->apbase + aperture - 1, 4);
446 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
451 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
447 sc->apbase + aperture - 1, 4);
448
449 return (0);
450}
451
452static void
453agp_amd64_via_init(device_t dev)
454{
455 struct agp_amd64_softc *sc = device_get_softc(dev);
456
457 agp_amd64_apbase_fixup(dev);
452 sc->apbase + aperture - 1, 4);
453
454 return (0);
455}
456
457static void
458agp_amd64_via_init(device_t dev)
459{
460 struct agp_amd64_softc *sc = device_get_softc(dev);
461
462 agp_amd64_apbase_fixup(dev);
458 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
459 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
460 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
463 pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
464 pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_GARTCTRL,
465 pci_cfgregread(0, 0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
461}
462
463static int
464agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
465{
466 uint32_t apsize;
467
468 apsize = ((aperture - 1) >> 20) ^ 0xff;
469 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
470 return (EINVAL);
466}
467
468static int
469agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
470{
471 uint32_t apsize;
472
473 apsize = ((aperture - 1) >> 20) ^ 0xff;
474 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
475 return (EINVAL);
471 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
476 pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
472
473 return (0);
474}
475
476static device_method_t agp_amd64_methods[] = {
477 /* Device interface */
478 DEVMETHOD(device_probe, agp_amd64_probe),
479 DEVMETHOD(device_attach, agp_amd64_attach),

--- 28 unchanged lines hidden --- 		477
478 return (0);
479}
480
481static device_method_t agp_amd64_methods[] = {
482 /* Device interface */
483 DEVMETHOD(device_probe, agp_amd64_probe),
484 DEVMETHOD(device_attach, agp_amd64_attach),

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