rk_pcie.c (1c799a6f29cadc7616362941c279dd0693c24645) rk_pcie.c (ee2324aaf6e3256ef7396ef6063ec4261486ef94)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 1148 unchanged lines hidden (view full) ---

1157 sc->bus_start = 0;
1158 sc->bus_end = 0x1F;
1159 sc->root_bus = sc->bus_start;
1160 sc->sub_bus = 1;
1161
1162 /* Read FDT properties */
1163 rv = rk_pcie_parse_fdt_resources(sc);
1164 if (rv != 0)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 1148 unchanged lines hidden (view full) ---

1157 sc->bus_start = 0;
1158 sc->bus_end = 0x1F;
1159 sc->root_bus = sc->bus_start;
1160 sc->sub_bus = 1;
1161
1162 /* Read FDT properties */
1163 rv = rk_pcie_parse_fdt_resources(sc);
1164 if (rv != 0)
1165 return (rv);
1165 goto out;
1166
1167 sc->coherent = OF_hasprop(sc->node, "dma-coherent");
1168 sc->no_l0s = OF_hasprop(sc->node, "aspm-no-l0s");
1169 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes,
1170 sizeof(sc->num_lanes));
1171 if (rv != sizeof(sc->num_lanes))
1172 sc->num_lanes = 1;
1173 if (sc->num_lanes != 1 && sc->num_lanes != 2 && sc->num_lanes != 4) {

--- 104 unchanged lines hidden (view full) ---

1278
1279 rv = ofw_pcib_init(dev);
1280 if (rv != 0)
1281 goto out;
1282
1283 rv = rk_pcie_decode_ranges(sc, sc->ofw_pci.sc_range,
1284 sc->ofw_pci.sc_nrange);
1285 if (rv != 0)
1166
1167 sc->coherent = OF_hasprop(sc->node, "dma-coherent");
1168 sc->no_l0s = OF_hasprop(sc->node, "aspm-no-l0s");
1169 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes,
1170 sizeof(sc->num_lanes));
1171 if (rv != sizeof(sc->num_lanes))
1172 sc->num_lanes = 1;
1173 if (sc->num_lanes != 1 && sc->num_lanes != 2 && sc->num_lanes != 4) {

--- 104 unchanged lines hidden (view full) ---

1278
1279 rv = ofw_pcib_init(dev);
1280 if (rv != 0)
1281 goto out;
1282
1283 rv = rk_pcie_decode_ranges(sc, sc->ofw_pci.sc_range,
1284 sc->ofw_pci.sc_nrange);
1285 if (rv != 0)
1286 goto out;
1286 goto out_full;
1287 rv = rk_pcie_setup_hw(sc);
1288 if (rv != 0)
1287 rv = rk_pcie_setup_hw(sc);
1288 if (rv != 0)
1289 goto out;
1289 goto out_full;
1290
1291 rv = rk_pcie_setup_sw(sc);
1292 if (rv != 0)
1290
1291 rv = rk_pcie_setup_sw(sc);
1292 if (rv != 0)
1293 goto out;
1293 goto out_full;
1294
1295 rv = bus_setup_intr(dev, sc->client_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1296 rk_pcie_client_irq, NULL, sc, &sc->client_irq_cookie);
1297 if (rv != 0) {
1298 device_printf(dev, "cannot setup client interrupt handler\n");
1299 rv = ENXIO;
1294
1295 rv = bus_setup_intr(dev, sc->client_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1296 rk_pcie_client_irq, NULL, sc, &sc->client_irq_cookie);
1297 if (rv != 0) {
1298 device_printf(dev, "cannot setup client interrupt handler\n");
1299 rv = ENXIO;
1300 goto out;
1300 goto out_full;
1301 }
1302
1303 rv = bus_setup_intr(dev, sc->legacy_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1304 rk_pcie_legacy_irq, NULL, sc, &sc->legacy_irq_cookie);
1305 if (rv != 0) {
1306 device_printf(dev, "cannot setup client interrupt handler\n");
1307 rv = ENXIO;
1301 }
1302
1303 rv = bus_setup_intr(dev, sc->legacy_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1304 rk_pcie_legacy_irq, NULL, sc, &sc->legacy_irq_cookie);
1305 if (rv != 0) {
1306 device_printf(dev, "cannot setup client interrupt handler\n");
1307 rv = ENXIO;
1308 goto out;
1308 goto out_full;
1309 }
1310
1311 rv = bus_setup_intr(dev, sc->sys_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1312 rk_pcie_sys_irq, NULL, sc, &sc->sys_irq_cookie);
1313 if (rv != 0) {
1314 device_printf(dev, "cannot setup client interrupt handler\n");
1315 rv = ENXIO;
1309 }
1310
1311 rv = bus_setup_intr(dev, sc->sys_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1312 rk_pcie_sys_irq, NULL, sc, &sc->sys_irq_cookie);
1313 if (rv != 0) {
1314 device_printf(dev, "cannot setup client interrupt handler\n");
1315 rv = ENXIO;
1316 goto out;
1316 goto out_full;
1317 }
1318
1319 /* Enable interrupts */
1320 val =
1321 PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR |
1322 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA |
1323 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG |
1324 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_INTA |

--- 14 unchanged lines hidden (view full) ---

1339
1340 val = APB_RD4(sc, PCIE_RC_CONFIG_LCS);
1341 val |= PCIEM_LINK_CTL_LBMIE | PCIEM_LINK_CTL_LABIE;
1342 APB_WR4(sc, PCIE_RC_CONFIG_LCS, val);
1343
1344 DELAY(250000);
1345 device_add_child(dev, "pci", -1);
1346 return (bus_generic_attach(dev));
1317 }
1318
1319 /* Enable interrupts */
1320 val =
1321 PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR |
1322 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA |
1323 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG |
1324 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_INTA |

--- 14 unchanged lines hidden (view full) ---

1339
1340 val = APB_RD4(sc, PCIE_RC_CONFIG_LCS);
1341 val |= PCIEM_LINK_CTL_LBMIE | PCIEM_LINK_CTL_LABIE;
1342 APB_WR4(sc, PCIE_RC_CONFIG_LCS, val);
1343
1344 DELAY(250000);
1345 device_add_child(dev, "pci", -1);
1346 return (bus_generic_attach(dev));
1347
1348out_full:
1349 bus_teardown_intr(dev, sc->sys_irq_res, sc->sys_irq_cookie);
1350 bus_teardown_intr(dev, sc->legacy_irq_res, sc->legacy_irq_cookie);
1351 bus_teardown_intr(dev, sc->client_irq_res, sc->client_irq_cookie);
1352 ofw_pcib_fini(dev);
1347out:
1353out:
1348 /* XXX Cleanup */
1354 bus_dma_tag_destroy(sc->dmat);
1355 bus_free_resource(dev, SYS_RES_IRQ, sc->sys_irq_res);
1356 bus_free_resource(dev, SYS_RES_IRQ, sc->legacy_irq_res);
1357 bus_free_resource(dev, SYS_RES_IRQ, sc->client_irq_res);
1358 bus_free_resource(dev, SYS_RES_MEMORY, sc->apb_mem_res);
1359 bus_free_resource(dev, SYS_RES_MEMORY, sc->axi_mem_res);
1360 /* GPIO */
1361 gpio_pin_release(sc->gpio_ep);
1362 /* Phys */
1363 for (int i = 0; i < MAX_LANES; i++) {
1364 phy_release(sc->phys[i]);
1365 }
1366 /* Clocks */
1367 clk_release(sc->clk_aclk);
1368 clk_release(sc->clk_aclk_perf);
1369 clk_release(sc->clk_hclk);
1370 clk_release(sc->clk_pm);
1371 /* Resets */
1372 hwreset_release(sc->hwreset_core);
1373 hwreset_release(sc->hwreset_mgmt);
1374 hwreset_release(sc->hwreset_pipe);
1375 hwreset_release(sc->hwreset_pm);
1376 hwreset_release(sc->hwreset_aclk);
1377 hwreset_release(sc->hwreset_pclk);
1378 /* Regulators */
1379 regulator_release(sc->supply_12v);
1380 regulator_release(sc->supply_3v3);
1381 regulator_release(sc->supply_1v8);
1382 regulator_release(sc->supply_0v9);
1349 return (rv);
1350}
1351
1352static device_method_t rk_pcie_methods[] = {
1353 /* Device interface */
1354 DEVMETHOD(device_probe, rk_pcie_probe),
1355 DEVMETHOD(device_attach, rk_pcie_attach),
1356

--- 31 unchanged lines hidden --- 		1383 return (rv);
1384}
1385
1386static device_method_t rk_pcie_methods[] = {
1387 /* Device interface */
1388 DEVMETHOD(device_probe, rk_pcie_probe),
1389 DEVMETHOD(device_attach, rk_pcie_attach),
1390

--- 31 unchanged lines hidden ---