ti_cpuid.c (3b8f08459569bf0faa21473e5cec2491e95c9349) ti_cpuid.c (56d8b96cbc3bd204e30061ff5c554f0c9acb3662)
1/*-
2 * Copyright (c) 2011
3 * Ben Gray <ben.r.gray@gmail.com>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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44#include <machine/cpufunc.h>
45#include <machine/resource.h>
46#include <machine/intr.h>
47
48#include <arm/ti/tivar.h>
49#include <arm/ti/ti_cpuid.h>
50
51#include <arm/ti/omap4/omap4_reg.h>
1/*-
2 * Copyright (c) 2011
3 * Ben Gray <ben.r.gray@gmail.com>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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44#include <machine/cpufunc.h>
45#include <machine/resource.h>
46#include <machine/intr.h>
47
48#include <arm/ti/tivar.h>
49#include <arm/ti/ti_cpuid.h>
50
51#include <arm/ti/omap4/omap4_reg.h>
52#include <arm/ti/omap3/omap3_reg.h>
53#include <arm/ti/am335x/am335x_reg.h>
54
55#define OMAP4_STD_FUSE_DIE_ID_0 0x2200
56#define OMAP4_ID_CODE 0x2204
57#define OMAP4_STD_FUSE_DIE_ID_1 0x2208
58#define OMAP4_STD_FUSE_DIE_ID_2 0x220C
59#define OMAP4_STD_FUSE_DIE_ID_3 0x2210
60#define OMAP4_STD_FUSE_PROD_ID_0 0x2214

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193 OMAP_REV_MINOR(chip_revision));
194 }
195 else {
196 printf("Texas Instruments unknown OMAP chip: %04x, rev %d\n",
197 hawkeye, revision);
198 }
199}
200
52#include <arm/ti/am335x/am335x_reg.h>
53
54#define OMAP4_STD_FUSE_DIE_ID_0 0x2200
55#define OMAP4_ID_CODE 0x2204
56#define OMAP4_STD_FUSE_DIE_ID_1 0x2208
57#define OMAP4_STD_FUSE_DIE_ID_2 0x220C
58#define OMAP4_STD_FUSE_DIE_ID_3 0x2210
59#define OMAP4_STD_FUSE_PROD_ID_0 0x2214

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192 OMAP_REV_MINOR(chip_revision));
193 }
194 else {
195 printf("Texas Instruments unknown OMAP chip: %04x, rev %d\n",
196 hawkeye, revision);
197 }
198}
199
201/**
202 * omap3_get_revision - determines omap3 revision
203 *
204 * Reads the registers to determine the revision of the chip we are currently
205 * running on. Stores the information in global variables.
206 *
207 * WARNING: This function currently only really works for OMAP3530 devices.
208 *
209 *
210 *
211 */
212static void
200static void
213omap3_get_revision(void)
214{
215 uint32_t id_code;
216 uint32_t revision;
217 uint32_t hawkeye;
218 bus_space_handle_t bsh;
219
220 /* The chip revsion is read from the device identification registers and
221 * the JTAG (?) tap registers, which are located in address 0x4A00_2200 to
222 * 0x4A00_2218. This is part of the L4_CORE memory range and should have
223 * been mapped in by the machdep.c code.
224 *
225 * CONTROL_IDCODE 0x4830 A204 (this is the only one we need)
226 *
227 *
228 */
229 bus_space_map(fdtbus_bs_tag, OMAP35XX_L4_WAKEUP_HWBASE, 0x10000, 0, &bsh);
230 id_code = bus_space_read_4(fdtbus_bs_tag, bsh, OMAP3_ID_CODE);
231 bus_space_unmap(fdtbus_bs_tag, bsh, 0x10000);
232
233 hawkeye = ((id_code >> 12) & 0xffff);
234 revision = ((id_code >> 28) & 0xf);
235
236 switch (hawkeye) {
237 case 0xB6D6:
238 chip_revision = OMAP3350_REV_ES1_0;
239 break;
240 case 0xB7AE:
241 if (revision == 1)
242 chip_revision = OMAP3530_REV_ES2_0;
243 else if (revision == 2)
244 chip_revision = OMAP3530_REV_ES2_1;
245 else if (revision == 3)
246 chip_revision = OMAP3530_REV_ES3_0;
247 else if (revision == 4)
248 chip_revision = OMAP3530_REV_ES3_1;
249 else if (revision == 7)
250 chip_revision = OMAP3530_REV_ES3_1_2;
251 break;
252 default:
253 /* Default to the latest revision if we can't determine type */
254 chip_revision = OMAP3530_REV_ES3_1_2;
255 break;
256 }
257 printf("Texas Instruments OMAP%04x Processor, Revision ES%u.%u\n",
258 OMAP_REV_DEVICE(chip_revision), OMAP_REV_MAJOR(chip_revision),
259 OMAP_REV_MINOR(chip_revision));
260}
261
262static void
263am335x_get_revision(void)
264{
265 uint32_t dev_feature;
266 uint8_t cpu_last_char;
267 bus_space_handle_t bsh;
268
269 bus_space_map(fdtbus_bs_tag, AM335X_CONTROL_BASE, AM335X_CONTROL_SIZE, 0, &bsh);
270 chip_revision = bus_space_read_4(fdtbus_bs_tag, bsh, AM335X_CONTROL_DEVICE_ID);

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308 * and writes rather than going through the bus stuff.
309 *
310 *
311 */
312static void
313ti_cpu_ident(void *dummy)
314{
315 switch(ti_chip()) {
201am335x_get_revision(void)
202{
203 uint32_t dev_feature;
204 uint8_t cpu_last_char;
205 bus_space_handle_t bsh;
206
207 bus_space_map(fdtbus_bs_tag, AM335X_CONTROL_BASE, AM335X_CONTROL_SIZE, 0, &bsh);
208 chip_revision = bus_space_read_4(fdtbus_bs_tag, bsh, AM335X_CONTROL_DEVICE_ID);

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246 * and writes rather than going through the bus stuff.
247 *
248 *
249 */
250static void
251ti_cpu_ident(void *dummy)
252{
253 switch(ti_chip()) {
316 case CHIP_OMAP_3:
317 omap3_get_revision();
318 break;
319 case CHIP_OMAP_4:
320 omap4_get_revision();
321 break;
322 case CHIP_AM335X:
323 am335x_get_revision();
324 break;
325 default:
326 panic("Unknown chip type, fixme!\n");
327 }
328}
329
330SYSINIT(ti_cpu_ident, SI_SUB_CPU, SI_ORDER_SECOND, ti_cpu_ident, NULL);
254 case CHIP_OMAP_4:
255 omap4_get_revision();
256 break;
257 case CHIP_AM335X:
258 am335x_get_revision();
259 break;
260 default:
261 panic("Unknown chip type, fixme!\n");
262 }
263}
264
265SYSINIT(ti_cpu_ident, SI_SUB_CPU, SI_ORDER_SECOND, ti_cpu_ident, NULL);