mptramp.S (d0307444ed57c082fa6445f4ed5ecef57758e240) mptramp.S (47fdf913c13a1d0e0f39bb3db422caac9d8c00b1)
1/*-
2 * Copyright 2011 Semihalf
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * SUCH DAMAGE.
25 */
26
27#include <machine/asm.h>
28#include <machine/armreg.h>
29
30__FBSDID("$FreeBSD$");
31
1/*-
2 * Copyright 2011 Semihalf
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * SUCH DAMAGE.
25 */
26
27#include <machine/asm.h>
28#include <machine/armreg.h>
29
30__FBSDID("$FreeBSD$");
31
32.global _C_LABEL(mptramp_pmu_boot)
33
32ASENTRY_NP(mptramp)
33 mov r0, #0
34 mcr p15, 0, r0, c7, c7, 0
35
36 mrs r3, cpsr
37 bic r3, r3, #(PSR_MODE)
38 orr r3, r3, #(PSR_SVC32_MODE)
39 msr cpsr_fsxc, r3
40
41 mrc p15, 0, r0, c0, c0, 5
42 and r0, #0x0f /* Get CPU ID */
43
44 /* Read boot address for CPU */
45 mov r1, #0x100
46 mul r2, r0, r1
34ASENTRY_NP(mptramp)
35 mov r0, #0
36 mcr p15, 0, r0, c7, c7, 0
37
38 mrs r3, cpsr
39 bic r3, r3, #(PSR_MODE)
40 orr r3, r3, #(PSR_SVC32_MODE)
41 msr cpsr_fsxc, r3
42
43 mrc p15, 0, r0, c0, c0, 5
44 and r0, #0x0f /* Get CPU ID */
45
46 /* Read boot address for CPU */
47 mov r1, #0x100
48 mul r2, r0, r1
47 ldr r1, Lpmureg
49 ldr r1, mptramp_pmu_boot
48 add r0, r2, r1
49 ldr r1, [r0], #0x00
50
51 mov pc, r1
52
50 add r0, r2, r1
51 ldr r1, [r0], #0x00
52
53 mov pc, r1
54
53Lpmureg:
54 .word 0xd0022124
55_C_LABEL(mptramp_pmu_boot):
56 .word 0x0
57
55END(mptramp)
56
57 .global _C_LABEL(mptramp_end)
58_C_LABEL(mptramp_end):
58END(mptramp)
59
60 .global _C_LABEL(mptramp_end)
61_C_LABEL(mptramp_end):