| ppbus.4 (c9ebdae49966f40fc2496650ab76aa4adb558d01) | ppbus.4 (bc35c17446fab005a7e11b67b9004736f1c8498b) |
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| 1.\" Copyright (c) 1998, Nicolas Souchu | 1.\" Copyright (c) 1998, 1999 Nicolas Souchu |
| 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright --- 23 unchanged lines hidden (view full) --- 33.Sh SYNOPSIS 34.Cd "controller ppbus0" 35.Pp 36.Cd "controller vpo0 at ppbus?" 37.Pp 38.Cd "device nlpt0 at ppbus?" 39.Cd "device plip0 at ppbus?" 40.Cd "device ppi0 at ppbus?" | 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright --- 23 unchanged lines hidden (view full) --- 33.Sh SYNOPSIS 34.Cd "controller ppbus0" 35.Pp 36.Cd "controller vpo0 at ppbus?" 37.Pp 38.Cd "device nlpt0 at ppbus?" 39.Cd "device plip0 at ppbus?" 40.Cd "device ppi0 at ppbus?" |
| 41.Cd "device pps0 at ppbus?" 42.Cd "device lpbb0 at ppbus?" |
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| 41.Sh DESCRIPTION 42The 43.Em ppbus 44system provides a uniform, modular and architecture-independent 45system for the implementation of drivers to control various parallel devices, 46and to utilize different parallel port chipsets. 47.Sh DEVICE DRIVERS 48In order to write new drivers or port existing drivers, the ppbus system --- 14 unchanged lines hidden (view full) --- 63The ppbus system has been designed to support the development of standard 64and non-standard software: 65.Pp 66.Bl -column "Driver" -compact 67.It Em Driver Ta Em Description 68.It Sy vpo Ta "VPI0 parallel to Adaptec AIC-7110 SCSI controller driver." 69It uses standard and non-standard parallel port accesses 70.It Sy ppi Ta "Parallel port interface for general I/O" | 43.Sh DESCRIPTION 44The 45.Em ppbus 46system provides a uniform, modular and architecture-independent 47system for the implementation of drivers to control various parallel devices, 48and to utilize different parallel port chipsets. 49.Sh DEVICE DRIVERS 50In order to write new drivers or port existing drivers, the ppbus system --- 14 unchanged lines hidden (view full) --- 65The ppbus system has been designed to support the development of standard 66and non-standard software: 67.Pp 68.Bl -column "Driver" -compact 69.It Em Driver Ta Em Description 70.It Sy vpo Ta "VPI0 parallel to Adaptec AIC-7110 SCSI controller driver." 71It uses standard and non-standard parallel port accesses 72.It Sy ppi Ta "Parallel port interface for general I/O" |
| 73.It Sy pps Ta "Pulse per second Timing Interface" 74.It Sy lpbb Ta "Philips official parallel port I2C bit-banging interface" |
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| 71.El 72.Ss Porting existing drivers 73.Pp 74Another approach to the ppbus system is to port existing drivers. 75Various drivers have already been ported: 76.Pp 77.Bl -column "Driver" -compact 78.It Em Driver Ta Em Description --- 71 unchanged lines hidden (view full) --- 150.Ss Enhanced Parallel Port mode 151The EPP protocol was originally developed as a means to provide a high 152performance parallel port link that would still be compatible with the 153standard parallel port. 154.Ss Mixed modes 155Some manufacturers, like SMC, have implemented chipsets that support mixed 156modes. With such chipsets, mode switching is available at any time by 157accessing the extended control register. | 75.El 76.Ss Porting existing drivers 77.Pp 78Another approach to the ppbus system is to port existing drivers. 79Various drivers have already been ported: 80.Pp 81.Bl -column "Driver" -compact 82.It Em Driver Ta Em Description --- 71 unchanged lines hidden (view full) --- 154.Ss Enhanced Parallel Port mode 155The EPP protocol was originally developed as a means to provide a high 156performance parallel port link that would still be compatible with the 157standard parallel port. 158.Ss Mixed modes 159Some manufacturers, like SMC, have implemented chipsets that support mixed 160modes. With such chipsets, mode switching is available at any time by 161accessing the extended control register. |
| 162.Sh IEEE1284-1994 Standard 163.Ss Background 164This standard is also named "IEEE Standard Signaling Method for a 165Bidirectional Parallel Peripheral Interface for Personal Computers". It 166defines a signaling method for asynchroneous, fully interlocked, bidirectional 167parallel communications between hosts and printers or other peripherals. It 168also specifies a format for a peripheral identification string and a method of 169returning this string to the host outside of the bidirectional data stream. 170.Pp 171This standard is architecture independent and only specifiy dialog handshake 172at signal level. One should refer to any architecture specific document in 173order to manipulate machine dependent registers, mapped memory or whatelse 174to control these signals. 175.Pp 176The IEEE1284 protocol is fully oriented with all supported parallel port 177modes. The computer acts as master and the peripheral as slave. 178.Pp 179Any transfer is defined as a finite state automate. It allows software to 180properly manage the fully interlocked scheme of the signaling method. 181The compatible mode is supported "as is" without any negociation because it 182is compatible. Any other mode must be firstly negociated by the host to check 183it is supported by the peripheral, then to enter one of the forward idle 184states. 185.Pp 186At any time, the slave may want to send data to the host. This is only 187possible from forward idle states (nibble, byte, ecp...). So, the 188host must have previously negociated to permit the peripheral to 189request transfer. Interrupt lines may be dedicated to the requesting signals 190to prevent time consuming polling methods. 191.Pp 192But peripheral requests are only a hint to the master host. If the host 193accepts the transfer, it must firstly negociate the reverse mode and then 194starts the transfer. At any time during reverse transfer, the host may 195terminate the transfer or the slave may drive wires to signal that no more 196data is available. 197.Ss Implementation 198IEEE1284 Standard support has been implemented at the top of the ppbus system 199as a set of procedures that perform high level functions like negociation, 200termination, transfer in any mode without bothering you with low level 201caracteristics of the stantdard. 202.Pp 203IEEE1284 interacts with the ppbus system as least as possible. That means 204you still have to request the ppbus when you want to access it, the negociate 205function doesn't do it for you. And of course, release it later. |
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| 158.Sh ARCHITECTURE 159.Ss adapter, ppbus and device layers 160First, there is the 161.Em adapter 162layer, the lowest of the ppbus system. It provides 163chipset abstraction throw a set of low level functions that maps the logical 164model to the underlying hardware. 165.Pp --- 102 unchanged lines hidden --- | 206.Sh ARCHITECTURE 207.Ss adapter, ppbus and device layers 208First, there is the 209.Em adapter 210layer, the lowest of the ppbus system. It provides 211chipset abstraction throw a set of low level functions that maps the logical 212model to the underlying hardware. 213.Pp --- 102 unchanged lines hidden --- |