| pmc.westmere.3 (026dbd291e755e792b8427a9f84ad107e2d1470c) | pmc.westmere.3 (3102cfe2e21aaea969dcc5245c0b70d9ae643e34) |
|---|---|
| 1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright --- 9 unchanged lines hidden (view full) --- 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" | 1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright --- 9 unchanged lines hidden (view full) --- 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" |
| 26.Dd March 24, 2010 | 26.Dd February 25, 2012 |
| 27.Dt PMC.WESTMERE 3 28.Os 29.Sh NAME 30.Nm pmc.westmere 31.Nd measurement events for 32.Tn Intel 33.Tn Westmere 34family CPUs --- 603 unchanged lines hidden (view full) --- 638.Pq Event 60H , Umask 04H 639Counts weighted cycles of offcore demand RFO requests. Does not include L2 640prefetch requests. 641Counter 0. 642.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ 643.Pq Event 60H , Umask 08H 644Counts weighted cycles of offcore read requests of any kind. Include L2 645prefetch requests. | 27.Dt PMC.WESTMERE 3 28.Os 29.Sh NAME 30.Nm pmc.westmere 31.Nd measurement events for 32.Tn Intel 33.Tn Westmere 34family CPUs --- 603 unchanged lines hidden (view full) --- 638.Pq Event 60H , Umask 04H 639Counts weighted cycles of offcore demand RFO requests. Does not include L2 640prefetch requests. 641Counter 0. 642.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ 643.Pq Event 60H , Umask 08H 644Counts weighted cycles of offcore read requests of any kind. Include L2 645prefetch requests. |
| 646Ccounter 0. | 646Counter 0. |
| 647.It Li CACHE_LOCK_CYCLES.L1D_L2 648.Pq Event 63H , Umask 01H 649Cycle count during which the L1D and L2 are locked. A lock is asserted when 650there is a locked memory access, due to uncacheable memory, a locked 651operation that spans two cache lines, or a page walk from an uncacheable 652page table. 653Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and 654it is highly recommended to avoid such accesses. --- 675 unchanged lines hidden --- | 647.It Li CACHE_LOCK_CYCLES.L1D_L2 648.Pq Event 63H , Umask 01H 649Cycle count during which the L1D and L2 are locked. A lock is asserted when 650there is a locked memory access, due to uncacheable memory, a locked 651operation that spans two cache lines, or a page walk from an uncacheable 652page table. 653Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and 654it is highly recommended to avoid such accesses. --- 675 unchanged lines hidden --- |