libpmc.c (1fa7f10bac396ef8fe623f3845b7d9280e078abd) libpmc.c (ebccf1e3a6b11b97cbf5f813dd76636e892a9035)
1/*-
1/*-
2 * Copyright (c) 2003-2008 Joseph Koshy
2 * Copyright (c) 2003,2004 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 6 unchanged lines hidden (view full) ---

17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 6 unchanged lines hidden (view full) ---

17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include <sys/types.h>
31#include <sys/module.h>
32#include <sys/pmc.h>
33#include <sys/syscall.h>
34
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD$");
31
32#include <sys/types.h>
33#include <sys/module.h>
34#include <sys/pmc.h>
35#include <sys/syscall.h>
36
37#include <machine/pmc_mdep.h>
38
35#include <ctype.h>
36#include <errno.h>
37#include <fcntl.h>
38#include <pmc.h>
39#include <stdio.h>
40#include <stdlib.h>
41#include <string.h>
42#include <strings.h>
43#include <unistd.h>
44
39#include <ctype.h>
40#include <errno.h>
41#include <fcntl.h>
42#include <pmc.h>
43#include <stdio.h>
44#include <stdlib.h>
45#include <string.h>
46#include <strings.h>
47#include <unistd.h>
48
45#include "libpmcinternal.h"
46
47/* Function prototypes */
49/* Function prototypes */
48#if defined(__i386__)
50#if __i386__
49static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
50 struct pmc_op_pmcallocate *_pmc_config);
51static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
52 struct pmc_op_pmcallocate *_pmc_config);
51#endif
52#if defined(__amd64__) || defined(__i386__)
53static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
53static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
54 struct pmc_op_pmcallocate *_pmc_config);
54 struct pmc_op_pmcallocate *_pmc_config);
55static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
57static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
59static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
61static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
62 struct pmc_op_pmcallocate *_pmc_config);
63static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
64 struct pmc_op_pmcallocate *_pmc_config);
55static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
65#endif
66#if defined(__i386__)
67static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
68 struct pmc_op_pmcallocate *_pmc_config);
57static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
69static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
59#elif __amd64__
60static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
70 struct pmc_op_pmcallocate *_pmc_config);
71#endif
61 struct pmc_op_pmcallocate *_pmc_config);
62#endif
72#if defined(__amd64__) || defined(__i386__)
73static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
74 struct pmc_op_pmcallocate *_pmc_config);
75#endif
76#if defined(__XSCALE__)
77static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
78 struct pmc_op_pmcallocate *_pmc_config);
79#endif
80
63
81#if defined(__mips__)
82static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec,
83 struct pmc_op_pmcallocate *_pmc_config);
84#endif /* __mips__ */
85
86
87#define PMC_CALL(cmd, params) \
88 syscall(pmc_syscall, PMC_OP_##cmd, (params))
89
90/*
91 * Event aliases provide a way for the user to ask for generic events
92 * like "cache-misses", or "instructions-retired". These aliases are
93 * mapped to the appropriate canonical event descriptions using a
94 * lookup table.
95 */
64#define PMC_CALL(cmd, params) \
65 syscall(pmc_syscall, PMC_OP_##cmd, (params))
66
67/*
68 * Event aliases provide a way for the user to ask for generic events
69 * like "cache-misses", or "instructions-retired". These aliases are
70 * mapped to the appropriate canonical event descriptions using a
71 * lookup table.
72 */
73
96struct pmc_event_alias {
97 const char *pm_alias;
98 const char *pm_spec;
99};
100
101static const struct pmc_event_alias *pmc_mdep_event_aliases;
102
103/*
74struct pmc_event_alias {
75 const char *pm_alias;
76 const char *pm_spec;
77};
78
79static const struct pmc_event_alias *pmc_mdep_event_aliases;
80
81/*
104 * The pmc_event_descr structure maps symbolic names known to the user
82 * The pmc_event_descr table maps symbolic names known to the user
105 * to integer codes used by the PMC KLD.
106 */
83 * to integer codes used by the PMC KLD.
84 */
85
107struct pmc_event_descr {
108 const char *pm_ev_name;
109 enum pmc_event pm_ev_code;
86struct pmc_event_descr {
87 const char *pm_ev_name;
88 enum pmc_event pm_ev_code;
89 enum pmc_class pm_ev_class;
110};
111
90};
91
112/*
113 * The pmc_class_descr structure maps class name prefixes for
114 * event names to event tables and other PMC class data.
115 */
116struct pmc_class_descr {
117 const char *pm_evc_name;
118 size_t pm_evc_name_size;
119 enum pmc_class pm_evc_class;
120 const struct pmc_event_descr *pm_evc_event_table;
121 size_t pm_evc_event_table_size;
122 int (*pm_evc_allocate_pmc)(enum pmc_event _pe,
123 char *_ctrspec, struct pmc_op_pmcallocate *_pa);
124};
125
126#define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0]))
127#define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
128
129#undef __PMC_EV
130#define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
131
132/*
133 * PMC_CLASSDEP_TABLE(NAME, CLASS)
134 *
135 * Define a table mapping event names and aliases to HWPMC event IDs.
136 */
137#define PMC_CLASSDEP_TABLE(N, C) \
138 static const struct pmc_event_descr N##_event_table[] = \
139 { \
140 __PMC_EV_##C() \
141 }
142
143PMC_CLASSDEP_TABLE(iaf, IAF);
144PMC_CLASSDEP_TABLE(k7, K7);
145PMC_CLASSDEP_TABLE(k8, K8);
146PMC_CLASSDEP_TABLE(p4, P4);
147PMC_CLASSDEP_TABLE(p5, P5);
148PMC_CLASSDEP_TABLE(p6, P6);
149PMC_CLASSDEP_TABLE(xscale, XSCALE);
150PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
151PMC_CLASSDEP_TABLE(ucf, UCF);
152
153#undef __PMC_EV_ALIAS
154#define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
155
156static const struct pmc_event_descr atom_event_table[] =
92static const struct pmc_event_descr
93pmc_event_table[] =
157{
94{
158 __PMC_EV_ALIAS_ATOM()
95#undef __PMC_EV
96#define __PMC_EV(C,N,EV) { #EV, PMC_EV_ ## C ## _ ## N, PMC_CLASS_ ## C },
97 __PMC_EVENTS()
159};
160
98};
99
161static const struct pmc_event_descr core_event_table[] =
162{
163 __PMC_EV_ALIAS_CORE()
164};
165
166
167static const struct pmc_event_descr core2_event_table[] =
168{
169 __PMC_EV_ALIAS_CORE2()
170};
171
172static const struct pmc_event_descr corei7_event_table[] =
173{
174 __PMC_EV_ALIAS_COREI7()
175};
176
177static const struct pmc_event_descr westmere_event_table[] =
178{
179 __PMC_EV_ALIAS_WESTMERE()
180};
181
182static const struct pmc_event_descr corei7uc_event_table[] =
183{
184 __PMC_EV_ALIAS_COREI7UC()
185};
186
187static const struct pmc_event_descr westmereuc_event_table[] =
188{
189 __PMC_EV_ALIAS_WESTMEREUC()
190};
191
192/*
100/*
193 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
194 *
195 * Map a CPU to the PMC classes it supports.
196 */
197#define PMC_MDEP_TABLE(N,C,...) \
198 static const enum pmc_class N##_pmc_classes[] = { \
199 PMC_CLASS_##C, __VA_ARGS__ \
200 }
201
202PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
203PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC);
204PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
205PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
206PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
207PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC);
208PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC);
209PMC_MDEP_TABLE(p4, P4, PMC_CLASS_TSC);
210PMC_MDEP_TABLE(p5, P5, PMC_CLASS_TSC);
211PMC_MDEP_TABLE(p6, P6, PMC_CLASS_TSC);
212PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_XSCALE);
213PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_MIPS24K);
214
215static const struct pmc_event_descr tsc_event_table[] =
216{
217 __PMC_EV_TSC()
218};
219
220#undef PMC_CLASS_TABLE_DESC
221#define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \
222static const struct pmc_class_descr NAME##_class_table_descr = \
223 { \
224 .pm_evc_name = #CLASS "-", \
225 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \
226 .pm_evc_class = PMC_CLASS_##CLASS , \
227 .pm_evc_event_table = EVENTS##_event_table , \
228 .pm_evc_event_table_size = \
229 PMC_EVENT_TABLE_SIZE(EVENTS), \
230 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
231 }
232
233#if defined(__i386__) || defined(__amd64__)
234PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
235PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
236PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
237PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
238PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
239PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
240PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
241PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
242PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
243#endif
244#if defined(__i386__)
245PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
246#endif
247#if defined(__i386__) || defined(__amd64__)
248PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
249PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
250#endif
251#if defined(__i386__)
252PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
253PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
254#endif
255#if defined(__i386__) || defined(__amd64__)
256PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
257#endif
258#if defined(__XSCALE__)
259PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
260#endif
261
262#if defined(__mips__)
263PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k);
264#endif /* __mips__ */
265
266#undef PMC_CLASS_TABLE_DESC
267
268static const struct pmc_class_descr **pmc_class_table;
269#define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass
270
271static const enum pmc_class *pmc_mdep_class_list;
272static size_t pmc_mdep_class_list_size;
273
274/*
275 * Mapping tables, mapping enumeration values to human readable
276 * strings.
277 */
278
279static const char * pmc_capability_names[] = {
280#undef __PMC_CAP
281#define __PMC_CAP(N,V,D) #N ,
282 __PMC_CAPS()
283};
284
285static const char * pmc_class_names[] = {
286#undef __PMC_CLASS
287#define __PMC_CLASS(C) #C ,
288 __PMC_CLASSES()
289};
290
101 * Mapping tables, mapping enumeration values to human readable
102 * strings.
103 */
104
105static const char * pmc_capability_names[] = {
106#undef __PMC_CAP
107#define __PMC_CAP(N,V,D) #N ,
108 __PMC_CAPS()
109};
110
111static const char * pmc_class_names[] = {
112#undef __PMC_CLASS
113#define __PMC_CLASS(C) #C ,
114 __PMC_CLASSES()
115};
116
291struct pmc_cputype_map {
292 enum pmc_class pm_cputype;
293 const char *pm_name;
294};
295
296static const struct pmc_cputype_map pmc_cputype_names[] = {
117static const char * pmc_cputype_names[] = {
297#undef __PMC_CPU
118#undef __PMC_CPU
298#define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
119#define __PMC_CPU(S, D) #S ,
299 __PMC_CPUS()
300};
301
302static const char * pmc_disposition_names[] = {
303#undef __PMC_DISP
304#define __PMC_DISP(D) #D ,
305 __PMC_DISPOSITIONS()
306};

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314static const char * pmc_state_names[] = {
315#undef __PMC_STATE
316#define __PMC_STATE(S) #S ,
317 __PMC_STATES()
318};
319
320static int pmc_syscall = -1; /* filled in by pmc_init() */
321
120 __PMC_CPUS()
121};
122
123static const char * pmc_disposition_names[] = {
124#undef __PMC_DISP
125#define __PMC_DISP(D) #D ,
126 __PMC_DISPOSITIONS()
127};

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135static const char * pmc_state_names[] = {
136#undef __PMC_STATE
137#define __PMC_STATE(S) #S ,
138 __PMC_STATES()
139};
140
141static int pmc_syscall = -1; /* filled in by pmc_init() */
142
322static struct pmc_cpuinfo cpu_info; /* filled in by pmc_init() */
143struct pmc_op_getcpuinfo cpu_info; /* filled in by pmc_init() */
323
144
145/* Architecture dependent event parsing */
146static int (*pmc_mdep_allocate_pmc)(enum pmc_event _pe, char *_ctrspec,
147 struct pmc_op_pmcallocate *_pmc_config);
148
324/* Event masks for events */
325struct pmc_masks {
326 const char *pm_name;
327 const uint32_t pm_value;
328};
329#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
149/* Event masks for events */
150struct pmc_masks {
151 const char *pm_name;
152 const uint32_t pm_value;
153};
154#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
330#define NULLMASK { .pm_name = NULL }
155#define NULLMASK PMCMASK(NULL,0)
331
156
332#if defined(__amd64__) || defined(__i386__)
333static int
334pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
335{
336 const struct pmc_masks *pm;
337 char *q, *r;
338 int c;
339
340 if (pmask == NULL) /* no mask keywords */
157static int
158pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
159{
160 const struct pmc_masks *pm;
161 char *q, *r;
162 int c;
163
164 if (pmask == NULL) /* no mask keywords */
341 return (-1);
342 q = strchr(p, '='); /* skip '=' */
165 return -1;
166 q = strchr(p, '='); /* skip '=' */
343 if (*++q == '\0') /* no more data */
167 if (*++q == '\0') /* no more data */
344 return (-1);
168 return -1;
345 c = 0; /* count of mask keywords seen */
346 while ((r = strsep(&q, "+")) != NULL) {
169 c = 0; /* count of mask keywords seen */
170 while ((r = strsep(&q, "+")) != NULL) {
347 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
348 pm++)
171 for (pm = pmask; pm->pm_name && strcmp(r, pm->pm_name); pm++)
349 ;
350 if (pm->pm_name == NULL) /* not found */
172 ;
173 if (pm->pm_name == NULL) /* not found */
351 return (-1);
174 return -1;
352 *evmask |= pm->pm_value;
353 c++;
354 }
175 *evmask |= pm->pm_value;
176 c++;
177 }
355 return (c);
178 return c;
356}
179}
357#endif
358
359#define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
360#define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
361#define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
362
180
181#define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
182#define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
183#define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
184
363#if defined(__i386__)
185#if __i386__
364
365/*
366 * AMD K7 (Athlon) CPUs.
367 */
368
369static struct pmc_event_alias k7_aliases[] = {
186
187/*
188 * AMD K7 (Athlon) CPUs.
189 */
190
191static struct pmc_event_alias k7_aliases[] = {
370 EV_ALIAS("branches", "k7-retired-branches"),
371 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"),
372 EV_ALIAS("cycles", "tsc"),
373 EV_ALIAS("dc-misses", "k7-dc-misses"),
374 EV_ALIAS("ic-misses", "k7-ic-misses"),
375 EV_ALIAS("instructions", "k7-retired-instructions"),
376 EV_ALIAS("interrupts", "k7-hardware-interrupts"),
377 EV_ALIAS(NULL, NULL)
192EV_ALIAS("branches", "k7-retired-branches"),
193EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"),
194EV_ALIAS("cycles", "tsc"),
195EV_ALIAS("dc-misses", "k7-dc-misses,mask=moesi"),
196EV_ALIAS("ic-misses", "k7-ic-misses"),
197EV_ALIAS("instructions", "k7-retired-instructions"),
198EV_ALIAS("interrupts", "k7-hardware-interrupts"),
199EV_ALIAS(NULL, NULL)
378};
379
380#define K7_KW_COUNT "count"
381#define K7_KW_EDGE "edge"
382#define K7_KW_INV "inv"
383#define K7_KW_OS "os"
384#define K7_KW_UNITMASK "unitmask"
385#define K7_KW_USR "usr"
386
387static int
388k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
389 struct pmc_op_pmcallocate *pmc_config)
390{
200};
201
202#define K7_KW_COUNT "count"
203#define K7_KW_EDGE "edge"
204#define K7_KW_INV "inv"
205#define K7_KW_OS "os"
206#define K7_KW_UNITMASK "unitmask"
207#define K7_KW_USR "usr"
208
209static int
210k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
211 struct pmc_op_pmcallocate *pmc_config)
212{
391 char *e, *p, *q;
392 int c, has_unitmask;
213 char *e, *p, *q;
214 int c, has_unitmask;
393 uint32_t count, unitmask;
394
215 uint32_t count, unitmask;
216
395 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
396 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
217 pmc_config->pm_amd_config = 0;
218 pmc_config->pm_caps |= PMC_CAP_READ;
397
219
220 if (pe == PMC_EV_TSC_TSC) {
221 /* TSC events must be unqualified. */
222 if (ctrspec && *ctrspec != '\0')
223 return -1;
224 return 0;
225 }
226
398 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
399 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
400 pe == PMC_EV_K7_DC_WRITEBACKS) {
401 has_unitmask = 1;
227 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
228 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
229 pe == PMC_EV_K7_DC_WRITEBACKS) {
230 has_unitmask = 1;
402 unitmask = AMD_PMC_UNITMASK_MOESI;
231 unitmask = K7_PMC_UNITMASK_MOESI;
403 } else
404 unitmask = has_unitmask = 0;
405
232 } else
233 unitmask = has_unitmask = 0;
234
235 pmc_config->pm_caps |= PMC_CAP_WRITE;
236
406 while ((p = strsep(&ctrspec, ",")) != NULL) {
407 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
408 q = strchr(p, '=');
409 if (*++q == '\0') /* skip '=' */
237 while ((p = strsep(&ctrspec, ",")) != NULL) {
238 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
239 q = strchr(p, '=');
240 if (*++q == '\0') /* skip '=' */
410 return (-1);
241 return -1;
411
412 count = strtol(q, &e, 0);
413 if (e == q || *e != '\0')
242
243 count = strtol(q, &e, 0);
244 if (e == q || *e != '\0')
414 return (-1);
245 return -1;
415
416 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
246
247 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
417 pmc_config->pm_md.pm_amd.pm_amd_config |=
418 AMD_PMC_TO_COUNTER(count);
248 pmc_config->pm_amd_config |= K7_PMC_TO_COUNTER(count);
419
420 } else if (KWMATCH(p, K7_KW_EDGE)) {
421 pmc_config->pm_caps |= PMC_CAP_EDGE;
422 } else if (KWMATCH(p, K7_KW_INV)) {
423 pmc_config->pm_caps |= PMC_CAP_INVERT;
424 } else if (KWMATCH(p, K7_KW_OS)) {
425 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
426 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
427 if (has_unitmask == 0)
249
250 } else if (KWMATCH(p, K7_KW_EDGE)) {
251 pmc_config->pm_caps |= PMC_CAP_EDGE;
252 } else if (KWMATCH(p, K7_KW_INV)) {
253 pmc_config->pm_caps |= PMC_CAP_INVERT;
254 } else if (KWMATCH(p, K7_KW_OS)) {
255 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
256 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
257 if (has_unitmask == 0)
428 return (-1);
258 return -1;
429 unitmask = 0;
430 q = strchr(p, '=');
431 if (*++q == '\0') /* skip '=' */
259 unitmask = 0;
260 q = strchr(p, '=');
261 if (*++q == '\0') /* skip '=' */
432 return (-1);
262 return -1;
433
434 while ((c = tolower(*q++)) != 0)
435 if (c == 'm')
263
264 while ((c = tolower(*q++)) != 0)
265 if (c == 'm')
436 unitmask |= AMD_PMC_UNITMASK_M;
266 unitmask |= K7_PMC_UNITMASK_M;
437 else if (c == 'o')
267 else if (c == 'o')
438 unitmask |= AMD_PMC_UNITMASK_O;
268 unitmask |= K7_PMC_UNITMASK_O;
439 else if (c == 'e')
269 else if (c == 'e')
440 unitmask |= AMD_PMC_UNITMASK_E;
270 unitmask |= K7_PMC_UNITMASK_E;
441 else if (c == 's')
271 else if (c == 's')
442 unitmask |= AMD_PMC_UNITMASK_S;
272 unitmask |= K7_PMC_UNITMASK_S;
443 else if (c == 'i')
273 else if (c == 'i')
444 unitmask |= AMD_PMC_UNITMASK_I;
274 unitmask |= K7_PMC_UNITMASK_I;
445 else if (c == '+')
446 continue;
447 else
275 else if (c == '+')
276 continue;
277 else
448 return (-1);
278 return -1;
449
450 if (unitmask == 0)
279
280 if (unitmask == 0)
451 return (-1);
281 return -1;
452
453 } else if (KWMATCH(p, K7_KW_USR)) {
454 pmc_config->pm_caps |= PMC_CAP_USER;
455 } else
282
283 } else if (KWMATCH(p, K7_KW_USR)) {
284 pmc_config->pm_caps |= PMC_CAP_USER;
285 } else
456 return (-1);
286 return -1;
457 }
458
459 if (has_unitmask) {
460 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
287 }
288
289 if (has_unitmask) {
290 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
461 pmc_config->pm_md.pm_amd.pm_amd_config |=
462 AMD_PMC_TO_UNITMASK(unitmask);
291 pmc_config->pm_amd_config |=
292 K7_PMC_TO_UNITMASK(unitmask);
463 }
464
293 }
294
465 return (0);
295 return 0;
466
467}
468
296
297}
298
469#endif
470
471#if defined(__amd64__) || defined(__i386__)
472
473/*
299/*
474 * Intel Core (Family 6, Model E) PMCs.
475 */
476
477static struct pmc_event_alias core_aliases[] = {
478 EV_ALIAS("branches", "iap-br-instr-ret"),
479 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"),
480 EV_ALIAS("cycles", "tsc-tsc"),
481 EV_ALIAS("ic-misses", "iap-icache-misses"),
482 EV_ALIAS("instructions", "iap-instr-ret"),
483 EV_ALIAS("interrupts", "iap-core-hw-int-rx"),
484 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"),
485 EV_ALIAS(NULL, NULL)
486};
487
488/*
489 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
490 * and Atom (Family 6, model 1CH) PMCs.
491 *
492 * We map aliases to events on the fixed-function counters if these
493 * are present. Note that not all CPUs in this family contain fixed-function
494 * counters.
495 */
496
497static struct pmc_event_alias core2_aliases[] = {
498 EV_ALIAS("branches", "iap-br-inst-retired.any"),
499 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
500 EV_ALIAS("cycles", "tsc-tsc"),
501 EV_ALIAS("ic-misses", "iap-l1i-misses"),
502 EV_ALIAS("instructions", "iaf-instr-retired.any"),
503 EV_ALIAS("interrupts", "iap-hw-int-rcv"),
504 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"),
505 EV_ALIAS(NULL, NULL)
506};
507
508static struct pmc_event_alias core2_aliases_without_iaf[] = {
509 EV_ALIAS("branches", "iap-br-inst-retired.any"),
510 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
511 EV_ALIAS("cycles", "tsc-tsc"),
512 EV_ALIAS("ic-misses", "iap-l1i-misses"),
513 EV_ALIAS("instructions", "iap-inst-retired.any_p"),
514 EV_ALIAS("interrupts", "iap-hw-int-rcv"),
515 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"),
516 EV_ALIAS(NULL, NULL)
517};
518
519#define atom_aliases core2_aliases
520#define atom_aliases_without_iaf core2_aliases_without_iaf
521#define corei7_aliases core2_aliases
522#define corei7_aliases_without_iaf core2_aliases_without_iaf
523#define westmere_aliases core2_aliases
524#define westmere_aliases_without_iaf core2_aliases_without_iaf
525
526#define IAF_KW_OS "os"
527#define IAF_KW_USR "usr"
528#define IAF_KW_ANYTHREAD "anythread"
529
530/*
531 * Parse an event specifier for Intel fixed function counters.
532 */
533static int
534iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
535 struct pmc_op_pmcallocate *pmc_config)
536{
537 char *p;
538
539 (void) pe;
540
541 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
542 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
543
544 while ((p = strsep(&ctrspec, ",")) != NULL) {
545 if (KWMATCH(p, IAF_KW_OS))
546 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
547 else if (KWMATCH(p, IAF_KW_USR))
548 pmc_config->pm_caps |= PMC_CAP_USER;
549 else if (KWMATCH(p, IAF_KW_ANYTHREAD))
550 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
551 else
552 return (-1);
553 }
554
555 return (0);
556}
557
558/*
559 * Core/Core2 support.
560 */
561
562#define IAP_KW_AGENT "agent"
563#define IAP_KW_ANYTHREAD "anythread"
564#define IAP_KW_CACHESTATE "cachestate"
565#define IAP_KW_CMASK "cmask"
566#define IAP_KW_CORE "core"
567#define IAP_KW_EDGE "edge"
568#define IAP_KW_INV "inv"
569#define IAP_KW_OS "os"
570#define IAP_KW_PREFETCH "prefetch"
571#define IAP_KW_SNOOPRESPONSE "snoopresponse"
572#define IAP_KW_SNOOPTYPE "snooptype"
573#define IAP_KW_TRANSITION "trans"
574#define IAP_KW_USR "usr"
575#define IAP_KW_RSP "rsp"
576
577static struct pmc_masks iap_core_mask[] = {
578 PMCMASK(all, (0x3 << 14)),
579 PMCMASK(this, (0x1 << 14)),
580 NULLMASK
581};
582
583static struct pmc_masks iap_agent_mask[] = {
584 PMCMASK(this, 0),
585 PMCMASK(any, (0x1 << 13)),
586 NULLMASK
587};
588
589static struct pmc_masks iap_prefetch_mask[] = {
590 PMCMASK(both, (0x3 << 12)),
591 PMCMASK(only, (0x1 << 12)),
592 PMCMASK(exclude, 0),
593 NULLMASK
594};
595
596static struct pmc_masks iap_cachestate_mask[] = {
597 PMCMASK(i, (1 << 8)),
598 PMCMASK(s, (1 << 9)),
599 PMCMASK(e, (1 << 10)),
600 PMCMASK(m, (1 << 11)),
601 NULLMASK
602};
603
604static struct pmc_masks iap_snoopresponse_mask[] = {
605 PMCMASK(clean, (1 << 8)),
606 PMCMASK(hit, (1 << 9)),
607 PMCMASK(hitm, (1 << 11)),
608 NULLMASK
609};
610
611static struct pmc_masks iap_snooptype_mask[] = {
612 PMCMASK(cmp2s, (1 << 8)),
613 PMCMASK(cmp2i, (1 << 9)),
614 NULLMASK
615};
616
617static struct pmc_masks iap_transition_mask[] = {
618 PMCMASK(any, 0x00),
619 PMCMASK(frequency, 0x10),
620 NULLMASK
621};
622
623static struct pmc_masks iap_rsp_mask[] = {
624 PMCMASK(DMND_DATA_RD, (1 << 0)),
625 PMCMASK(DMND_RFO, (1 << 1)),
626 PMCMASK(DMND_IFETCH, (1 << 2)),
627 PMCMASK(WB, (1 << 3)),
628 PMCMASK(PF_DATA_RD, (1 << 4)),
629 PMCMASK(PF_RFO, (1 << 5)),
630 PMCMASK(PF_IFETCH, (1 << 6)),
631 PMCMASK(OTHER, (1 << 7)),
632 PMCMASK(UNCORE_HIT, (1 << 8)),
633 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)),
634 PMCMASK(OTHER_CORE_HITM, (1 << 10)),
635 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)),
636 PMCMASK(REMOTE_DRAM, (1 << 13)),
637 PMCMASK(LOCAL_DRAM, (1 << 14)),
638 PMCMASK(NON_DRAM, (1 << 15)),
639 NULLMASK
640};
641
642static int
643iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
644 struct pmc_op_pmcallocate *pmc_config)
645{
646 char *e, *p, *q;
647 uint32_t cachestate, evmask, rsp;
648 int count, n;
649
650 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
651 PMC_CAP_QUALIFIER);
652 pmc_config->pm_md.pm_iap.pm_iap_config = 0;
653
654 cachestate = evmask = rsp = 0;
655
656 /* Parse additional modifiers if present */
657 while ((p = strsep(&ctrspec, ",")) != NULL) {
658
659 n = 0;
660 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
661 q = strchr(p, '=');
662 if (*++q == '\0') /* skip '=' */
663 return (-1);
664 count = strtol(q, &e, 0);
665 if (e == q || *e != '\0')
666 return (-1);
667 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
668 pmc_config->pm_md.pm_iap.pm_iap_config |=
669 IAP_CMASK(count);
670 } else if (KWMATCH(p, IAP_KW_EDGE)) {
671 pmc_config->pm_caps |= PMC_CAP_EDGE;
672 } else if (KWMATCH(p, IAP_KW_INV)) {
673 pmc_config->pm_caps |= PMC_CAP_INVERT;
674 } else if (KWMATCH(p, IAP_KW_OS)) {
675 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
676 } else if (KWMATCH(p, IAP_KW_USR)) {
677 pmc_config->pm_caps |= PMC_CAP_USER;
678 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
679 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
680 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
681 n = pmc_parse_mask(iap_core_mask, p, &evmask);
682 if (n != 1)
683 return (-1);
684 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
685 n = pmc_parse_mask(iap_agent_mask, p, &evmask);
686 if (n != 1)
687 return (-1);
688 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
689 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
690 if (n != 1)
691 return (-1);
692 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
693 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
694 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
695 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
696 n = pmc_parse_mask(iap_transition_mask, p, &evmask);
697 if (n != 1)
698 return (-1);
699 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
700 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
701 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
702 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
703 n = pmc_parse_mask(iap_snoopresponse_mask, p,
704 &evmask);
705 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
706 n = pmc_parse_mask(iap_snooptype_mask, p,
707 &evmask);
708 } else
709 return (-1);
710 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
711 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
712 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
713 n = pmc_parse_mask(iap_rsp_mask, p, &rsp);
714 } else
715 return (-1);
716 } else
717 return (-1);
718
719 if (n < 0) /* Parsing failed. */
720 return (-1);
721 }
722
723 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
724
725 /*
726 * If the event requires a 'cachestate' qualifier but was not
727 * specified by the user, use a sensible default.
728 */
729 switch (pe) {
730 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
731 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
732 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
733 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
734 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
735 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
736 case PMC_EV_IAP_EVENT_32H: /* Core */
737 case PMC_EV_IAP_EVENT_40H: /* Core */
738 case PMC_EV_IAP_EVENT_41H: /* Core */
739 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
740 case PMC_EV_IAP_EVENT_77H: /* Core */
741 if (cachestate == 0)
742 cachestate = (0xF << 8);
743 default:
744 break;
745 }
746
747 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
748 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
749
750 return (0);
751}
752
753/*
754 * Intel Uncore.
755 */
756
757static int
758ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
759 struct pmc_op_pmcallocate *pmc_config)
760{
761 (void) pe;
762 (void) ctrspec;
763
764 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
765 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
766
767 return (0);
768}
769
770#define UCP_KW_CMASK "cmask"
771#define UCP_KW_EDGE "edge"
772#define UCP_KW_INV "inv"
773
774static int
775ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
776 struct pmc_op_pmcallocate *pmc_config)
777{
778 char *e, *p, *q;
779 int count, n;
780
781 (void) pe;
782
783 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
784 PMC_CAP_QUALIFIER);
785 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
786
787 /* Parse additional modifiers if present */
788 while ((p = strsep(&ctrspec, ",")) != NULL) {
789
790 n = 0;
791 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
792 q = strchr(p, '=');
793 if (*++q == '\0') /* skip '=' */
794 return (-1);
795 count = strtol(q, &e, 0);
796 if (e == q || *e != '\0')
797 return (-1);
798 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
799 pmc_config->pm_md.pm_ucp.pm_ucp_config |=
800 UCP_CMASK(count);
801 } else if (KWMATCH(p, UCP_KW_EDGE)) {
802 pmc_config->pm_caps |= PMC_CAP_EDGE;
803 } else if (KWMATCH(p, UCP_KW_INV)) {
804 pmc_config->pm_caps |= PMC_CAP_INVERT;
805 } else
806 return (-1);
807
808 if (n < 0) /* Parsing failed. */
809 return (-1);
810 }
811
812 return (0);
813}
814
815/*
816 * AMD K8 PMCs.
817 *
818 * These are very similar to AMD K7 PMCs, but support more kinds of
819 * events.
820 */
821
822static struct pmc_event_alias k8_aliases[] = {
823 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),
824 EV_ALIAS("branch-mispredicts",
825 "k8-fr-retired-taken-branches-mispredicted"),
826 EV_ALIAS("cycles", "tsc"),
827 EV_ALIAS("dc-misses", "k8-dc-miss"),
828 EV_ALIAS("ic-misses", "k8-ic-miss"),
829 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
830 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"),
831 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"),
832 EV_ALIAS(NULL, NULL)
833};
834
835#define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
836
837/*
838 * Parsing tables
839 */
840
841/* fp dispatched fpu ops */
842static const struct pmc_masks k8_mask_fdfo[] = {
843 __K8MASK(add-pipe-excluding-junk-ops, 0),
844 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
845 __K8MASK(store-pipe-excluding-junk-ops, 2),
846 __K8MASK(add-pipe-junk-ops, 3),
847 __K8MASK(multiply-pipe-junk-ops, 4),
848 __K8MASK(store-pipe-junk-ops, 5),
849 NULLMASK
850};
851
852/* ls segment register loads */
853static const struct pmc_masks k8_mask_lsrl[] = {
854 __K8MASK(es, 0),
855 __K8MASK(cs, 1),
856 __K8MASK(ss, 2),
857 __K8MASK(ds, 3),
858 __K8MASK(fs, 4),
859 __K8MASK(gs, 5),
860 __K8MASK(hs, 6),
861 NULLMASK
862};
863
864/* ls locked operation */
865static const struct pmc_masks k8_mask_llo[] = {
866 __K8MASK(locked-instructions, 0),
867 __K8MASK(cycles-in-request, 1),
868 __K8MASK(cycles-to-complete, 2),
869 NULLMASK
870};
871
872/* dc refill from {l2,system} and dc copyback */
873static const struct pmc_masks k8_mask_dc[] = {
874 __K8MASK(invalid, 0),
875 __K8MASK(shared, 1),
876 __K8MASK(exclusive, 2),
877 __K8MASK(owner, 3),
878 __K8MASK(modified, 4),
879 NULLMASK
880};
881
882/* dc one bit ecc error */
883static const struct pmc_masks k8_mask_dobee[] = {
884 __K8MASK(scrubber, 0),
885 __K8MASK(piggyback, 1),
886 NULLMASK
887};
888
889/* dc dispatched prefetch instructions */
890static const struct pmc_masks k8_mask_ddpi[] = {
891 __K8MASK(load, 0),
892 __K8MASK(store, 1),
893 __K8MASK(nta, 2),
894 NULLMASK
895};
896
897/* dc dcache accesses by locks */
898static const struct pmc_masks k8_mask_dabl[] = {
899 __K8MASK(accesses, 0),
900 __K8MASK(misses, 1),
901 NULLMASK
902};
903
904/* bu internal l2 request */
905static const struct pmc_masks k8_mask_bilr[] = {
906 __K8MASK(ic-fill, 0),
907 __K8MASK(dc-fill, 1),
908 __K8MASK(tlb-reload, 2),
909 __K8MASK(tag-snoop, 3),
910 __K8MASK(cancelled, 4),
911 NULLMASK
912};
913
914/* bu fill request l2 miss */
915static const struct pmc_masks k8_mask_bfrlm[] = {
916 __K8MASK(ic-fill, 0),
917 __K8MASK(dc-fill, 1),
918 __K8MASK(tlb-reload, 2),
919 NULLMASK
920};
921
922/* bu fill into l2 */
923static const struct pmc_masks k8_mask_bfil[] = {
924 __K8MASK(dirty-l2-victim, 0),
925 __K8MASK(victim-from-l2, 1),
926 NULLMASK
927};
928
929/* fr retired fpu instructions */
930static const struct pmc_masks k8_mask_frfi[] = {
931 __K8MASK(x87, 0),
932 __K8MASK(mmx-3dnow, 1),
933 __K8MASK(packed-sse-sse2, 2),
934 __K8MASK(scalar-sse-sse2, 3),
935 NULLMASK
936};
937
938/* fr retired fastpath double op instructions */
939static const struct pmc_masks k8_mask_frfdoi[] = {
940 __K8MASK(low-op-pos-0, 0),
941 __K8MASK(low-op-pos-1, 1),
942 __K8MASK(low-op-pos-2, 2),
943 NULLMASK
944};
945
946/* fr fpu exceptions */
947static const struct pmc_masks k8_mask_ffe[] = {
948 __K8MASK(x87-reclass-microfaults, 0),
949 __K8MASK(sse-retype-microfaults, 1),
950 __K8MASK(sse-reclass-microfaults, 2),
951 __K8MASK(sse-and-x87-microtraps, 3),
952 NULLMASK
953};
954
955/* nb memory controller page access event */
956static const struct pmc_masks k8_mask_nmcpae[] = {
957 __K8MASK(page-hit, 0),
958 __K8MASK(page-miss, 1),
959 __K8MASK(page-conflict, 2),
960 NULLMASK
961};
962
963/* nb memory controller turnaround */
964static const struct pmc_masks k8_mask_nmct[] = {
965 __K8MASK(dimm-turnaround, 0),
966 __K8MASK(read-to-write-turnaround, 1),
967 __K8MASK(write-to-read-turnaround, 2),
968 NULLMASK
969};
970
971/* nb memory controller bypass saturation */
972static const struct pmc_masks k8_mask_nmcbs[] = {
973 __K8MASK(memory-controller-hi-pri-bypass, 0),
974 __K8MASK(memory-controller-lo-pri-bypass, 1),
975 __K8MASK(dram-controller-interface-bypass, 2),
976 __K8MASK(dram-controller-queue-bypass, 3),
977 NULLMASK
978};
979
980/* nb sized commands */
981static const struct pmc_masks k8_mask_nsc[] = {
982 __K8MASK(nonpostwrszbyte, 0),
983 __K8MASK(nonpostwrszdword, 1),
984 __K8MASK(postwrszbyte, 2),
985 __K8MASK(postwrszdword, 3),
986 __K8MASK(rdszbyte, 4),
987 __K8MASK(rdszdword, 5),
988 __K8MASK(rdmodwr, 6),
989 NULLMASK
990};
991
992/* nb probe result */
993static const struct pmc_masks k8_mask_npr[] = {
994 __K8MASK(probe-miss, 0),
995 __K8MASK(probe-hit, 1),
996 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
997 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
998 NULLMASK
999};
1000
1001/* nb hypertransport bus bandwidth */
1002static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
1003 __K8MASK(command, 0),
1004 __K8MASK(data, 1),
1005 __K8MASK(buffer-release, 2),
1006 __K8MASK(nop, 3),
1007 NULLMASK
1008};
1009
1010#undef __K8MASK
1011
1012#define K8_KW_COUNT "count"
1013#define K8_KW_EDGE "edge"
1014#define K8_KW_INV "inv"
1015#define K8_KW_MASK "mask"
1016#define K8_KW_OS "os"
1017#define K8_KW_USR "usr"
1018
1019static int
1020k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1021 struct pmc_op_pmcallocate *pmc_config)
1022{
1023 char *e, *p, *q;
1024 int n;
1025 uint32_t count, evmask;
1026 const struct pmc_masks *pm, *pmask;
1027
1028 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1029 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1030
1031 pmask = NULL;
1032 evmask = 0;
1033
1034#define __K8SETMASK(M) pmask = k8_mask_##M
1035
1036 /* setup parsing tables */
1037 switch (pe) {
1038 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1039 __K8SETMASK(fdfo);
1040 break;
1041 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1042 __K8SETMASK(lsrl);
1043 break;
1044 case PMC_EV_K8_LS_LOCKED_OPERATION:
1045 __K8SETMASK(llo);
1046 break;
1047 case PMC_EV_K8_DC_REFILL_FROM_L2:
1048 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1049 case PMC_EV_K8_DC_COPYBACK:
1050 __K8SETMASK(dc);
1051 break;
1052 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1053 __K8SETMASK(dobee);
1054 break;
1055 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1056 __K8SETMASK(ddpi);
1057 break;
1058 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1059 __K8SETMASK(dabl);
1060 break;
1061 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1062 __K8SETMASK(bilr);
1063 break;
1064 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1065 __K8SETMASK(bfrlm);
1066 break;
1067 case PMC_EV_K8_BU_FILL_INTO_L2:
1068 __K8SETMASK(bfil);
1069 break;
1070 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1071 __K8SETMASK(frfi);
1072 break;
1073 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1074 __K8SETMASK(frfdoi);
1075 break;
1076 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1077 __K8SETMASK(ffe);
1078 break;
1079 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1080 __K8SETMASK(nmcpae);
1081 break;
1082 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1083 __K8SETMASK(nmct);
1084 break;
1085 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1086 __K8SETMASK(nmcbs);
1087 break;
1088 case PMC_EV_K8_NB_SIZED_COMMANDS:
1089 __K8SETMASK(nsc);
1090 break;
1091 case PMC_EV_K8_NB_PROBE_RESULT:
1092 __K8SETMASK(npr);
1093 break;
1094 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1095 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1096 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1097 __K8SETMASK(nhbb);
1098 break;
1099
1100 default:
1101 break; /* no options defined */
1102 }
1103
1104 while ((p = strsep(&ctrspec, ",")) != NULL) {
1105 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1106 q = strchr(p, '=');
1107 if (*++q == '\0') /* skip '=' */
1108 return (-1);
1109
1110 count = strtol(q, &e, 0);
1111 if (e == q || *e != '\0')
1112 return (-1);
1113
1114 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1115 pmc_config->pm_md.pm_amd.pm_amd_config |=
1116 AMD_PMC_TO_COUNTER(count);
1117
1118 } else if (KWMATCH(p, K8_KW_EDGE)) {
1119 pmc_config->pm_caps |= PMC_CAP_EDGE;
1120 } else if (KWMATCH(p, K8_KW_INV)) {
1121 pmc_config->pm_caps |= PMC_CAP_INVERT;
1122 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1123 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1124 return (-1);
1125 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1126 } else if (KWMATCH(p, K8_KW_OS)) {
1127 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1128 } else if (KWMATCH(p, K8_KW_USR)) {
1129 pmc_config->pm_caps |= PMC_CAP_USER;
1130 } else
1131 return (-1);
1132 }
1133
1134 /* other post processing */
1135 switch (pe) {
1136 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1137 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1138 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1139 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1140 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1141 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1142 /* XXX only available in rev B and later */
1143 break;
1144 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1145 /* XXX only available in rev C and later */
1146 break;
1147 case PMC_EV_K8_LS_LOCKED_OPERATION:
1148 /* XXX CPU Rev A,B evmask is to be zero */
1149 if (evmask & (evmask - 1)) /* > 1 bit set */
1150 return (-1);
1151 if (evmask == 0) {
1152 evmask = 0x01; /* Rev C and later: #instrs */
1153 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1154 }
1155 break;
1156 default:
1157 if (evmask == 0 && pmask != NULL) {
1158 for (pm = pmask; pm->pm_name; pm++)
1159 evmask |= pm->pm_value;
1160 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1161 }
1162 }
1163
1164 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1165 pmc_config->pm_md.pm_amd.pm_amd_config =
1166 AMD_PMC_TO_UNITMASK(evmask);
1167
1168 return (0);
1169}
1170
1171#endif
1172
1173#if defined(__amd64__) || defined(__i386__)
1174
1175/*
1176 * Intel P4 PMCs
1177 */
1178
1179static struct pmc_event_alias p4_aliases[] = {
300 * Intel P4 PMCs
301 */
302
303static struct pmc_event_alias p4_aliases[] = {
1180 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"),
1181 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"),
1182 EV_ALIAS("cycles", "tsc"),
1183 EV_ALIAS("instructions",
1184 "p4-instr-retired,mask=nbogusntag+nbogustag"),
1185 EV_ALIAS("unhalted-cycles", "p4-global-power-events"),
304 EV_ALIAS("cycles", "tsc"),
1186 EV_ALIAS(NULL, NULL)
1187};
1188
1189#define P4_KW_ACTIVE "active"
1190#define P4_KW_ACTIVE_ANY "any"
1191#define P4_KW_ACTIVE_BOTH "both"
1192#define P4_KW_ACTIVE_NONE "none"
1193#define P4_KW_ACTIVE_SINGLE "single"

--- 196 unchanged lines hidden (view full) ---

1390
1391static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
1392 __P4MASK(from-tc-build, 0),
1393 __P4MASK(from-tc-deliver, 1),
1394 __P4MASK(from-rom, 2),
1395 NULLMASK
1396};
1397
305 EV_ALIAS(NULL, NULL)
306};
307
308#define P4_KW_ACTIVE "active"
309#define P4_KW_ACTIVE_ANY "any"
310#define P4_KW_ACTIVE_BOTH "both"
311#define P4_KW_ACTIVE_NONE "none"
312#define P4_KW_ACTIVE_SINGLE "single"

--- 196 unchanged lines hidden (view full) ---

509
510static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
511 __P4MASK(from-tc-build, 0),
512 __P4MASK(from-tc-deliver, 1),
513 __P4MASK(from-rom, 2),
514 NULLMASK
515};
516
1398static const struct pmc_masks p4_mask_rmbt[] = {
1399 /* retired mispred branch type */
517static const struct pmc_masks p4_mask_rmbt[] = { /* retired mispred branch type */
1400 __P4MASK(conditional, 1),
1401 __P4MASK(call, 2),
1402 __P4MASK(return, 3),
1403 __P4MASK(indirect, 4),
1404 NULLMASK
1405};
1406
1407static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */

--- 94 unchanged lines hidden (view full) ---

1502 struct pmc_op_pmcallocate *pmc_config)
1503{
1504
1505 char *e, *p, *q;
1506 int count, has_tag, has_busreqtype, n;
1507 uint32_t evmask, cccractivemask;
1508 const struct pmc_masks *pm, *pmask;
1509
518 __P4MASK(conditional, 1),
519 __P4MASK(call, 2),
520 __P4MASK(return, 3),
521 __P4MASK(indirect, 4),
522 NULLMASK
523};
524
525static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */

--- 94 unchanged lines hidden (view full) ---

620 struct pmc_op_pmcallocate *pmc_config)
621{
622
623 char *e, *p, *q;
624 int count, has_tag, has_busreqtype, n;
625 uint32_t evmask, cccractivemask;
626 const struct pmc_masks *pm, *pmask;
627
1510 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1511 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig =
1512 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0;
628 pmc_config->pm_caps |= PMC_CAP_READ;
629 pmc_config->pm_p4_cccrconfig = pmc_config->pm_p4_escrconfig = 0;
1513
630
631 if (pe == PMC_EV_TSC_TSC) {
632 /* TSC must not be further qualified */
633 if (ctrspec && *ctrspec != '\0')
634 return -1;
635 return 0;
636 }
637
1514 pmask = NULL;
1515 evmask = 0;
1516 cccractivemask = 0x3;
1517 has_tag = has_busreqtype = 0;
638 pmask = NULL;
639 evmask = 0;
640 cccractivemask = 0x3;
641 has_tag = has_busreqtype = 0;
642 pmc_config->pm_caps |= PMC_CAP_WRITE;
1518
1519#define __P4SETMASK(M) do { \
643
644#define __P4SETMASK(M) do { \
1520 pmask = p4_mask_##M; \
645 pmask = p4_mask_##M; \
1521} while (0)
1522
1523 switch (pe) {
1524 case PMC_EV_P4_TC_DELIVER_MODE:
1525 __P4SETMASK(tcdm);
1526 break;
1527 case PMC_EV_P4_BPU_FETCH_REQUEST:
1528 __P4SETMASK(bfr);

--- 116 unchanged lines hidden (view full) ---

1645 break;
1646 case PMC_EV_P4_X87_ASSIST:
1647 __P4SETMASK(xa);
1648 break;
1649 case PMC_EV_P4_MACHINE_CLEAR:
1650 __P4SETMASK(machclr);
1651 break;
1652 default:
646} while (0)
647
648 switch (pe) {
649 case PMC_EV_P4_TC_DELIVER_MODE:
650 __P4SETMASK(tcdm);
651 break;
652 case PMC_EV_P4_BPU_FETCH_REQUEST:
653 __P4SETMASK(bfr);

--- 116 unchanged lines hidden (view full) ---

770 break;
771 case PMC_EV_P4_X87_ASSIST:
772 __P4SETMASK(xa);
773 break;
774 case PMC_EV_P4_MACHINE_CLEAR:
775 __P4SETMASK(machclr);
776 break;
777 default:
1653 return (-1);
778 return -1;
1654 }
1655
1656 /* process additional flags */
1657 while ((p = strsep(&ctrspec, ",")) != NULL) {
1658 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
1659 q = strchr(p, '=');
1660 if (*++q == '\0') /* skip '=' */
779 }
780
781 /* process additional flags */
782 while ((p = strsep(&ctrspec, ",")) != NULL) {
783 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
784 q = strchr(p, '=');
785 if (*++q == '\0') /* skip '=' */
1661 return (-1);
786 return -1;
1662
787
1663 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0)
788 if (strcmp(q, P4_KW_ACTIVE_NONE) == 0)
1664 cccractivemask = 0x0;
789 cccractivemask = 0x0;
1665 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0)
790 else if (strcmp(q, P4_KW_ACTIVE_SINGLE) == 0)
1666 cccractivemask = 0x1;
791 cccractivemask = 0x1;
1667 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0)
792 else if (strcmp(q, P4_KW_ACTIVE_BOTH) == 0)
1668 cccractivemask = 0x2;
793 cccractivemask = 0x2;
1669 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0)
794 else if (strcmp(q, P4_KW_ACTIVE_ANY) == 0)
1670 cccractivemask = 0x3;
1671 else
795 cccractivemask = 0x3;
796 else
1672 return (-1);
797 return -1;
1673
1674 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
1675 if (has_busreqtype == 0)
798
799 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
800 if (has_busreqtype == 0)
1676 return (-1);
801 return -1;
1677
1678 q = strchr(p, '=');
1679 if (*++q == '\0') /* skip '=' */
802
803 q = strchr(p, '=');
804 if (*++q == '\0') /* skip '=' */
1680 return (-1);
805 return -1;
1681
1682 count = strtol(q, &e, 0);
1683 if (e == q || *e != '\0')
806
807 count = strtol(q, &e, 0);
808 if (e == q || *e != '\0')
1684 return (-1);
809 return -1;
1685 evmask = (evmask & ~0x1F) | (count & 0x1F);
1686 } else if (KWMATCH(p, P4_KW_CASCADE))
1687 pmc_config->pm_caps |= PMC_CAP_CASCADE;
1688 else if (KWMATCH(p, P4_KW_EDGE))
1689 pmc_config->pm_caps |= PMC_CAP_EDGE;
1690 else if (KWMATCH(p, P4_KW_INV))
1691 pmc_config->pm_caps |= PMC_CAP_INVERT;
1692 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
1693 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
810 evmask = (evmask & ~0x1F) | (count & 0x1F);
811 } else if (KWMATCH(p, P4_KW_CASCADE))
812 pmc_config->pm_caps |= PMC_CAP_CASCADE;
813 else if (KWMATCH(p, P4_KW_EDGE))
814 pmc_config->pm_caps |= PMC_CAP_EDGE;
815 else if (KWMATCH(p, P4_KW_INV))
816 pmc_config->pm_caps |= PMC_CAP_INVERT;
817 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
818 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1694 return (-1);
819 return -1;
1695 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1696 } else if (KWMATCH(p, P4_KW_OS))
1697 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1698 else if (KWMATCH(p, P4_KW_PRECISE))
1699 pmc_config->pm_caps |= PMC_CAP_PRECISE;
1700 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
1701 if (has_tag == 0)
820 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
821 } else if (KWMATCH(p, P4_KW_OS))
822 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
823 else if (KWMATCH(p, P4_KW_PRECISE))
824 pmc_config->pm_caps |= PMC_CAP_PRECISE;
825 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
826 if (has_tag == 0)
1702 return (-1);
827 return -1;
1703
1704 q = strchr(p, '=');
1705 if (*++q == '\0') /* skip '=' */
828
829 q = strchr(p, '=');
830 if (*++q == '\0') /* skip '=' */
1706 return (-1);
831 return -1;
1707
1708 count = strtol(q, &e, 0);
1709 if (e == q || *e != '\0')
832
833 count = strtol(q, &e, 0);
834 if (e == q || *e != '\0')
1710 return (-1);
835 return -1;
1711
1712 pmc_config->pm_caps |= PMC_CAP_TAGGING;
836
837 pmc_config->pm_caps |= PMC_CAP_TAGGING;
1713 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |=
838 pmc_config->pm_p4_escrconfig |=
1714 P4_ESCR_TO_TAG_VALUE(count);
1715 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
1716 q = strchr(p, '=');
1717 if (*++q == '\0') /* skip '=' */
839 P4_ESCR_TO_TAG_VALUE(count);
840 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
841 q = strchr(p, '=');
842 if (*++q == '\0') /* skip '=' */
1718 return (-1);
843 return -1;
1719
1720 count = strtol(q, &e, 0);
1721 if (e == q || *e != '\0')
844
845 count = strtol(q, &e, 0);
846 if (e == q || *e != '\0')
1722 return (-1);
847 return -1;
1723
1724 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
848
849 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1725 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &=
1726 ~P4_CCCR_THRESHOLD_MASK;
1727 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1728 P4_CCCR_TO_THRESHOLD(count);
850 pmc_config->pm_p4_cccrconfig &= ~P4_CCCR_THRESHOLD_MASK;
851 pmc_config->pm_p4_cccrconfig |= P4_CCCR_TO_THRESHOLD(count);
1729 } else if (KWMATCH(p, P4_KW_USR))
1730 pmc_config->pm_caps |= PMC_CAP_USER;
1731 else
852 } else if (KWMATCH(p, P4_KW_USR))
853 pmc_config->pm_caps |= PMC_CAP_USER;
854 else
1732 return (-1);
855 return -1;
1733 }
1734
1735 /* other post processing */
1736 if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
1737 pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
1738 pe == PMC_EV_P4_BSQ_ALLOCATION)
1739 pmc_config->pm_caps |= PMC_CAP_EDGE;
1740
1741 /* fill in thread activity mask */
856 }
857
858 /* other post processing */
859 if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
860 pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
861 pe == PMC_EV_P4_BSQ_ALLOCATION)
862 pmc_config->pm_caps |= PMC_CAP_EDGE;
863
864 /* fill in thread activity mask */
1742 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
865 pmc_config->pm_p4_cccrconfig |=
1743 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
1744
1745 if (evmask)
1746 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1747
1748 switch (pe) {
1749 case PMC_EV_P4_FSB_DATA_ACTIVITY:
1750 if ((evmask & 0x06) == 0x06 ||
1751 (evmask & 0x18) == 0x18)
866 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
867
868 if (evmask)
869 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
870
871 switch (pe) {
872 case PMC_EV_P4_FSB_DATA_ACTIVITY:
873 if ((evmask & 0x06) == 0x06 ||
874 (evmask & 0x18) == 0x18)
1752 return (-1); /* can't have own+other bits together */
875 return -1; /* can't have own+other bits together */
1753 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
1754 evmask = 0x1D;
1755 break;
1756 case PMC_EV_P4_MACHINE_CLEAR:
1757 /* only one bit is allowed to be set */
1758 if ((evmask & (evmask - 1)) != 0)
876 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
877 evmask = 0x1D;
878 break;
879 case PMC_EV_P4_MACHINE_CLEAR:
880 /* only one bit is allowed to be set */
881 if ((evmask & (evmask - 1)) != 0)
1759 return (-1);
882 return -1;
1760 if (evmask == 0) {
883 if (evmask == 0) {
1761 evmask = 0x1; /* 'CLEAR' */
884 evmask = 0x1; /* 'CLEAR' */
1762 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1763 }
1764 break;
1765 default:
1766 if (evmask == 0 && pmask) {
1767 for (pm = pmask; pm->pm_name; pm++)
1768 evmask |= pm->pm_value;
1769 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1770 }
1771 }
1772
885 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
886 }
887 break;
888 default:
889 if (evmask == 0 && pmask) {
890 for (pm = pmask; pm->pm_name; pm++)
891 evmask |= pm->pm_value;
892 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
893 }
894 }
895
1773 pmc_config->pm_md.pm_p4.pm_p4_escrconfig =
1774 P4_ESCR_TO_EVENT_MASK(evmask);
896 pmc_config->pm_p4_escrconfig = P4_ESCR_TO_EVENT_MASK(evmask);
1775
897
1776 return (0);
898 return 0;
1777}
1778
899}
900
1779#endif
1780
1781#if defined(__i386__)
1782
1783/*
901/*
1784 * Pentium style PMCs
1785 */
1786
1787static struct pmc_event_alias p5_aliases[] = {
1788 EV_ALIAS("branches", "p5-taken-branches"),
1789 EV_ALIAS("cycles", "tsc"),
1790 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"),
1791 EV_ALIAS("ic-misses", "p5-code-cache-miss"),
1792 EV_ALIAS("instructions", "p5-instructions-executed"),
1793 EV_ALIAS("interrupts", "p5-hardware-interrupts"),
1794 EV_ALIAS("unhalted-cycles",
1795 "p5-number-of-cycles-not-in-halt-state"),
1796 EV_ALIAS(NULL, NULL)
1797};
1798
1799static int
1800p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
1801 struct pmc_op_pmcallocate *pmc_config)
1802{
1803 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */
1804}
1805
1806/*
1807 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III,
1808 * and Pentium M CPUs.
1809 */
1810
1811static struct pmc_event_alias p6_aliases[] = {
902 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III,
903 * and Pentium M CPUs.
904 */
905
906static struct pmc_event_alias p6_aliases[] = {
1812 EV_ALIAS("branches", "p6-br-inst-retired"),
1813 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"),
1814 EV_ALIAS("cycles", "tsc"),
1815 EV_ALIAS("dc-misses", "p6-dcu-lines-in"),
1816 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"),
1817 EV_ALIAS("instructions", "p6-inst-retired"),
1818 EV_ALIAS("interrupts", "p6-hw-int-rx"),
1819 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"),
1820 EV_ALIAS(NULL, NULL)
907EV_ALIAS("branches", "p6-br-inst-retired"),
908EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"),
909EV_ALIAS("cycles", "tsc"),
910EV_ALIAS("instructions", "p6-inst-retired"),
911EV_ALIAS("interrupts", "p6-hw-int-rx"),
912EV_ALIAS(NULL, NULL)
1821};
1822
1823#define P6_KW_CMASK "cmask"
1824#define P6_KW_EDGE "edge"
1825#define P6_KW_INV "inv"
1826#define P6_KW_OS "os"
1827#define P6_KW_UMASK "umask"
1828#define P6_KW_USR "usr"

--- 102 unchanged lines hidden (view full) ---

1931p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
1932 struct pmc_op_pmcallocate *pmc_config)
1933{
1934 char *e, *p, *q;
1935 uint32_t evmask;
1936 int count, n;
1937 const struct pmc_masks *pm, *pmask;
1938
913};
914
915#define P6_KW_CMASK "cmask"
916#define P6_KW_EDGE "edge"
917#define P6_KW_INV "inv"
918#define P6_KW_OS "os"
919#define P6_KW_UMASK "umask"
920#define P6_KW_USR "usr"

--- 102 unchanged lines hidden (view full) ---

1023p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
1024 struct pmc_op_pmcallocate *pmc_config)
1025{
1026 char *e, *p, *q;
1027 uint32_t evmask;
1028 int count, n;
1029 const struct pmc_masks *pm, *pmask;
1030
1939 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1940 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0;
1031 pmc_config->pm_caps |= PMC_CAP_READ;
1032 pmc_config->pm_p6_config = 0;
1941
1033
1034 if (pe == PMC_EV_TSC_TSC) {
1035 if (ctrspec && *ctrspec != '\0')
1036 return -1;
1037 return 0;
1038 }
1039
1040 pmc_config->pm_caps |= PMC_CAP_WRITE;
1942 evmask = 0;
1943
1944#define P6MASKSET(M) pmask = p6_mask_ ## M
1945
1946 switch(pe) {
1041 evmask = 0;
1042
1043#define P6MASKSET(M) pmask = p6_mask_ ## M
1044
1045 switch(pe) {
1947 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break;
1046 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break;
1948 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break;
1949 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break;
1950 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break;
1951 case PMC_EV_P6_BUS_DRDY_CLOCKS:
1952 case PMC_EV_P6_BUS_LOCK_CLOCKS:
1953 case PMC_EV_P6_BUS_TRAN_BRD:
1954 case PMC_EV_P6_BUS_TRAN_RFO:
1955 case PMC_EV_P6_BUS_TRANS_WB:

--- 43 unchanged lines hidden (view full) ---

1999 P6MASKSET(hw);
2000 }
2001
2002 /* Parse additional modifiers if present */
2003 while ((p = strsep(&ctrspec, ",")) != NULL) {
2004 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
2005 q = strchr(p, '=');
2006 if (*++q == '\0') /* skip '=' */
1047 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break;
1048 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break;
1049 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break;
1050 case PMC_EV_P6_BUS_DRDY_CLOCKS:
1051 case PMC_EV_P6_BUS_LOCK_CLOCKS:
1052 case PMC_EV_P6_BUS_TRAN_BRD:
1053 case PMC_EV_P6_BUS_TRAN_RFO:
1054 case PMC_EV_P6_BUS_TRANS_WB:

--- 43 unchanged lines hidden (view full) ---

1098 P6MASKSET(hw);
1099 }
1100
1101 /* Parse additional modifiers if present */
1102 while ((p = strsep(&ctrspec, ",")) != NULL) {
1103 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
1104 q = strchr(p, '=');
1105 if (*++q == '\0') /* skip '=' */
2007 return (-1);
1106 return -1;
2008 count = strtol(q, &e, 0);
2009 if (e == q || *e != '\0')
1107 count = strtol(q, &e, 0);
1108 if (e == q || *e != '\0')
2010 return (-1);
1109 return -1;
2011 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1110 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
2012 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2013 P6_EVSEL_TO_CMASK(count);
1111 pmc_config->pm_p6_config |= P6_EVSEL_TO_CMASK(count);
2014 } else if (KWMATCH(p, P6_KW_EDGE)) {
2015 pmc_config->pm_caps |= PMC_CAP_EDGE;
2016 } else if (KWMATCH(p, P6_KW_INV)) {
2017 pmc_config->pm_caps |= PMC_CAP_INVERT;
2018 } else if (KWMATCH(p, P6_KW_OS)) {
2019 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2020 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
2021 evmask = 0;
2022 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1112 } else if (KWMATCH(p, P6_KW_EDGE)) {
1113 pmc_config->pm_caps |= PMC_CAP_EDGE;
1114 } else if (KWMATCH(p, P6_KW_INV)) {
1115 pmc_config->pm_caps |= PMC_CAP_INVERT;
1116 } else if (KWMATCH(p, P6_KW_OS)) {
1117 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1118 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
1119 evmask = 0;
1120 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
2023 return (-1);
1121 return -1;
2024 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
2025 pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
2026 pe == PMC_EV_P6_BUS_TRAN_BRD ||
2027 pe == PMC_EV_P6_BUS_TRAN_RFO ||
2028 pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
2029 pe == PMC_EV_P6_BUS_TRAN_INVAL ||
2030 pe == PMC_EV_P6_BUS_TRAN_PWR ||
2031 pe == PMC_EV_P6_BUS_TRAN_DEF ||

--- 7 unchanged lines hidden (view full) ---

2039 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
2040 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
2041 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
2042 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
2043 pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
2044 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
2045 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
2046 pe == PMC_EV_P6_FP_MMX_TRANS)
1122 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
1123 pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
1124 pe == PMC_EV_P6_BUS_TRAN_BRD ||
1125 pe == PMC_EV_P6_BUS_TRAN_RFO ||
1126 pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
1127 pe == PMC_EV_P6_BUS_TRAN_INVAL ||
1128 pe == PMC_EV_P6_BUS_TRAN_PWR ||
1129 pe == PMC_EV_P6_BUS_TRAN_DEF ||

--- 7 unchanged lines hidden (view full) ---

1137 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
1138 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
1139 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
1140 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
1141 pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
1142 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
1143 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
1144 pe == PMC_EV_P6_FP_MMX_TRANS)
2047 && (n > 1)) /* Only one mask keyword is allowed. */
2048 return (-1);
1145 && (n > 1))
1146 return -1; /* only one mask keyword allowed */
2049 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2050 } else if (KWMATCH(p, P6_KW_USR)) {
2051 pmc_config->pm_caps |= PMC_CAP_USER;
2052 } else
1147 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1148 } else if (KWMATCH(p, P6_KW_USR)) {
1149 pmc_config->pm_caps |= PMC_CAP_USER;
1150 } else
2053 return (-1);
1151 return -1;
2054 }
2055
2056 /* post processing */
2057 switch (pe) {
2058
2059 /*
2060 * The following events default to an evmask of 0
2061 */

--- 36 unchanged lines hidden (view full) ---

2098 case PMC_EV_P6_EMON_EST_TRANS:
2099 break;
2100
2101 case PMC_EV_P6_MMX_UOPS_EXEC:
2102 evmask = 0x0F; /* only value allowed */
2103 break;
2104
2105 default:
1152 }
1153
1154 /* post processing */
1155 switch (pe) {
1156
1157 /*
1158 * The following events default to an evmask of 0
1159 */

--- 36 unchanged lines hidden (view full) ---

1196 case PMC_EV_P6_EMON_EST_TRANS:
1197 break;
1198
1199 case PMC_EV_P6_MMX_UOPS_EXEC:
1200 evmask = 0x0F; /* only value allowed */
1201 break;
1202
1203 default:
1204
2106 /*
2107 * For all other events, set the default event mask
2108 * to a logical OR of all the allowed event mask bits.
2109 */
1205 /*
1206 * For all other events, set the default event mask
1207 * to a logical OR of all the allowed event mask bits.
1208 */
1209
2110 if (evmask == 0 && pmask) {
2111 for (pm = pmask; pm->pm_name; pm++)
2112 evmask |= pm->pm_value;
2113 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2114 }
2115
2116 break;
2117 }
2118
2119 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1210 if (evmask == 0 && pmask) {
1211 for (pm = pmask; pm->pm_name; pm++)
1212 evmask |= pm->pm_value;
1213 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1214 }
1215
1216 break;
1217 }
1218
1219 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
2120 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2121 P6_EVSEL_TO_UMASK(evmask);
1220 pmc_config->pm_p6_config |= P6_EVSEL_TO_UMASK(evmask);
2122
1221
2123 return (0);
1222 return 0;
2124}
2125
1223}
1224
2126#endif
1225/*
1226 * Pentium style PMCs
1227 */
2127
1228
2128#if defined(__i386__) || defined(__amd64__)
1229static struct pmc_event_alias p5_aliases[] = {
1230 EV_ALIAS("cycles", "tsc"),
1231 EV_ALIAS(NULL, NULL)
1232};
1233
2129static int
1234static int
2130tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
1235p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
2131 struct pmc_op_pmcallocate *pmc_config)
2132{
1236 struct pmc_op_pmcallocate *pmc_config)
1237{
2133 if (pe != PMC_EV_TSC_TSC)
2134 return (-1);
1238 return -1 || pe || ctrspec || pmc_config; /* shut up gcc */
1239}
2135
1240
2136 /* TSC events must be unqualified. */
2137 if (ctrspec && *ctrspec != '\0')
2138 return (-1);
1241#elif __amd64__
2139
1242
2140 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
2141 pmc_config->pm_caps |= PMC_CAP_READ;
1243/*
1244 * AMD K8 PMCs.
1245 *
1246 * These are very similar to AMD K7 PMCs, but support more kinds of
1247 * events.
1248 */
2142
1249
2143 return (0);
2144}
2145#endif
1250static struct pmc_event_alias k8_aliases[] = {
1251 EV_ALIAS("cycles", "tsc"),
1252 EV_ALIAS(NULL, NULL)
1253};
2146
1254
2147#if defined(__XSCALE__)
1255#define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
2148
1256
2149static struct pmc_event_alias xscale_aliases[] = {
2150 EV_ALIAS("branches", "BRANCH_RETIRED"),
2151 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
2152 EV_ALIAS("dc-misses", "DC_MISS"),
2153 EV_ALIAS("ic-misses", "IC_MISS"),
2154 EV_ALIAS("instructions", "INSTR_RETIRED"),
2155 EV_ALIAS(NULL, NULL)
1257/*
1258 * Parsing tables
1259 */
1260
1261/* fp dispatched fpu ops */
1262static const struct pmc_masks k8_mask_fdfo[] = {
1263 __K8MASK(add-pipe-excluding-junk-ops, 0),
1264 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
1265 __K8MASK(store-pipe-excluding-junk-ops, 2),
1266 __K8MASK(add-pipe-junk-ops, 3),
1267 __K8MASK(multiply-pipe-junk-ops, 4),
1268 __K8MASK(store-pipe-junk-ops, 5),
1269 NULLMASK
2156};
1270};
2157static int
2158xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2159 struct pmc_op_pmcallocate *pmc_config __unused)
2160{
2161 switch (pe) {
2162 default:
2163 break;
2164 }
2165
1271
2166 return (0);
2167}
2168#endif
1272/* ls segment register loads */
1273static const struct pmc_masks k8_mask_lsrl[] = {
1274 __K8MASK(es, 0),
1275 __K8MASK(cs, 1),
1276 __K8MASK(ss, 2),
1277 __K8MASK(ds, 3),
1278 __K8MASK(fs, 4),
1279 __K8MASK(gs, 5),
1280 __K8MASK(hs, 6),
1281 NULLMASK
1282};
2169
1283
2170#if defined(__mips__)
1284/* ls locked operation */
1285static const struct pmc_masks k8_mask_llo[] = {
1286 __K8MASK(locked-instructions, 0),
1287 __K8MASK(cycles-in-request, 1),
1288 __K8MASK(cycles-to-complete, 2),
1289 NULLMASK
1290};
2171
1291
2172static struct pmc_event_alias mips24k_aliases[] = {
2173 EV_ALIAS("instructions", "INSTR_EXECUTED"),
2174 EV_ALIAS("branches", "BRANCH_COMPLETED"),
2175 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
2176 EV_ALIAS(NULL, NULL)
1292/* dc refill from {l2,system} and dc copyback */
1293static const struct pmc_masks k8_mask_dc[] = {
1294 __K8MASK(invalid, 0),
1295 __K8MASK(shared, 1),
1296 __K8MASK(exclusive, 2),
1297 __K8MASK(owner, 3),
1298 __K8MASK(modified, 4),
1299 NULLMASK
2177};
2178
1300};
1301
2179#define MIPS24K_KW_OS "os"
2180#define MIPS24K_KW_USR "usr"
2181#define MIPS24K_KW_ANYTHREAD "anythread"
1302/* dc one bit ecc error */
1303static const struct pmc_masks k8_mask_dobee[] = {
1304 __K8MASK(scrubber, 0),
1305 __K8MASK(piggyback, 1),
1306 NULLMASK
1307};
2182
1308
1309/* dc dispatched prefetch instructions */
1310static const struct pmc_masks k8_mask_ddpi[] = {
1311 __K8MASK(load, 0),
1312 __K8MASK(store, 1),
1313 __K8MASK(nta, 2),
1314 NULLMASK
1315};
1316
1317/* dc dcache accesses by locks */
1318static const struct pmc_masks k8_mask_dabl[] = {
1319 __K8MASK(accesses, 0),
1320 __K8MASK(misses, 1),
1321 NULLMASK
1322};
1323
1324/* bu internal l2 request */
1325static const struct pmc_masks k8_mask_bilr[] = {
1326 __K8MASK(ic-fill, 0),
1327 __K8MASK(dc-fill, 1),
1328 __K8MASK(tlb-reload, 2),
1329 __K8MASK(tag-snoop, 3),
1330 __K8MASK(cancelled, 4),
1331 NULLMASK
1332};
1333
1334/* bu fill request l2 miss */
1335static const struct pmc_masks k8_mask_bfrlm[] = {
1336 __K8MASK(ic-fill, 0),
1337 __K8MASK(dc-fill, 1),
1338 __K8MASK(tlb-reload, 2),
1339 NULLMASK
1340};
1341
1342/* bu fill into l2 */
1343static const struct pmc_masks k8_mask_bfil[] = {
1344 __K8MASK(dirty-l2-victim, 0),
1345 __K8MASK(victim-from-l2, 1),
1346 NULLMASK
1347};
1348
1349/* fr retired fpu instructions */
1350static const struct pmc_masks k8_mask_frfi[] = {
1351 __K8MASK(x87, 0),
1352 __K8MASK(mmx-3dnow, 1),
1353 __K8MASK(packed-sse-sse2, 2),
1354 __K8MASK(scalar-sse-sse2, 3),
1355 NULLMASK
1356};
1357
1358/* fr retired fastpath double op instructions */
1359static const struct pmc_masks k8_mask_frfdoi[] = {
1360 __K8MASK(low-op-pos-0, 0),
1361 __K8MASK(low-op-pos-1, 1),
1362 __K8MASK(low-op-pos-2, 2),
1363 NULLMASK
1364};
1365
1366/* fr fpu exceptions */
1367static const struct pmc_masks k8_mask_ffe[] = {
1368 __K8MASK(x87-reclass-microfaults, 0),
1369 __K8MASK(sse-retype-microfaults, 1),
1370 __K8MASK(sse-reclass-microfaults, 2),
1371 __K8MASK(sse-and-x87-microtraps, 3),
1372 NULLMASK
1373};
1374
1375/* nb memory controller page access event */
1376static const struct pmc_masks k8_mask_nmcpae[] = {
1377 __K8MASK(page-hit, 0),
1378 __K8MASK(page-miss, 1),
1379 __K8MASK(page-conflict, 2),
1380 NULLMASK
1381};
1382
1383/* nb memory controller turnaround */
1384static const struct pmc_masks k8_mask_nmct[] = {
1385 __K8MASK(dimm-turnaround, 0),
1386 __K8MASK(read-to-write-turnaround, 1),
1387 __K8MASK(write-to-read-turnaround, 2),
1388 NULLMASK
1389};
1390
1391/* nb memory controller bypass saturation */
1392static const struct pmc_masks k8_mask_nmcbs[] = {
1393 __K8MASK(memory-controller-hi-pri-bypass, 0),
1394 __K8MASK(memory-controller-lo-pri-bypass, 1),
1395 __K8MASK(dram-controller-interface-bypass, 2),
1396 __K8MASK(dram-controller-queue-bypass, 3),
1397 NULLMASK
1398};
1399
1400/* nb sized commands */
1401static const struct pmc_masks k8_mask_nsc[] = {
1402 __K8MASK(nonpostwrszbyte, 0),
1403 __K8MASK(nonpostwrszdword, 1),
1404 __K8MASK(postwrszbyte, 2),
1405 __K8MASK(postwrszdword, 3),
1406 __K8MASK(rdszbyte, 4),
1407 __K8MASK(rdszdword, 5),
1408 __K8MASK(rdmodwr, 6),
1409 NULLMASK
1410};
1411
1412/* nb probe result */
1413static const struct pmc_masks k8_mask_npr[] = {
1414 __K8MASK(probe-miss, 0),
1415 __K8MASK(probe-hit, 1),
1416 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
1417 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
1418 NULLMASK
1419};
1420
1421/* nb hypertransport bus bandwidth */
1422static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
1423 __K8MASK(command, 0),
1424 __K8MASK(data, 1),
1425 __K8MASK(buffer-release, 2),
1426 __K8MASK(nop, 3),
1427 NULLMASK
1428};
1429
1430#undef __K8MASK
1431
1432#define K8_KW_COUNT "count"
1433#define K8_KW_EDGE "edge"
1434#define K8_KW_INV "inv"
1435#define K8_KW_MASK "mask"
1436#define K8_KW_OS "os"
1437#define K8_KW_USR "usr"
1438
2183static int
1439static int
2184mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2185 struct pmc_op_pmcallocate *pmc_config __unused)
1440k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1441 struct pmc_op_pmcallocate *pmc_config)
2186{
1442{
2187 char *p;
1443 char *e, *p, *q;
1444 int n;
1445 uint32_t count, evmask;
1446 const struct pmc_masks *pm, *pmask;
2188
1447
2189 (void) pe;
1448 pmc_config->pm_caps |= PMC_CAP_READ;
1449 pmc_config->pm_amd_config = 0;
2190
1450
2191 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2192
2193 while ((p = strsep(&ctrspec, ",")) != NULL) {
2194 if (KWMATCH(p, MIPS24K_KW_OS))
2195 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2196 else if (KWMATCH(p, MIPS24K_KW_USR))
2197 pmc_config->pm_caps |= PMC_CAP_USER;
2198 else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD))
2199 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2200 else
2201 return (-1);
1451 if (pe == PMC_EV_TSC_TSC) {
1452 /* TSC events must be unqualified. */
1453 if (ctrspec && *ctrspec != '\0')
1454 return -1;
1455 return 0;
2202 }
2203
1456 }
1457
2204 return (0);
2205}
2206#endif /* __mips__ */
1458 pmask = NULL;
1459 evmask = 0;
2207
1460
1461#define __K8SETMASK(M) pmask = k8_mask_##M
2208
1462
2209/*
2210 * Match an event name `name' with its canonical form.
2211 *
2212 * Matches are case insensitive and spaces, periods, underscores and
2213 * hyphen characters are considered to match each other.
2214 *
2215 * Returns 1 for a match, 0 otherwise.
2216 */
1463 /* setup parsing tables */
1464 switch (pe) {
1465 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1466 __K8SETMASK(fdfo);
1467 break;
1468 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1469 __K8SETMASK(lsrl);
1470 break;
1471 case PMC_EV_K8_LS_LOCKED_OPERATION:
1472 __K8SETMASK(llo);
1473 break;
1474 case PMC_EV_K8_DC_REFILL_FROM_L2:
1475 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1476 case PMC_EV_K8_DC_COPYBACK:
1477 __K8SETMASK(dc);
1478 break;
1479 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1480 __K8SETMASK(dobee);
1481 break;
1482 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1483 __K8SETMASK(ddpi);
1484 break;
1485 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1486 __K8SETMASK(dabl);
1487 break;
1488 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1489 __K8SETMASK(bilr);
1490 break;
1491 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1492 __K8SETMASK(bfrlm);
1493 break;
1494 case PMC_EV_K8_BU_FILL_INTO_L2:
1495 __K8SETMASK(bfil);
1496 break;
1497 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1498 __K8SETMASK(frfi);
1499 break;
1500 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1501 __K8SETMASK(frfdoi);
1502 break;
1503 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1504 __K8SETMASK(ffe);
1505 break;
1506 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1507 __K8SETMASK(nmcpae);
1508 break;
1509 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1510 __K8SETMASK(nmct);
1511 break;
1512 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1513 __K8SETMASK(nmcbs);
1514 break;
1515 case PMC_EV_K8_NB_SIZED_COMMANDS:
1516 __K8SETMASK(nsc);
1517 break;
1518 case PMC_EV_K8_NB_PROBE_RESULT:
1519 __K8SETMASK(npr);
1520 break;
1521 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1522 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1523 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1524 __K8SETMASK(nhbb);
1525 break;
2217
1526
2218static int
2219pmc_match_event_name(const char *name, const char *canonicalname)
2220{
2221 int cc, nc;
2222 const unsigned char *c, *n;
1527 default:
1528 break; /* no options defined */
1529 }
2223
1530
2224 c = (const unsigned char *) canonicalname;
2225 n = (const unsigned char *) name;
1531 pmc_config->pm_caps |= PMC_CAP_WRITE;
2226
1532
2227 for (; (nc = *n) && (cc = *c); n++, c++) {
1533 while ((p = strsep(&ctrspec, ",")) != NULL) {
1534 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1535 q = strchr(p, '=');
1536 if (*++q == '\0') /* skip '=' */
1537 return -1;
2228
1538
2229 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
2230 (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
2231 continue;
1539 count = strtol(q, &e, 0);
1540 if (e == q || *e != '\0')
1541 return -1;
2232
1542
2233 if (toupper(nc) == toupper(cc))
2234 continue;
1543 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1544 pmc_config->pm_amd_config |= K8_PMC_TO_COUNTER(count);
2235
1545
1546 } else if (KWMATCH(p, K8_KW_EDGE)) {
1547 pmc_config->pm_caps |= PMC_CAP_EDGE;
1548 } else if (KWMATCH(p, K8_KW_INV)) {
1549 pmc_config->pm_caps |= PMC_CAP_INVERT;
1550 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1551 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1552 return -1;
1553 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1554 } else if (KWMATCH(p, K8_KW_OS)) {
1555 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1556 } else if (KWMATCH(p, K8_KW_USR)) {
1557 pmc_config->pm_caps |= PMC_CAP_USER;
1558 } else
1559 return -1;
1560 }
2236
1561
2237 return (0);
1562 /* other post processing */
1563
1564 switch (pe) {
1565 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1566 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1567 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1568 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1569 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1570 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1571 /* XXX only available in rev B and later */
1572 break;
1573 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1574 /* XXX only available in rev C and later */
1575 break;
1576 case PMC_EV_K8_LS_LOCKED_OPERATION:
1577 /* XXX CPU Rev A,B evmask is to be zero */
1578 if (evmask & (evmask - 1)) /* > 1 bit set */
1579 return -1;
1580 if (evmask == 0) {
1581 evmask = 0x01; /* Rev C and later: #instrs */
1582 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1583 }
1584 break;
1585 default:
1586 if (evmask == 0 && pmask != NULL) {
1587 for (pm = pmask; pm->pm_name; pm++)
1588 evmask |= pm->pm_value;
1589 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1590 }
2238 }
2239
1591 }
1592
2240 if (*n == '\0' && *c == '\0')
2241 return (1);
1593 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1594 pmc_config->pm_amd_config = K8_PMC_TO_UNITMASK(evmask);
2242
1595
2243 return (0);
1596 return 0;
2244}
1597}
1598#endif
2245
2246/*
1599
1600/*
2247 * Match an event name against all the event named supported by a
2248 * PMC class.
2249 *
2250 * Returns an event descriptor pointer on match or NULL otherwise.
1601 * API entry points
2251 */
1602 */
2252static const struct pmc_event_descr *
2253pmc_match_event_class(const char *name,
2254 const struct pmc_class_descr *pcd)
1603
1604int
1605pmc_init(void)
2255{
1606{
2256 size_t n;
2257 const struct pmc_event_descr *ev;
1607 int error, pmc_mod_id;
1608 uint32_t abi_version;
1609 struct module_stat pmc_modstat;
2258
1610
2259 ev = pcd->pm_evc_event_table;
2260 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
2261 if (pmc_match_event_name(name, ev->pm_ev_name))
2262 return (ev);
1611 if (pmc_syscall != -1) /* already inited */
1612 return 0;
2263
1613
2264 return (NULL);
2265}
1614 /* retrieve the system call number from the KLD */
1615 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
1616 return -1;
2266
1617
2267static int
2268pmc_mdep_is_compatible_class(enum pmc_class pc)
2269{
2270 size_t n;
1618 pmc_modstat.version = sizeof(struct module_stat);
1619 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
1620 return -1;
2271
1621
2272 for (n = 0; n < pmc_mdep_class_list_size; n++)
2273 if (pmc_mdep_class_list[n] == pc)
2274 return (1);
2275 return (0);
2276}
1622 pmc_syscall = pmc_modstat.data.intval;
2277
1623
2278/*
2279 * API entry points
2280 */
1624 /* check ABI version against compiled-in version */
1625 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
1626 return (pmc_syscall = -1);
2281
1627
1628 /* ignore patch numbers for the comparision */
1629 if ((abi_version & 0xFFFF0000) != (PMC_VERSION & 0xFFFF0000)) {
1630 errno = EPROGMISMATCH;
1631 return (pmc_syscall = -1);
1632 }
1633
1634 if (PMC_CALL(GETCPUINFO, &cpu_info) < 0)
1635 return (pmc_syscall = -1);
1636
1637 /* set parser pointer */
1638 switch (cpu_info.pm_cputype) {
1639#if __i386__
1640 case PMC_CPU_AMD_K7:
1641 pmc_mdep_event_aliases = k7_aliases;
1642 pmc_mdep_allocate_pmc = k7_allocate_pmc;
1643 break;
1644 case PMC_CPU_INTEL_P5:
1645 pmc_mdep_event_aliases = p5_aliases;
1646 pmc_mdep_allocate_pmc = p5_allocate_pmc;
1647 break;
1648 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */
1649 case PMC_CPU_INTEL_PII: /* similar PMCs. */
1650 case PMC_CPU_INTEL_PIII:
1651 case PMC_CPU_INTEL_PM:
1652 pmc_mdep_event_aliases = p6_aliases;
1653 pmc_mdep_allocate_pmc = p6_allocate_pmc;
1654 break;
1655 case PMC_CPU_INTEL_PIV:
1656 pmc_mdep_event_aliases = p4_aliases;
1657 pmc_mdep_allocate_pmc = p4_allocate_pmc;
1658 break;
1659#elif __amd64__
1660 case PMC_CPU_AMD_K8:
1661 pmc_mdep_event_aliases = k8_aliases;
1662 pmc_mdep_allocate_pmc = k8_allocate_pmc;
1663 break;
1664#endif
1665
1666 default:
1667 /*
1668 * Some kind of CPU this version of the library knows nothing
1669 * about. This shouldn't happen since the abi version check
1670 * should have caught this.
1671 */
1672 errno = ENXIO;
1673 return (pmc_syscall = -1);
1674 }
1675
1676 return 0;
1677}
1678
2282int
2283pmc_allocate(const char *ctrspec, enum pmc_mode mode,
2284 uint32_t flags, int cpu, pmc_id_t *pmcid)
2285{
1679int
1680pmc_allocate(const char *ctrspec, enum pmc_mode mode,
1681 uint32_t flags, int cpu, pmc_id_t *pmcid)
1682{
2286 size_t n;
2287 int retval;
1683 int retval;
1684 enum pmc_event pe;
2288 char *r, *spec_copy;
2289 const char *ctrname;
1685 char *r, *spec_copy;
1686 const char *ctrname;
2290 const struct pmc_event_descr *ev;
2291 const struct pmc_event_alias *alias;
1687 const struct pmc_event_alias *p;
2292 struct pmc_op_pmcallocate pmc_config;
1688 struct pmc_op_pmcallocate pmc_config;
2293 const struct pmc_class_descr *pcd;
2294
2295 spec_copy = NULL;
2296 retval = -1;
2297
2298 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
2299 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
2300 errno = EINVAL;
2301 goto out;
2302 }
2303
2304 /* replace an event alias with the canonical event specifier */
2305 if (pmc_mdep_event_aliases)
1689
1690 spec_copy = NULL;
1691 retval = -1;
1692
1693 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
1694 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
1695 errno = EINVAL;
1696 goto out;
1697 }
1698
1699 /* replace an event alias with the canonical event specifier */
1700 if (pmc_mdep_event_aliases)
2306 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
2307 if (!strcasecmp(ctrspec, alias->pm_alias)) {
2308 spec_copy = strdup(alias->pm_spec);
1701 for (p = pmc_mdep_event_aliases; p->pm_alias; p++)
1702 if (!strcmp(ctrspec, p->pm_alias)) {
1703 spec_copy = strdup(p->pm_spec);
2309 break;
2310 }
2311
2312 if (spec_copy == NULL)
2313 spec_copy = strdup(ctrspec);
2314
2315 r = spec_copy;
2316 ctrname = strsep(&r, ",");
2317
1704 break;
1705 }
1706
1707 if (spec_copy == NULL)
1708 spec_copy = strdup(ctrspec);
1709
1710 r = spec_copy;
1711 ctrname = strsep(&r, ",");
1712
2318 /*
2319 * If a explicit class prefix was given by the user, restrict the
2320 * search for the event to the specified PMC class.
2321 */
2322 ev = NULL;
2323 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
2324 pcd = pmc_class_table[n];
2325 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) &&
2326 strncasecmp(ctrname, pcd->pm_evc_name,
2327 pcd->pm_evc_name_size) == 0) {
2328 if ((ev = pmc_match_event_class(ctrname +
2329 pcd->pm_evc_name_size, pcd)) == NULL) {
2330 errno = EINVAL;
2331 goto out;
2332 }
1713 /* look for the given counter name */
1714
1715 for (pe = PMC_EVENT_FIRST; pe < (PMC_EVENT_LAST+1); pe++)
1716 if (!strcmp(ctrname, pmc_event_table[pe].pm_ev_name))
2333 break;
1717 break;
2334 }
2335 }
2336
1718
2337 /*
2338 * Otherwise, search for this event in all compatible PMC
2339 * classes.
2340 */
2341 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
2342 pcd = pmc_class_table[n];
2343 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class))
2344 ev = pmc_match_event_class(ctrname, pcd);
2345 }
2346
2347 if (ev == NULL) {
1719 if (pe > PMC_EVENT_LAST) {
2348 errno = EINVAL;
2349 goto out;
2350 }
2351
2352 bzero(&pmc_config, sizeof(pmc_config));
1720 errno = EINVAL;
1721 goto out;
1722 }
1723
1724 bzero(&pmc_config, sizeof(pmc_config));
2353 pmc_config.pm_ev = ev->pm_ev_code;
2354 pmc_config.pm_class = pcd->pm_evc_class;
1725 pmc_config.pm_ev = pmc_event_table[pe].pm_ev_code;
1726 pmc_config.pm_class = pmc_event_table[pe].pm_ev_class;
2355 pmc_config.pm_cpu = cpu;
2356 pmc_config.pm_mode = mode;
2357 pmc_config.pm_flags = flags;
2358
2359 if (PMC_IS_SAMPLING_MODE(mode))
2360 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
2361
1727 pmc_config.pm_cpu = cpu;
1728 pmc_config.pm_mode = mode;
1729 pmc_config.pm_flags = flags;
1730
1731 if (PMC_IS_SAMPLING_MODE(mode))
1732 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
1733
2362 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
1734 if (pmc_mdep_allocate_pmc(pe, r, &pmc_config) < 0) {
2363 errno = EINVAL;
2364 goto out;
2365 }
2366
2367 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
2368 goto out;
2369
2370 *pmcid = pmc_config.pm_pmcid;
2371
2372 retval = 0;
2373
2374 out:
2375 if (spec_copy)
2376 free(spec_copy);
2377
1735 errno = EINVAL;
1736 goto out;
1737 }
1738
1739 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
1740 goto out;
1741
1742 *pmcid = pmc_config.pm_pmcid;
1743
1744 retval = 0;
1745
1746 out:
1747 if (spec_copy)
1748 free(spec_copy);
1749
2378 return (retval);
1750 return retval;
2379}
2380
2381int
2382pmc_attach(pmc_id_t pmc, pid_t pid)
2383{
2384 struct pmc_op_pmcattach pmc_attach_args;
2385
2386 pmc_attach_args.pm_pmc = pmc;
2387 pmc_attach_args.pm_pid = pid;
2388
1751}
1752
1753int
1754pmc_attach(pmc_id_t pmc, pid_t pid)
1755{
1756 struct pmc_op_pmcattach pmc_attach_args;
1757
1758 pmc_attach_args.pm_pmc = pmc;
1759 pmc_attach_args.pm_pid = pid;
1760
2389 return (PMC_CALL(PMCATTACH, &pmc_attach_args));
1761 return PMC_CALL(PMCATTACH, &pmc_attach_args);
2390}
2391
2392int
1762}
1763
1764int
2393pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
2394{
2395 unsigned int i;
2396 enum pmc_class cl;
2397
2398 cl = PMC_ID_TO_CLASS(pmcid);
2399 for (i = 0; i < cpu_info.pm_nclass; i++)
2400 if (cpu_info.pm_classes[i].pm_class == cl) {
2401 *caps = cpu_info.pm_classes[i].pm_caps;
2402 return (0);
2403 }
2404 errno = EINVAL;
2405 return (-1);
2406}
2407
2408int
2409pmc_configure_logfile(int fd)
2410{
2411 struct pmc_op_configurelog cla;
2412
2413 cla.pm_logfd = fd;
2414 if (PMC_CALL(CONFIGURELOG, &cla) < 0)
2415 return (-1);
2416 return (0);
2417}
2418
2419int
2420pmc_cpuinfo(const struct pmc_cpuinfo **pci)
2421{
2422 if (pmc_syscall == -1) {
2423 errno = ENXIO;
2424 return (-1);
2425 }
2426
2427 *pci = &cpu_info;
2428 return (0);
2429}
2430
2431int
2432pmc_detach(pmc_id_t pmc, pid_t pid)
2433{
2434 struct pmc_op_pmcattach pmc_detach_args;
2435
2436 pmc_detach_args.pm_pmc = pmc;
2437 pmc_detach_args.pm_pid = pid;
1765pmc_detach(pmc_id_t pmc, pid_t pid)
1766{
1767 struct pmc_op_pmcattach pmc_detach_args;
1768
1769 pmc_detach_args.pm_pmc = pmc;
1770 pmc_detach_args.pm_pid = pid;
2438 return (PMC_CALL(PMCDETACH, &pmc_detach_args));
2439}
2440
1771
2441int
2442pmc_disable(int cpu, int pmc)
2443{
2444 struct pmc_op_pmcadmin ssa;
2445
2446 ssa.pm_cpu = cpu;
2447 ssa.pm_pmc = pmc;
2448 ssa.pm_state = PMC_STATE_DISABLED;
2449 return (PMC_CALL(PMCADMIN, &ssa));
1772 return PMC_CALL(PMCDETACH, &pmc_detach_args);
2450}
2451
2452int
1773}
1774
1775int
2453pmc_enable(int cpu, int pmc)
1776pmc_release(pmc_id_t pmc)
2454{
1777{
2455 struct pmc_op_pmcadmin ssa;
1778 struct pmc_op_simple pmc_release_args;
2456
1779
2457 ssa.pm_cpu = cpu;
2458 ssa.pm_pmc = pmc;
2459 ssa.pm_state = PMC_STATE_FREE;
2460 return (PMC_CALL(PMCADMIN, &ssa));
2461}
1780 pmc_release_args.pm_pmcid = pmc;
2462
1781
2463/*
2464 * Return a list of events known to a given PMC class. 'cl' is the
2465 * PMC class identifier, 'eventnames' is the returned list of 'const
2466 * char *' pointers pointing to the names of the events. 'nevents' is
2467 * the number of event name pointers returned.
2468 *
2469 * The space for 'eventnames' is allocated using malloc(3). The caller
2470 * is responsible for freeing this space when done.
2471 */
2472int
2473pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2474 int *nevents)
2475{
2476 int count;
2477 const char **names;
2478 const struct pmc_event_descr *ev;
2479
2480 switch (cl)
2481 {
2482 case PMC_CLASS_IAF:
2483 ev = iaf_event_table;
2484 count = PMC_EVENT_TABLE_SIZE(iaf);
2485 break;
2486 case PMC_CLASS_IAP:
2487 /*
2488 * Return the most appropriate set of event name
2489 * spellings for the current CPU.
2490 */
2491 switch (cpu_info.pm_cputype) {
2492 default:
2493 case PMC_CPU_INTEL_ATOM:
2494 ev = atom_event_table;
2495 count = PMC_EVENT_TABLE_SIZE(atom);
2496 break;
2497 case PMC_CPU_INTEL_CORE:
2498 ev = core_event_table;
2499 count = PMC_EVENT_TABLE_SIZE(core);
2500 break;
2501 case PMC_CPU_INTEL_CORE2:
2502 case PMC_CPU_INTEL_CORE2EXTREME:
2503 ev = core2_event_table;
2504 count = PMC_EVENT_TABLE_SIZE(core2);
2505 break;
2506 case PMC_CPU_INTEL_COREI7:
2507 ev = corei7_event_table;
2508 count = PMC_EVENT_TABLE_SIZE(corei7);
2509 break;
2510 case PMC_CPU_INTEL_WESTMERE:
2511 ev = westmere_event_table;
2512 count = PMC_EVENT_TABLE_SIZE(westmere);
2513 break;
2514 }
2515 break;
2516 case PMC_CLASS_UCF:
2517 ev = ucf_event_table;
2518 count = PMC_EVENT_TABLE_SIZE(ucf);
2519 break;
2520 case PMC_CLASS_UCP:
2521 /*
2522 * Return the most appropriate set of event name
2523 * spellings for the current CPU.
2524 */
2525 switch (cpu_info.pm_cputype) {
2526 default:
2527 case PMC_CPU_INTEL_COREI7:
2528 ev = corei7uc_event_table;
2529 count = PMC_EVENT_TABLE_SIZE(corei7uc);
2530 break;
2531 case PMC_CPU_INTEL_WESTMERE:
2532 ev = westmereuc_event_table;
2533 count = PMC_EVENT_TABLE_SIZE(westmereuc);
2534 break;
2535 }
2536 break;
2537 case PMC_CLASS_TSC:
2538 ev = tsc_event_table;
2539 count = PMC_EVENT_TABLE_SIZE(tsc);
2540 break;
2541 case PMC_CLASS_K7:
2542 ev = k7_event_table;
2543 count = PMC_EVENT_TABLE_SIZE(k7);
2544 break;
2545 case PMC_CLASS_K8:
2546 ev = k8_event_table;
2547 count = PMC_EVENT_TABLE_SIZE(k8);
2548 break;
2549 case PMC_CLASS_P4:
2550 ev = p4_event_table;
2551 count = PMC_EVENT_TABLE_SIZE(p4);
2552 break;
2553 case PMC_CLASS_P5:
2554 ev = p5_event_table;
2555 count = PMC_EVENT_TABLE_SIZE(p5);
2556 break;
2557 case PMC_CLASS_P6:
2558 ev = p6_event_table;
2559 count = PMC_EVENT_TABLE_SIZE(p6);
2560 break;
2561 case PMC_CLASS_XSCALE:
2562 ev = xscale_event_table;
2563 count = PMC_EVENT_TABLE_SIZE(xscale);
2564 break;
2565 case PMC_CLASS_MIPS24K:
2566 ev = mips24k_event_table;
2567 count = PMC_EVENT_TABLE_SIZE(mips24k);
2568 break;
2569 default:
2570 errno = EINVAL;
2571 return (-1);
2572 }
2573
2574 if ((names = malloc(count * sizeof(const char *))) == NULL)
2575 return (-1);
2576
2577 *eventnames = names;
2578 *nevents = count;
2579
2580 for (;count--; ev++, names++)
2581 *names = ev->pm_ev_name;
2582 return (0);
1782 return PMC_CALL(PMCRELEASE, &pmc_release_args);
2583}
2584
2585int
1783}
1784
1785int
2586pmc_flush_logfile(void)
1786pmc_start(pmc_id_t pmc)
2587{
1787{
2588 return (PMC_CALL(FLUSHLOG,0));
2589}
1788 struct pmc_op_simple pmc_start_args;
2590
1789
2591int
2592pmc_get_driver_stats(struct pmc_driverstats *ds)
2593{
2594 struct pmc_op_getdriverstats gms;
2595
2596 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0)
2597 return (-1);
2598
2599 /* copy out fields in the current userland<->library interface */
2600 ds->pm_intr_ignored = gms.pm_intr_ignored;
2601 ds->pm_intr_processed = gms.pm_intr_processed;
2602 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
2603 ds->pm_syscalls = gms.pm_syscalls;
2604 ds->pm_syscall_errors = gms.pm_syscall_errors;
2605 ds->pm_buffer_requests = gms.pm_buffer_requests;
2606 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
2607 ds->pm_log_sweeps = gms.pm_log_sweeps;
2608 return (0);
1790 pmc_start_args.pm_pmcid = pmc;
1791 return PMC_CALL(PMCSTART, &pmc_start_args);
2609}
2610
2611int
1792}
1793
1794int
2612pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
1795pmc_stop(pmc_id_t pmc)
2613{
1796{
2614 struct pmc_op_getmsr gm;
1797 struct pmc_op_simple pmc_stop_args;
2615
1798
2616 gm.pm_pmcid = pmc;
2617 if (PMC_CALL(PMCGETMSR, &gm) < 0)
2618 return (-1);
2619 *msr = gm.pm_msr;
2620 return (0);
1799 pmc_stop_args.pm_pmcid = pmc;
1800 return PMC_CALL(PMCSTOP, &pmc_stop_args);
2621}
2622
2623int
1801}
1802
1803int
2624pmc_init(void)
1804pmc_read(pmc_id_t pmc, pmc_value_t *value)
2625{
1805{
2626 int error, pmc_mod_id;
2627 unsigned int n;
2628 uint32_t abi_version;
2629 struct module_stat pmc_modstat;
2630 struct pmc_op_getcpuinfo op_cpu_info;
2631#if defined(__amd64__) || defined(__i386__)
2632 int cpu_has_iaf_counters;
2633 unsigned int t;
2634#endif
1806 struct pmc_op_pmcrw pmc_read_op;
2635
1807
2636 if (pmc_syscall != -1) /* already inited */
2637 return (0);
1808 pmc_read_op.pm_pmcid = pmc;
1809 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
1810 pmc_read_op.pm_value = -1;
2638
1811
2639 /* retrieve the system call number from the KLD */
2640 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
2641 return (-1);
1812 if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
1813 return -1;
2642
1814
2643 pmc_modstat.version = sizeof(struct module_stat);
2644 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
2645 return (-1);
1815 *value = pmc_read_op.pm_value;
2646
1816
2647 pmc_syscall = pmc_modstat.data.intval;
2648
2649 /* check the kernel module's ABI against our compiled-in version */
2650 abi_version = PMC_VERSION;
2651 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
2652 return (pmc_syscall = -1);
2653
2654 /* ignore patch & minor numbers for the comparision */
2655 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
2656 errno = EPROGMISMATCH;
2657 return (pmc_syscall = -1);
2658 }
2659
2660 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0)
2661 return (pmc_syscall = -1);
2662
2663 cpu_info.pm_cputype = op_cpu_info.pm_cputype;
2664 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu;
2665 cpu_info.pm_npmc = op_cpu_info.pm_npmc;
2666 cpu_info.pm_nclass = op_cpu_info.pm_nclass;
2667 for (n = 0; n < cpu_info.pm_nclass; n++)
2668 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n];
2669
2670 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
2671 sizeof(struct pmc_class_descr *));
2672
2673 if (pmc_class_table == NULL)
2674 return (-1);
2675
2676 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
2677 pmc_class_table[n] = NULL;
2678
2679 /*
2680 * Fill in the class table.
2681 */
2682 n = 0;
2683#if defined(__amd64__) || defined(__i386__)
2684 pmc_class_table[n++] = &tsc_class_table_descr;
2685
2686 /*
2687 * Check if this CPU has fixed function counters.
2688 */
2689 cpu_has_iaf_counters = 0;
2690 for (t = 0; t < cpu_info.pm_nclass; t++)
2691 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF)
2692 cpu_has_iaf_counters = 1;
2693#endif
2694
2695#define PMC_MDEP_INIT(C) do { \
2696 pmc_mdep_event_aliases = C##_aliases; \
2697 pmc_mdep_class_list = C##_pmc_classes; \
2698 pmc_mdep_class_list_size = \
2699 PMC_TABLE_SIZE(C##_pmc_classes); \
2700 } while (0)
2701
2702#define PMC_MDEP_INIT_INTEL_V2(C) do { \
2703 PMC_MDEP_INIT(C); \
2704 if (cpu_has_iaf_counters) \
2705 pmc_class_table[n++] = &iaf_class_table_descr; \
2706 else \
2707 pmc_mdep_event_aliases = \
2708 C##_aliases_without_iaf; \
2709 pmc_class_table[n] = &C##_class_table_descr; \
2710 } while (0)
2711
2712 /* Configure the event name parser. */
2713 switch (cpu_info.pm_cputype) {
2714#if defined(__i386__)
2715 case PMC_CPU_AMD_K7:
2716 PMC_MDEP_INIT(k7);
2717 pmc_class_table[n] = &k7_class_table_descr;
2718 break;
2719 case PMC_CPU_INTEL_P5:
2720 PMC_MDEP_INIT(p5);
2721 pmc_class_table[n] = &p5_class_table_descr;
2722 break;
2723 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */
2724 case PMC_CPU_INTEL_PII: /* similar PMCs. */
2725 case PMC_CPU_INTEL_PIII:
2726 case PMC_CPU_INTEL_PM:
2727 PMC_MDEP_INIT(p6);
2728 pmc_class_table[n] = &p6_class_table_descr;
2729 break;
2730#endif
2731#if defined(__amd64__) || defined(__i386__)
2732 case PMC_CPU_AMD_K8:
2733 PMC_MDEP_INIT(k8);
2734 pmc_class_table[n] = &k8_class_table_descr;
2735 break;
2736 case PMC_CPU_INTEL_ATOM:
2737 PMC_MDEP_INIT_INTEL_V2(atom);
2738 break;
2739 case PMC_CPU_INTEL_CORE:
2740 PMC_MDEP_INIT(core);
2741 pmc_class_table[n] = &core_class_table_descr;
2742 break;
2743 case PMC_CPU_INTEL_CORE2:
2744 case PMC_CPU_INTEL_CORE2EXTREME:
2745 PMC_MDEP_INIT_INTEL_V2(core2);
2746 break;
2747 case PMC_CPU_INTEL_COREI7:
2748 pmc_class_table[n++] = &ucf_class_table_descr;
2749 pmc_class_table[n++] = &corei7uc_class_table_descr;
2750 PMC_MDEP_INIT_INTEL_V2(corei7);
2751 break;
2752 case PMC_CPU_INTEL_WESTMERE:
2753 pmc_class_table[n++] = &ucf_class_table_descr;
2754 pmc_class_table[n++] = &westmereuc_class_table_descr;
2755 PMC_MDEP_INIT_INTEL_V2(westmere);
2756 break;
2757 case PMC_CPU_INTEL_PIV:
2758 PMC_MDEP_INIT(p4);
2759 pmc_class_table[n] = &p4_class_table_descr;
2760 break;
2761#endif
2762#if defined(__XSCALE__)
2763 case PMC_CPU_INTEL_XSCALE:
2764 PMC_MDEP_INIT(xscale);
2765 pmc_class_table[n] = &xscale_class_table_descr;
2766 break;
2767#endif
2768#if defined(__mips__)
2769 case PMC_CPU_MIPS_24K:
2770 PMC_MDEP_INIT(mips24k);
2771 pmc_class_table[n] = &mips24k_class_table_descr;
2772 break;
2773#endif /* __mips__ */
2774 default:
2775 /*
2776 * Some kind of CPU this version of the library knows nothing
2777 * about. This shouldn't happen since the abi version check
2778 * should have caught this.
2779 */
2780 errno = ENXIO;
2781 return (pmc_syscall = -1);
2782 }
2783
2784 return (0);
1817 return 0;
2785}
2786
1818}
1819
2787const char *
2788pmc_name_of_capability(enum pmc_caps cap)
1820int
1821pmc_write(pmc_id_t pmc, pmc_value_t value)
2789{
1822{
2790 int i;
1823 struct pmc_op_pmcrw pmc_write_op;
2791
1824
2792 /*
2793 * 'cap' should have a single bit set and should be in
2794 * range.
2795 */
2796 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
2797 cap > PMC_CAP_LAST) {
2798 errno = EINVAL;
2799 return (NULL);
2800 }
1825 pmc_write_op.pm_pmcid = pmc;
1826 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
1827 pmc_write_op.pm_value = value;
2801
1828
2802 i = ffs(cap);
2803 return (pmc_capability_names[i - 1]);
1829 return PMC_CALL(PMCRW, &pmc_write_op);
2804}
2805
1830}
1831
2806const char *
2807pmc_name_of_class(enum pmc_class pc)
1832int
1833pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
2808{
1834{
2809 if ((int) pc >= PMC_CLASS_FIRST &&
2810 pc <= PMC_CLASS_LAST)
2811 return (pmc_class_names[pc]);
1835 struct pmc_op_pmcrw pmc_rw_op;
2812
1836
2813 errno = EINVAL;
2814 return (NULL);
2815}
1837 pmc_rw_op.pm_pmcid = pmc;
1838 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
1839 pmc_rw_op.pm_value = newvalue;
2816
1840
2817const char *
2818pmc_name_of_cputype(enum pmc_cputype cp)
2819{
2820 size_t n;
1841 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
1842 return -1;
2821
1843
2822 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
2823 if (cp == pmc_cputype_names[n].pm_cputype)
2824 return (pmc_cputype_names[n].pm_name);
1844 *oldvaluep = pmc_rw_op.pm_value;
2825
1845
2826 errno = EINVAL;
2827 return (NULL);
1846 return 0;
2828}
2829
1847}
1848
2830const char *
2831pmc_name_of_disposition(enum pmc_disp pd)
1849int
1850pmc_set(pmc_id_t pmc, pmc_value_t value)
2832{
1851{
2833 if ((int) pd >= PMC_DISP_FIRST &&
2834 pd <= PMC_DISP_LAST)
2835 return (pmc_disposition_names[pd]);
1852 struct pmc_op_pmcsetcount sc;
2836
1853
2837 errno = EINVAL;
2838 return (NULL);
2839}
1854 sc.pm_pmcid = pmc;
1855 sc.pm_count = value;
2840
1856
2841const char *
2842_pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
2843{
2844 const struct pmc_event_descr *ev, *evfence;
1857 if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
1858 return -1;
2845
1859
2846 ev = evfence = NULL;
2847 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) {
2848 ev = iaf_event_table;
2849 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf);
2850 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) {
2851 switch (cpu) {
2852 case PMC_CPU_INTEL_ATOM:
2853 ev = atom_event_table;
2854 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
2855 break;
2856 case PMC_CPU_INTEL_CORE:
2857 ev = core_event_table;
2858 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
2859 break;
2860 case PMC_CPU_INTEL_CORE2:
2861 case PMC_CPU_INTEL_CORE2EXTREME:
2862 ev = core2_event_table;
2863 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
2864 break;
2865 case PMC_CPU_INTEL_COREI7:
2866 ev = corei7_event_table;
2867 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
2868 break;
2869 case PMC_CPU_INTEL_WESTMERE:
2870 ev = westmere_event_table;
2871 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
2872 break;
2873 default: /* Unknown CPU type. */
2874 break;
2875 }
2876 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
2877 ev = ucf_event_table;
2878 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
2879 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
2880 switch (cpu) {
2881 case PMC_CPU_INTEL_COREI7:
2882 ev = corei7uc_event_table;
2883 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
2884 break;
2885 case PMC_CPU_INTEL_WESTMERE:
2886 ev = westmereuc_event_table;
2887 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
2888 break;
2889 default: /* Unknown CPU type. */
2890 break;
2891 }
2892 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
2893 ev = k7_event_table;
2894 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
2895 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
2896 ev = k8_event_table;
2897 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
2898 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
2899 ev = p4_event_table;
2900 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
2901 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
2902 ev = p5_event_table;
2903 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
2904 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
2905 ev = p6_event_table;
2906 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6);
2907 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) {
2908 ev = xscale_event_table;
2909 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale);
2910 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
2911 ev = mips24k_event_table;
2912 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k
2913);
2914 } else if (pe == PMC_EV_TSC_TSC) {
2915 ev = tsc_event_table;
2916 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
2917 }
1860 return 0;
2918
1861
2919 for (; ev != evfence; ev++)
2920 if (pe == ev->pm_ev_code)
2921 return (ev->pm_ev_name);
2922
2923 return (NULL);
2924}
2925
1862}
1863
2926const char *
2927pmc_name_of_event(enum pmc_event pe)
1864int
1865pmc_configure_logfile(int fd)
2928{
1866{
2929 const char *n;
1867 struct pmc_op_configurelog cla;
2930
1868
2931 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
2932 return (n);
1869 cla.pm_logfd = fd;
1870 if (PMC_CALL(CONFIGURELOG, &cla) < 0)
1871 return -1;
2933
1872
2934 errno = EINVAL;
2935 return (NULL);
1873 return 0;
2936}
2937
1874}
1875
2938const char *
2939pmc_name_of_mode(enum pmc_mode pm)
1876int
1877pmc_get_driver_stats(struct pmc_op_getdriverstats *gms)
2940{
1878{
2941 if ((int) pm >= PMC_MODE_FIRST &&
2942 pm <= PMC_MODE_LAST)
2943 return (pmc_mode_names[pm]);
2944
2945 errno = EINVAL;
2946 return (NULL);
1879 return PMC_CALL(GETDRIVERSTATS, gms);
2947}
2948
1880}
1881
2949const char *
2950pmc_name_of_state(enum pmc_state ps)
2951{
2952 if ((int) ps >= PMC_STATE_FIRST &&
2953 ps <= PMC_STATE_LAST)
2954 return (pmc_state_names[ps]);
2955
2956 errno = EINVAL;
2957 return (NULL);
2958}
2959
2960int
2961pmc_ncpu(void)
2962{
2963 if (pmc_syscall == -1) {
2964 errno = ENXIO;
1882int
1883pmc_ncpu(void)
1884{
1885 if (pmc_syscall == -1) {
1886 errno = ENXIO;
2965 return (-1);
1887 return -1;
2966 }
2967
1888 }
1889
2968 return (cpu_info.pm_ncpu);
1890 return cpu_info.pm_ncpu;
2969}
2970
2971int
2972pmc_npmc(int cpu)
2973{
2974 if (pmc_syscall == -1) {
2975 errno = ENXIO;
1891}
1892
1893int
1894pmc_npmc(int cpu)
1895{
1896 if (pmc_syscall == -1) {
1897 errno = ENXIO;
2976 return (-1);
1898 return -1;
2977 }
2978
2979 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
2980 errno = EINVAL;
1899 }
1900
1901 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
1902 errno = EINVAL;
2981 return (-1);
1903 return -1;
2982 }
2983
1904 }
1905
2984 return (cpu_info.pm_npmc);
1906 return cpu_info.pm_npmc;
2985}
2986
2987int
1907}
1908
1909int
2988pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
1910pmc_enable(int cpu, int pmc)
2989{
1911{
2990 int nbytes, npmc;
1912 struct pmc_op_pmcadmin ssa;
1913
1914 ssa.pm_cpu = cpu;
1915 ssa.pm_pmc = pmc;
1916 ssa.pm_state = PMC_STATE_FREE;
1917 return PMC_CALL(PMCADMIN, &ssa);
1918}
1919
1920int
1921pmc_disable(int cpu, int pmc)
1922{
1923 struct pmc_op_pmcadmin ssa;
1924
1925 ssa.pm_cpu = cpu;
1926 ssa.pm_pmc = pmc;
1927 ssa.pm_state = PMC_STATE_DISABLED;
1928 return PMC_CALL(PMCADMIN, &ssa);
1929}
1930
1931
1932int
1933pmc_pmcinfo(int cpu, struct pmc_op_getpmcinfo **ppmci)
1934{
1935 int nbytes, npmc, saved_errno;
2991 struct pmc_op_getpmcinfo *pmci;
2992
2993 if ((npmc = pmc_npmc(cpu)) < 0)
1936 struct pmc_op_getpmcinfo *pmci;
1937
1938 if ((npmc = pmc_npmc(cpu)) < 0)
2994 return (-1);
1939 return -1;
2995
2996 nbytes = sizeof(struct pmc_op_getpmcinfo) +
2997 npmc * sizeof(struct pmc_info);
2998
2999 if ((pmci = calloc(1, nbytes)) == NULL)
1940
1941 nbytes = sizeof(struct pmc_op_getpmcinfo) +
1942 npmc * sizeof(struct pmc_info);
1943
1944 if ((pmci = calloc(1, nbytes)) == NULL)
3000 return (-1);
1945 return -1;
3001
3002 pmci->pm_cpu = cpu;
3003
3004 if (PMC_CALL(GETPMCINFO, pmci) < 0) {
1946
1947 pmci->pm_cpu = cpu;
1948
1949 if (PMC_CALL(GETPMCINFO, pmci) < 0) {
1950 saved_errno = errno;
3005 free(pmci);
1951 free(pmci);
3006 return (-1);
1952 errno = saved_errno;
1953 return -1;
3007 }
3008
1954 }
1955
3009 /* kernel<->library, library<->userland interfaces are identical */
3010 *ppmci = (struct pmc_pmcinfo *) pmci;
3011 return (0);
1956 *ppmci = pmci;
1957 return 0;
3012}
3013
3014int
1958}
1959
1960int
3015pmc_read(pmc_id_t pmc, pmc_value_t *value)
1961pmc_cpuinfo(const struct pmc_op_getcpuinfo **pci)
3016{
1962{
3017 struct pmc_op_pmcrw pmc_read_op;
1963 if (pmc_syscall == -1) {
1964 errno = ENXIO;
1965 return -1;
1966 }
3018
1967
3019 pmc_read_op.pm_pmcid = pmc;
3020 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
3021 pmc_read_op.pm_value = -1;
1968 *pci = &cpu_info;
1969 return 0;
1970}
3022
1971
3023 if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
3024 return (-1);
3025
3026 *value = pmc_read_op.pm_value;
3027 return (0);
1972const char *
1973pmc_name_of_cputype(enum pmc_cputype cp)
1974{
1975 if ((int) cp >= PMC_CPU_FIRST &&
1976 cp <= PMC_CPU_LAST)
1977 return pmc_cputype_names[cp];
1978 errno = EINVAL;
1979 return NULL;
3028}
3029
1980}
1981
3030int
3031pmc_release(pmc_id_t pmc)
1982const char *
1983pmc_name_of_class(enum pmc_class pc)
3032{
1984{
3033 struct pmc_op_simple pmc_release_args;
1985 if ((int) pc >= PMC_CLASS_FIRST &&
1986 pc <= PMC_CLASS_LAST)
1987 return pmc_class_names[pc];
3034
1988
3035 pmc_release_args.pm_pmcid = pmc;
3036 return (PMC_CALL(PMCRELEASE, &pmc_release_args));
1989 errno = EINVAL;
1990 return NULL;
3037}
3038
1991}
1992
3039int
3040pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
1993const char *
1994pmc_name_of_mode(enum pmc_mode pm)
3041{
1995{
3042 struct pmc_op_pmcrw pmc_rw_op;
1996 if ((int) pm >= PMC_MODE_FIRST &&
1997 pm <= PMC_MODE_LAST)
1998 return pmc_mode_names[pm];
3043
1999
3044 pmc_rw_op.pm_pmcid = pmc;
3045 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
3046 pmc_rw_op.pm_value = newvalue;
3047
3048 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
3049 return (-1);
3050
3051 *oldvaluep = pmc_rw_op.pm_value;
3052 return (0);
2000 errno = EINVAL;
2001 return NULL;
3053}
3054
2002}
2003
3055int
3056pmc_set(pmc_id_t pmc, pmc_value_t value)
2004const char *
2005pmc_name_of_event(enum pmc_event pe)
3057{
2006{
3058 struct pmc_op_pmcsetcount sc;
2007 if ((int) pe >= PMC_EVENT_FIRST &&
2008 pe <= PMC_EVENT_LAST)
2009 return pmc_event_table[pe].pm_ev_name;
3059
2010
3060 sc.pm_pmcid = pmc;
3061 sc.pm_count = value;
3062
3063 if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
3064 return (-1);
3065 return (0);
2011 errno = EINVAL;
2012 return NULL;
3066}
3067
2013}
2014
3068int
3069pmc_start(pmc_id_t pmc)
2015const char *
2016pmc_name_of_state(enum pmc_state ps)
3070{
2017{
3071 struct pmc_op_simple pmc_start_args;
2018 if ((int) ps >= PMC_STATE_FIRST &&
2019 ps <= PMC_STATE_LAST)
2020 return pmc_state_names[ps];
3072
2021
3073 pmc_start_args.pm_pmcid = pmc;
3074 return (PMC_CALL(PMCSTART, &pmc_start_args));
2022 errno = EINVAL;
2023 return NULL;
3075}
3076
2024}
2025
3077int
3078pmc_stop(pmc_id_t pmc)
2026const char *
2027pmc_name_of_disposition(enum pmc_disp pd)
3079{
2028{
3080 struct pmc_op_simple pmc_stop_args;
2029 if ((int) pd >= PMC_DISP_FIRST &&
2030 pd <= PMC_DISP_LAST)
2031 return pmc_disposition_names[pd];
3081
2032
3082 pmc_stop_args.pm_pmcid = pmc;
3083 return (PMC_CALL(PMCSTOP, &pmc_stop_args));
2033 errno = EINVAL;
2034 return NULL;
3084}
3085
2035}
2036
3086int
3087pmc_width(pmc_id_t pmcid, uint32_t *width)
2037const char *
2038pmc_name_of_capability(enum pmc_caps cap)
3088{
2039{
3089 unsigned int i;
3090 enum pmc_class cl;
2040 int i;
3091
2041
3092 cl = PMC_ID_TO_CLASS(pmcid);
3093 for (i = 0; i < cpu_info.pm_nclass; i++)
3094 if (cpu_info.pm_classes[i].pm_class == cl) {
3095 *width = cpu_info.pm_classes[i].pm_width;
3096 return (0);
3097 }
3098 errno = EINVAL;
3099 return (-1);
2042 /*
2043 * 'cap' should have a single bit set and should be in
2044 * range.
2045 */
2046
2047 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
2048 cap > PMC_CAP_LAST) {
2049 errno = EINVAL;
2050 return NULL;
2051 }
2052
2053 i = ffs(cap);
2054
2055 return pmc_capability_names[i - 1];
3100}
3101
2056}
2057
2058/*
2059 * Return a list of events known to a given PMC class. 'cl' is the
2060 * PMC class identifier, 'eventnames' is the returned list of 'const
2061 * char *' pointers pointing to the names of the events. 'nevents' is
2062 * the number of event name pointers returned.
2063 *
2064 * The space for 'eventnames' is allocated using malloc(3). The caller
2065 * is responsible for freeing this space when done.
2066 */
2067
3102int
2068int
3103pmc_write(pmc_id_t pmc, pmc_value_t value)
2069pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2070 int *nevents)
3104{
2071{
3105 struct pmc_op_pmcrw pmc_write_op;
2072 int count;
2073 const char **names;
2074 const struct pmc_event_descr *ev;
3106
2075
3107 pmc_write_op.pm_pmcid = pmc;
3108 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
3109 pmc_write_op.pm_value = value;
3110 return (PMC_CALL(PMCRW, &pmc_write_op));
2076 switch (cl)
2077 {
2078 case PMC_CLASS_TSC:
2079 ev = &pmc_event_table[PMC_EV_TSC_TSC];
2080 count = 1;
2081 break;
2082 case PMC_CLASS_K7:
2083 ev = &pmc_event_table[PMC_EV_K7_FIRST];
2084 count = PMC_EV_K7_LAST - PMC_EV_K7_FIRST + 1;
2085 break;
2086 case PMC_CLASS_K8:
2087 ev = &pmc_event_table[PMC_EV_K8_FIRST];
2088 count = PMC_EV_K8_LAST - PMC_EV_K8_FIRST + 1;
2089 break;
2090 case PMC_CLASS_P5:
2091 ev = &pmc_event_table[PMC_EV_P5_FIRST];
2092 count = PMC_EV_P5_LAST - PMC_EV_P5_FIRST + 1;
2093 break;
2094 case PMC_CLASS_P6:
2095 ev = &pmc_event_table[PMC_EV_P6_FIRST];
2096 count = PMC_EV_P6_LAST - PMC_EV_P6_FIRST + 1;
2097 break;
2098 case PMC_CLASS_P4:
2099 ev = &pmc_event_table[PMC_EV_P4_FIRST];
2100 count = PMC_EV_P4_LAST - PMC_EV_P4_FIRST + 1;
2101 break;
2102 default:
2103 errno = EINVAL;
2104 return -1;
2105 }
2106
2107 if ((names = malloc(count * sizeof(const char *))) == NULL)
2108 return -1;
2109
2110 *eventnames = names;
2111 *nevents = count;
2112
2113 for (;count--; ev++, names++)
2114 *names = ev->pm_ev_name;
2115 return 0;
3111}
3112
2116}
2117
2118/*
2119 * Architecture specific APIs
2120 */
2121
2122#if __i386__ || __amd64__
2123
3113int
2124int
3114pmc_writelog(uint32_t userdata)
2125pmc_x86_get_msr(pmc_id_t pmc, uint32_t *msr)
3115{
2126{
3116 struct pmc_op_writelog wl;
2127 struct pmc_op_x86_getmsr gm;
3117
2128
3118 wl.pm_userdata = userdata;
3119 return (PMC_CALL(WRITELOG, &wl));
2129 gm.pm_pmcid = pmc;
2130 if (PMC_CALL(PMCX86GETMSR, &gm) < 0)
2131 return -1;
2132 *msr = gm.pm_msr;
2133 return 0;
3120}
2134}
2135
2136#endif