xref: /titanic_53/usr/src/uts/common/sys/cpudrv.h (revision 5cff782560a1c3cf913ba5574a5123a299f3315e)
1*5cff7825Smh27603 /*
2*5cff7825Smh27603  * CDDL HEADER START
3*5cff7825Smh27603  *
4*5cff7825Smh27603  * The contents of this file are subject to the terms of the
5*5cff7825Smh27603  * Common Development and Distribution License (the "License").
6*5cff7825Smh27603  * You may not use this file except in compliance with the License.
7*5cff7825Smh27603  *
8*5cff7825Smh27603  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*5cff7825Smh27603  * or http://www.opensolaris.org/os/licensing.
10*5cff7825Smh27603  * See the License for the specific language governing permissions
11*5cff7825Smh27603  * and limitations under the License.
12*5cff7825Smh27603  *
13*5cff7825Smh27603  * When distributing Covered Code, include this CDDL HEADER in each
14*5cff7825Smh27603  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*5cff7825Smh27603  * If applicable, add the following below this CDDL HEADER, with the
16*5cff7825Smh27603  * fields enclosed by brackets "[]" replaced with your own identifying
17*5cff7825Smh27603  * information: Portions Copyright [yyyy] [name of copyright owner]
18*5cff7825Smh27603  *
19*5cff7825Smh27603  * CDDL HEADER END
20*5cff7825Smh27603  */
21*5cff7825Smh27603 /*
22*5cff7825Smh27603  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23*5cff7825Smh27603  * Use is subject to license terms.
24*5cff7825Smh27603  */
25*5cff7825Smh27603 
26*5cff7825Smh27603 #ifndef _SYS_CPUDRV_H
27*5cff7825Smh27603 #define	_SYS_CPUDRV_H
28*5cff7825Smh27603 
29*5cff7825Smh27603 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30*5cff7825Smh27603 
31*5cff7825Smh27603 #include <sys/promif.h>
32*5cff7825Smh27603 #include <sys/cpuvar.h>
33*5cff7825Smh27603 #include <sys/taskq.h>
34*5cff7825Smh27603 
35*5cff7825Smh27603 #ifdef	__cplusplus
36*5cff7825Smh27603 extern "C" {
37*5cff7825Smh27603 #endif
38*5cff7825Smh27603 
39*5cff7825Smh27603 #ifdef _KERNEL
40*5cff7825Smh27603 
41*5cff7825Smh27603 /*
42*5cff7825Smh27603  * CPU power management data
43*5cff7825Smh27603  */
44*5cff7825Smh27603 /*
45*5cff7825Smh27603  * Data related to a particular speed.
46*5cff7825Smh27603  *
47*5cff7825Smh27603  * All per speed data nodes for a CPU are linked together using down_spd.
48*5cff7825Smh27603  * The link list is ordered with first node containing data for
49*5cff7825Smh27603  * normal (maximum) speed. up_spd points to the next speed up. Currently
50*5cff7825Smh27603  * all up_spd's point to the normal speed but this can be changed in future.
51*5cff7825Smh27603  * quant_cnt is the number of ticks when monitoring system will be called
52*5cff7825Smh27603  * next. There are different quant_cnt for different speeds.
53*5cff7825Smh27603  *
54*5cff7825Smh27603  * Note that 'speed' has different meaning depending upon the platform.
55*5cff7825Smh27603  * On SPARC, the speed is really a divisor of the maximum speed (e.g., a speed
56*5cff7825Smh27603  * of 2 means that it's 1/2 the maximum speed). On x86, speed is a processor
57*5cff7825Smh27603  * frequency.
58*5cff7825Smh27603  */
59*5cff7825Smh27603 typedef struct cpudrv_pm_spd {
60*5cff7825Smh27603 	uint_t			speed;		/* platform dependent notion */
61*5cff7825Smh27603 	uint_t			quant_cnt;	/* quantum count in ticks */
62*5cff7825Smh27603 	struct cpudrv_pm_spd	*down_spd;	/* ptr to next speed down */
63*5cff7825Smh27603 	struct cpudrv_pm_spd	*up_spd;	/* ptr to next speed up */
64*5cff7825Smh27603 	uint_t			idle_hwm;	/* down if idle thread >= hwm */
65*5cff7825Smh27603 	uint_t			idle_lwm;	/* up if idle thread < lwm */
66*5cff7825Smh27603 	uint_t			idle_bhwm_cnt;	/* # of iters idle is < hwm */
67*5cff7825Smh27603 	uint_t			idle_blwm_cnt;	/* # of iters idle is < lwm */
68*5cff7825Smh27603 	uint_t			user_hwm;	/* up if user thread > hwm */
69*5cff7825Smh27603 	int			user_lwm;	/* down if user thread <= lwm */
70*5cff7825Smh27603 	int			pm_level;	/* power level for framework */
71*5cff7825Smh27603 } cpudrv_pm_spd_t;
72*5cff7825Smh27603 
73*5cff7825Smh27603 /*
74*5cff7825Smh27603  * Power management data
75*5cff7825Smh27603  */
76*5cff7825Smh27603 typedef struct cpudrv_pm {
77*5cff7825Smh27603 	cpudrv_pm_spd_t	*head_spd;	/* ptr to head of speed */
78*5cff7825Smh27603 	cpudrv_pm_spd_t	*cur_spd;	/* ptr to current speed */
79*5cff7825Smh27603 	cpudrv_pm_spd_t	*targ_spd;	/* target speed when cur_spd */
80*5cff7825Smh27603 					/* is unknown (i.e. NULL) */
81*5cff7825Smh27603 	uint_t		num_spd;	/* number of speeds */
82*5cff7825Smh27603 	hrtime_t	lastquan_mstate[NCMSTATES]; /* last quantum's mstate */
83*5cff7825Smh27603 	clock_t		lastquan_lbolt;	/* last quantum's lbolt */
84*5cff7825Smh27603 	int		pm_busycnt;	/* pm_busy_component() count  */
85*5cff7825Smh27603 	taskq_t		*tq;		/* taskq handler for CPU monitor */
86*5cff7825Smh27603 	timeout_id_t	timeout_id;	/* cpudrv_pm_monitor()'s timeout_id */
87*5cff7825Smh27603 	int		timeout_count;	/* count dispatched timeouts */
88*5cff7825Smh27603 	kmutex_t	timeout_lock;	/* protect timeout_count */
89*5cff7825Smh27603 	kcondvar_t	timeout_cv;	/* wait on timeout_count change */
90*5cff7825Smh27603 #if defined(__x86)
91*5cff7825Smh27603 	kthread_t	*pm_throttle_thread; /* throttling thread */
92*5cff7825Smh27603 #endif
93*5cff7825Smh27603 } cpudrv_pm_t;
94*5cff7825Smh27603 
95*5cff7825Smh27603 /*
96*5cff7825Smh27603  * Idle & user threads water marks in percentage
97*5cff7825Smh27603  */
98*5cff7825Smh27603 #if defined(__x86)
99*5cff7825Smh27603 #define	CPUDRV_PM_IDLE_LWM		80	/* idle low water mark */
100*5cff7825Smh27603 #else
101*5cff7825Smh27603 #define	CPUDRV_PM_IDLE_LWM		8	/* idle low water mark */
102*5cff7825Smh27603 #endif
103*5cff7825Smh27603 #define	CPUDRV_PM_IDLE_HWM		98	/* idle high water mark */
104*5cff7825Smh27603 #define	CPUDRV_PM_USER_HWM		20	/* user high water mark */
105*5cff7825Smh27603 #define	CPUDRV_PM_IDLE_BUF_ZONE		4    /* buffer zone when going down */
106*5cff7825Smh27603 
107*5cff7825Smh27603 #define	CPUDRV_PM_IDLE_BLWM_CNT_MAX	2    /* # of iters idle can be < lwm */
108*5cff7825Smh27603 #define	CPUDRV_PM_IDLE_BHWM_CNT_MAX	2    /* # of iters idle can be < hwm */
109*5cff7825Smh27603 
110*5cff7825Smh27603 /*
111*5cff7825Smh27603  * Maximums for creating 'pm-components' property
112*5cff7825Smh27603  */
113*5cff7825Smh27603 #define	CPUDRV_PM_COMP_MAX_DIG	4	/* max digits in power level */
114*5cff7825Smh27603 					/* or divisor */
115*5cff7825Smh27603 #define	CPUDRV_PM_COMP_MAX_VAL	9999	/* max value in above digits */
116*5cff7825Smh27603 
117*5cff7825Smh27603 /*
118*5cff7825Smh27603  * Component number for calls to PM framework
119*5cff7825Smh27603  */
120*5cff7825Smh27603 #define	CPUDRV_PM_COMP_NUM	0	/* first component is 0 */
121*5cff7825Smh27603 
122*5cff7825Smh27603 /*
123*5cff7825Smh27603  * Quantum counts for normal and other clock speeds in terms of ticks.
124*5cff7825Smh27603  *
125*5cff7825Smh27603  * In determining the quantum count, we need to balance two opposing factors:
126*5cff7825Smh27603  *
127*5cff7825Smh27603  *	1) Minimal delay when user start using the CPU that is in low
128*5cff7825Smh27603  *	power mode -- requires that we monitor more frequently,
129*5cff7825Smh27603  *
130*5cff7825Smh27603  *	2) Extra code executed because of frequent monitoring -- requires
131*5cff7825Smh27603  *	that we monitor less frequently.
132*5cff7825Smh27603  *
133*5cff7825Smh27603  * We reach a tradeoff between these two requirements by monitoring
134*5cff7825Smh27603  * more frequently when we are in low speed mode (CPUDRV_PM_QUANT_CNT_OTHR)
135*5cff7825Smh27603  * so we can bring the CPU up without user noticing it. Moreover, at low
136*5cff7825Smh27603  * speed we are not using CPU much so extra code execution should be fine.
137*5cff7825Smh27603  * Since we are in no hurry to bring CPU down and at normal speed and we
138*5cff7825Smh27603  * might really be using the CPU fully, we monitor less frequently
139*5cff7825Smh27603  * (CPUDRV_PM_QUANT_CNT_NORMAL).
140*5cff7825Smh27603  */
141*5cff7825Smh27603 #define	CPUDRV_PM_QUANT_CNT_NORMAL	(hz * 5)	/* 5 sec */
142*5cff7825Smh27603 #define	CPUDRV_PM_QUANT_CNT_OTHR	(hz * 1)	/* 1 sec */
143*5cff7825Smh27603 
144*5cff7825Smh27603 /*
145*5cff7825Smh27603  * Taskq parameters
146*5cff7825Smh27603  */
147*5cff7825Smh27603 #define	CPUDRV_PM_TASKQ_THREADS		1    /* # threads to run CPU monitor */
148*5cff7825Smh27603 #define	CPUDRV_PM_TASKQ_MIN		2	/* min # of taskq entries */
149*5cff7825Smh27603 #define	CPUDRV_PM_TASKQ_MAX		2	/* max # of taskq entries */
150*5cff7825Smh27603 
151*5cff7825Smh27603 
152*5cff7825Smh27603 /*
153*5cff7825Smh27603  * Device driver state structure
154*5cff7825Smh27603  */
155*5cff7825Smh27603 typedef struct cpudrv_devstate {
156*5cff7825Smh27603 	dev_info_t	*dip;		/* devinfo handle */
157*5cff7825Smh27603 	processorid_t	cpu_id;		/* CPU number for this node */
158*5cff7825Smh27603 	cpudrv_pm_t	cpudrv_pm;	/* power management data */
159*5cff7825Smh27603 	kmutex_t	lock;		/* protects state struct */
160*5cff7825Smh27603 #if defined(__x86)
161*5cff7825Smh27603 	void		*acpi_handle;	/* ACPI cache */
162*5cff7825Smh27603 	void		*module_state;  /* CPU module state */
163*5cff7825Smh27603 #endif
164*5cff7825Smh27603 } cpudrv_devstate_t;
165*5cff7825Smh27603 
166*5cff7825Smh27603 extern void	*cpudrv_state;
167*5cff7825Smh27603 
168*5cff7825Smh27603 /*
169*5cff7825Smh27603  * Debugging definitions
170*5cff7825Smh27603  */
171*5cff7825Smh27603 #ifdef	DEBUG
172*5cff7825Smh27603 #define	D_INIT			0x00000001
173*5cff7825Smh27603 #define	D_FINI			0x00000002
174*5cff7825Smh27603 #define	D_ATTACH		0x00000004
175*5cff7825Smh27603 #define	D_DETACH		0x00000008
176*5cff7825Smh27603 #define	D_POWER			0x00000010
177*5cff7825Smh27603 #define	D_PM_INIT		0x00000020
178*5cff7825Smh27603 #define	D_PM_FREE		0x00000040
179*5cff7825Smh27603 #define	D_PM_COMP_CREATE	0x00000080
180*5cff7825Smh27603 #define	D_PM_MONITOR		0x00000100
181*5cff7825Smh27603 #define	D_PM_MONITOR_VERBOSE	0x00000200
182*5cff7825Smh27603 #define	D_PM_MONITOR_DELAY	0x00000400
183*5cff7825Smh27603 
184*5cff7825Smh27603 extern uint_t	cpudrv_debug;
185*5cff7825Smh27603 
186*5cff7825Smh27603 #define	_PRINTF prom_printf
187*5cff7825Smh27603 #define	DPRINTF(flag, args)	if (cpudrv_debug & flag) _PRINTF args;
188*5cff7825Smh27603 #else
189*5cff7825Smh27603 #define	DPRINTF(flag, args)
190*5cff7825Smh27603 #endif /* DEBUG */
191*5cff7825Smh27603 
192*5cff7825Smh27603 extern int cpudrv_pm_change_speed(cpudrv_devstate_t *, cpudrv_pm_spd_t *);
193*5cff7825Smh27603 extern boolean_t cpudrv_pm_get_cpu_id(dev_info_t *, processorid_t *);
194*5cff7825Smh27603 extern boolean_t cpudrv_pm_all_instances_ready(void);
195*5cff7825Smh27603 extern boolean_t cpudrv_pm_is_throttle_thread(cpudrv_pm_t *);
196*5cff7825Smh27603 extern boolean_t cpudrv_pm_init_module(cpudrv_devstate_t *);
197*5cff7825Smh27603 extern void cpudrv_pm_free_module(cpudrv_devstate_t *);
198*5cff7825Smh27603 
199*5cff7825Smh27603 #endif /* _KERNEL */
200*5cff7825Smh27603 
201*5cff7825Smh27603 #ifdef	__cplusplus
202*5cff7825Smh27603 }
203*5cff7825Smh27603 #endif
204*5cff7825Smh27603 
205*5cff7825Smh27603 #endif /* _SYS_CPUDRV_H */
206