1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Hypervisor calls 31 */ 32 33#include <sys/asm_linkage.h> 34#include <sys/machasi.h> 35#include <sys/machparam.h> 36#include <sys/hypervisor_api.h> 37#include <io/px/px_ioapi.h> 38 39#if defined(lint) || defined(__lint) 40 41/*ARGSUSED*/ 42int64_t 43hv_cnputchar(uint8_t ch) 44{ return (0); } 45 46/*ARGSUSED*/ 47int64_t 48hv_cngetchar(uint8_t *ch) 49{ return (0); } 50 51/*ARGSUSED*/ 52uint64_t 53hv_tod_get(uint64_t *seconds) 54{ return (0); } 55 56/*ARGSUSED*/ 57uint64_t 58hv_tod_set(uint64_t seconds) 59{ return (0);} 60 61/*ARGSUSED*/ 62uint64_t 63hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 64{ return (0); } 65 66/*ARGSUSED*/ 67uint64_t 68hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 69{ return (0); } 70 71/*ARGSUSED*/ 72uint64_t 73hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 74{ return (0); } 75 76/*ARGSUSED*/ 77uint64_t 78hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 79{ return (0); } 80 81#ifdef SET_MMU_STATS 82/*ARGSUSED*/ 83uint64_t 84hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 85{ return (0); } 86#endif /* SET_MMU_STATS */ 87 88/*ARGSUSED*/ 89uint64_t 90hv_cpu_qconf(int queue, uint64_t paddr, int size) 91{ return (0); } 92 93/*ARGSUSED*/ 94uint64_t 95hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 96 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p) 97{ return (0); } 98 99/*ARGSUSED*/ 100uint64_t 101hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 102 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data) 103{ return (0); } 104 105/*ARGSUSED*/ 106uint64_t 107hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 108{ return (0); } 109 110/*ARGSUSED*/ 111uint64_t 112hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 113{ return (0); } 114 115/*ARGSUSED*/ 116uint64_t 117hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 118{ return (0); } 119 120/*ARGSUSED*/ 121uint64_t 122hvio_intr_getstate(uint64_t sysino, int *intr_state) 123{ return (0); } 124 125/*ARGSUSED*/ 126uint64_t 127hvio_intr_setstate(uint64_t sysino, int intr_state) 128{ return (0); } 129 130/*ARGSUSED*/ 131uint64_t 132hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 133{ return (0); } 134 135/*ARGSUSED*/ 136uint64_t 137hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 138{ return (0); } 139 140/*ARGSUSED*/ 141uint64_t 142hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 143 pages_t pages, io_attributes_t io_attributes, 144 io_page_list_t *io_page_list_p, pages_t *pages_mapped) 145{ return (0); } 146 147/*ARGSUSED*/ 148uint64_t 149hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 150 pages_t pages, pages_t *pages_demapped) 151{ return (0); } 152 153/*ARGSUSED*/ 154uint64_t 155hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 156 io_attributes_t *attributes_p, r_addr_t *r_addr_p) 157{ return (0); } 158 159/*ARGSUSED*/ 160uint64_t 161hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 162 io_attributes_t io_attributes, io_addr_t *io_addr_p) 163{ return (0); } 164 165/*ARGSUSED*/ 166uint64_t 167hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, 168 uint64_t *data_p) 169{ return (0); } 170 171/*ARGSUSED*/ 172uint64_t 173hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, 174 r_addr_t ra2, uint32_t *rdbk_status) 175{ return (0); } 176 177/*ARGSUSED*/ 178uint64_t 179hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, 180 int io_sync_direction, size_t *bytes_synched) 181{ return (0); } 182 183/*ARGSUSED*/ 184uint64_t 185hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, 186 uint_t msiq_rec_cnt) 187{ return (0); } 188 189/*ARGSUSED*/ 190uint64_t 191hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, 192 uint_t *msiq_rec_cnt_p) 193{ return (0); } 194 195/*ARGSUSED*/ 196uint64_t 197hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 198 pci_msiq_valid_state_t *msiq_valid_state) 199{ return (0); } 200 201/*ARGSUSED*/ 202uint64_t 203hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 204 pci_msiq_valid_state_t msiq_valid_state) 205{ return (0); } 206 207/*ARGSUSED*/ 208uint64_t 209hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 210 pci_msiq_state_t *msiq_state) 211{ return (0); } 212 213/*ARGSUSED*/ 214uint64_t 215hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 216 pci_msiq_state_t msiq_state) 217{ return (0); } 218 219/*ARGSUSED*/ 220uint64_t 221hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 222 msiqhead_t *msiq_head) 223{ return (0); } 224 225/*ARGSUSED*/ 226uint64_t 227hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 228 msiqhead_t msiq_head) 229{ return (0); } 230 231/*ARGSUSED*/ 232uint64_t 233hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 234 msiqtail_t *msiq_tail) 235{ return (0); } 236 237/*ARGSUSED*/ 238uint64_t 239hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 240 msiqid_t *msiq_id) 241{ return (0); } 242 243/*ARGSUSED*/ 244uint64_t 245hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 246 msiqid_t msiq_id, msi_type_t msitype) 247{ return (0); } 248 249/*ARGSUSED*/ 250uint64_t 251hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 252 pci_msi_valid_state_t *msi_valid_state) 253{ return (0); } 254 255/*ARGSUSED*/ 256uint64_t 257hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 258 pci_msi_valid_state_t msi_valid_state) 259{ return (0); } 260 261/*ARGSUSED*/ 262uint64_t 263hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 264 pci_msi_state_t *msi_state) 265{ return (0); } 266 267/*ARGSUSED*/ 268uint64_t 269hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 270 pci_msi_state_t msi_state) 271{ return (0); } 272 273/*ARGSUSED*/ 274uint64_t 275hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 276 msiqid_t *msiq_id) 277{ return (0); } 278 279/*ARGSUSED*/ 280uint64_t 281hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 282 msiqid_t msiq_id) 283{ return (0); } 284 285/*ARGSUSED*/ 286uint64_t 287hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 288 pcie_msg_valid_state_t *msg_valid_state) 289{ return (0); } 290 291/*ARGSUSED*/ 292uint64_t 293hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 294 pcie_msg_valid_state_t msg_valid_state) 295{ return (0); } 296 297uint64_t 298hv_cpu_yield(void) 299{ return (0); } 300 301/*ARGSUSED*/ 302uint64_t 303hv_service_recv(uint64_t s_id, uint64_t buf_pa, uint64_t size, 304 uint64_t *recv_bytes) 305{ return (0); } 306 307/*ARGSUSED*/ 308uint64_t 309hv_service_send(uint64_t s_id, uint64_t buf_pa, uint64_t size, 310 uint64_t *send_bytes) 311{ return (0); } 312 313/*ARGSUSED*/ 314uint64_t 315hv_service_getstatus(uint64_t s_id, uint64_t *vreg) 316{ return (0); } 317 318/*ARGSUSED*/ 319uint64_t 320hv_service_clrstatus(uint64_t s_id, uint64_t bits) 321{ return (0); } 322 323/*ARGSUSED*/ 324uint64_t 325hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 326{ return (0); } 327 328/*ARGSUSED*/ 329uint64_t 330hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 331{ return (0); } 332 333/*ARGSUSED*/ 334uint64_t 335hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 336{ return (0); } 337 338/*ARGSUSED*/ 339uint64_t 340hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 341{ return (0); } 342 343/*ARGSUSED*/ 344uint64_t 345hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 346{ return (0); } 347 348/*ARGSUSED*/ 349uint64_t 350hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 351{ return (0); } 352 353/*ARGSUSED*/ 354uint64_t 355hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 356{ return (0); } 357 358/*ARGSUSED*/ 359uint64_t 360hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 361{ return (0); } 362 363/*ARGSUSED*/ 364uint64_t 365hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 366{ return (0); } 367 368/*ARGSUSED*/ 369uint64_t 370hv_ncs_request(int cmd, uint64_t realaddr, size_t sz) 371{ return (0); } 372 373#else /* lint || __lint */ 374 375 /* 376 * %o0 - character 377 */ 378 ENTRY(hv_cnputchar) 379 mov CONS_WRITE, %o5 380 ta FAST_TRAP 381 tst %o0 382 retl 383 movnz %xcc, -1, %o0 384 SET_SIZE(hv_cnputchar) 385 386 /* 387 * %o0 pointer to character buffer 388 * return values: 389 * 0 success 390 * hv_errno failure 391 */ 392 ENTRY(hv_cngetchar) 393 mov %o0, %o2 394 mov CONS_READ, %o5 395 ta FAST_TRAP 396 brnz,a %o0, 1f ! failure, just return error 397 mov 1, %o0 398 399 cmp %o1, H_BREAK 400 be 1f 401 mov %o1, %o0 402 403 cmp %o1, H_HUP 404 be 1f 405 mov %o1, %o0 406 407 stb %o1, [%o2] ! success, save character and return 0 408 mov 0, %o0 4091: 410 retl 411 nop 412 SET_SIZE(hv_cngetchar) 413 414 ENTRY(hv_tod_get) 415 mov %o0, %o4 416 mov TOD_GET, %o5 417 ta FAST_TRAP 418 retl 419 stx %o1, [%o4] 420 SET_SIZE(hv_tod_get) 421 422 ENTRY(hv_tod_set) 423 mov TOD_SET, %o5 424 ta FAST_TRAP 425 retl 426 nop 427 SET_SIZE(hv_tod_set) 428 429 /* 430 * Map permanent address 431 * arg0 vaddr (%o0) 432 * arg1 context (%o1) 433 * arg2 tte (%o2) 434 * arg3 flags (%o3) 0x1=d 0x2=i 435 */ 436 ENTRY(hv_mmu_map_perm_addr) 437 mov MAP_PERM_ADDR, %o5 438 ta FAST_TRAP 439 retl 440 nop 441 SET_SIZE(hv_mmu_map_perm_addr) 442 443 /* 444 * Unmap permanent address 445 * arg0 vaddr (%o0) 446 * arg1 context (%o1) 447 * arg2 flags (%o2) 0x1=d 0x2=i 448 */ 449 ENTRY(hv_mmu_unmap_perm_addr) 450 mov UNMAP_PERM_ADDR, %o5 451 ta FAST_TRAP 452 retl 453 nop 454 SET_SIZE(hv_mmu_unmap_perm_addr) 455 456 /* 457 * Set TSB for context 0 458 * arg0 ntsb_descriptor (%o0) 459 * arg1 desc_ra (%o1) 460 */ 461 ENTRY(hv_set_ctx0) 462 mov MMU_TSB_CTX0, %o5 463 ta FAST_TRAP 464 retl 465 nop 466 SET_SIZE(hv_set_ctx0) 467 468 /* 469 * Set TSB for context non0 470 * arg0 ntsb_descriptor (%o0) 471 * arg1 desc_ra (%o1) 472 */ 473 ENTRY(hv_set_ctxnon0) 474 mov MMU_TSB_CTXNON0, %o5 475 ta FAST_TRAP 476 retl 477 nop 478 SET_SIZE(hv_set_ctxnon0) 479 480#ifdef SET_MMU_STATS 481 /* 482 * Returns old stat area on success 483 */ 484 ENTRY(hv_mmu_set_stat_area) 485 mov MMU_STAT_AREA, %o5 486 ta FAST_TRAP 487 retl 488 nop 489 SET_SIZE(hv_mmu_set_stat_area) 490#endif /* SET_MMU_STATS */ 491 492 /* 493 * CPU Q Configure 494 * arg0 queue (%o0) 495 * arg1 Base address RA (%o1) 496 * arg2 Size (%o2) 497 */ 498 ENTRY(hv_cpu_qconf) 499 mov CPU_QCONF, %o5 500 ta FAST_TRAP 501 retl 502 nop 503 SET_SIZE(hv_cpu_qconf) 504 505 /* 506 * arg0 - devhandle 507 * arg1 - pci_device 508 * arg2 - pci_config_offset 509 * arg3 - pci_config_size 510 * 511 * ret0 - status 512 * ret1 - error_flag 513 * ret2 - pci_cfg_data 514 */ 515 ENTRY(hvio_config_get) 516 mov HVIO_CONFIG_GET, %o5 517 ta FAST_TRAP 518 brnz %o0, 1f 519 movrnz %o1, -1, %o2 520 brz,a %o1, 1f 521 stuw %o2, [%o4] 5221: retl 523 nop 524 SET_SIZE(hvio_config_get) 525 526 /* 527 * arg0 - devhandle 528 * arg1 - pci_device 529 * arg2 - pci_config_offset 530 * arg3 - pci_config_size 531 * arg4 - pci_cfg_data 532 * 533 * ret0 - status 534 * ret1 - error_flag 535 */ 536 ENTRY(hvio_config_put) 537 mov HVIO_CONFIG_PUT, %o5 538 ta FAST_TRAP 539 retl 540 nop 541 SET_SIZE(hvio_config_put) 542 543 /* 544 * arg0 - devhandle 545 * arg1 - devino 546 * 547 * ret0 - status 548 * ret1 - sysino 549 */ 550 ENTRY(hvio_intr_devino_to_sysino) 551 mov HVIO_INTR_DEVINO2SYSINO, %o5 552 ta FAST_TRAP 553 brz,a %o0, 1f 554 stx %o1, [%o2] 5551: retl 556 nop 557 SET_SIZE(hvio_intr_devino_to_sysino) 558 559 /* 560 * arg0 - sysino 561 * 562 * ret0 - status 563 * ret1 - intr_valid_state 564 */ 565 ENTRY(hvio_intr_getvalid) 566 mov %o1, %o2 567 mov HVIO_INTR_GETVALID, %o5 568 ta FAST_TRAP 569 brz,a %o0, 1f 570 stuw %o1, [%o2] 5711: retl 572 nop 573 SET_SIZE(hvio_intr_getvalid) 574 575 /* 576 * arg0 - sysino 577 * arg1 - intr_valid_state 578 * 579 * ret0 - status 580 */ 581 ENTRY(hvio_intr_setvalid) 582 mov HVIO_INTR_SETVALID, %o5 583 ta FAST_TRAP 584 retl 585 nop 586 SET_SIZE(hvio_intr_setvalid) 587 588 /* 589 * arg0 - sysino 590 * 591 * ret0 - status 592 * ret1 - intr_state 593 */ 594 ENTRY(hvio_intr_getstate) 595 mov %o1, %o2 596 mov HVIO_INTR_GETSTATE, %o5 597 ta FAST_TRAP 598 brz,a %o0, 1f 599 stuw %o1, [%o2] 6001: retl 601 nop 602 SET_SIZE(hvio_intr_getstate) 603 604 /* 605 * arg0 - sysino 606 * arg1 - intr_state 607 * 608 * ret0 - status 609 */ 610 ENTRY(hvio_intr_setstate) 611 mov HVIO_INTR_SETSTATE, %o5 612 ta FAST_TRAP 613 retl 614 nop 615 SET_SIZE(hvio_intr_setstate) 616 617 /* 618 * arg0 - sysino 619 * 620 * ret0 - status 621 * ret1 - cpu_id 622 */ 623 ENTRY(hvio_intr_gettarget) 624 mov %o1, %o2 625 mov HVIO_INTR_GETTARGET, %o5 626 ta FAST_TRAP 627 brz,a %o0, 1f 628 stuw %o1, [%o2] 6291: retl 630 nop 631 SET_SIZE(hvio_intr_gettarget) 632 633 /* 634 * arg0 - sysino 635 * arg1 - cpu_id 636 * 637 * ret0 - status 638 */ 639 ENTRY(hvio_intr_settarget) 640 mov HVIO_INTR_SETTARGET, %o5 641 ta FAST_TRAP 642 retl 643 nop 644 SET_SIZE(hvio_intr_settarget) 645 646 /* 647 * arg0 - devhandle 648 * arg1 - tsbid 649 * arg2 - pages 650 * arg3 - io_attributes 651 * arg4 - io_page_list_p 652 * 653 * ret1 - pages_mapped 654 */ 655 ENTRY(hvio_iommu_map) 656 save %sp, -SA(MINFRAME64), %sp 657 mov %i0, %o0 658 mov %i1, %o1 659 mov %i2, %o2 660 mov %i3, %o3 661 mov %i4, %o4 662 mov HVIO_IOMMU_MAP, %o5 663 ta FAST_TRAP 664 brnz %o0, 1f 665 mov %o0, %i0 666 stuw %o1, [%i5] 6671: 668 ret 669 restore 670 SET_SIZE(hvio_iommu_map) 671 672 /* 673 * arg0 - devhandle 674 * arg1 - tsbid 675 * arg2 - pages 676 * 677 * ret1 - pages_demapped 678 */ 679 ENTRY(hvio_iommu_demap) 680 mov HVIO_IOMMU_DEMAP, %o5 681 ta FAST_TRAP 682 brz,a %o0, 1f 683 stuw %o1, [%o3] 6841: retl 685 nop 686 SET_SIZE(hvio_iommu_demap) 687 688 /* 689 * arg0 - devhandle 690 * arg1 - tsbid 691 * 692 * 693 * ret0 - status 694 * ret1 - io_attributes 695 * ret2 - r_addr 696 */ 697 ENTRY(hvio_iommu_getmap) 698 mov %o2, %o4 699 mov HVIO_IOMMU_GETMAP, %o5 700 ta FAST_TRAP 701 brnz %o0, 1f 702 nop 703 stx %o2, [%o3] 704 st %o1, [%o4] 7051: 706 retl 707 nop 708 SET_SIZE(hvio_iommu_getmap) 709 710 /* 711 * arg0 - devhandle 712 * arg1 - r_addr 713 * arg2 - io_attributes 714 * 715 * 716 * ret0 - status 717 * ret1 - io_addr 718 */ 719 ENTRY(hvio_iommu_getbypass) 720 mov HVIO_IOMMU_GETBYPASS, %o5 721 ta FAST_TRAP 722 brz,a %o0, 1f 723 stx %o1, [%o3] 7241: retl 725 nop 726 SET_SIZE(hvio_iommu_getbypass) 727 728 /* 729 * arg0 - devhandle 730 * arg1 - r_addr 731 * arg2 - size 732 * 733 * ret1 - error_flag 734 * ret2 - data 735 */ 736 ENTRY(hvio_peek) 737 mov HVIO_PEEK, %o5 738 ta FAST_TRAP 739 brnz %o0, 1f 740 nop 741 stx %o2, [%o4] 742 st %o1, [%o3] 7431: 744 retl 745 nop 746 SET_SIZE(hvio_peek) 747 748 /* 749 * arg0 - devhandle 750 * arg1 - r_addr 751 * arg2 - sizes 752 * arg3 - data 753 * arg4 - r_addr2 754 * 755 * ret1 - error_flag 756 */ 757 ENTRY(hvio_poke) 758 save %sp, -SA(MINFRAME64), %sp 759 mov %i0, %o0 760 mov %i1, %o1 761 mov %i2, %o2 762 mov %i3, %o3 763 mov %i4, %o4 764 mov HVIO_POKE, %o5 765 ta FAST_TRAP 766 brnz %o0, 1f 767 mov %o0, %i0 768 stuw %o1, [%i5] 7691: 770 ret 771 restore 772 SET_SIZE(hvio_poke) 773 774 /* 775 * arg0 - devhandle 776 * arg1 - r_addr 777 * arg2 - num_bytes 778 * arg3 - io_sync_direction 779 * 780 * ret0 - status 781 * ret1 - bytes_synched 782 */ 783 ENTRY(hvio_dma_sync) 784 mov HVIO_DMA_SYNC, %o5 785 ta FAST_TRAP 786 brz,a %o0, 1f 787 stx %o1, [%o4] 7881: retl 789 nop 790 SET_SIZE(hvio_dma_sync) 791 792 /* 793 * arg0 - devhandle 794 * arg1 - msiq_id 795 * arg2 - r_addr 796 * arg3 - nentries 797 * 798 * ret0 - status 799 */ 800 ENTRY(hvio_msiq_conf) 801 mov HVIO_MSIQ_CONF, %o5 802 ta FAST_TRAP 803 retl 804 nop 805 SET_SIZE(hvio_msiq_conf) 806 807 /* 808 * arg0 - devhandle 809 * arg1 - msiq_id 810 * 811 * ret0 - status 812 * ret1 - r_addr 813 * ret1 - nentries 814 */ 815 ENTRY(hvio_msiq_info) 816 mov %o2, %o4 817 mov HVIO_MSIQ_INFO, %o5 818 ta FAST_TRAP 819 brnz 1f 820 nop 821 stx %o1, [%o4] 822 stuw %o2, [%o3] 8231: retl 824 nop 825 SET_SIZE(hvio_msiq_info) 826 827 /* 828 * arg0 - devhandle 829 * arg1 - msiq_id 830 * 831 * ret0 - status 832 * ret1 - msiq_valid_state 833 */ 834 ENTRY(hvio_msiq_getvalid) 835 mov HVIO_MSIQ_GETVALID, %o5 836 ta FAST_TRAP 837 brz,a %o0, 1f 838 stuw %o1, [%o2] 8391: retl 840 nop 841 SET_SIZE(hvio_msiq_getvalid) 842 843 /* 844 * arg0 - devhandle 845 * arg1 - msiq_id 846 * arg2 - msiq_valid_state 847 * 848 * ret0 - status 849 */ 850 ENTRY(hvio_msiq_setvalid) 851 mov HVIO_MSIQ_SETVALID, %o5 852 ta FAST_TRAP 853 retl 854 nop 855 SET_SIZE(hvio_msiq_setvalid) 856 857 /* 858 * arg0 - devhandle 859 * arg1 - msiq_id 860 * 861 * ret0 - status 862 * ret1 - msiq_state 863 */ 864 ENTRY(hvio_msiq_getstate) 865 mov HVIO_MSIQ_GETSTATE, %o5 866 ta FAST_TRAP 867 brz,a %o0, 1f 868 stuw %o1, [%o2] 8691: retl 870 nop 871 SET_SIZE(hvio_msiq_getstate) 872 873 /* 874 * arg0 - devhandle 875 * arg1 - msiq_id 876 * arg2 - msiq_state 877 * 878 * ret0 - status 879 */ 880 ENTRY(hvio_msiq_setstate) 881 mov HVIO_MSIQ_SETSTATE, %o5 882 ta FAST_TRAP 883 retl 884 nop 885 SET_SIZE(hvio_msiq_setstate) 886 887 /* 888 * arg0 - devhandle 889 * arg1 - msiq_id 890 * 891 * ret0 - status 892 * ret1 - msiq_head 893 */ 894 ENTRY(hvio_msiq_gethead) 895 mov HVIO_MSIQ_GETHEAD, %o5 896 ta FAST_TRAP 897 brz,a %o0, 1f 898 stx %o1, [%o2] 8991: retl 900 nop 901 SET_SIZE(hvio_msiq_gethead) 902 903 /* 904 * arg0 - devhandle 905 * arg1 - msiq_id 906 * arg2 - msiq_head 907 * 908 * ret0 - status 909 */ 910 ENTRY(hvio_msiq_sethead) 911 mov HVIO_MSIQ_SETHEAD, %o5 912 ta FAST_TRAP 913 retl 914 nop 915 SET_SIZE(hvio_msiq_sethead) 916 917 /* 918 * arg0 - devhandle 919 * arg1 - msiq_id 920 * 921 * ret0 - status 922 * ret1 - msiq_tail 923 */ 924 ENTRY(hvio_msiq_gettail) 925 mov HVIO_MSIQ_GETTAIL, %o5 926 ta FAST_TRAP 927 brz,a %o0, 1f 928 stx %o1, [%o2] 9291: retl 930 nop 931 SET_SIZE(hvio_msiq_gettail) 932 933 /* 934 * arg0 - devhandle 935 * arg1 - msi_num 936 * 937 * ret0 - status 938 * ret1 - msiq_id 939 */ 940 ENTRY(hvio_msi_getmsiq) 941 mov HVIO_MSI_GETMSIQ, %o5 942 ta FAST_TRAP 943 brz,a %o0, 1f 944 stuw %o1, [%o2] 9451: retl 946 nop 947 SET_SIZE(hvio_msi_getmsiq) 948 949 /* 950 * arg0 - devhandle 951 * arg1 - msi_num 952 * arg2 - msiq_id 953 * arg2 - msitype 954 * 955 * ret0 - status 956 */ 957 ENTRY(hvio_msi_setmsiq) 958 mov HVIO_MSI_SETMSIQ, %o5 959 ta FAST_TRAP 960 retl 961 nop 962 SET_SIZE(hvio_msi_setmsiq) 963 964 /* 965 * arg0 - devhandle 966 * arg1 - msi_num 967 * 968 * ret0 - status 969 * ret1 - msi_valid_state 970 */ 971 ENTRY(hvio_msi_getvalid) 972 mov HVIO_MSI_GETVALID, %o5 973 ta FAST_TRAP 974 brz,a %o0, 1f 975 stuw %o1, [%o2] 9761: retl 977 nop 978 SET_SIZE(hvio_msi_getvalid) 979 980 /* 981 * arg0 - devhandle 982 * arg1 - msi_num 983 * arg2 - msi_valid_state 984 * 985 * ret0 - status 986 */ 987 ENTRY(hvio_msi_setvalid) 988 mov HVIO_MSI_SETVALID, %o5 989 ta FAST_TRAP 990 retl 991 nop 992 SET_SIZE(hvio_msi_setvalid) 993 994 /* 995 * arg0 - devhandle 996 * arg1 - msi_num 997 * 998 * ret0 - status 999 * ret1 - msi_state 1000 */ 1001 ENTRY(hvio_msi_getstate) 1002 mov HVIO_MSI_GETSTATE, %o5 1003 ta FAST_TRAP 1004 brz,a %o0, 1f 1005 stuw %o1, [%o2] 10061: retl 1007 nop 1008 SET_SIZE(hvio_msi_getstate) 1009 1010 /* 1011 * arg0 - devhandle 1012 * arg1 - msi_num 1013 * arg2 - msi_state 1014 * 1015 * ret0 - status 1016 */ 1017 ENTRY(hvio_msi_setstate) 1018 mov HVIO_MSI_SETSTATE, %o5 1019 ta FAST_TRAP 1020 retl 1021 nop 1022 SET_SIZE(hvio_msi_setstate) 1023 1024 /* 1025 * arg0 - devhandle 1026 * arg1 - msg_type 1027 * 1028 * ret0 - status 1029 * ret1 - msiq_id 1030 */ 1031 ENTRY(hvio_msg_getmsiq) 1032 mov HVIO_MSG_GETMSIQ, %o5 1033 ta FAST_TRAP 1034 brz,a %o0, 1f 1035 stuw %o1, [%o2] 10361: retl 1037 nop 1038 SET_SIZE(hvio_msg_getmsiq) 1039 1040 /* 1041 * arg0 - devhandle 1042 * arg1 - msg_type 1043 * arg2 - msiq_id 1044 * 1045 * ret0 - status 1046 */ 1047 ENTRY(hvio_msg_setmsiq) 1048 mov HVIO_MSG_SETMSIQ, %o5 1049 ta FAST_TRAP 1050 retl 1051 nop 1052 SET_SIZE(hvio_msg_setmsiq) 1053 1054 /* 1055 * arg0 - devhandle 1056 * arg1 - msg_type 1057 * 1058 * ret0 - status 1059 * ret1 - msg_valid_state 1060 */ 1061 ENTRY(hvio_msg_getvalid) 1062 mov HVIO_MSG_GETVALID, %o5 1063 ta FAST_TRAP 1064 brz,a %o0, 1f 1065 stuw %o1, [%o2] 10661: retl 1067 nop 1068 SET_SIZE(hvio_msg_getvalid) 1069 1070 /* 1071 * arg0 - devhandle 1072 * arg1 - msg_type 1073 * arg2 - msg_valid_state 1074 * 1075 * ret0 - status 1076 */ 1077 ENTRY(hvio_msg_setvalid) 1078 mov HVIO_MSG_SETVALID, %o5 1079 ta FAST_TRAP 1080 retl 1081 nop 1082 SET_SIZE(hvio_msg_setvalid) 1083 1084 /* 1085 * hv_cpu_yield(void) 1086 */ 1087 ENTRY(hv_cpu_yield) 1088#ifdef NIAGARA_ERRATUM_39 1089 /* 1090 * If niagara_erratum_39 is set, then we need to halt the strand by 1091 * executing a synthetic "halt" instruction which maps to a 1092 * wrasr %asr26 with a data value which has bit 0 clear. 1093 * 1094 * Note that we don't halt the strand if there are any pending 1095 * soft interrupts (%asr22). 1096 */ 1097 set niagara_erratum_39, %o0 1098 ld [%o0], %o1 1099 brz %o1, 2f 1100 nop 1101 1102 rd %asr26, %o0 1103 andn %o0, 1, %o0 1104 rd %asr22, %o1 ! don't halt if soft interrupts pending 1105 brnz %o1, 1f 1106 nop 1107 wr %o0, %asr26 ! halt the strand 11081: 1109 mov %g0, %o0 1110 retl 1111 nop 11122: 1113#endif /* NIAGARA_ERRATUM_39 */ 1114 mov HV_CPU_YIELD, %o5 1115 ta FAST_TRAP 1116 retl 1117 nop 1118 SET_SIZE(hv_cpu_yield) 1119 1120 /* 1121 * hv_service_recv(uint64_t s_id, uint64_t buf_pa, 1122 * uint64_t size, uint64_t *recv_bytes); 1123 */ 1124 ENTRY(hv_service_recv) 1125 save %sp, -SA(MINFRAME), %sp 1126 mov %i0, %o0 1127 mov %i1, %o1 1128 mov %i2, %o2 1129 mov %i3, %o3 1130 mov SVC_RECV, %o5 1131 ta FAST_TRAP 1132 brnz %o0, 1f 1133 mov %o0, %i0 1134 stx %o1, [%i3] 11351: 1136 ret 1137 restore 1138 SET_SIZE(hv_service_recv) 1139 1140 /* 1141 * hv_service_send(uint64_t s_id, uint64_t buf_pa, 1142 * uint64_t size, uint64_t *recv_bytes); 1143 */ 1144 ENTRY(hv_service_send) 1145 save %sp, -SA(MINFRAME), %sp 1146 mov %i0, %o0 1147 mov %i1, %o1 1148 mov %i2, %o2 1149 mov %i3, %o3 1150 mov SVC_SEND, %o5 1151 ta FAST_TRAP 1152 brnz %o0, 1f 1153 mov %o0, %i0 1154 stx %o1, [%i3] 11551: 1156 ret 1157 restore 1158 SET_SIZE(hv_service_send) 1159 1160 /* 1161 * hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 1162 */ 1163 ENTRY(hv_service_getstatus) 1164 mov %o1, %o4 ! save datap 1165 mov SVC_GETSTATUS, %o5 1166 ta FAST_TRAP 1167 brz,a %o0, 1f 1168 stx %o1, [%o4] 11691: 1170 retl 1171 nop 1172 SET_SIZE(hv_service_getstatus) 1173 1174 /* 1175 * hv_service_clrstatus(uint64_t s_id, uint64_t bits); 1176 */ 1177 ENTRY(hv_service_clrstatus) 1178 mov SVC_CLRSTATUS, %o5 1179 ta FAST_TRAP 1180 retl 1181 nop 1182 SET_SIZE(hv_service_clrstatus) 1183 1184 /* 1185 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 1186 */ 1187 ENTRY(hv_cpu_state) 1188 mov %o1, %o4 ! save datap 1189 mov HV_CPU_STATE, %o5 1190 ta FAST_TRAP 1191 brz,a %o0, 1f 1192 stx %o1, [%o4] 11931: 1194 retl 1195 nop 1196 SET_SIZE(hv_cpu_state) 1197 1198 /* 1199 * HV state dump zone Configure 1200 * arg0 real adrs of dump buffer (%o0) 1201 * arg1 size of dump buffer (%o1) 1202 * ret0 status (%o0) 1203 * ret1 size of buffer on success and min size on EINVAL (%o1) 1204 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 1205 */ 1206 ENTRY(hv_dump_buf_update) 1207 mov DUMP_BUF_UPDATE, %o5 1208 ta FAST_TRAP 1209 retl 1210 stx %o1, [%o2] 1211 SET_SIZE(hv_dump_buf_update) 1212 1213 1214 /* 1215 * For memory scrub 1216 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 1217 * uint64_t *scrubbed_len); 1218 * Retun %o0 -- status 1219 * %o1 -- bytes scrubbed 1220 */ 1221 ENTRY(hv_mem_scrub) 1222 mov %o2, %o4 1223 mov HV_MEM_SCRUB, %o5 1224 ta FAST_TRAP 1225 retl 1226 stx %o1, [%o4] 1227 SET_SIZE(hv_mem_scrub) 1228 1229 /* 1230 * Flush ecache 1231 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 1232 * uint64_t *flushed_len); 1233 * Retun %o0 -- status 1234 * %o1 -- bytes flushed 1235 */ 1236 ENTRY(hv_mem_sync) 1237 mov %o2, %o4 1238 mov HV_MEM_SYNC, %o5 1239 ta FAST_TRAP 1240 retl 1241 stx %o1, [%o4] 1242 SET_SIZE(hv_mem_sync) 1243 1244 /* 1245 * TTRACE_BUF_CONF Configure 1246 * arg0 RA base of buffer (%o0) 1247 * arg1 buf size in no. of entries (%o1) 1248 * ret0 status (%o0) 1249 * ret1 minimum size in no. of entries on failure, 1250 * actual size in no. of entries on success (%o1) 1251 */ 1252 ENTRY(hv_ttrace_buf_conf) 1253 mov TTRACE_BUF_CONF, %o5 1254 ta FAST_TRAP 1255 retl 1256 stx %o1, [%o2] 1257 SET_SIZE(hv_ttrace_buf_conf) 1258 1259 /* 1260 * TTRACE_BUF_INFO 1261 * ret0 status (%o0) 1262 * ret1 RA base of buffer (%o1) 1263 * ret2 size in no. of entries (%o2) 1264 */ 1265 ENTRY(hv_ttrace_buf_info) 1266 mov %o0, %o3 1267 mov %o1, %o4 1268 mov TTRACE_BUF_INFO, %o5 1269 ta FAST_TRAP 1270 stx %o1, [%o3] 1271 retl 1272 stx %o2, [%o4] 1273 SET_SIZE(hv_ttrace_buf_info) 1274 1275 /* 1276 * TTRACE_ENABLE 1277 * arg0 enable/ disable (%o0) 1278 * ret0 status (%o0) 1279 * ret1 previous enable state (%o1) 1280 */ 1281 ENTRY(hv_ttrace_enable) 1282 mov %o1, %o2 1283 mov TTRACE_ENABLE, %o5 1284 ta FAST_TRAP 1285 retl 1286 stx %o1, [%o2] 1287 SET_SIZE(hv_ttrace_enable) 1288 1289 /* 1290 * TTRACE_FREEZE 1291 * arg0 enable/ freeze (%o0) 1292 * ret0 status (%o0) 1293 * ret1 previous freeze state (%o1) 1294 */ 1295 ENTRY(hv_ttrace_freeze) 1296 mov %o1, %o2 1297 mov TTRACE_FREEZE, %o5 1298 ta FAST_TRAP 1299 retl 1300 stx %o1, [%o2] 1301 SET_SIZE(hv_ttrace_freeze) 1302 1303 /* 1304 * MACH_DESC 1305 * arg0 buffer real address 1306 * arg1 pointer to uint64_t for size of buffer 1307 * ret0 status 1308 * ret1 return required size of buffer / returned data size 1309 */ 1310 ENTRY(hv_mach_desc) 1311 mov %o1, %o4 ! save datap 1312 ldx [%o1], %o1 1313 mov HV_MACH_DESC, %o5 1314 ta FAST_TRAP 1315 retl 1316 stx %o1, [%o4] 1317 SET_SIZE(hv_mach_desc) 1318 1319 /* 1320 * hv_ncs_request(int cmd, uint64_t realaddr, size_t sz) 1321 */ 1322 ENTRY(hv_ncs_request) 1323 mov HV_NCS_REQUEST, %o5 1324 ta FAST_TRAP 1325 retl 1326 nop 1327 SET_SIZE(hv_ncs_request) 1328 1329#ifdef NIAGARA_ERRATUM_39 1330 .seg ".data" 1331 .align 4 1332 .global niagara_erratum_39 1333niagara_erratum_39: 1334 .word 0 1335 .seg ".text" 1336#endif 1337#endif /* lint || __lint */ 1338