1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #ifndef _SYS_PX_LIB4V_H 26 #define _SYS_PX_LIB4V_H 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * Fasttrap numbers for VPCI hypervisor functions. 34 */ 35 36 #define HVIO_IOMMU_MAP 0xb0 37 #define HVIO_IOMMU_DEMAP 0xb1 38 #define HVIO_IOMMU_GETMAP 0xb2 39 #define HVIO_IOMMU_GETBYPASS 0xb3 40 41 #define HVIO_CONFIG_GET 0xb4 42 #define HVIO_CONFIG_PUT 0xb5 43 44 #define HVIO_PEEK 0xb6 45 #define HVIO_POKE 0xb7 46 47 #define HVIO_DMA_SYNC 0xb8 48 49 #define HVIO_MSIQ_CONF 0xc0 50 #define HVIO_MSIQ_INFO 0xc1 51 #define HVIO_MSIQ_GETVALID 0xc2 52 #define HVIO_MSIQ_SETVALID 0xc3 53 #define HVIO_MSIQ_GETSTATE 0xc4 54 #define HVIO_MSIQ_SETSTATE 0xc5 55 #define HVIO_MSIQ_GETHEAD 0xc6 56 #define HVIO_MSIQ_SETHEAD 0xc7 57 #define HVIO_MSIQ_GETTAIL 0xc8 58 59 #define HVIO_MSI_GETVALID 0xc9 60 #define HVIO_MSI_SETVALID 0xca 61 #define HVIO_MSI_GETMSIQ 0xcb 62 #define HVIO_MSI_SETMSIQ 0xcc 63 #define HVIO_MSI_GETSTATE 0xcd 64 #define HVIO_MSI_SETSTATE 0xce 65 66 #define HVIO_MSG_GETMSIQ 0xd0 67 #define HVIO_MSG_SETMSIQ 0xd1 68 #define HVIO_MSG_GETVALID 0xd2 69 #define HVIO_MSG_SETVALID 0xd3 70 71 /* 72 * Fasttrap numbers for SDIO hypervisor functions. 73 */ 74 #define PCI_IOV_ROOT_CONFIGURED 0xf8 75 76 /* 77 * Fasttrap numbers for SDIO ERR hypervisor functions. 78 */ 79 #define PCI_ERROR_SEND 0xff 80 81 #ifndef _ASM 82 83 /* 84 * The device handle uniquely identifies a SUN4V device. 85 * It consists of the lower 28-bits of the hi-cell of the 86 * first entry of the SUN4V device's "reg" property as 87 * defined by the SUN4V Bus Binding to Open Firmware. 88 */ 89 #define DEVHDLE_MASK 0xFFFFFFF 90 91 #define PX_ADDR2PFN(addr, index, flags, i) \ 92 ((flags & MMU_MAP_PFN) ? \ 93 PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \ 94 hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i)))) 95 96 /* 97 * Hypercall service versioning 98 */ 99 #define PX_HSVC_MAJOR_VER_1 0x1ull 100 #define PX_HSVC_MAJOR_VER_2 0x2ull 101 #define PX_HSVC_MINOR_VER_0 0x0ull 102 #define PX_HSVC_MINOR_VER_1 0x1ull 103 #define PX_HSVC_MINOR_VER_2 0x2ull 104 105 /* 106 * VPCI API versioning. 107 * Currently PX nexus driver supports VPCI API version 2.0 108 * 1.0 - Negotiated/supported. 109 * 1.1/1.2 - Deprecated. 110 * 2.0 - Negotiated/supported. 111 */ 112 #define PX_VPCI_MAJOR_VER PX_HSVC_MAJOR_VER_2 113 #define PX_VPCI_MINOR_VER PX_HSVC_MINOR_VER_0 114 115 /* 116 * SDIO API versioning. 117 * Currently PX nexus driver supports SDIO API version 1.0 118 */ 119 #define PX_SDIO_MAJOR_VER PX_HSVC_MAJOR_VER_1 120 #define PX_SDIO_MINOR_VER PX_HSVC_MINOR_VER_0 121 122 /* 123 * SDIO ERR API versioning. 124 * Currently PX nexus driver supports SDIO ERR API version 1.0 125 */ 126 #define PX_SDIO_ERR_MAJOR_VER PX_HSVC_MAJOR_VER_1 127 #define PX_SDIO_ERR_MINOR_VER PX_HSVC_MINOR_VER_0 128 129 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 130 pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p, 131 pages_t *pages_mapped); 132 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 133 pages_t pages, pages_t *pages_demapped); 134 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 135 io_attributes_t *attr_p, r_addr_t *r_addr_p); 136 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 137 io_attributes_t attr, io_addr_t *io_addr_p); 138 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 139 size_t num_bytes, io_sync_direction_t io_sync_direction, 140 size_t *bytes_synched); 141 142 /* 143 * MSIQ Functions: 144 */ 145 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 146 r_addr_t ra, uint_t msiq_rec_cnt); 147 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 148 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 149 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 150 pci_msiq_valid_state_t *msiq_valid_state); 151 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 152 pci_msiq_valid_state_t msiq_valid_state); 153 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 154 pci_msiq_state_t *msiq_state); 155 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 156 pci_msiq_state_t msiq_state); 157 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 158 msiqhead_t *msiq_head); 159 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 160 msiqhead_t msiq_head); 161 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 162 msiqtail_t *msiq_tail); 163 164 /* 165 * MSI Functions: 166 */ 167 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 168 msiqid_t *msiq_id); 169 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 170 msiqid_t msiq_id, msi_type_t msitype); 171 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 172 pci_msi_valid_state_t *msi_valid_state); 173 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 174 pci_msi_valid_state_t msi_valid_state); 175 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 176 pci_msi_state_t *msi_state); 177 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 178 pci_msi_state_t msi_state); 179 180 181 extern uint64_t pci_error_send(devhandle_t dev_hdl, devino_t devino, 182 pci_device_t bdf); 183 184 /* 185 * MSG Functions: 186 */ 187 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 188 msiqid_t *msiq_id); 189 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 190 msiqid_t msiq_id); 191 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 192 pcie_msg_valid_state_t *msg_valid_state); 193 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 194 pcie_msg_valid_state_t msg_valid_state); 195 196 typedef struct px_config_acc_pvt { 197 dev_info_t *dip; 198 uint32_t raddr; 199 uint32_t vaddr; 200 } px_config_acc_pvt_t; 201 202 /* 203 * Peek/poke functionality: 204 */ 205 206 extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 207 uint32_t *status, uint64_t *data_p); 208 extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 209 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 210 extern uint64_t hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf, 211 int32_t *mps_cap); 212 extern uint64_t hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, 213 int32_t mps); 214 215 /* 216 * Priviledged physical access: 217 */ 218 extern uint64_t hv_ra2pa(uint64_t ra); 219 extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, 220 uint64_t arg3); 221 extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); 222 223 /* 224 * PCI IOV SDIO Funcitons: 225 */ 226 extern uint64_t pci_iov_root_configured(devhandle_t dev_hdl); 227 228 #endif /* _ASM */ 229 230 #ifdef __cplusplus 231 } 232 #endif 233 234 #endif /* _SYS_PX_LIB4V_H */ 235