1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#pragma ident "%Z%%M% %I% %E% SMI" 27 28/* 29 * Hypervisor calls called by px nexus driver. 30*/ 31 32#include <sys/asm_linkage.h> 33#include <sys/hypervisor_api.h> 34#include <sys/dditypes.h> 35#include <px_ioapi.h> 36#include "px_lib4v.h" 37 38#if defined(lint) || defined(__lint) 39 40/*ARGSUSED*/ 41uint64_t 42hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 43 pci_config_size_t size, pci_cfg_data_t *data_p) 44{ return (0); } 45 46/*ARGSUSED*/ 47uint64_t 48hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 49 pci_config_size_t size, pci_cfg_data_t data) 50{ return (0); } 51 52/*ARGSUSED*/ 53uint64_t 54hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 55 io_attributes_t attr, io_page_list_t *io_page_list_p, 56 pages_t *pages_mapped) 57{ return (0); } 58 59/*ARGSUSED*/ 60uint64_t 61hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 62 pages_t *pages_demapped) 63{ return (0); } 64 65/*ARGSUSED*/ 66uint64_t 67hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p, 68 r_addr_t *r_addr_p) 69{ return (0); } 70 71/*ARGSUSED*/ 72uint64_t 73hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr, 74 io_addr_t *io_addr_p) 75{ return (0); } 76 77/*ARGSUSED*/ 78uint64_t 79hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, 80 uint64_t *data_p) 81{ return (0); } 82 83/*ARGSUSED*/ 84uint64_t 85hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, 86 r_addr_t ra2, uint32_t *rdbk_status) 87{ return (0); } 88 89/*ARGSUSED*/ 90uint64_t 91hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, 92 io_sync_direction_t io_sync_direction, size_t *bytes_synched) 93{ return (0); } 94 95/*ARGSUSED*/ 96uint64_t 97hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, 98 uint_t msiq_rec_cnt) 99{ return (0); } 100 101/*ARGSUSED*/ 102uint64_t 103hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, 104 uint_t *msiq_rec_cnt_p) 105{ return (0); } 106 107/*ARGSUSED*/ 108uint64_t 109hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 110 pci_msiq_valid_state_t *msiq_valid_state) 111{ return (0); } 112 113/*ARGSUSED*/ 114uint64_t 115hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 116 pci_msiq_valid_state_t msiq_valid_state) 117{ return (0); } 118 119/*ARGSUSED*/ 120uint64_t 121hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 122 pci_msiq_state_t *msiq_state) 123{ return (0); } 124 125/*ARGSUSED*/ 126uint64_t 127hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 128 pci_msiq_state_t msiq_state) 129{ return (0); } 130 131/*ARGSUSED*/ 132uint64_t 133hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 134 msiqhead_t *msiq_head) 135{ return (0); } 136 137/*ARGSUSED*/ 138uint64_t 139hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 140 msiqhead_t msiq_head) 141{ return (0); } 142 143/*ARGSUSED*/ 144uint64_t 145hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 146 msiqtail_t *msiq_tail) 147{ return (0); } 148 149/*ARGSUSED*/ 150uint64_t 151hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 152 msiqid_t *msiq_id) 153{ return (0); } 154 155/*ARGSUSED*/ 156uint64_t 157hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 158 msiqid_t msiq_id, msi_type_t msitype) 159{ return (0); } 160 161/*ARGSUSED*/ 162uint64_t 163hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 164 pci_msi_valid_state_t *msi_valid_state) 165{ return (0); } 166 167/*ARGSUSED*/ 168uint64_t 169hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 170 pci_msi_valid_state_t msi_valid_state) 171{ return (0); } 172 173/*ARGSUSED*/ 174uint64_t 175hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 176 pci_msi_state_t *msi_state) 177{ return (0); } 178 179/*ARGSUSED*/ 180uint64_t 181hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 182 pci_msi_state_t msi_state) 183{ return (0); } 184 185/*ARGSUSED*/ 186uint64_t 187hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 188 msiqid_t *msiq_id) 189{ return (0); } 190 191/*ARGSUSED*/ 192uint64_t 193hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 194 msiqid_t msiq_id) 195{ return (0); } 196 197/*ARGSUSED*/ 198uint64_t 199hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 200 pcie_msg_valid_state_t *msg_valid_state) 201{ return (0); } 202 203/*ARGSUSED*/ 204uint64_t 205hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 206 pcie_msg_valid_state_t msg_valid_state) 207{ return (0); } 208 209/* 210 * First arg to both of these functions is a dummy, to accomodate how 211 * hv_hpriv() works. 212 */ 213/*ARGSUSED*/ 214int 215px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr) 216{ return (0); } 217 218#else /* lint || __lint */ 219 220 /* 221 * arg0 - devhandle 222 * arg1 - pci_device 223 * arg2 - pci_config_offset 224 * arg3 - pci_config_size 225 * 226 * ret0 - status 227 * ret1 - error_flag 228 * ret2 - pci_cfg_data 229 */ 230 ENTRY(hvio_config_get) 231 mov HVIO_CONFIG_GET, %o5 232 ta FAST_TRAP 233 brnz %o0, 1f 234 movrnz %o1, -1, %o2 235 brz,a %o1, 1f 236 stuw %o2, [%o4] 2371: retl 238 nop 239 SET_SIZE(hvio_config_get) 240 241 /* 242 * arg0 - devhandle 243 * arg1 - pci_device 244 * arg2 - pci_config_offset 245 * arg3 - pci_config_size 246 * arg4 - pci_cfg_data 247 * 248 * ret0 - status 249 * ret1 - error_flag 250 */ 251 ENTRY(hvio_config_put) 252 mov HVIO_CONFIG_PUT, %o5 253 ta FAST_TRAP 254 retl 255 nop 256 SET_SIZE(hvio_config_put) 257 258 /* 259 * arg0 - devhandle 260 * arg1 - tsbid 261 * arg2 - pages 262 * arg3 - io_attributes 263 * arg4 - io_page_list_p 264 * 265 * ret1 - pages_mapped 266 */ 267 ENTRY(hvio_iommu_map) 268 save %sp, -SA(MINFRAME64), %sp 269 mov %i0, %o0 270 mov %i1, %o1 271 mov %i2, %o2 272 mov %i3, %o3 273 mov %i4, %o4 274 mov HVIO_IOMMU_MAP, %o5 275 ta FAST_TRAP 276 brnz %o0, 1f 277 mov %o0, %i0 278 stuw %o1, [%i5] 2791: 280 ret 281 restore 282 SET_SIZE(hvio_iommu_map) 283 284 /* 285 * arg0 - devhandle 286 * arg1 - tsbid 287 * arg2 - pages 288 * 289 * ret1 - pages_demapped 290 */ 291 ENTRY(hvio_iommu_demap) 292 mov HVIO_IOMMU_DEMAP, %o5 293 ta FAST_TRAP 294 brz,a %o0, 1f 295 stuw %o1, [%o3] 2961: retl 297 nop 298 SET_SIZE(hvio_iommu_demap) 299 300 /* 301 * arg0 - devhandle 302 * arg1 - tsbid 303 * 304 * 305 * ret0 - status 306 * ret1 - io_attributes 307 * ret2 - r_addr 308 */ 309 ENTRY(hvio_iommu_getmap) 310 mov %o2, %o4 311 mov HVIO_IOMMU_GETMAP, %o5 312 ta FAST_TRAP 313 brnz %o0, 1f 314 nop 315 stx %o2, [%o3] 316 st %o1, [%o4] 3171: 318 retl 319 nop 320 SET_SIZE(hvio_iommu_getmap) 321 322 /* 323 * arg0 - devhandle 324 * arg1 - r_addr 325 * arg2 - io_attributes 326 * 327 * 328 * ret0 - status 329 * ret1 - io_addr 330 */ 331 ENTRY(hvio_iommu_getbypass) 332 mov HVIO_IOMMU_GETBYPASS, %o5 333 ta FAST_TRAP 334 brz,a %o0, 1f 335 stx %o1, [%o3] 3361: retl 337 nop 338 SET_SIZE(hvio_iommu_getbypass) 339 340 /* 341 * arg0 - devhandle 342 * arg1 - r_addr 343 * arg2 - size 344 * 345 * ret1 - error_flag 346 * ret2 - data 347 */ 348 ENTRY(hvio_peek) 349 mov HVIO_PEEK, %o5 350 ta FAST_TRAP 351 brnz %o0, 1f 352 nop 353 stx %o2, [%o4] 354 st %o1, [%o3] 3551: 356 retl 357 nop 358 SET_SIZE(hvio_peek) 359 360 /* 361 * arg0 - devhandle 362 * arg1 - r_addr 363 * arg2 - sizes 364 * arg3 - data 365 * arg4 - r_addr2 366 * 367 * ret1 - error_flag 368 */ 369 ENTRY(hvio_poke) 370 save %sp, -SA(MINFRAME64), %sp 371 mov %i0, %o0 372 mov %i1, %o1 373 mov %i2, %o2 374 mov %i3, %o3 375 mov %i4, %o4 376 mov HVIO_POKE, %o5 377 ta FAST_TRAP 378 brnz %o0, 1f 379 mov %o0, %i0 380 stuw %o1, [%i5] 3811: 382 ret 383 restore 384 SET_SIZE(hvio_poke) 385 386 /* 387 * arg0 - devhandle 388 * arg1 - r_addr 389 * arg2 - num_bytes 390 * arg3 - io_sync_direction 391 * 392 * ret0 - status 393 * ret1 - bytes_synched 394 */ 395 ENTRY(hvio_dma_sync) 396 mov HVIO_DMA_SYNC, %o5 397 ta FAST_TRAP 398 brz,a %o0, 1f 399 stx %o1, [%o4] 4001: retl 401 nop 402 SET_SIZE(hvio_dma_sync) 403 404 /* 405 * arg0 - devhandle 406 * arg1 - msiq_id 407 * arg2 - r_addr 408 * arg3 - nentries 409 * 410 * ret0 - status 411 */ 412 ENTRY(hvio_msiq_conf) 413 mov HVIO_MSIQ_CONF, %o5 414 ta FAST_TRAP 415 retl 416 nop 417 SET_SIZE(hvio_msiq_conf) 418 419 /* 420 * arg0 - devhandle 421 * arg1 - msiq_id 422 * 423 * ret0 - status 424 * ret1 - r_addr 425 * ret1 - nentries 426 */ 427 ENTRY(hvio_msiq_info) 428 mov %o2, %o4 429 mov HVIO_MSIQ_INFO, %o5 430 ta FAST_TRAP 431 brnz 1f 432 nop 433 stx %o1, [%o4] 434 stuw %o2, [%o3] 4351: retl 436 nop 437 SET_SIZE(hvio_msiq_info) 438 439 /* 440 * arg0 - devhandle 441 * arg1 - msiq_id 442 * 443 * ret0 - status 444 * ret1 - msiq_valid_state 445 */ 446 ENTRY(hvio_msiq_getvalid) 447 mov HVIO_MSIQ_GETVALID, %o5 448 ta FAST_TRAP 449 brz,a %o0, 1f 450 stuw %o1, [%o2] 4511: retl 452 nop 453 SET_SIZE(hvio_msiq_getvalid) 454 455 /* 456 * arg0 - devhandle 457 * arg1 - msiq_id 458 * arg2 - msiq_valid_state 459 * 460 * ret0 - status 461 */ 462 ENTRY(hvio_msiq_setvalid) 463 mov HVIO_MSIQ_SETVALID, %o5 464 ta FAST_TRAP 465 retl 466 nop 467 SET_SIZE(hvio_msiq_setvalid) 468 469 /* 470 * arg0 - devhandle 471 * arg1 - msiq_id 472 * 473 * ret0 - status 474 * ret1 - msiq_state 475 */ 476 ENTRY(hvio_msiq_getstate) 477 mov HVIO_MSIQ_GETSTATE, %o5 478 ta FAST_TRAP 479 brz,a %o0, 1f 480 stuw %o1, [%o2] 4811: retl 482 nop 483 SET_SIZE(hvio_msiq_getstate) 484 485 /* 486 * arg0 - devhandle 487 * arg1 - msiq_id 488 * arg2 - msiq_state 489 * 490 * ret0 - status 491 */ 492 ENTRY(hvio_msiq_setstate) 493 mov HVIO_MSIQ_SETSTATE, %o5 494 ta FAST_TRAP 495 retl 496 nop 497 SET_SIZE(hvio_msiq_setstate) 498 499 /* 500 * arg0 - devhandle 501 * arg1 - msiq_id 502 * 503 * ret0 - status 504 * ret1 - msiq_head 505 */ 506 ENTRY(hvio_msiq_gethead) 507 mov HVIO_MSIQ_GETHEAD, %o5 508 ta FAST_TRAP 509 brz,a %o0, 1f 510 stx %o1, [%o2] 5111: retl 512 nop 513 SET_SIZE(hvio_msiq_gethead) 514 515 /* 516 * arg0 - devhandle 517 * arg1 - msiq_id 518 * arg2 - msiq_head 519 * 520 * ret0 - status 521 */ 522 ENTRY(hvio_msiq_sethead) 523 mov HVIO_MSIQ_SETHEAD, %o5 524 ta FAST_TRAP 525 retl 526 nop 527 SET_SIZE(hvio_msiq_sethead) 528 529 /* 530 * arg0 - devhandle 531 * arg1 - msiq_id 532 * 533 * ret0 - status 534 * ret1 - msiq_tail 535 */ 536 ENTRY(hvio_msiq_gettail) 537 mov HVIO_MSIQ_GETTAIL, %o5 538 ta FAST_TRAP 539 brz,a %o0, 1f 540 stx %o1, [%o2] 5411: retl 542 nop 543 SET_SIZE(hvio_msiq_gettail) 544 545 /* 546 * arg0 - devhandle 547 * arg1 - msi_num 548 * 549 * ret0 - status 550 * ret1 - msiq_id 551 */ 552 ENTRY(hvio_msi_getmsiq) 553 mov HVIO_MSI_GETMSIQ, %o5 554 ta FAST_TRAP 555 brz,a %o0, 1f 556 stuw %o1, [%o2] 5571: retl 558 nop 559 SET_SIZE(hvio_msi_getmsiq) 560 561 /* 562 * arg0 - devhandle 563 * arg1 - msi_num 564 * arg2 - msiq_id 565 * arg2 - msitype 566 * 567 * ret0 - status 568 */ 569 ENTRY(hvio_msi_setmsiq) 570 mov HVIO_MSI_SETMSIQ, %o5 571 ta FAST_TRAP 572 retl 573 nop 574 SET_SIZE(hvio_msi_setmsiq) 575 576 /* 577 * arg0 - devhandle 578 * arg1 - msi_num 579 * 580 * ret0 - status 581 * ret1 - msi_valid_state 582 */ 583 ENTRY(hvio_msi_getvalid) 584 mov HVIO_MSI_GETVALID, %o5 585 ta FAST_TRAP 586 brz,a %o0, 1f 587 stuw %o1, [%o2] 5881: retl 589 nop 590 SET_SIZE(hvio_msi_getvalid) 591 592 /* 593 * arg0 - devhandle 594 * arg1 - msi_num 595 * arg2 - msi_valid_state 596 * 597 * ret0 - status 598 */ 599 ENTRY(hvio_msi_setvalid) 600 mov HVIO_MSI_SETVALID, %o5 601 ta FAST_TRAP 602 retl 603 nop 604 SET_SIZE(hvio_msi_setvalid) 605 606 /* 607 * arg0 - devhandle 608 * arg1 - msi_num 609 * 610 * ret0 - status 611 * ret1 - msi_state 612 */ 613 ENTRY(hvio_msi_getstate) 614 mov HVIO_MSI_GETSTATE, %o5 615 ta FAST_TRAP 616 brz,a %o0, 1f 617 stuw %o1, [%o2] 6181: retl 619 nop 620 SET_SIZE(hvio_msi_getstate) 621 622 /* 623 * arg0 - devhandle 624 * arg1 - msi_num 625 * arg2 - msi_state 626 * 627 * ret0 - status 628 */ 629 ENTRY(hvio_msi_setstate) 630 mov HVIO_MSI_SETSTATE, %o5 631 ta FAST_TRAP 632 retl 633 nop 634 SET_SIZE(hvio_msi_setstate) 635 636 /* 637 * arg0 - devhandle 638 * arg1 - msg_type 639 * 640 * ret0 - status 641 * ret1 - msiq_id 642 */ 643 ENTRY(hvio_msg_getmsiq) 644 mov HVIO_MSG_GETMSIQ, %o5 645 ta FAST_TRAP 646 brz,a %o0, 1f 647 stuw %o1, [%o2] 6481: retl 649 nop 650 SET_SIZE(hvio_msg_getmsiq) 651 652 /* 653 * arg0 - devhandle 654 * arg1 - msg_type 655 * arg2 - msiq_id 656 * 657 * ret0 - status 658 */ 659 ENTRY(hvio_msg_setmsiq) 660 mov HVIO_MSG_SETMSIQ, %o5 661 ta FAST_TRAP 662 retl 663 nop 664 SET_SIZE(hvio_msg_setmsiq) 665 666 /* 667 * arg0 - devhandle 668 * arg1 - msg_type 669 * 670 * ret0 - status 671 * ret1 - msg_valid_state 672 */ 673 ENTRY(hvio_msg_getvalid) 674 mov HVIO_MSG_GETVALID, %o5 675 ta FAST_TRAP 676 brz,a %o0, 1f 677 stuw %o1, [%o2] 6781: retl 679 nop 680 SET_SIZE(hvio_msg_getvalid) 681 682 /* 683 * arg0 - devhandle 684 * arg1 - msg_type 685 * arg2 - msg_valid_state 686 * 687 * ret0 - status 688 */ 689 ENTRY(hvio_msg_setvalid) 690 mov HVIO_MSG_SETVALID, %o5 691 ta FAST_TRAP 692 retl 693 nop 694 SET_SIZE(hvio_msg_setvalid) 695 696#define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3 697 698! px_phys_acc_4v: Do physical address read. 699! 700! After SHIFT_REGS: 701! %o0 is "from" address 702! %o1 is "to" address 703! 704! Assumes 8 byte data and that alignment is correct. 705! 706! Always returns success (0) in %o0 707 708 ! px_phys_acc_4v must not be split across pages. 709 ! 710 ! ATTN: Be sure that the alignment value is larger than the size of 711 ! the px_phys_acc_4v function. 712 ! 713 .align 0x40 714 715 ENTRY(px_phys_acc_4v) 716 717 SHIFT_REGS 718 ldx [%o0], %g1 719 stx %g1, [%o1] 720 membar #Sync ! Make sure the loads take 721 mov %g0, %o0 722 done 723 SET_SIZE(px_phys_acc_4v) 724 725#endif /* lint || __lint */ 726