1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_INTREG_H 27 #define _SYS_INTREG_H 28 29 #include <sys/machintreg.h> 30 31 #ifndef _ASM 32 #include <sys/types.h> 33 #endif 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #define INO_SIZE 6 /* Interrupt Number Offset bit size */ 40 #define INR_SIZE (IGN_SIZE + INO_SIZE) /* Interrupt Number bit size */ 41 #define MAX_IGN (1 << IGN_SIZE) /* Max Interrupt Group Number size */ 42 #define MAX_INO (1 << INO_SIZE) /* Max Interrupt Number per group */ 43 #define MAXDEVINTRS (MAX_IGN * MAX_INO) /* Max hardware intrs allowed */ 44 45 /* 46 * A platform may require use of the system interrupt table beyond 47 * the maximum hardware interrupts specified above for virtual device 48 * interrupts. If the platform does not specify MAXVINTRS we default to 0. 49 */ 50 #ifndef MAXVINTRS 51 #define MAXVINTRS 0 52 #endif 53 54 /* 55 * maximum system interrupts allowed 56 */ 57 #define MAXIVNUM (MAXDEVINTRS + MAXVINTRS) 58 59 /* 60 * Interrupt State Machine 61 * Each interrupt source has a 2-bit state machine which ensures that 62 * software sees exactly one interrupt packet per assertion of the 63 * interrupt signal. 64 */ 65 #define ISM_IDLE 0x0 /* not asserted or pending */ 66 #define ISM_TRANSMIT 0x1 /* asserted but is not dispatched */ 67 #define ISM_PENDING 0x2 /* dispatched to a processor or is in transit */ 68 69 /* 70 * Per-Processor Soft Interrupt Register 71 * XXX use %asr when the new assembler supports them 72 */ 73 #define SET_SOFTINT %asr20 /* ASR 0x14 */ 74 #define CLEAR_SOFTINT %asr21 /* ASR 0x15 */ 75 #define SOFTINT %asr22 /* ASR 0x16 */ 76 #define SOFTINT_MASK 0xFFFE /* <15:1> */ 77 #define TICK_INT_MASK 0x1 /* <0> */ 78 #define STICK_INT_MASK 0x10000 /* <0> */ 79 80 /* 81 * Per-Processor TICK Register and TICK_Compare registers 82 * 83 */ 84 #define TICK_COMPARE %asr23 /* ASR 0x17 */ 85 #define STICK %asr24 /* ASR 0x18 */ 86 #define STICK_COMPARE %asr25 /* ASR 0x19 */ 87 #define TICKINT_DIS_SHFT 0x3f 88 89 #ifndef _ASM 90 91 /* 92 * Interrupt Packet (mondo) 93 */ 94 struct intr_packet { 95 uint64_t intr_data0; /* can be an interrupt number or a pc */ 96 uint64_t intr_data1; 97 uint64_t intr_data2; 98 }; 99 100 /* 101 * Leftover bogus stuff; removed them later 102 */ 103 struct cpu_intreg { 104 uint_t pend; 105 uint_t clr_pend; 106 uint_t set_pend; 107 uchar_t filler[0x1000 - 0xc]; 108 }; 109 110 struct sys_intreg { 111 uint_t sys_pend; 112 uint_t sys_m; 113 uint_t sys_mclear; 114 uint_t sys_mset; 115 uint_t itr; 116 }; 117 118 #endif /* _ASM */ 119 120 #ifdef __cplusplus 121 } 122 #endif 123 124 #endif /* _SYS_INTREG_H */ 125