1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 22 * Use is subject to license terms. 23 */ 24 25 #ifndef _MC_AMD_H 26 #define _MC_AMD_H 27 28 #include <sys/mc.h> 29 #include <sys/isa_defs.h> 30 #include <sys/x86_archext.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Definitions, register offsets, register structure etc pertaining to 38 * the memory controller on AMD64 systems. These are used by both the 39 * AMD cpu module and the mc-amd driver. 40 */ 41 42 /* 43 * The mc-amd driver exports an nvlist to userland, where the primary 44 * consumer is the "chip" topology enumerator for this platform type which 45 * builds a full topology subtree from this information. Others can use 46 * it, too, but don't depend on it not changing without an ARC contract 47 * (and the contract should probably concern the topology, not this nvlist). 48 * 49 * In the initial mc-amd implementation this nvlist was not versioned; 50 * we'll think of that as version 0 and it may be recognised by the absence 51 * of a "mcamd-nvlist-version member. 52 * 53 * Version 1 is defined as follows. A name in square brackets indicates 54 * that member is optional (only present if the actual value is valid). 55 * 56 * Name Type Description 57 * -------------------- --------------- --------------------------------------- 58 * mcamd-nvlist-version uint8 Exported nvlist version number 59 * num uint64 Chip id of this memory controller 60 * revision uint64 cpuid_getchiprev() result 61 * revname string cpuid_getchiprevstr() result 62 * socket string "Socket 755|939|940|AM2|F(1207)|S1g1" 63 * ecc-type string "ChipKill 128/16" or "Normal 64/8" 64 * base-addr uint64 Node base address 65 * lim-addr uint64 Node limit address 66 * node-ilen uint64 0|1|3|7 for 0/2/4/8 way node interleave 67 * node-ilsel uint64 Node interleave position of this node 68 * cs-intlv-factor uint64 chip-select interleave: 1/2/4/8 69 * dram-hole-size uint64 size in bytes from dram hole addr reg 70 * access-width uint64 MC mode, 64 or 128 bit 71 * bank-mapping uint64 Raw DRAM Bank Address Mapping Register 72 * bankswizzle uint64 1 if bank swizzling enabled; else 0 73 * mismatched-dimm-support uint64 1 if active; else 0 74 * [spare-csnum] uint64 Chip-select pair number of any spare 75 * [bad-csnum] uint64 Chip-select pair number of swapped cs 76 * cslist nvlist array See below; may have 0 members 77 * dimmlist nvlist array See below; may have 0 members 78 * 79 * cslist is an array of nvlist, each as follows: 80 * 81 * Name Type Description 82 * -------------------- --------------- --------------------------------------- 83 * num uint64 Chip-select base/mask pair number 84 * base-addr uint64 Chip-select base address (rel to node) 85 * mask uint64 Chip-select mask 86 * size uint64 Chip-select size in bytes 87 * dimm1-num uint64 First dimm (lodimm if a pair) 88 * dimm1-csname string Socket cs# line name for 1st dimm rank 89 * [dimm2-num] uint64 Second dimm if applicable (updimm) 90 * [dimm2-csname] string Socket cs# line name for 2nd dimm rank 91 * 92 * dimmlist is an array of nvlist, each as follows: 93 * 94 * Name Type Description 95 * -------------------- --------------- --------------------------------------- 96 * num uint64 DIMM instance number 97 * size uint64 DIMM size in bytes 98 * csnums uint64 array CS base/mask pair(s) on this DIMM 99 * csnames string array Socket cs# line name(s) on this DIMM 100 * 101 * The n'th csnums entry corresponds to the n'th csnames entry 102 */ 103 #define MC_NVLIST_VERSTR "mcamd-nvlist-version" 104 #define MC_NVLIST_VERS0 0 105 #define MC_NVLIST_VERS1 1 106 #define MC_NVLIST_VERS MC_NVLIST_VERS1 107 108 /* 109 * Constants and feature/revision test macros that are not expected to vary 110 * among different AMD family 0xf processor revisions. 111 */ 112 113 /* 114 * Configuration constants 115 */ 116 #define MC_CHIP_MAXNODES 8 /* max number of MCs in system */ 117 #define MC_CHIP_NDIMM 8 /* max dimms per MC */ 118 #define MC_CHIP_NCS 8 /* number of chip-selects per MC */ 119 #define MC_CHIP_NDRAMCHAN 2 /* maximum number of dram channels */ 120 #define MC_CHIP_DIMMRANKMAX 4 /* largest number of ranks per dimm */ 121 #define MC_CHIP_DIMMPERCS 2 /* max number of dimms per cs */ 122 #define MC_CHIP_DIMMPAIR(csnum) (csnum / MC_CHIP_DIMMPERCS) 123 124 /* 125 * Memory controller registers are read via PCI config space accesses on 126 * bus 0, device 0x18 + NodeId, and function as follows: 127 * 128 * Function 0: HyperTransport Technology Configuration 129 * Function 1: Address Map 130 * Function 2: DRAM Controller & HyperTransport Technology Trace Mode 131 * Function 3: Miscellaneous Control 132 */ 133 134 #define MC_AMD_DEV_OFFSET 0x18 /* node ID + offset == PCI dev num */ 135 136 enum mc_funcnum { 137 MC_FUNC_HTCONFIG = 0, 138 MC_FUNC_ADDRMAP = 1, 139 MC_FUNC_DRAMCTL = 2, 140 MC_FUNC_MISCCTL = 3 141 }; 142 143 /* 144 * For a given (bus, device, function) a particular offset selects the 145 * desired register. All registers are 32-bits wide. 146 * 147 * Different family 0xf processor revisions vary slightly in the content 148 * of these configuration registers. The biggest change is with rev F 149 * where DDR2 support has been introduced along with some hardware-controlled 150 * correctable memory error thresholding. Fortunately most of the config info 151 * required by the mc-amd driver is similar across revisions. 152 * 153 * We will try to insulate most of the driver code from config register 154 * details by reading all memory-controller PCI config registers that we 155 * will need at driver attach time for each of functions 0 through 3, and 156 * storing them in a "cooked" form as memory controller properties. 157 * These are to be accessed directly where we have an mc_t to hand, otherwise 158 * through mcamd_get_numprop. As such we expect most/all use of the 159 * structures and macros defined below to be in those attach codepaths. 160 */ 161 162 /* 163 * Function 0 (HT Config) offsets 164 */ 165 #define MC_HT_REG_RTBL_NODE_0 0x40 166 #define MC_HT_REG_RTBL_INCR 4 167 #define MC_HT_REG_NODEID 0x60 168 #define MC_HT_REG_UNITID 0x64 169 170 /* 171 * Function 1 (address map) offsets for DRAM base, DRAM limit, DRAM hole 172 * registers. 173 */ 174 #define MC_AM_REG_DRAMBASE_0 0x40 /* Offset for DRAM Base 0 */ 175 #define MC_AM_REG_DRAMLIM_0 0x44 /* Offset for DRAM Limit 0 */ 176 #define MC_AM_REG_DRAM_INCR 8 /* incr between base/limit pairs */ 177 #define MC_AM_REG_HOLEADDR 0xf0 /* DRAM Hole Address Register */ 178 179 /* 180 * Function 2 (dram controller) offsets for chip-select base, chip-select mask, 181 * DRAM bank address mapping, DRAM configuration registers. 182 */ 183 #define MC_DC_REG_CS_INCR 4 /* incr for CS base and mask */ 184 #define MC_DC_REG_CSBASE_0 0x40 /* 0x40 - 0x5c */ 185 #define MC_DC_REG_CSMASK_0 0x60 /* 0x60 - 0x7c */ 186 #define MC_DC_REG_BANKADDRMAP 0x80 /* DRAM Bank Address Mapping */ 187 #define MC_DC_REG_DRAMCFGLO 0x90 /* DRAM Configuration Low */ 188 #define MC_DC_REG_DRAMCFGHI 0x94 /* DRAM Configuration High */ 189 #define MC_DC_REG_DRAMMISC 0xa0 /* DRAM Miscellaneous */ 190 191 /* 192 * Function 3 (misc control) offset for NB MCA config, scrubber control, 193 * online spare control and NB capabilities. 194 */ 195 #define MC_CTL_REG_NBCFG 0x44 /* MCA NB configuration register */ 196 #define MC_CTL_REG_SCRUBCTL 0x58 /* Scrub control register */ 197 #define MC_CTL_REG_SCRUBADDR_LO 0x5c /* DRAM Scrub Address Low */ 198 #define MC_CTL_REG_SCRUBADDR_HI 0x60 /* DRAM Scrub Address High */ 199 #define MC_CTL_REG_SPARECTL 0xb0 /* On-line spare control register */ 200 #define MC_CTL_REG_NBCAP 0xe8 /* NB Capabilities */ 201 202 #define MC_NBCAP_L3CAPABLE (1U << 25) 203 #define MC_NBCAP_MULTINODECPU (1U << 29) 204 205 /* 206 * MC4_MISC MSR and MC4_MISCj MSRs 207 */ 208 #define MC_MSR_NB_MISC0 0x413 209 #define MC_MSR_NB_MISC1 0xc0000408 210 #define MC_MSR_NB_MISC2 0xc0000409 211 #define MC_MSR_NB_MISC3 0xc000040a 212 #define MC_MSR_NB_MISC(j) \ 213 ((j) == 0 ? MC_MSR_NB_MISC0 : MC_MSR_NB_MISC1 + (j) - 1) 214 215 /* 216 * PCI registers will be represented as unions, with one fixed-width unsigned 217 * integer member providing access to the raw register value and one or more 218 * structs breaking the register out into bitfields (more than one struct if 219 * the register definitions varies across processor revisions). 220 * 221 * The "raw" union member will always be '_val32'. Use MCREG_VAL32 to 222 * access this member. 223 * 224 * The bitfield structs are all named _fmt_xxx where xxx identifies the 225 * processor revision to which it applies. At this point the only xxx 226 * values in use are: 227 * 'cmn' - applies to all revisions 228 * 'f_preF' - applies to revisions E and earlier 229 * 'f_revFG' - applies to revisions F and G 230 * 231 * Variants such as 'preD', 'revDE', 'postCG' etc should be introduced 232 * as requirements arise. The MC_REV_* and MC_REV_MATCH etc macros 233 * will also need to grow to match. Use MCREG_FIELD_* to access the 234 * individual bitfields of a register, perhaps using MC_REV_* and MC_REV_MATCH 235 * to decide which revision suffix to provide. Where a bitfield appears 236 * in different revisions but has the same use it should be named identically 237 * (even if the BKDG varies a little) so that the MC_REG_FIELD_* macros 238 * can lookup that member based on revision only. 239 */ 240 241 #define MC_REV_UNKNOWN X86_CHIPREV_UNKNOWN 242 243 #define MC_F_REV_B X86_CHIPREV_AMD_F_REV_B 244 #define MC_F_REV_C (X86_CHIPREV_AMD_F_REV_C0 | X86_CHIPREV_AMD_F_REV_CG) 245 #define MC_F_REV_D X86_CHIPREV_AMD_F_REV_D 246 #define MC_F_REV_E X86_CHIPREV_AMD_F_REV_E 247 #define MC_F_REV_F X86_CHIPREV_AMD_F_REV_F 248 #define MC_F_REV_G X86_CHIPREV_AMD_F_REV_G 249 250 #define MC_10_REV_A X86_CHIPREV_AMD_10_REV_A 251 #define MC_10_REV_B X86_CHIPREV_AMD_10_REV_B 252 253 /* 254 * The most common groupings for memory controller features. 255 */ 256 #define MC_F_REVS_BC (MC_F_REV_B | MC_F_REV_C) 257 #define MC_F_REVS_DE (MC_F_REV_D | MC_F_REV_E) 258 #define MC_F_REVS_BCDE (MC_F_REVS_BC | MC_F_REVS_DE) 259 #define MC_F_REVS_FG (MC_F_REV_F | MC_F_REV_G) 260 261 #define MC_10_REVS_AB (MC_10_REV_A | MC_10_REV_B) 262 263 /* 264 * Is 'rev' included in the 'revmask' bitmask? 265 */ 266 #define MC_REV_MATCH(rev, revmask) X86_CHIPREV_MATCH(rev, revmask) 267 268 /* 269 * Is 'rev' at least revision 'revmin' or greater 270 */ 271 #define MC_REV_ATLEAST(rev, minrev) X86_CHIPREV_ATLEAST(rev, minrev) 272 273 #define _MCREG_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field) 274 275 #define MCREG_VAL32(up) ((up)->_val32) 276 277 /* 278 * Access a field that has the same structure in all families and revisions 279 */ 280 #define MCREG_FIELD_CMN(up, field) _MCREG_FIELD(up, cmn, field) 281 282 /* 283 * Access a field as defined for family 0xf prior to revision F 284 */ 285 #define MCREG_FIELD_F_preF(up, field) _MCREG_FIELD(up, f_preF, field) 286 287 /* 288 * Access a field as defined for family 0xf revisions F and G 289 */ 290 #define MCREG_FIELD_F_revFG(up, field) _MCREG_FIELD(up, f_revFG, field) 291 292 /* 293 * Access a field as defined for family 0x10 revisions A and 294 */ 295 #define MCREG_FIELD_10_revAB(up, field) _MCREG_FIELD(up, 10_revAB, field) 296 297 /* 298 * We will only define the register bitfields for little-endian order 299 */ 300 #ifdef _BIT_FIELDS_LTOH 301 302 /* 303 * Function 0 - HT Configuration: Routing Table Node Register 304 */ 305 union mcreg_htroute { 306 uint32_t _val32; 307 struct { 308 uint32_t RQRte:4; /* 3:0 */ 309 uint32_t reserved1:4; /* 7:4 */ 310 uint32_t RPRte:4; /* 11:8 */ 311 uint32_t reserved2:4; /* 15:12 */ 312 uint32_t BCRte:4; /* 19:16 */ 313 uint32_t reserved3:12; /* 31:20 */ 314 } _fmt_cmn; 315 }; 316 317 /* 318 * Function 0 - HT Configuration: Node ID Register 319 */ 320 union mcreg_nodeid { 321 uint32_t _val32; 322 struct { 323 uint32_t NodeId:3; /* 2:0 */ 324 uint32_t reserved1:1; /* 3:3 */ 325 uint32_t NodeCnt:3; /* 6:4 */ 326 uint32_t reserved2:1; /* 7:7 */ 327 uint32_t SbNode:3; /* 10:8 */ 328 uint32_t reserved3:1; /* 11:11 */ 329 uint32_t LkNode:3; /* 14:12 */ 330 uint32_t reserved4:1; /* 15:15 */ 331 uint32_t CpuCnt:4; /* 19:16 */ 332 uint32_t reserved:12; /* 31:20 */ 333 } _fmt_cmn; 334 }; 335 336 #define HT_COHERENTNODES(up) (MCREG_FIELD_CMN(up, NodeCnt) + 1) 337 #define HT_SYSTEMCORECOUNT(up) (MCREG_FIELD_CMN(up, CpuCnt) + 1) 338 339 /* 340 * Function 0 - HT Configuration: Unit ID Register 341 */ 342 union mcreg_unitid { 343 uint32_t _val32; 344 struct { 345 uint32_t C0Unit:2; /* 1:0 */ 346 uint32_t C1Unit:2; /* 3:2 */ 347 uint32_t McUnit:2; /* 5:4 */ 348 uint32_t HbUnit:2; /* 7:6 */ 349 uint32_t SbLink:2; /* 9:8 */ 350 uint32_t reserved:22; /* 31:10 */ 351 } _fmt_cmn; 352 }; 353 354 /* 355 * Function 1 - DRAM Address Map: DRAM Base i Registers 356 * 357 */ 358 359 union mcreg_drambase { 360 uint32_t _val32; 361 struct { 362 uint32_t RE:1; /* 0:0 - Read Enable */ 363 uint32_t WE:1; /* 1:1 - Write Enable */ 364 uint32_t reserved1:6; /* 7:2 */ 365 uint32_t IntlvEn:3; /* 10:8 - Interleave Enable */ 366 uint32_t reserved2:5; /* 15:11 */ 367 uint32_t DRAMBasei:16; /* 31:16 - Base Addr 39:24 */ 368 } _fmt_cmn; 369 }; 370 371 #define MC_DRAMBASE(up) ((uint64_t)MCREG_FIELD_CMN(up, DRAMBasei) << 24) 372 373 /* 374 * Function 1 - DRAM Address Map: DRAM Limit i Registers 375 * 376 */ 377 378 union mcreg_dramlimit { 379 uint32_t _val32; 380 struct { 381 uint32_t DstNode:3; /* 2:0 - Destination Node */ 382 uint32_t reserved1:5; /* 7:3 */ 383 uint32_t IntlvSel:3; /* 10:8 - Interleave Select */ 384 uint32_t reserved2:5; /* 15:11 */ 385 uint32_t DRAMLimiti:16; /* 31:16 - Limit Addr 39:24 */ 386 } _fmt_cmn; 387 }; 388 389 #define MC_DRAMLIM(up) \ 390 ((uint64_t)MCREG_FIELD_CMN(up, DRAMLimiti) << 24 | \ 391 (MCREG_FIELD_CMN(up, DRAMLimiti) ? ((1 << 24) - 1) : 0)) 392 393 /* 394 * Function 1 - DRAM Address Map: DRAM Hole Address Register 395 */ 396 397 union mcreg_dramhole { 398 uint32_t _val32; 399 struct { 400 uint32_t DramHoleValid:1; /* 0:0 */ 401 uint32_t reserved1:7; /* 7:1 */ 402 uint32_t DramHoleOffset:8; /* 15:8 */ 403 uint32_t reserved2:8; /* 23:16 */ 404 uint32_t DramHoleBase:8; /* 31:24 */ 405 } _fmt_cmn; 406 }; 407 408 #define MC_DRAMHOLE_SIZE(up) (MCREG_FIELD_CMN(up, DramHoleOffset) << 24) 409 410 /* 411 * Function 2 - DRAM Controller: DRAM CS Base Address Registers 412 */ 413 414 union mcreg_csbase { 415 uint32_t _val32; 416 /* 417 * Register format in family 0xf revisions E and earlier 418 */ 419 struct { 420 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */ 421 uint32_t reserved1:8; /* 8:1 */ 422 uint32_t BaseAddrLo:7; /* 15:9 - Base Addr 19:13 */ 423 uint32_t reserved2:5; /* 20:16 */ 424 uint32_t BaseAddrHi:11; /* 31:21 - Base Addr 35:25 */ 425 } _fmt_f_preF; 426 /* 427 * Register format in family 0xf revisions F and G 428 */ 429 struct { 430 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */ 431 uint32_t Spare:1; /* 1:1 - Spare Rank */ 432 uint32_t TestFail:1; /* 2:2 - Memory Test Failed */ 433 uint32_t reserved1:2; /* 4:3 */ 434 uint32_t BaseAddrLo:9; /* 13:5 - Base Addr 21:13 */ 435 uint32_t reserved2:5; /* 18:14 */ 436 uint32_t BaseAddrHi:10; /* 28:19 - Base Addr 36:27 */ 437 uint32_t reserved3:3; /* 31:39 */ 438 } _fmt_f_revFG; 439 }; 440 441 #define MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? \ 442 (uint64_t)MCREG_FIELD_F_revFG(up, BaseAddrHi) << 27 | \ 443 (uint64_t)MCREG_FIELD_F_revFG(up, BaseAddrLo) << 13 : \ 444 (uint64_t)MCREG_FIELD_F_preF(up, BaseAddrHi) << 25 | \ 445 (uint64_t)MCREG_FIELD_F_preF(up, BaseAddrLo) << 13) 446 447 /* 448 * Function 2 - DRAM Controller: DRAM CS Mask Registers 449 */ 450 451 union mcreg_csmask { 452 uint32_t _val32; 453 /* 454 * Register format in family 0xf revisions E and earlier 455 */ 456 struct { 457 uint32_t reserved1:9; /* 8:0 */ 458 uint32_t AddrMaskLo:7; /* 15:9 - Addr Mask 19:13 */ 459 uint32_t reserved2:5; /* 20:16 */ 460 uint32_t AddrMaskHi:9; /* 29:21 - Addr Mask 33:25 */ 461 uint32_t reserved3:2; /* 31:30 */ 462 } _fmt_f_preF; 463 /* 464 * Register format in family 0xf revisions F and G 465 */ 466 struct { 467 uint32_t reserved1:5; /* 4:0 */ 468 uint32_t AddrMaskLo:9; /* 13:5 - Addr Mask 21:13 */ 469 uint32_t reserved2:5; /* 18:14 */ 470 uint32_t AddrMaskHi:10; /* 28:19 - Addr Mask 36:27 */ 471 uint32_t reserved3:3; /* 31:29 */ 472 } _fmt_f_revFG; 473 }; 474 475 #define MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 13 : 13) 476 #define MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 21 : 19) 477 478 #define MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 27 : 25) 479 #define MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 36 : 33) 480 481 #define MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 0 : 2) 482 483 #define MC_CSMASK(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? \ 484 (uint64_t)MCREG_FIELD_F_revFG(up, AddrMaskHi) << 27 | \ 485 (uint64_t)MCREG_FIELD_F_revFG(up, AddrMaskLo) << 13 | 0x7c01fff : \ 486 (uint64_t)MCREG_FIELD_F_preF(up, AddrMaskHi) << 25 | \ 487 (uint64_t)MCREG_FIELD_F_preF(up, AddrMaskLo) << 13 | 0x1f01fff) 488 489 /* 490 * Function 2 - DRAM Controller: DRAM Bank Address Mapping Registers 491 */ 492 493 union mcreg_bankaddrmap { 494 uint32_t _val32; 495 /* 496 * Register format in family 0xf revisions E and earlier 497 */ 498 struct { 499 uint32_t cs10:4; /* 3:0 - CS1/0 */ 500 uint32_t cs32:4; /* 7:4 - CS3/2 */ 501 uint32_t cs54:4; /* 11:8 - CS5/4 */ 502 uint32_t cs76:4; /* 15:12 - CS7/6 */ 503 uint32_t reserved1:14; /* 29:16 */ 504 uint32_t BankSwizzleMode:1; /* 30:30 */ 505 uint32_t reserved2:1; /* 31:31 */ 506 } _fmt_f_preF; 507 /* 508 * Register format in family 0xf revisions F and G 509 */ 510 struct { 511 uint32_t cs10:4; /* 3:0 - CS1/0 */ 512 uint32_t cs32:4; /* 7:4 - CS3/2 */ 513 uint32_t cs54:4; /* 11:8 - CS5/4 */ 514 uint32_t cs76:4; /* 15:12 - CS7/6 */ 515 uint32_t reserved1:16; /* 31:16 */ 516 } _fmt_f_revFG; 517 /* 518 * Accessing all mode encodings as one uint16 519 */ 520 struct { 521 uint32_t allcsmodes:16; /* 15:0 */ 522 uint32_t pad:16; /* 31:16 */ 523 } _fmt_bankmodes; 524 }; 525 526 #define MC_DC_BAM_CSBANK_MASK 0x0000000f 527 #define MC_DC_BAM_CSBANK_SHIFT 4 528 529 #define MC_CSBANKMODE(up, csnum) ((up)->_fmt_bankmodes.allcsmodes >> \ 530 MC_DC_BAM_CSBANK_SHIFT * MC_CHIP_DIMMPAIR(csnum) & MC_DC_BAM_CSBANK_MASK) 531 532 /* 533 * Function 2 - DRAM Controller: DRAM Configuration Low and High 534 */ 535 536 union mcreg_dramcfg_lo { 537 uint32_t _val32; 538 /* 539 * Register format in family 0xf revisions E and earlier. 540 * Bit 7 is a BIOS ScratchBit in revs D and earlier, 541 * PwrDwnTriEn in revision E; we don't use it so 542 * we'll call it ambig1. 543 */ 544 struct { 545 uint32_t DLL_Dis:1; /* 0 */ 546 uint32_t D_DRV:1; /* 1 */ 547 uint32_t QFC_EN:1; /* 2 */ 548 uint32_t DisDqsHys:1; /* 3 */ 549 uint32_t reserved1:1; /* 4 */ 550 uint32_t Burst2Opt:1; /* 5 */ 551 uint32_t Mod64BitMux:1; /* 6 */ 552 uint32_t ambig1:1; /* 7 */ 553 uint32_t DramInit:1; /* 8 */ 554 uint32_t DualDimmEn:1; /* 9 */ 555 uint32_t DramEnable:1; /* 10 */ 556 uint32_t MemClrStatus:1; /* 11 */ 557 uint32_t ESR:1; /* 12 */ 558 uint32_t SR_S:1; /* 13 */ 559 uint32_t RdWrQByp:2; /* 15:14 */ 560 uint32_t Width128:1; /* 16 */ 561 uint32_t DimmEcEn:1; /* 17 */ 562 uint32_t UnBufDimm:1; /* 18 */ 563 uint32_t ByteEn32:1; /* 19 */ 564 uint32_t x4DIMMs:4; /* 23:20 */ 565 uint32_t DisInRcvrs:1; /* 24 */ 566 uint32_t BypMax:3; /* 27:25 */ 567 uint32_t En2T:1; /* 28 */ 568 uint32_t UpperCSMap:1; /* 29 */ 569 uint32_t PwrDownCtl:2; /* 31:30 */ 570 } _fmt_f_preF; 571 /* 572 * Register format in family 0xf revisions F and G 573 */ 574 struct { 575 uint32_t InitDram:1; /* 0 */ 576 uint32_t ExitSelfRef:1; /* 1 */ 577 uint32_t reserved1:2; /* 3:2 */ 578 uint32_t DramTerm:2; /* 5:4 */ 579 uint32_t reserved2:1; /* 6 */ 580 uint32_t DramDrvWeak:1; /* 7 */ 581 uint32_t ParEn:1; /* 8 */ 582 uint32_t SelRefRateEn:1; /* 9 */ 583 uint32_t BurstLength32:1; /* 10 */ 584 uint32_t Width128:1; /* 11 */ 585 uint32_t x4DIMMs:4; /* 15:12 */ 586 uint32_t UnBuffDimm:1; /* 16 */ 587 uint32_t reserved3:2; /* 18:17 */ 588 uint32_t DimmEccEn:1; /* 19 */ 589 uint32_t reserved4:12; /* 31:20 */ 590 } _fmt_f_revFG; 591 }; 592 593 /* 594 * Function 2 - DRAM Controller: DRAM Controller Miscellaneous Data 595 */ 596 597 union mcreg_drammisc { 598 uint32_t _val32; 599 /* 600 * Register format in family 0xf revisions F and G 601 */ 602 struct { 603 uint32_t reserved2:1; /* 0 */ 604 uint32_t DisableJitter:1; /* 1 */ 605 uint32_t RdWrQByp:2; /* 3:2 */ 606 uint32_t Mod64Mux:1; /* 4 */ 607 uint32_t DCC_EN:1; /* 5 */ 608 uint32_t ILD_lmt:3; /* 8:6 */ 609 uint32_t DramEnabled:1; /* 9 */ 610 uint32_t PwrSavingsEn:1; /* 10 */ 611 uint32_t reserved1:13; /* 23:11 */ 612 uint32_t MemClkDis:8; /* 31:24 */ 613 } _fmt_f_revFG; 614 }; 615 616 union mcreg_dramcfg_hi { 617 uint32_t _val32; 618 /* 619 * Register format in family 0xf revisions E and earlier. 620 */ 621 struct { 622 uint32_t AsyncLat:4; /* 3:0 */ 623 uint32_t reserved1:4; /* 7:4 */ 624 uint32_t RdPreamble:4; /* 11:8 */ 625 uint32_t reserved2:1; /* 12 */ 626 uint32_t MemDQDrvStren:2; /* 14:13 */ 627 uint32_t DisableJitter:1; /* 15 */ 628 uint32_t ILD_lmt:3; /* 18:16 */ 629 uint32_t DCC_EN:1; /* 19 */ 630 uint32_t MemClk:3; /* 22:20 */ 631 uint32_t reserved3:2; /* 24:23 */ 632 uint32_t MCR:1; /* 25 */ 633 uint32_t MC0_EN:1; /* 26 */ 634 uint32_t MC1_EN:1; /* 27 */ 635 uint32_t MC2_EN:1; /* 28 */ 636 uint32_t MC3_EN:1; /* 29 */ 637 uint32_t reserved4:1; /* 30 */ 638 uint32_t OddDivisorCorrect:1; /* 31 */ 639 } _fmt_f_preF; 640 /* 641 * Register format in family 0xf revisions F and G 642 */ 643 struct { 644 uint32_t MemClkFreq:3; /* 2:0 */ 645 uint32_t MemClkFreqVal:1; /* 3 */ 646 uint32_t MaxAsyncLat:4; /* 7:4 */ 647 uint32_t reserved1:4; /* 11:8 */ 648 uint32_t RDqsEn:1; /* 12 */ 649 uint32_t reserved2:1; /* 13 */ 650 uint32_t DisDramInterface:1; /* 14 */ 651 uint32_t PowerDownEn:1; /* 15 */ 652 uint32_t PowerDownMode:1; /* 16 */ 653 uint32_t FourRankSODimm:1; /* 17 */ 654 uint32_t FourRankRDimm:1; /* 18 */ 655 uint32_t reserved3:1; /* 19 */ 656 uint32_t SlowAccessMode:1; /* 20 */ 657 uint32_t reserved4:1; /* 21 */ 658 uint32_t BankSwizzleMode:1; /* 22 */ 659 uint32_t undocumented1:1; /* 23 */ 660 uint32_t DcqBypassMax:4; /* 27:24 */ 661 uint32_t FourActWindow:4; /* 31:28 */ 662 } _fmt_f_revFG; 663 }; 664 665 /* 666 * Function 3 - Miscellaneous Control: Scrub Control Register 667 */ 668 669 union mcreg_scrubctl { 670 uint32_t _val32; 671 struct { 672 uint32_t DramScrub:5; /* 4:0 */ 673 uint32_t reserved3:3; /* 7:5 */ 674 uint32_t L2Scrub:5; /* 12:8 */ 675 uint32_t reserved2:3; /* 15:13 */ 676 uint32_t DcacheScrub:5; /* 20:16 */ 677 uint32_t reserved1:11; /* 31:21 */ 678 } _fmt_cmn; 679 }; 680 681 union mcreg_dramscrublo { 682 uint32_t _val32; 683 struct { 684 uint32_t ScrubReDirEn:1; /* 0 */ 685 uint32_t reserved:5; /* 5:1 */ 686 uint32_t ScrubAddrLo:26; /* 31:6 */ 687 } _fmt_cmn; 688 }; 689 690 union mcreg_dramscrubhi { 691 uint32_t _val32; 692 struct { 693 uint32_t ScrubAddrHi:8; /* 7:0 */ 694 uint32_t reserved:24; /* 31:8 */ 695 } _fmt_cmn; 696 }; 697 698 /* 699 * Function 3 - Miscellaneous Control: On-Line Spare Control Register 700 */ 701 702 union mcreg_nbcfg { 703 uint32_t _val32; 704 /* 705 * Register format in family 0xf revisions E and earlier. 706 */ 707 struct { 708 uint32_t CpuEccErrEn:1; /* 0 */ 709 uint32_t CpuRdDatErrEn:1; /* 1 */ 710 uint32_t SyncOnUcEccEn:1; /* 2 */ 711 uint32_t SyncPktGenDis:1; /* 3 */ 712 uint32_t SyncPktPropDis:1; /* 4 */ 713 uint32_t IoMstAbortDis:1; /* 5 */ 714 uint32_t CpuErrDis:1; /* 6 */ 715 uint32_t IoErrDis:1; /* 7 */ 716 uint32_t WdogTmrDis:1; /* 8 */ 717 uint32_t WdogTmrCntSel:3; /* 11:9 */ 718 uint32_t WdogTmrBaseSel:2; /* 13:12 */ 719 uint32_t LdtLinkSel:2; /* 15:14 */ 720 uint32_t GenCrcErrByte0:1; /* 16 */ 721 uint32_t GenCrcErrByte1:1; /* 17 */ 722 uint32_t reserved1:2; /* 19:18 */ 723 uint32_t SyncOnWdogEn:1; /* 20 */ 724 uint32_t SyncOnAnyErrEn:1; /* 21 */ 725 uint32_t EccEn:1; /* 22 */ 726 uint32_t ChipKillEccEn:1; /* 23 */ 727 uint32_t IoRdDatErrEn:1; /* 24 */ 728 uint32_t DisPciCfgCpuErrRsp:1; /* 25 */ 729 uint32_t reserved2:1; /* 26 */ 730 uint32_t NbMcaToMstCpuEn:1; /* 27 */ 731 uint32_t reserved3:4; /* 31:28 */ 732 } _fmt_f_preF; 733 /* 734 * Register format in family 0xf revisions F and G 735 */ 736 struct { 737 uint32_t CpuEccErrEn:1; /* 0 */ 738 uint32_t CpuRdDatErrEn:1; /* 1 */ 739 uint32_t SyncOnUcEccEn:1; /* 2 */ 740 uint32_t SyncPktGenDis:1; /* 3 */ 741 uint32_t SyncPktPropDis:1; /* 4 */ 742 uint32_t IoMstAbortDis:1; /* 5 */ 743 uint32_t CpuErrDis:1; /* 6 */ 744 uint32_t IoErrDis:1; /* 7 */ 745 uint32_t WdogTmrDis:1; /* 8 */ 746 uint32_t WdogTmrCntSel:3; /* 11:9 */ 747 uint32_t WdogTmrBaseSel:2; /* 13:12 */ 748 uint32_t LdtLinkSel:2; /* 15:14 */ 749 uint32_t GenCrcErrByte0:1; /* 16 */ 750 uint32_t GenCrcErrByte1:1; /* 17 */ 751 uint32_t reserved1:2; /* 19:18 */ 752 uint32_t SyncOnWdogEn:1; /* 20 */ 753 uint32_t SyncOnAnyErrEn:1; /* 21 */ 754 uint32_t EccEn:1; /* 22 */ 755 uint32_t ChipKillEccEn:1; /* 23 */ 756 uint32_t IoRdDatErrEn:1; /* 24 */ 757 uint32_t DisPciCfgCpuErrRsp:1; /* 25 */ 758 uint32_t reserved2:1; /* 26 */ 759 uint32_t NbMcaToMstCpuEn:1; /* 27 */ 760 uint32_t DisTgtAbtCpuErrRsp:1; /* 28 */ 761 uint32_t DisMstAbtCpuErrRsp:1; /* 29 */ 762 uint32_t SyncOnDramAdrParErrEn:1; /* 30 */ 763 uint32_t reserved3:1; /* 31 */ 764 765 } _fmt_f_revFG; 766 }; 767 768 /* 769 * Function 3 - Miscellaneous Control: On-Line Spare Control Register 770 */ 771 772 union mcreg_sparectl { 773 uint32_t _val32; 774 /* 775 * Register format in family 0xf revisions F and G 776 */ 777 struct { 778 uint32_t SwapEn:1; /* 0 */ 779 uint32_t SwapDone:1; /* 1 */ 780 uint32_t reserved1:2; /* 3:2 */ 781 uint32_t BadDramCs:3; /* 6:4 */ 782 uint32_t reserved2:5; /* 11:7 */ 783 uint32_t SwapDoneInt:2; /* 13:12 */ 784 uint32_t EccErrInt:2; /* 15:14 */ 785 uint32_t EccErrCntDramCs:3; /* 18:16 */ 786 uint32_t reserved3:1; /* 19 */ 787 uint32_t EccErrCntDramChan:1; /* 20 */ 788 uint32_t reserved4:2; /* 22:21 */ 789 uint32_t EccErrCntWrEn:1; /* 23 */ 790 uint32_t EccErrCnt:4; /* 27:24 */ 791 uint32_t reserved5:4; /* 31:28 */ 792 } _fmt_f_revFG; 793 /* 794 * Regiser format in family 0x10 revisions A and B 795 */ 796 struct { 797 uint32_t SwapEn0:1; /* 0 */ 798 uint32_t SwapDone0:1; /* 1 */ 799 uint32_t SwapEn1:1; /* 2 */ 800 uint32_t SwapDone1:1; /* 3 */ 801 uint32_t BadDramCs0:3; /* 6:4 */ 802 uint32_t reserved1:1; /* 7 */ 803 uint32_t BadDramCs1:3; /* 10:8 */ 804 uint32_t reserved2:1; /* 11 */ 805 uint32_t SwapDoneInt:2; /* 13:12 */ 806 uint32_t EccErrInt:2; /* 15:14 */ 807 uint32_t EccErrCntDramCs:4; /* 19:16 */ 808 uint32_t EccErrCntDramChan:2; /* 21:20 */ 809 uint32_t reserved4:1; /* 22 */ 810 uint32_t EccErrCntWrEn:1; /* 23 */ 811 uint32_t EccErrCnt:4; /* 27:24 */ 812 uint32_t LvtOffset:4; /* 31:28 */ 813 } _fmt_10_revAB; 814 }; 815 816 /* 817 * Since the NB is on-chip some registers are also accessible as MSRs. 818 * We will represent such registers as bitfields as in the 32-bit PCI 819 * registers above, with the restriction that we must compile for 32-bit 820 * kernels and so 64-bit bitfields cannot be used. 821 */ 822 823 #define _MCMSR_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field) 824 825 #define MCMSR_VAL(up) ((up)->_val64) 826 827 #define MCMSR_FIELD_CMN(up, field) _MCMSR_FIELD(up, cmn, field) 828 #define MCMSR_FIELD_F_preF(up, field) _MCMSR_FIELD(up, f_preF, field) 829 #define MCMSR_FIELD_F_revFG(up, field) _MCMSR_FIELD(up, f_revFG, field) 830 #define MCMSR_FIELD_10_revAB(up, field) _MCMSR_FIELD(up, 10_revAB, field) 831 832 /* 833 * The NB MISC registers. On family 0xf rev F this was introduced with 834 * a 12-bit ECC error count of all ECC errors observed on this memory- 835 * controller (regardless of channel or chip-select) and the ability to 836 * raise an interrupt or SMI on overflow. In family 0x10 it has a similar 837 * purpose, but the register is is split into 4 misc registers 838 * MC4_MISC{0,1,2,3} accessible via both MSRs and PCI config space; 839 * they perform thresholding for dram, l3, HT errors. 840 */ 841 842 union mcmsr_nbmisc { 843 uint64_t _val64; 844 /* 845 * MSR format in family 0xf revision F and later 846 */ 847 struct { 848 /* 849 * Lower 32 bits 850 */ 851 struct { 852 uint32_t _reserved; /* 31:0 */ 853 } _mcimisc_lo; 854 /* 855 * Upper 32 bits 856 */ 857 struct { 858 uint32_t _ErrCount:12; /* 43:32 */ 859 uint32_t _reserved1:4; /* 47:44 */ 860 uint32_t _Ovrflw:1; /* 48 */ 861 uint32_t _IntType:2; /* 50:49 */ 862 uint32_t _CntEn:1; /* 51 */ 863 uint32_t _LvtOff:4; /* 55:52 */ 864 uint32_t _reserved2:5; /* 60:56 */ 865 uint32_t _Locked:1; /* 61 */ 866 uint32_t _CntP:1; /* 62 */ 867 uint32_t _Valid:1; /* 63 */ 868 } _mcimisc_hi; 869 } _fmt_f_revFG; 870 /* 871 * MSR format in family 0x10 revisions A and B 872 */ 873 struct { 874 /* 875 * Lower 32 bits 876 */ 877 struct { 878 uint32_t _reserved:24; /* 23:0 */ 879 uint32_t _BlkPtr:8; /* 31:24 */ 880 } _mcimisc_lo; 881 /* 882 * Upper 32 bits 883 */ 884 struct { 885 uint32_t _ErrCnt:12; /* 43:32 */ 886 uint32_t _reserved1:4; /* 47:44 */ 887 uint32_t _Ovrflw:1; /* 48 */ 888 uint32_t _IntType:2; /* 50:49 */ 889 uint32_t _CntEn:1; /* 51 */ 890 uint32_t _LvtOff:4; /* 55:52 */ 891 uint32_t _reserved2:5; /* 60:56 */ 892 uint32_t _Locked:1; /* 61 */ 893 uint32_t _CntP:1; /* 62 */ 894 uint32_t _Valid:1; /* 63 */ 895 896 } _mcimisc_hi; 897 } _fmt_10_revAB; 898 }; 899 900 #define mcmisc_BlkPtr _mcimisc_lo._BlkPtr 901 #define mcmisc_ErrCount _mcimisc_hi._ErrCount 902 #define mcmisc_Ovrflw _mcimisc_hi._Ovrflw 903 #define mcmisc_IntType _mcimisc_hi._IntType 904 #define mcmisc_CntEn _mcimisc_hi._CntEn 905 #define mcmisc_LvtOff _mcimisc_hi._LvtOff 906 #define mcmisc_Locked _mcimisc_hi._Locked 907 #define mcmisc_CntP _mcimisc_hi._CntP 908 #define mcmisc_Valid _mcimisc_hi._Valid 909 910 #endif /* _BIT_FIELDS_LTOH */ 911 912 #ifdef __cplusplus 913 } 914 #endif 915 916 #endif /* _MC_AMD_H */ 917