1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * x86-specific routines used by the CPU Performance counter driver. 28 */ 29 30 #include <sys/types.h> 31 #include <sys/time.h> 32 #include <sys/atomic.h> 33 #include <sys/regset.h> 34 #include <sys/privregs.h> 35 #include <sys/x86_archext.h> 36 #include <sys/cpuvar.h> 37 #include <sys/machcpuvar.h> 38 #include <sys/archsystm.h> 39 #include <sys/cpc_pcbe.h> 40 #include <sys/cpc_impl.h> 41 #include <sys/x_call.h> 42 #include <sys/cmn_err.h> 43 #include <sys/cmt.h> 44 #include <sys/spl.h> 45 #include <sys/apic.h> 46 47 static const uint64_t allstopped = 0; 48 static kcpc_ctx_t *(*overflow_intr_handler)(caddr_t); 49 50 /* Do threads share performance monitoring hardware? */ 51 static int strands_perfmon_shared = 0; 52 53 int kcpc_hw_overflow_intr_installed; /* set by APIC code */ 54 extern kcpc_ctx_t *kcpc_overflow_intr(caddr_t arg, uint64_t bitmap); 55 56 extern int kcpc_counts_include_idle; /* Project Private /etc/system variable */ 57 58 void (*kcpc_hw_enable_cpc_intr)(void); /* set by APIC code */ 59 60 int 61 kcpc_hw_add_ovf_intr(kcpc_ctx_t *(*handler)(caddr_t)) 62 { 63 if (x86_type != X86_TYPE_P6) 64 return (0); 65 overflow_intr_handler = handler; 66 return (ipltospl(APIC_PCINT_IPL)); 67 } 68 69 void 70 kcpc_hw_rem_ovf_intr(void) 71 { 72 overflow_intr_handler = NULL; 73 } 74 75 /* 76 * Hook used on P4 systems to catch online/offline events. 77 */ 78 /*ARGSUSED*/ 79 static int 80 kcpc_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 81 { 82 pg_cmt_t *chip_pg; 83 int active_cpus_cnt; 84 85 if (what != CPU_ON) 86 return (0); 87 88 /* 89 * If any CPU-bound contexts exist, we don't need to invalidate 90 * anything, as no per-LWP contexts can coexist. 91 */ 92 if (kcpc_cpuctx) 93 return (0); 94 95 /* 96 * If this chip now has more than 1 active cpu, we must invalidate all 97 * contexts in the system. 98 */ 99 chip_pg = (pg_cmt_t *)pghw_find_pg(cpu[cpuid], PGHW_CHIP); 100 if (chip_pg != NULL) { 101 active_cpus_cnt = GROUP_SIZE(&chip_pg->cmt_cpus_actv); 102 if (active_cpus_cnt > 1) 103 kcpc_invalidate_all(); 104 } 105 106 return (0); 107 } 108 109 static kmutex_t cpu_setup_lock; /* protects setup_registered */ 110 static int setup_registered; 111 112 113 void 114 kcpc_hw_init(cpu_t *cp) 115 { 116 kthread_t *t = cp->cpu_idle_thread; 117 uint32_t versionid; 118 struct cpuid_regs cpuid; 119 120 strands_perfmon_shared = 0; 121 if (x86_feature & X86_HTT) { 122 if (cpuid_getvendor(cpu[0]) == X86_VENDOR_Intel) { 123 /* 124 * Intel processors that support Architectural 125 * Performance Monitoring Version 3 have per strand 126 * performance monitoring hardware. 127 * Hence we can allow use of performance counters on 128 * multiple strands on the same core simultaneously. 129 */ 130 cpuid.cp_eax = 0x0; 131 (void) __cpuid_insn(&cpuid); 132 if (cpuid.cp_eax < 0xa) { 133 strands_perfmon_shared = 1; 134 } else { 135 cpuid.cp_eax = 0xa; 136 (void) __cpuid_insn(&cpuid); 137 138 versionid = cpuid.cp_eax & 0xFF; 139 if (versionid < 3) { 140 strands_perfmon_shared = 1; 141 } 142 } 143 } else { 144 strands_perfmon_shared = 1; 145 } 146 } 147 148 if (strands_perfmon_shared) { 149 mutex_enter(&cpu_setup_lock); 150 if (setup_registered == 0) { 151 mutex_enter(&cpu_lock); 152 register_cpu_setup_func(kcpc_cpu_setup, NULL); 153 mutex_exit(&cpu_lock); 154 setup_registered = 1; 155 } 156 mutex_exit(&cpu_setup_lock); 157 } 158 159 mutex_init(&cp->cpu_cpc_ctxlock, "cpu_cpc_ctxlock", MUTEX_DEFAULT, 0); 160 161 if (kcpc_counts_include_idle) 162 return; 163 164 installctx(t, cp, kcpc_idle_save, kcpc_idle_restore, 165 NULL, NULL, NULL, NULL); 166 } 167 168 void 169 kcpc_hw_fini(cpu_t *cp) 170 { 171 ASSERT(cp->cpu_idle_thread == NULL); 172 173 mutex_destroy(&cp->cpu_cpc_ctxlock); 174 } 175 176 #define BITS(v, u, l) \ 177 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1)) 178 179 #define PCBE_NAMELEN 30 /* Enough Room for pcbe.manuf.model.family.stepping */ 180 181 /* 182 * Examine the processor and load an appropriate PCBE. 183 */ 184 int 185 kcpc_hw_load_pcbe(void) 186 { 187 return (kcpc_pcbe_tryload(cpuid_getvendorstr(CPU), cpuid_getfamily(CPU), 188 cpuid_getmodel(CPU), cpuid_getstep(CPU))); 189 } 190 191 static int 192 kcpc_remotestop_func(void) 193 { 194 ASSERT(CPU->cpu_cpc_ctx != NULL); 195 pcbe_ops->pcbe_allstop(); 196 atomic_or_uint(&CPU->cpu_cpc_ctx->kc_flags, KCPC_CTX_INVALID_STOPPED); 197 198 return (0); 199 } 200 201 /* 202 * Ensure the counters are stopped on the given processor. 203 * 204 * Callers must ensure kernel preemption is disabled. 205 */ 206 void 207 kcpc_remote_stop(cpu_t *cp) 208 { 209 cpuset_t set; 210 211 CPUSET_ZERO(set); 212 213 CPUSET_ADD(set, cp->cpu_id); 214 215 xc_sync(0, 0, 0, X_CALL_HIPRI, set, (xc_func_t)kcpc_remotestop_func); 216 } 217 218 /* 219 * Called by the generic framework to check if it's OK to bind a set to a CPU. 220 */ 221 int 222 kcpc_hw_cpu_hook(processorid_t cpuid, ulong_t *kcpc_cpumap) 223 { 224 cpu_t *cpu, *p; 225 pg_t *chip_pg; 226 pg_cpu_itr_t itr; 227 228 if (!strands_perfmon_shared) 229 return (0); 230 231 /* 232 * Only one logical CPU on each Pentium 4 HT CPU may be bound to at 233 * once. 234 * 235 * This loop is protected by holding cpu_lock, in order to properly 236 * access the cpu_t of the desired cpu. 237 */ 238 mutex_enter(&cpu_lock); 239 if ((cpu = cpu_get(cpuid)) == NULL) { 240 mutex_exit(&cpu_lock); 241 return (-1); 242 } 243 244 chip_pg = (pg_t *)pghw_find_pg(cpu, PGHW_CHIP); 245 246 PG_CPU_ITR_INIT(chip_pg, itr); 247 while ((p = pg_cpu_next(&itr)) != NULL) { 248 if (p == cpu) 249 continue; 250 if (BT_TEST(kcpc_cpumap, p->cpu_id)) { 251 mutex_exit(&cpu_lock); 252 return (-1); 253 } 254 } 255 256 mutex_exit(&cpu_lock); 257 return (0); 258 } 259 260 /* 261 * Called by the generic framework to check if it's OK to bind a set to an LWP. 262 */ 263 int 264 kcpc_hw_lwp_hook(void) 265 { 266 pg_cmt_t *chip; 267 group_t *chips; 268 group_iter_t i; 269 270 if (!strands_perfmon_shared) 271 return (0); 272 273 /* 274 * Only one CPU per chip may be online. 275 */ 276 mutex_enter(&cpu_lock); 277 278 chips = pghw_set_lookup(PGHW_CHIP); 279 if (chips == NULL) { 280 mutex_exit(&cpu_lock); 281 return (0); 282 } 283 284 group_iter_init(&i); 285 while ((chip = group_iterate(chips, &i)) != NULL) { 286 if (GROUP_SIZE(&chip->cmt_cpus_actv) > 1) { 287 mutex_exit(&cpu_lock); 288 return (-1); 289 } 290 } 291 292 mutex_exit(&cpu_lock); 293 return (0); 294 } 295 296 static int 297 kcpc_remoteprogram_func(void) 298 { 299 ASSERT(CPU->cpu_cpc_ctx != NULL); 300 301 pcbe_ops->pcbe_program(CPU->cpu_cpc_ctx); 302 303 return (0); 304 } 305 306 /* 307 * Ensure counters are enabled on the given processor. 308 */ 309 void 310 kcpc_remote_program(cpu_t *cp) 311 { 312 cpuset_t set; 313 314 CPUSET_ZERO(set); 315 316 CPUSET_ADD(set, cp->cpu_id); 317 318 xc_sync(0, 0, 0, X_CALL_HIPRI, set, (xc_func_t)kcpc_remoteprogram_func); 319 } 320