1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SATA_DEFS_H 28 #define _SATA_DEFS_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/scsi/generic/mode.h> 35 36 /* 37 * Common ATA commands (subset) 38 */ 39 #define SATAC_DIAG 0x90 /* diagnose command */ 40 #define SATAC_RECAL 0x10 /* restore cmd, 4 bits step rate */ 41 #define SATAC_FORMAT 0x50 /* format track command */ 42 #define SATAC_SET_FEATURES 0xef /* set features */ 43 #define SATAC_IDLE_IM 0xe1 /* idle immediate */ 44 #define SATAC_STANDBY_IM 0xe0 /* standby immediate */ 45 #define SATAC_DOOR_LOCK 0xde /* door lock */ 46 #define SATAC_DOOR_UNLOCK 0xdf /* door unlock */ 47 #define SATAC_IDLE 0xe3 /* idle */ 48 #define SATAC_STANDBY 0xe2 /* standby */ 49 50 /* 51 * ATA/ATAPI disk commands (subset) 52 */ 53 #define SATAC_DEVICE_RESET 0x08 /* ATAPI device reset */ 54 #define SATAC_DOWNLOAD_MICROCODE 0x92 /* Download microcode */ 55 #define SATAC_EJECT 0xed /* media eject */ 56 #define SATAC_FLUSH_CACHE 0xe7 /* flush write-cache */ 57 #define SATAC_ID_DEVICE 0xec /* IDENTIFY DEVICE */ 58 #define SATAC_ID_PACKET_DEVICE 0xa1 /* ATAPI identify packet device */ 59 #define SATAC_INIT_DEVPARMS 0x91 /* initialize device parameters */ 60 #define SATAC_PACKET 0xa0 /* ATAPI packet */ 61 #define SATAC_RDMULT 0xc4 /* read multiple w/DMA */ 62 #define SATAC_RDSEC 0x20 /* read sector */ 63 #define SATAC_RDVER 0x40 /* read verify */ 64 #define SATAC_READ_DMA 0xc8 /* read DMA */ 65 #define SATAC_SEEK 0x70 /* seek */ 66 #define SATAC_SERVICE 0xa2 /* queued/overlap service */ 67 #define SATAC_SETMULT 0xc6 /* set multiple mode */ 68 #define SATAC_WRITE_DMA 0xca /* write (multiple) w/DMA */ 69 #define SATAC_WRMULT 0xc5 /* write multiple */ 70 #define SATAC_WRSEC 0x30 /* write sector */ 71 #define SATAC_RDSEC_EXT 0x24 /* read sector extended (LBA48) */ 72 #define SATAC_READ_DMA_EXT 0x25 /* read DMA extended (LBA48) */ 73 #define SATAC_RDMULT_EXT 0x29 /* read multiple extended (LBA48) */ 74 #define SATAC_WRSEC_EXT 0x34 /* read sector extended (LBA48) */ 75 #define SATAC_WRITE_DMA_EXT 0x35 /* read DMA extended (LBA48) */ 76 #define SATAC_WRMULT_EXT 0x39 /* read multiple extended (LBA48) */ 77 78 #define SATAC_READ_DMA_QUEUED 0xc7 /* read DMA / may be queued */ 79 #define SATAC_READ_DMA_QUEUED_EXT 0x26 /* read DMA ext / may be queued */ 80 #define SATAC_WRITE_DMA_QUEUED 0xcc /* read DMA / may be queued */ 81 #define SATAC_WRITE_DMA_QUEUED_EXT 0x36 /* read DMA ext / may be queued */ 82 #define SATAC_READ_PM_REG 0xe4 /* read port mult reg */ 83 #define SATAC_WRITE_PM_REG 0xe8 /* write port mult reg */ 84 85 #define SATAC_READ_FPDMA_QUEUED 0x60 /* First-Party-DMA read queued */ 86 #define SATAC_WRITE_FPDMA_QUEUED 0x61 /* First-Party-DMA write queued */ 87 88 #define SATAC_READ_LOG_EXT 0x2f /* read log */ 89 90 #define SATAC_SMART 0xb0 /* SMART */ 91 92 #define SATA_LOG_PAGE_10 0x10 /* log page 0x10 - SATA error */ 93 /* 94 * Port Multiplier Commands 95 */ 96 #define SATAC_READ_PORTMULT 0xe4 /* read port multiplier */ 97 #define SATAC_WRITE_PORTMULT 0xe8 /* write port multiplier */ 98 99 /* 100 * Power Managment Commands (subset) 101 */ 102 #define SATAC_CHECK_POWER_MODE 0xe5 /* check power mode */ 103 104 #define SATA_PWRMODE_STANDBY 0 /* standby mode */ 105 #define SATA_PWRMODE_IDLE 0x80 /* idle mode */ 106 #define SATA_PWRMODE_ACTIVE_SPINDOWN 0x40 /* PM0 and spinning down */ 107 #define SATA_PWRMODE_ACTIVE_SPINUP 0x41 /* PM0 and spinning up */ 108 #define SATA_PWRMODE_ACTIVE 0xFF /* active or idle mode */ 109 110 111 /* 112 * SMART FEATURES Subcommands 113 */ 114 #define SATA_SMART_READ_DATA 0xd0 115 #define SATA_SMART_ATTR_AUTOSAVE 0xd2 116 #define SATA_SMART_EXECUTE_OFFLINE_IMM 0xd4 117 #define SATA_SMART_READ_LOG 0xd5 118 #define SATA_SMART_WRITE_LOG 0xd6 119 #define SATA_SMART_ENABLE_OPS 0xd8 120 #define SATA_SMART_DISABLE_OPS 0xd9 121 #define SATA_SMART_RETURN_STATUS 0xda 122 123 /* 124 * SET FEATURES Subcommands 125 */ 126 #define SATAC_SF_ENABLE_WRITE_CACHE 0x02 127 #define SATAC_SF_TRANSFER_MODE 0x03 128 #define SATAC_SF_DISABLE_RMSN 0x31 129 #define SATAC_SF_ENABLE_ACOUSTIC 0x42 130 #define SATAC_SF_DISABLE_READ_AHEAD 0x55 131 #define SATAC_SF_DISABLE_WRITE_CACHE 0x82 132 #define SATAC_SF_ENABLE_READ_AHEAD 0xaa 133 #define SATAC_SF_DISABLE_ACOUSTIC 0xc2 134 #define SATAC_SF_ENABLE_RMSN 0x95 135 136 /* 137 * SET FEATURES transfer mode values 138 */ 139 #define SATAC_TRANSFER_MODE_PIO_DEFAULT 0x00 140 #define SATAC_TRANSFER_MODE_PIO_DISABLE_IODRY 0x01 141 #define SATAC_TRANSFER_MODE_PIO_FLOW_CONTROL 0x08 142 #define SATAC_TRANSFER_MODE_MULTI_WORD_DMA 0x20 143 #define SATAC_TRANSFER_MODE_ULTRA_DMA 0x40 144 145 /* 146 * Download microcode subcommands 147 */ 148 #define SATA_DOWNLOAD_MCODE_TEMP 1 /* Revert on/ reset/pwr cycle */ 149 #define SATA_DOWNLOAD_MCODE_SAVE 7 /* No offset, keep mcode */ 150 151 152 /* Generic ATA definitions */ 153 154 #define SATA_TAG_QUEUING_SHIFT 3 155 #define SATA_TAG_QUEUING_MASK 0x1f 156 /* 157 * Identify Device data 158 * Although both ATA and ATAPI devices' Identify Data have the same length, 159 * some words have different meaning/content and/or are irrelevant for 160 * other type of device. 161 * Following is the ATA Device Identify data layout 162 */ 163 typedef struct sata_id { 164 /* WORD */ 165 /* OFFSET COMMENT */ 166 ushort_t ai_config; /* 0 general configuration bits */ 167 ushort_t ai_fixcyls; /* 1 # of cylinders (obsolete) */ 168 ushort_t ai_resv0; /* 2 # reserved */ 169 ushort_t ai_heads; /* 3 # of heads (obsolete) */ 170 ushort_t ai_trksiz; /* 4 # of bytes/track (retired) */ 171 ushort_t ai_secsiz; /* 5 # of bytes/sector (retired) */ 172 ushort_t ai_sectors; /* 6 # of sectors/track (obsolete) */ 173 ushort_t ai_resv1[3]; /* 7 "Vendor Unique" */ 174 char ai_drvser[20]; /* 10 Serial number */ 175 ushort_t ai_buftype; /* 20 Buffer type */ 176 ushort_t ai_bufsz; /* 21 Buffer size in 512 byte incr */ 177 ushort_t ai_ecc; /* 22 # of ecc bytes avail on rd/wr */ 178 char ai_fw[8]; /* 23 Firmware revision */ 179 char ai_model[40]; /* 27 Model # */ 180 ushort_t ai_mult1; /* 47 Multiple command flags */ 181 ushort_t ai_dwcap; /* 48 Doubleword capabilities */ 182 ushort_t ai_cap; /* 49 Capabilities */ 183 ushort_t ai_resv2; /* 50 Reserved */ 184 ushort_t ai_piomode; /* 51 PIO timing mode */ 185 ushort_t ai_dmamode; /* 52 DMA timing mode */ 186 ushort_t ai_validinfo; /* 53 bit0: wds 54-58, bit1: 64-70 */ 187 ushort_t ai_curcyls; /* 54 # of current cylinders */ 188 ushort_t ai_curheads; /* 55 # of current heads */ 189 ushort_t ai_cursectrk; /* 56 # of current sectors/track */ 190 ushort_t ai_cursccp[2]; /* 57 current sectors capacity */ 191 ushort_t ai_mult2; /* 59 multiple sectors info */ 192 ushort_t ai_addrsec[2]; /* 60 LBA only: no of addr secs */ 193 ushort_t ai_dirdma; /* 62 valid in ATA/ATAPI7, DMADIR */ 194 ushort_t ai_dworddma; /* 63 multi word dma modes */ 195 ushort_t ai_advpiomode; /* 64 advanced PIO modes supported */ 196 ushort_t ai_minmwdma; /* 65 min multi-word dma cycle info */ 197 ushort_t ai_recmwdma; /* 66 rec multi-word dma cycle info */ 198 ushort_t ai_minpio; /* 67 min PIO cycle info */ 199 ushort_t ai_minpioflow; /* 68 min PIO cycle info w/flow ctl */ 200 ushort_t ai_resv3[2]; /* 69,70 reserved */ 201 ushort_t ai_typtime[2]; /* 71-72 timing */ 202 ushort_t ai_resv4[2]; /* 73-74 reserved */ 203 ushort_t ai_qdepth; /* 75 queue depth */ 204 ushort_t ai_satacap; /* 76 SATA capabilities */ 205 ushort_t ai_resv5; /* 77 reserved */ 206 ushort_t ai_satafsup; /* 78 SATA features supported */ 207 ushort_t ai_satafenbl; /* 79 SATA features enabled */ 208 ushort_t ai_majorversion; /* 80 major versions supported */ 209 ushort_t ai_minorversion; /* 81 minor version number supported */ 210 ushort_t ai_cmdset82; /* 82 command set supported */ 211 ushort_t ai_cmdset83; /* 83 more command sets supported */ 212 ushort_t ai_cmdset84; /* 84 more command sets supported */ 213 ushort_t ai_features85; /* 85 enabled features */ 214 ushort_t ai_features86; /* 86 enabled features */ 215 ushort_t ai_features87; /* 87 enabled features */ 216 ushort_t ai_ultradma; /* 88 Ultra DMA mode */ 217 ushort_t ai_erasetime; /* 89 security erase time */ 218 ushort_t ai_erasetimex; /* 90 enhanced security erase time */ 219 ushort_t ai_adv_pwr_mgmt; /* 91 advanced power management time */ 220 ushort_t ai_master_pwd; /* 92 master password revision code */ 221 ushort_t ai_hrdwre_reset; /* 93 hardware reset result */ 222 ushort_t ai_acoustic; /* 94 accoustic management values */ 223 ushort_t ai_stream_min_sz; /* 95 stream minimum request size */ 224 ushort_t ai_stream_xfer_d; /* 96 streaming transfer time (DMA) */ 225 ushort_t ai_stream_lat; /* 97 streaming access latency */ 226 ushort_t ai_streamperf[2]; /* 98-99 streaming performance gran. */ 227 ushort_t ai_addrsecxt[4]; /* 100 extended max LBA sector */ 228 ushort_t ai_stream_xfer_p; /* 104 streaming transfer time (PIO) */ 229 ushort_t ai_padding1; /* 105 pad */ 230 ushort_t ai_phys_sect_sz; /* 106 physical sector size */ 231 ushort_t ai_seek_delay; /* 107 inter-seek delay time (usecs) */ 232 ushort_t ai_naa_ieee_oui; /* 108 NAA/IEEE OUI */ 233 ushort_t ai_ieee_oui_uid; /* 109 IEEE OUT/unique id */ 234 ushort_t ai_uid_mid; /* 110 unique id (mid) */ 235 ushort_t ai_uid_low; /* 111 unique id (low) */ 236 ushort_t ai_resv_wwn[4]; /* 112-115 reserved for WWN ext. */ 237 ushort_t ai_incits; /* 116 reserved for INCITS TR-37-2004 */ 238 ushort_t ai_words_lsec[2]; /* 117-118 words per logical sector */ 239 ushort_t ai_cmdset119; /* 119 more command sets supported */ 240 ushort_t ai_features120; /* 120 enabled features */ 241 ushort_t ai_padding2[6]; /* pad to 126 */ 242 ushort_t ai_rmsn; /* 127 removable media notification */ 243 ushort_t ai_securestatus; /* 128 security status */ 244 ushort_t ai_vendor[31]; /* 129-159 vendor specific */ 245 ushort_t ai_padding3[16]; /* 160 pad to 176 */ 246 ushort_t ai_curmedser[30]; /* 176-205 current media serial # */ 247 ushort_t ai_sctsupport; /* 206 SCT command transport */ 248 ushort_t ai_padding4[48]; /* 207 pad to 255 */ 249 ushort_t ai_integrity; /* 255 integrity word */ 250 } sata_id_t; 251 252 253 /* Identify Device: general config bits - word 0 */ 254 255 #define SATA_ATA_TYPE_MASK 0x8001 /* ATA Device type mask */ 256 #define SATA_ATA_TYPE 0x0000 /* ATA device */ 257 #define SATA_REM_MEDIA 0x0080 /* Removable media */ 258 #define SATA_INCOMPLETE_DATA 0x0004 /* Incomplete Identify Device data */ 259 #define SATA_CFA_TYPE 0x848a /* CFA feature set device */ 260 261 #define SATA_ID_SERIAL_OFFSET 10 262 #define SATA_ID_SERIAL_LEN 20 263 #define SATA_ID_MODEL_OFFSET 27 264 #define SATA_ID_MODEL_LEN 40 265 #define SATA_ID_FW_LEN 8 266 267 /* Identify Device: common capability bits - word 49 */ 268 269 #define SATA_DMA_SUPPORT 0x0100 270 #define SATA_LBA_SUPPORT 0x0200 271 #define SATA_IORDY_DISABLE 0x0400 272 #define SATA_IORDY_SUPPORT 0x0800 273 #define SATA_STANDBYTIMER 0x2000 274 275 /* Identify Device: ai_validinfo (word 53) */ 276 277 #define SATA_VALIDINFO_88 0x0004 /* word 88 supported fields valid */ 278 #define SATA_VALIDINFO_70_64 0x0004 /* words 70-64 fields valid */ 279 280 /* Identify Device: ai_majorversion (word 80) */ 281 282 #define SATA_MAJVER_7 0x0080 /* ATA/ATAPI-7 version supported */ 283 #define SATA_MAJVER_654 0x0070 /* ATA/ATAPI-6,5 or 4 ver supported */ 284 #define SATA_MAJVER_6 0x0040 /* ATA/ATAPI-6 version supported */ 285 #define SATA_MAJVER_5 0x0020 /* ATA/ATAPI-7 version supported */ 286 #define SATA_MAJVER_4 0x0010 /* ATA/ATAPI-4 version supported */ 287 288 /* Identify Device: command set supported/enabled bits - words 83 and 86 */ 289 290 #define SATA_EXT48 0x0400 /* 48 bit address feature */ 291 #define SATA_PWRUP_IN_STANDBY 0x0020 /* Power-up in standby mode supp/en */ 292 #define SATA_RM_STATUS_NOTIFIC 0x0010 /* Removable Media Stat Notification */ 293 #define SATA_RW_DMA_QUEUED_CMD 0x0002 /* R/W DMA Queued supported */ 294 #define SATA_DWNLOAD_MCODE_CMD 0x0001 /* Download Microcode CMD supp/enbld */ 295 #define SATA_ACOUSTIC_MGMT 0x0200 /* Acoustic Management features */ 296 297 /* Identify Device: command set supported/enabled bits - words 82 and 85 */ 298 299 #define SATA_SMART_SUPPORTED 0x0001 /* SMART feature set is supported */ 300 #define SATA_WRITE_CACHE 0x0020 /* Write Cache supported/enabled */ 301 #define SATA_LOOK_AHEAD 0x0040 /* Look Ahead supported/enabled */ 302 #define SATA_DEVICE_RESET_CMD 0x0200 /* Device Reset CMD supported/enbld */ 303 #define SATA_READ_BUFFER_CMD 0x2000 /* Read Buffer CMD supported/enbld */ 304 #define SATA_WRITE_BUFFER_CMD 0x1000 /* Write Buffer CMD supported/enbld */ 305 #define SATA_SMART_ENABLED 0x0001 /* SMART feature set is enabled */ 306 307 /* Identify Device: command set supported/enabled bits - words 84 & 87 */ 308 #define SATA_SMART_SELF_TEST_SUPPORTED 0x0002 /* SMART self-test supported */ 309 /* IDLE IMMEDIATE with UNLOAD FEATURE supported */ 310 #define SATA_IDLE_UNLOAD_SUPPORTED 0x2000 311 312 /* Identify (Packet) Device word 63, ATA/ATAPI-6 & 7 */ 313 #define SATA_MDMA_SEL_MASK 0x0700 /* Multiword DMA selected */ 314 #define SATA_MDMA_2_SEL 0x0400 /* Multiword DMA mode 2 selected */ 315 #define SATA_MDMA_1_SEL 0x0200 /* Multiword DMA mode 1 selected */ 316 #define SATA_MDMA_0_SEL 0x0100 /* Multiword DMA mode 0 selected */ 317 #define SATA_MDMA_2_SUP 0x0004 /* Multiword DMA mode 2 supported */ 318 #define SATA_MDMA_1_SUP 0x0002 /* Multiword DMA mode 1 supported */ 319 #define SATA_MDMA_0_SUP 0x0001 /* Multiword DMA mode 0 supported */ 320 #define SATA_MDMA_SUP_MASK 0x0007 /* Multiword DMA supported */ 321 322 /* Identify (Packet) Device Word 88 */ 323 #define SATA_UDMA_SUP_MASK 0x007f /* UDMA modes supported */ 324 #define SATA_UDMA_SEL_MASK 0x7f00 /* UDMA modes selected */ 325 326 /* Identify Device: command set supported/enabled bits - word 206 */ 327 328 /* All are SCT Command Transport support */ 329 #define SATA_SCT_CMD_TRANS_SUP 0x0001 /* anything */ 330 #define SATA_SCT_CMD_TRANS_LNG_SECT_SUP 0x0002 /* Long Sector Access */ 331 #define SATA_SCT_CMD_TRANS_WR_SAME_SUP 0x0004 /* Write Same */ 332 #define SATA_SCT_CMD_TRANS_ERR_RCOV_SUP 0x0008 /* Error Recovery Control */ 333 #define SATA_SCT_CMD_TRANS_FEAT_CTL_SUP 0x0010 /* Features Control */ 334 #define SATA_SCT_CMD_TRANS_DATA_TBL_SUP 0x0020 /* Data Tables supported */ 335 336 #define SATA_DISK_SECTOR_SIZE 512 /* HD physical sector size */ 337 338 /* Identify Packet Device data definitions (ATAPI devices) */ 339 340 /* Identify Packet Device: general config bits - word 0 */ 341 342 #define SATA_ATAPI_TYPE_MASK 0xc000 343 #define SATA_ATAPI_TYPE 0x8000 /* ATAPI device */ 344 #define SATA_ATAPI_ID_PKT_SZ 0x0003 /* Packet size mask */ 345 #define SATA_ATAPI_ID_PKT_12B 0x0000 /* Packet size 12 bytes */ 346 #define SATA_ATAPI_ID_PKT_16B 0x0001 /* Packet size 16 bytes */ 347 #define SATA_ATAPI_ID_DRQ_TYPE 0x0060 /* DRQ asserted in 3ms after pkt */ 348 #define SATA_ATAPI_ID_DRQ_INTR 0x0020 /* Obsolete in ATA/ATAPI 7 */ 349 350 #define SATA_ATAPI_ID_DEV_TYPE 0x0f00 /* device type/command set mask */ 351 #define SATA_ATAPI_ID_DEV_SHFT 8 352 #define SATA_ATAPI_DIRACC_DEV 0x0000 /* Direct Access device */ 353 #define SATA_ATAPI_SQACC_DEV 0x0100 /* Sequential access dev (tape ?) */ 354 #define SATA_ATAPI_CDROM_DEV 0x0500 /* CD_ROM device */ 355 356 /* 357 * Status bits from ATAPI Interrupt reason register (AT_COUNT) register 358 */ 359 #define SATA_ATAPI_I_COD 0x01 /* Command or Data */ 360 #define SATA_ATAPI_I_IO 0x02 /* IO direction */ 361 #define SATA_ATAPI_I_RELEASE 0x04 /* Release for ATAPI overlap */ 362 363 /* ATAPI feature reg definitions */ 364 365 #define SATA_ATAPI_F_DATA_DIR_READ 0x04 /* DMA transfer to the host */ 366 #define SATA_ATAPI_F_OVERLAP 0x02 /* Not used by Sun drivers */ 367 #define SATA_ATAPI_F_DMA 0x01 /* Packet DMA command */ 368 369 370 /* ATAPI IDENTIFY_DRIVE capabilities word (49) */ 371 372 #define SATA_ATAPI_ID_CAP_DMA 0x0100 /* if zero, check word 62 */ 373 #define SATA_ATAPI_ID_CAP_OVERLAP 0x2000 374 375 /* 376 * ATAPI Identify Packet Device word 62 377 * Word 62 is not valid for ATA/ATAPI-6 378 * Defs below are for ATA/ATAPI-7 379 */ 380 #define SATA_ATAPI_ID_DMADIR_REQ 0x8000 /* DMA direction required */ 381 #define SATA_ATAPI_ID_DMA_SUP 0x0400 /* DMA is supported */ 382 383 /* 384 * ATAPI signature bits 385 */ 386 #define SATA_ATAPI_SIG_HI 0xeb /* in high cylinder register */ 387 #define SATA_ATAPI_SIG_LO 0x14 /* in low cylinder register */ 388 389 /* These values are pre-set for CD_ROM/DVD ? */ 390 391 #define SATA_ATAPI_SECTOR_SIZE 2048 392 #define SATA_ATAPI_MAX_BYTES_PER_DRQ 0xf800 /* 16 bits - 2KB ie 62KB */ 393 #define SATA_ATAPI_HEADS 64 394 #define SATA_ATAPI_SECTORS_PER_TRK 32 395 396 /* SATA Capabilites bits (word 76) */ 397 398 #define SATA_NCQ 0x100 399 #define SATA_2_SPEED 0x004 400 #define SATA_1_SPEED 0x002 401 402 /* SATA Features Supported (word 78) - not used */ 403 404 /* SATA Features Enabled (word 79) - not used */ 405 406 #define SATA_READ_AHEAD_SUPPORTED(x) ((x).ai_cmdset82 & SATA_LOOK_AHEAD) 407 #define SATA_READ_AHEAD_ENABLED(x) ((x).ai_features85 & SATA_LOOK_AHEAD) 408 #define SATA_WRITE_CACHE_SUPPORTED(x) ((x).ai_cmdset82 & SATA_WRITE_CACHE) 409 #define SATA_WRITE_CACHE_ENABLED(x) ((x).ai_features85 & SATA_WRITE_CACHE) 410 #define SATA_RM_NOTIFIC_SUPPORTED(x) \ 411 ((x).ai_cmdset83 & SATA_RM_STATUS_NOTIFIC) 412 #define SATA_RM_NOTIFIC_ENABLED(x) \ 413 ((x).ai_features86 & SATA_RM_STATUS_NOTIFIC) 414 415 /* 416 * Generic NCQ related defines 417 */ 418 419 #define NQ 0x80 /* Not a queued cmd - tag not valid */ 420 #define NCQ_TAG_MASK 0x1f /* NCQ command tag mask */ 421 #define FIS_TYPE_REG_H2D 0x27 /* Reg FIS - Host to Device */ 422 #define FIS_CMD_UPDATE 0x80 423 /* 424 * Status bits from AT_STATUS register 425 */ 426 #define SATA_STATUS_BSY 0x80 /* controller busy */ 427 #define SATA_STATUS_DRDY 0x40 /* drive ready */ 428 #define SATA_STATUS_DF 0x20 /* device fault */ 429 #define SATA_STATUS_DSC 0x10 /* seek operation complete */ 430 #define SATA_STATUS_DRQ 0x08 /* data request */ 431 #define SATA_STATUS_CORR 0x04 /* obsolete */ 432 #define SATA_STATUS_IDX 0x02 /* obsolete */ 433 #define SATA_STATUS_ERR 0x01 /* error flag */ 434 435 /* 436 * Status bits from AT_ERROR register 437 */ 438 #define SATA_ERROR_ICRC 0x80 /* CRC data transfer error detected */ 439 #define SATA_ERROR_UNC 0x40 /* uncorrectable data error */ 440 #define SATA_ERROR_MC 0x20 /* Media change */ 441 #define SATA_ERROR_IDNF 0x10 /* ID/Address not found */ 442 #define SATA_ERROR_MCR 0x08 /* media change request */ 443 #define SATA_ERROR_ABORT 0x04 /* aborted command */ 444 #define SATA_ERROR_NM 0x02 /* no media */ 445 #define SATA_ERROR_EOM 0x02 /* end of media (Packet cmds) */ 446 #define SATA_ERROR_ILI 0x01 /* cmd sepcific */ 447 448 449 /* 450 * Bits from the device control register 451 */ 452 #define SATA_DEVCTL_NIEN 0x02 /* not interrupt enabled */ 453 #define SATA_DEVCTL_SRST 0x04 /* software reset */ 454 #define SATA_DEVCTL_HOB 0x80 /* high order bit */ 455 456 /* device_reg */ 457 #define SATA_ADH_LBA 0x40 /* addressing in LBA mode not chs */ 458 459 /* ATAPI transport version-in Inquiry data */ 460 #define SATA_ATAPI_TRANS_VERSION(inq) \ 461 (*((uint8_t *)(inq) + 3) >> 4) 462 463 #define SCSI_LOG_PAGE_HDR_LEN 4 /* # bytes of a SCSI log page header */ 464 #define SCSI_LOG_PARAM_HDR_LEN 4 /* # byttes of a SCSI log param hdr */ 465 466 /* Number of log entries per extended selftest log block */ 467 #define ENTRIES_PER_EXT_SELFTEST_LOG_BLK 19 468 469 /* Number of entries per SCSI LOG SENSE SELFTEST RESULTS page */ 470 #define SCSI_ENTRIES_IN_LOG_SENSE_SELFTEST_RESULTS 20 471 472 /* Length of a SCSI LOG SENSE SELFTEST RESULTS parameter */ 473 #define SCSI_LOG_SENSE_SELFTEST_PARAM_LEN 0x10 474 475 #define DIAGNOSTIC_FAILURE_ON_COMPONENT 0x40 476 477 #define SCSI_COMPONENT_81 0x81 478 #define SCSI_COMPONENT_82 0x82 479 #define SCSI_COMPONENT_83 0x83 480 #define SCSI_COMPONENT_84 0x84 481 #define SCSI_COMPONENT_85 0x85 482 #define SCSI_COMPONENT_86 0x86 483 #define SCSI_COMPONENT_87 0x87 484 #define SCSI_COMPONENT_88 0x88 485 486 #define SCSI_ASC_ATA_DEV_FEAT_NOT_ENABLED 0x67 487 #define SCSI_ASCQ_ATA_DEV_FEAT_NOT_ENABLED 0x0b 488 489 #define SCSI_PREDICTED_FAILURE 0x5d 490 #define SCSI_GENERAL_HD_FAILURE 0x10 491 492 #define SCSI_INFO_EXCEPTIONS_PARAM_LEN 4 493 494 #define READ_LOG_EXT_LOG_DIRECTORY 0 495 #define READ_LOG_EXT_NCQ_ERROR_RECOVERY 0x10 496 #define SMART_SELFTEST_LOG_PAGE 6 497 #define EXT_SMART_SELFTEST_LOG_PAGE 7 498 499 /* 500 * SATA NCQ error recovery page (0x10) 501 */ 502 struct sata_ncq_error_recovery_page { 503 uint8_t ncq_tag; 504 uint8_t reserved1; 505 uint8_t ncq_status; 506 uint8_t ncq_error; 507 uint8_t ncq_sector_number; 508 uint8_t ncq_cyl_low; 509 uint8_t ncq_cyl_high; 510 uint8_t ncq_dev_head; 511 uint8_t ncq_sector_number_ext; 512 uint8_t ncq_cyl_low_ext; 513 uint8_t ncq_cyl_high_ext; 514 uint8_t reserved2; 515 uint8_t ncq_sector_count; 516 uint8_t ncq_sector_count_ext; 517 uint8_t reserved3[242]; 518 uint8_t ncq_vendor_unique[255]; 519 uint8_t ncq_checksum; 520 }; 521 522 /* SMART attribute of Start/Stop Count */ 523 #define SMART_START_STOP_COUNT_ID 0x4 524 525 /* 526 * SMART data structures 527 */ 528 struct smart_data { 529 uint8_t smart_vendor_specific[362]; 530 uint8_t smart_offline_data_collection_status; 531 uint8_t smart_selftest_exec_status; 532 uint8_t smart_secs_to_complete_offline_data[2]; 533 uint8_t smart_vendor_specific2; 534 uint8_t smart_offline_data_collection_capability; 535 uint8_t smart_capability[2]; 536 uint8_t smart_error_logging_capability; 537 uint8_t smart_vendor_specific3; 538 uint8_t smart_short_selftest_polling_time; 539 uint8_t smart_extended_selftest_polling_time; 540 uint8_t smart_conveyance_selftest_polling_time; 541 uint8_t smart_reserved[11]; 542 uint8_t smart_vendor_specific4[125]; 543 uint8_t smart_checksum; 544 }; 545 546 struct smart_selftest_log_entry { 547 uint8_t smart_selftest_log_lba_low; 548 uint8_t smart_selftest_log_status; 549 uint8_t smart_selftest_log_timestamp[2]; 550 uint8_t smart_selftest_log_checkpoint; 551 uint8_t smart_selftest_log_failing_lba[4]; /* from LSB to MSB */ 552 uint8_t smart_selftest_log_vendor_specific[15]; 553 }; 554 555 #define NUM_SMART_SELFTEST_LOG_ENTRIES 21 556 struct smart_selftest_log { 557 uint8_t smart_selftest_log_revision[2]; 558 struct smart_selftest_log_entry 559 smart_selftest_log_entries[NUM_SMART_SELFTEST_LOG_ENTRIES]; 560 uint8_t smart_selftest_log_vendor_specific[2]; 561 uint8_t smart_selftest_log_index; 562 uint8_t smart_selftest_log_reserved[2]; 563 uint8_t smart_selftest_log_checksum; 564 }; 565 566 struct smart_ext_selftest_log_entry { 567 uint8_t smart_ext_selftest_log_lba_low; 568 uint8_t smart_ext_selftest_log_status; 569 uint8_t smart_ext_selftest_log_timestamp[2]; 570 uint8_t smart_ext_selftest_log_checkpoint; 571 uint8_t smart_ext_selftest_log_failing_lba[6]; 572 uint8_t smart_ext_selftest_log_vendor_specific[15]; 573 }; 574 575 struct smart_ext_selftest_log { 576 uint8_t smart_ext_selftest_log_rev; 577 uint8_t smart_ext_selftest_log_reserved; 578 uint8_t smart_ext_selftest_log_index[2]; 579 struct smart_ext_selftest_log_entry smart_ext_selftest_log_entries[19]; 580 uint8_t smart_ext_selftest_log_vendor_specific[2]; 581 uint8_t smart_ext_selftest_log_reserved2[11]; 582 uint8_t smart_ext_selftest_log_checksum; 583 }; 584 585 struct read_log_ext_directory { 586 uint8_t read_log_ext_vers[2]; /* general purpose log version */ 587 uint8_t read_log_ext_nblks[255][2]; /* # of blks @ log addr index+1 */ 588 }; 589 590 /* 591 * The definition of CONTROL byte field in SCSI command 592 * according to SAM 5 593 */ 594 #define CTL_BYTE_VENDOR_MASK 0xc0 595 #define CTL_BYTE_NACA_MASK 0x04 596 597 /* 598 * The definition of mask in START STOP UNIT command 599 */ 600 #define START_STOP_IMMED_MASK 0x01 601 #define START_STOP_POWER_COND_MASK 0xF0 602 #define START_STOP_START_MASK 0x01 603 #define START_STOP_LOEJ_MASK 0x02 604 #define START_STOP_NOFLUSH_MASK 0x04 605 #define START_STOP_MODIFIER_MASK 0x0f 606 #define START_STOP_POWER_COND_SHIFT 4 607 608 /* 609 * SMART specific data 610 * These eventually need to go to a generic scsi hearder file 611 * for now they will reside here 612 */ 613 #define PC_CUMULATIVE_VALUES 0x01 614 #define PAGE_CODE_GET_SUPPORTED_LOG_PAGES 0x00 615 #define PAGE_CODE_SELF_TEST_RESULTS 0x10 616 #define PAGE_CODE_INFORMATION_EXCEPTIONS 0x2f 617 #define PAGE_CODE_SMART_READ_DATA 0x30 618 #define PAGE_CODE_START_STOP_CYCLE_COUNTER 0x0e 619 620 621 struct log_parameter { 622 uint8_t param_code[2]; /* parameter dependant */ 623 uint8_t param_ctrl_flags; /* see defines below */ 624 uint8_t param_len; /* # of bytes following */ 625 uint8_t param_values[1]; /* # of bytes defined by param_len */ 626 }; 627 628 /* param_ctrl_flag fields */ 629 #define LOG_CTRL_LP 0x01 /* list parameter */ 630 #define LOG_CTRL_LBIN 0x02 /* list is binary */ 631 #define LOG_CTRL_TMC 0x0c /* threshold met criteria */ 632 #define LOG_CTRL_ETC 0x10 /* enable threshold comparison */ 633 #define LOG_CTRL_TSD 0x20 /* target save disable */ 634 #define LOG_CTRL_DS 0x40 /* disable save */ 635 #define LOG_CTRL_DU 0x80 /* disable update */ 636 637 #define SMART_MAGIC_VAL_1 0x4f 638 #define SMART_MAGIC_VAL_2 0xc2 639 #define SMART_MAGIC_VAL_3 0xf4 640 #define SMART_MAGIC_VAL_4 0x2c 641 642 #define SCT_STATUS_LOG_PAGE 0xe0 643 644 /* 645 * Acoustic management 646 */ 647 648 struct mode_acoustic_management { 649 struct mode_page mode_page; /* common mode page header */ 650 uchar_t acoustic_manag_enable; /* Set to 1 enable, Set 0 disable */ 651 uchar_t acoustic_manag_level; /* Acoustic management level */ 652 uchar_t vendor_recommended_value; /* Vendor recommended value */ 653 }; 654 655 #define PAGELENGTH_DAD_MODE_ACOUSTIC_MANAGEMENT 3 /* Acoustic manag pg len */ 656 #define P_CNTRL_CURRENT 0 657 #define P_CNTRL_CHANGEABLE 1 658 #define P_CNTRL_DEFAULT 2 659 #define P_CNTRL_SAVED 3 660 661 #define ACOUSTIC_DISABLED 0 662 #define ACOUSTIC_ENABLED 1 663 664 #define MODEPAGE_ACOUSTIC_MANAG 0x30 665 666 /* 667 * Port Multiplier registers' offsets 668 */ 669 #define SATA_PMULT_GSCR0 0x0 670 #define SATA_PMULT_GSCR1 0x1 671 #define SATA_PMULT_GSCR2 0x2 672 #define SATA_PMULT_GSCR32 0x20 673 #define SATA_PMULT_GSCR33 0x21 674 #define SATA_PMULT_GSCR64 0x40 675 #define SATA_PMULT_GSCR96 0x60 676 677 #define SATA_PMULT_PORTNUM_MASK 0xf 678 679 #define SATA_PMULT_PSCR0 0x0 680 #define SATA_PMULT_PSCR1 0x1 681 #define SATA_PMULT_PSCR2 0x2 682 #define SATA_PMULT_PSCR3 0x3 683 #define SATA_PMULT_PSCR4 0x4 684 685 #define SATA_PMULT_REG_SSTS (SATA_PMULT_PSCR0) 686 #define SATA_PMULT_REG_SERR (SATA_PMULT_PSCR1) 687 #define SATA_PMULT_REG_SCTL (SATA_PMULT_PSCR2) 688 #define SATA_PMULT_REG_SACT (SATA_PMULT_PSCR3) 689 #define SATA_PMULT_REG_SNTF (SATA_PMULT_PSCR4) 690 691 /* 692 * Port Multiplier capabilities 693 * (Indicated by GSCR64, and enabled by GSCR96) 694 */ 695 #define SATA_PMULT_CAP_BIST (1 << 0) 696 #define SATA_PMULT_CAP_PMREQ (1 << 1) 697 #define SATA_PMULT_CAP_SSC (1 << 2) 698 #define SATA_PMULT_CAP_SNOTIF (1 << 3) 699 #define SATA_PMULT_CAP_PHYEVENT (1 << 4) 700 701 /* 702 * sstatus field definitions 703 */ 704 #define SSTATUS_DET_SHIFT 0 705 #define SSTATUS_SPD_SHIFT 4 706 #define SSTATUS_IPM_SHIFT 8 707 708 #define SSTATUS_DET (0xf << SSTATUS_DET_SHIFT) 709 #define SSTATUS_SPD (0xf << SSTATUS_SPD_SHIFT) 710 #define SSTATUS_IPM (0xf << SSTATUS_IPM_SHIFT) 711 712 /* 713 * sstatus DET values 714 */ 715 #define SSTATUS_DET_NODEV 0 /* No dev detected */ 716 #define SSTATUS_DET_DEVPRE_NOPHYCOM 1 /* dev detected */ 717 #define SSTATUS_DET_DEVPRE_PHYCOM 3 /* dev detected */ 718 #define SSTATUS_DET_PHYOFFLINE 4 /* PHY is in offline */ 719 720 #define SSTATUS_GET_DET(x) \ 721 (x & SSTATUS_DET) 722 723 #define SSTATUS_SET_DET(x, new_val) \ 724 (x = (x & ~SSTATUS_DET) | (new_val & SSTATUS_DET)) 725 726 #define SSTATUS_SPD_NOLIMIT 0 /* No speed limit */ 727 #define SSTATUS_SPD_GEN1 1 /* Limit Gen 1 rate */ 728 #define SSTATUS_SPD_GEN2 2 /* Limit Gen 2 rate */ 729 730 /* 731 * sstatus IPM values 732 */ 733 #define SSTATUS_IPM_NODEV_NOPHYCOM 0x0 /* No dev, no PHY */ 734 #define SSTATUS_IPM_ACTIVE 0x1 /* Interface active */ 735 #define SSTATUS_IPM_POWERPARTIAL 0x2 /* partial power mgmnt */ 736 #define SSTATUS_IPM_POWERSLUMBER 0x6 /* slumber power mgmt */ 737 738 #define SSTATUS_GET_IPM(x) \ 739 ((x & SSTATUS_IPM) >> SSTATUS_IPM_SHIFT) 740 741 #define SSTATUS_SET_IPM(x, new_val) \ 742 (x = (x & ~SSTATUS_IPM) | \ 743 ((new_val << SSTATUS_IPM_SHIFT) & SSTATUS_IPM)) 744 745 746 /* 747 * serror register fields 748 */ 749 #define SERROR_DATA_ERR_FIXED (1 << 0) /* D integrity err */ 750 #define SERROR_COMM_ERR_FIXED (1 << 1) /* comm err recov */ 751 #define SERROR_DATA_ERR (1 << 8) /* D integrity err */ 752 #define SERROR_PERSISTENT_ERR (1 << 9) /* norecov com err */ 753 #define SERROR_PROTOCOL_ERR (1 << 10) /* protocol err */ 754 #define SERROR_INT_ERR (1 << 11) /* internal err */ 755 #define SERROR_PHY_RDY_CHG (1 << 16) /* PHY state change */ 756 #define SERROR_PHY_INT_ERR (1 << 17) /* PHY internal err */ 757 #define SERROR_COMM_WAKE (1 << 18) /* COM wake */ 758 #define SERROR_10B_TO_8B_ERR (1 << 19) /* 10B-to-8B decode */ 759 #define SERROR_DISPARITY_ERR (1 << 20) /* disparity err */ 760 #define SERROR_CRC_ERR (1 << 21) /* CRC err */ 761 #define SERROR_HANDSHAKE_ERR (1 << 22) /* Handshake err */ 762 #define SERROR_LINK_SEQ_ERR (1 << 23) /* Link seq err */ 763 #define SERROR_TRANS_ERR (1 << 24) /* Tran state err */ 764 #define SERROR_FIS_TYPE (1 << 25) /* FIS type err */ 765 #define SERROR_EXCHANGED_ERR (1 << 26) /* Device exchanged */ 766 767 /* 768 * S-Control Bridge port x register fields 769 */ 770 #define SCONTROL_DET_SHIFT 0 771 #define SCONTROL_SPD_SHIFT 4 772 #define SCONTROL_IPM_SHIFT 8 773 #define SCONTROL_SPM_SHIFT 12 774 775 #define SCONTROL_DET (0xf << SSTATUS_DET_SHIFT) 776 #define SCONTROL_SPD (0xf << SSTATUS_SPD_SHIFT) 777 #define SCONTROL_IPM (0xf << SSTATUS_IPM_SHIFT) 778 #define SCONTROL_SPM (0xf << SSTATUS_SPM_SHIFT) 779 780 #define SCONTROL_GET_DET(x) \ 781 (x & SCONTROL_DET) 782 783 #define SCONTROL_SET_DET(x, new_val) \ 784 (x = (x & ~SCONTROL_DET) | (new_val & SCONTROL_DET)) 785 786 #define SCONTROL_DET_NOACTION 0 /* Do nothing to port */ 787 #define SCONTROL_DET_COMRESET 1 /* Re-initialize port */ 788 #define SCONTROL_DET_DISABLE 4 /* Disable port */ 789 790 #define SCONTROL_SPD_NOLIMIT 0 /* No speed limit */ 791 #define SCONTROL_SPD_GEN1 1 /* Limit Gen 1 rate */ 792 #define SCONTROL_SPD_GEN2 2 /* Limit Gen 2 rate */ 793 794 #define SCONTROL_GET_IPM(x) \ 795 ((x & SCONTROL_IPM) >> SCONTROL_IPM_SHIFT) 796 797 #define SCONTROL_SET_IPM(x, new_val) \ 798 (x = (x & ~SCONTROL_IPM) | \ 799 ((new_val << SCONTROL_IPM_SHIFT) & SCONTROL_IPM)) 800 801 #define SCONTROL_IPM_NORESTRICT 0 /* No PM limit */ 802 #define SCONTROL_IPM_DISABLE_PARTIAL 1 /* Disable partial */ 803 #define SCONTROL_IPM_DISABLE_SLUMBER 2 /* Disable slumber */ 804 #define SCONTROL_IPM_DISABLE_BOTH 3 /* Disable both */ 805 806 #define SCONTROL_SPM_NORESTRICT 0 /* No PM limits */ 807 #define SCONTROL_SPM_DO_PARTIAL 1 /* Go to partial */ 808 #define SCONTROL_SPM_DO_SLUMBER 2 /* Go to slumber */ 809 #define SCONTROL_SPM_DO_ACTIVE 4 /* Go to active */ 810 811 #ifdef __cplusplus 812 } 813 #endif 814 815 #endif /* _SATA_DEFS_H */ 816