1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_hio.h> 28 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 int nxge_param_set_mac(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_ether_usr(p_nxge_t, 90 queue_t *, mblk_t *, char *, caddr_t); 91 static int nxge_param_set_ip_usr(p_nxge_t, 92 queue_t *, mblk_t *, char *, caddr_t); 93 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_fflp_hash_init(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 100 mblk_t *, char *, caddr_t); 101 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 102 mblk_t *, char *, caddr_t); 103 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 104 mblk_t *, char *, caddr_t); 105 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 106 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 107 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 108 p_mblk_t, caddr_t); 109 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 110 p_mblk_t, caddr_t); 111 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 112 p_mblk_t, caddr_t); 113 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_rx_intr_time(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 118 static int nxge_param_get_rx_intr_pkts(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 119 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 120 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 121 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 122 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 123 char *, caddr_t); 124 static int nxge_param_set_npi_debug_flag(p_nxge_t, 125 queue_t *, mblk_t *, char *, caddr_t); 126 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 127 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 128 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 129 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 130 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 131 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static void nxge_param_sync(p_nxge_t); 135 136 /* 137 * Global array of Neptune changable parameters. 138 * This array is initialized to correspond to the default 139 * Neptune 4 port configuration. This array would be copied 140 * into each port's parameter structure and modifed per 141 * fcode and nxge.conf configuration. Later, the parameters are 142 * exported to ndd to display and run-time configuration (at least 143 * some of them). 144 * 145 * Parameters with DONT_SHOW are not shown by ndd. 146 * 147 */ 148 149 static nxge_param_t nxge_param_arr[] = { 150 /* 151 * min max value old hw-name conf-name 152 */ 153 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 154 0, 999, 1000, 0, "instance", "instance"}, 155 156 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 157 0, 999, 1000, 0, "main-instance", "main_instance"}, 158 159 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 160 0, 3, 0, 0, "function-number", "function_number"}, 161 162 /* Partition Id */ 163 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 164 0, 8, 0, 0, "partition-id", "partition_id"}, 165 166 /* Read Write Permission Mode */ 167 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 168 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 169 170 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 171 0, 32, 0, 0, "version", "fw_version"}, 172 173 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 174 0, 32, 0, 0, "port-mode", "port_mode"}, 175 176 /* hw cfg types */ 177 /* control the DMA config of Neptune/NIU */ 178 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 179 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 180 "niu-cfg-type", "niu_cfg_type"}, 181 182 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 183 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 184 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 185 "tx-qcfg-type", "tx_qcfg_type"}, 186 187 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 188 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 189 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 190 "rx-qcfg-type", "rx_qcfg_type"}, 191 192 { nxge_param_get_mac, nxge_param_set_mac, 193 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 194 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 195 196 { nxge_param_get_mac, nxge_param_set_mac, 197 NXGE_PARAM_DONT_SHOW, 198 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 199 200 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 201 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 202 203 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 204 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 205 206 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 207 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 208 209 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 210 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 211 212 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 213 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 214 215 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 216 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 217 218 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 219 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 220 221 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 222 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 223 224 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 225 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 226 227 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 228 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 229 230 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 231 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 232 233 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 234 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 235 236 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 237 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 238 239 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 240 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 241 242 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 243 0, 255, 8, 8, "ipg0", "ipg0"}, 244 245 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 246 0, 255, 8, 8, "ipg1", "ipg1"}, 247 248 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 249 0, 255, 4, 4, "ipg2", "ipg2"}, 250 251 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 252 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 253 254 /* Transmit DMA channels */ 255 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 256 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 257 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 258 259 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 260 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 261 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 262 263 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 264 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 265 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 266 { nxge_param_get_txdma_info, NULL, 267 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 268 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 269 270 /* Receive DMA channels */ 271 { nxge_param_get_generic, NULL, 272 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 273 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 274 275 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 276 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 277 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 278 279 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 280 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 281 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 282 "rx-drr-weight", "rx_drr_weight"}, 283 284 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 285 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 286 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 287 288 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 289 NXGE_PARAM_DONT_SHOW, 290 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 291 292 { nxge_param_get_rxdma_info, NULL, 293 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 294 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 295 "rx-rbr-size", "rx_rbr_size"}, 296 297 { nxge_param_get_rxdma_info, NULL, 298 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 299 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 300 "rx-rcr-size", "rx_rcr_size"}, 301 302 { nxge_param_get_generic, nxge_param_set_port_rdc, 303 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 304 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 305 306 { nxge_param_get_rx_intr_time, nxge_param_rx_intr_time, 307 NXGE_PARAM_RXDMA_RW, 308 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 309 NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 310 311 { nxge_param_get_rx_intr_pkts, nxge_param_rx_intr_pkts, 312 NXGE_PARAM_RXDMA_RW, 313 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 314 NXGE_RDC_RCR_THRESHOLD, 0, 315 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 320 321 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 322 NXGE_PARAM_DONT_SHOW, 323 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 352 353 { nxge_param_get_generic, nxge_param_set_grp_rdc, 354 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 355 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 356 357 { nxge_param_get_rxdma_rdcgrp_info, NULL, 358 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 359 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 360 361 /* Logical device groups */ 362 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 363 0, 63, 0, 0, "start-ldg", "start_ldg"}, 364 365 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 366 0, 64, 0, 0, "max-ldg", "max_ldg" }, 367 368 /* MAC table information */ 369 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 370 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 371 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 372 373 /* VLAN table information */ 374 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 375 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 376 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 377 378 { nxge_param_get_generic, NULL, 379 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 380 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 381 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 386 387 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 388 NXGE_PARAM_DONT_SHOW, 389 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 390 391 { nxge_param_get_generic, nxge_param_tcam_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 394 395 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 398 399 { nxge_param_get_generic, nxge_param_llc_snap_enable, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_fflp_hash_init, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 410 411 { nxge_param_get_generic, nxge_param_set_ether_usr, 412 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 413 0, ALL_FF_32, 0x0, 0, 414 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 415 416 { nxge_param_get_generic, nxge_param_set_ether_usr, 417 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 418 0, ALL_FF_32, 0x0, 0, 419 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 420 421 { nxge_param_get_generic, nxge_param_set_ip_usr, 422 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 423 0, ALL_FF_32, 0x0, 0, 424 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 425 426 { nxge_param_get_generic, nxge_param_set_ip_usr, 427 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 428 0, ALL_FF_32, 0x0, 0, 429 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 430 431 { nxge_param_get_generic, nxge_param_set_ip_usr, 432 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 433 0, ALL_FF_32, 0x0, 0, 434 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 435 436 { nxge_param_get_generic, nxge_param_set_ip_usr, 437 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 438 0, ALL_FF_32, 0x0, 0, 439 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 440 441 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 442 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 443 0, ALL_FF_32, 0x0, 0, 444 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 445 446 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 447 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 448 0, ALL_FF_32, 0x0, 0, 449 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 450 451 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 452 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 453 0, ALL_FF_32, 0x0, 0, 454 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 455 456 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 457 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 458 0, ALL_FF_32, 0x0, 0, 459 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 460 461 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 462 NXGE_PARAM_CLASS_RWS, 463 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 464 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 465 466 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 467 NXGE_PARAM_CLASS_RWS, 468 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 469 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 470 471 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 472 NXGE_PARAM_CLASS_RWS, 473 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 474 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 475 476 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 477 NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 492 493 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 494 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 495 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 496 497 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 498 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 499 0ULL, ALL_FF_64, 0ULL, 0ULL, 500 "nxge-debug-flag", "nxge_debug_flag"}, 501 502 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 503 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 504 0ULL, ALL_FF_64, 0ULL, 0ULL, 505 "npi-debug-flag", "npi_debug_flag"}, 506 507 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 508 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 509 510 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 512 513 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 516 517 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 520 521 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 522 NXGE_PARAM_DONT_SHOW, 523 0, 0x0fffffff, 0x0fffffff, 0, 524 "dump-fflp-regs", "dump_fflp_regs"}, 525 526 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 527 NXGE_PARAM_DONT_SHOW, 528 0, 0x0fffffff, 0x0fffffff, 0, 529 "dump-vlan-table", "dump_vlan_table"}, 530 531 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 532 NXGE_PARAM_DONT_SHOW, 533 0, 0x0fffffff, 0x0fffffff, 0, 534 "dump-rdc-table", "dump_rdc_table"}, 535 536 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 537 NXGE_PARAM_DONT_SHOW, 538 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 539 540 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 541 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 542 }; 543 544 extern void *nxge_list; 545 546 void 547 nxge_get_param_soft_properties(p_nxge_t nxgep) 548 { 549 550 p_nxge_param_t param_arr; 551 uint_t prop_len; 552 int i, j; 553 uint32_t param_count; 554 uint32_t *int_prop_val; 555 556 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 557 558 param_arr = nxgep->param_arr; 559 param_count = nxgep->param_count; 560 for (i = 0; i < param_count; i++) { 561 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 562 continue; 563 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 564 continue; 565 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 566 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 567 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 568 nxgep->dip, 0, param_arr[i].fcode_name, 569 (int **)&int_prop_val, 570 (uint_t *)&prop_len) 571 == DDI_PROP_SUCCESS) { 572 uint32_t *cfg_value; 573 uint64_t prop_count; 574 575 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 576 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 577 #if defined(__i386) 578 cfg_value = 579 (uint32_t *)(int32_t)param_arr[i].value; 580 #else 581 cfg_value = (uint32_t *)param_arr[i].value; 582 #endif 583 for (j = 0; j < prop_len; j++) { 584 cfg_value[j] = int_prop_val[j]; 585 } 586 prop_count = prop_len; 587 param_arr[i].type |= 588 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 589 ddi_prop_free(int_prop_val); 590 } 591 continue; 592 } 593 594 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 595 param_arr[i].fcode_name, 596 (int **)&int_prop_val, 597 &prop_len) == DDI_PROP_SUCCESS) { 598 if ((*int_prop_val >= param_arr[i].minimum) && 599 (*int_prop_val <= param_arr[i].maximum)) 600 param_arr[i].value = *int_prop_val; 601 #ifdef NXGE_DEBUG_ERROR 602 else { 603 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 604 "nxge%d: 'prom' file parameter error\n", 605 nxgep->instance)); 606 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 607 "Parameter keyword '%s'" 608 " is outside valid range\n", 609 param_arr[i].name)); 610 } 611 #endif 612 ddi_prop_free(int_prop_val); 613 } 614 615 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 616 param_arr[i].name, 617 (int **)&int_prop_val, 618 &prop_len) == DDI_PROP_SUCCESS) { 619 if ((*int_prop_val >= param_arr[i].minimum) && 620 (*int_prop_val <= param_arr[i].maximum)) 621 param_arr[i].value = *int_prop_val; 622 #ifdef NXGE_DEBUG_ERROR 623 else { 624 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 625 "nxge%d: 'conf' file parameter error\n", 626 nxgep->instance)); 627 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 628 "Parameter keyword '%s'" 629 "is outside valid range\n", 630 param_arr[i].name)); 631 } 632 #endif 633 ddi_prop_free(int_prop_val); 634 } 635 } 636 } 637 638 static int 639 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 640 { 641 int status = B_TRUE; 642 int channel; 643 uint8_t grp; 644 char *prop_name; 645 char *end; 646 uint32_t name_chars; 647 648 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 649 "nxge_private_param_register %s", param_arr->name)); 650 651 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 652 return (B_TRUE); 653 654 prop_name = param_arr->name; 655 if (param_arr->type & NXGE_PARAM_RXDMA) { 656 if (strncmp("rxdma_intr", prop_name, 10) == 0) 657 return (B_TRUE); 658 name_chars = strlen("default_grp"); 659 if (strncmp("default_grp", prop_name, name_chars) == 0) { 660 prop_name += name_chars; 661 grp = mi_strtol(prop_name, &end, 10); 662 /* now check if this rdcgrp is in config */ 663 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 664 } 665 name_chars = strlen(prop_name); 666 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 667 return (B_TRUE); 668 } 669 return (B_FALSE); 670 } 671 672 if (param_arr->type & NXGE_PARAM_TXDMA) { 673 name_chars = strlen("txdma"); 674 if (strncmp("txdma", prop_name, name_chars) == 0) { 675 prop_name += name_chars; 676 channel = mi_strtol(prop_name, &end, 10); 677 /* now check if this rdc is in config */ 678 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 679 " nxge_private_param_register: %d", 680 channel)); 681 return (nxge_check_txdma_port_member(nxgep, channel)); 682 } 683 return (B_FALSE); 684 } 685 686 status = B_FALSE; 687 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 688 689 return (status); 690 } 691 692 void 693 nxge_setup_param(p_nxge_t nxgep) 694 { 695 p_nxge_param_t param_arr; 696 int i; 697 pfi_t set_pfi; 698 699 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 700 701 /* 702 * Make sure the param_instance is set to a valid device instance. 703 */ 704 if (nxge_param_arr[param_instance].value == 1000) 705 nxge_param_arr[param_instance].value = nxgep->instance; 706 707 param_arr = nxgep->param_arr; 708 param_arr[param_instance].value = nxgep->instance; 709 param_arr[param_function_number].value = nxgep->function_num; 710 711 for (i = 0; i < nxgep->param_count; i++) { 712 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 713 (nxge_private_param_register(nxgep, 714 ¶m_arr[i]) == B_FALSE)) { 715 param_arr[i].setf = NULL; 716 param_arr[i].getf = NULL; 717 } 718 719 if (param_arr[i].type & NXGE_PARAM_CMPLX) 720 param_arr[i].setf = NULL; 721 722 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 723 param_arr[i].setf = NULL; 724 param_arr[i].getf = NULL; 725 } 726 727 set_pfi = (pfi_t)param_arr[i].setf; 728 729 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 730 set_pfi = NULL; 731 } 732 733 } 734 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 735 } 736 737 void 738 nxge_init_param(p_nxge_t nxgep) 739 { 740 p_nxge_param_t param_arr; 741 int i, alloc_size; 742 uint64_t alloc_count; 743 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 744 /* 745 * Make sure the param_instance is set to a valid device instance. 746 */ 747 if (nxge_param_arr[param_instance].value == 1000) 748 nxge_param_arr[param_instance].value = nxgep->instance; 749 750 param_arr = nxgep->param_arr; 751 if (param_arr == NULL) { 752 param_arr = (p_nxge_param_t) 753 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 754 } 755 756 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 757 param_arr[i] = nxge_param_arr[i]; 758 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 759 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 760 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 761 alloc_size = alloc_count * sizeof (uint64_t); 762 param_arr[i].value = 763 #if defined(__i386) 764 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 765 KM_SLEEP); 766 #else 767 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 768 #endif 769 param_arr[i].old_value = 770 #if defined(__i386) 771 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 772 KM_SLEEP); 773 #else 774 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 775 #endif 776 param_arr[i].type |= 777 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 778 } 779 } 780 781 nxgep->param_arr = param_arr; 782 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 783 784 nxge_param_sync(nxgep); 785 786 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 787 nxgep->param_count)); 788 } 789 790 void 791 nxge_destroy_param(p_nxge_t nxgep) 792 { 793 int i; 794 uint64_t free_size, free_count; 795 796 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 797 798 if (nxgep->param_arr == NULL) 799 return; 800 /* 801 * Make sure the param_instance is set to a valid device instance. 802 */ 803 if (nxge_param_arr[param_instance].value == nxgep->instance) { 804 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 805 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 806 (i != nxgep->instance)) 807 break; 808 } 809 nxge_param_arr[param_instance].value = i; 810 } 811 812 for (i = 0; i < nxgep->param_count; i++) 813 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 814 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 815 free_count = ((nxgep->param_arr[i].type & 816 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 817 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 818 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 819 free_size = sizeof (uint64_t) * free_count; 820 #if defined(__i386) 821 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 822 free_size); 823 #else 824 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 825 #endif 826 #if defined(__i386) 827 KMEM_FREE((void *)(uint32_t) 828 nxgep->param_arr[i].old_value, free_size); 829 #else 830 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 831 free_size); 832 #endif 833 } 834 835 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 836 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 837 } 838 839 /* 840 * Extracts the value from the 'nxge' parameter array and prints the 841 * parameter value. cp points to the required parameter. 842 */ 843 844 /* ARGSUSED */ 845 int 846 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 847 { 848 p_nxge_param_t pa = (p_nxge_param_t)cp; 849 850 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 851 "==> nxge_param_get_generic name %s ", pa->name)); 852 853 if (pa->value > 0xffffffff) 854 (void) mi_mpprintf(mp, "%x%x", 855 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 856 else 857 (void) mi_mpprintf(mp, "%x", (int)pa->value); 858 859 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 860 return (0); 861 } 862 863 /* ARGSUSED */ 864 static int 865 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 866 { 867 p_nxge_param_t pa = (p_nxge_param_t)cp; 868 869 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 870 871 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 872 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 873 return (0); 874 } 875 876 /* ARGSUSED */ 877 static int 878 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 879 { 880 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 881 882 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 883 nxgep->instance, nxgep->vpd_info.ver); 884 885 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 886 return (0); 887 } 888 889 /* ARGSUSED */ 890 static int 891 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 892 { 893 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 894 895 switch (nxgep->mac.portmode) { 896 case PORT_1G_COPPER: 897 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 898 nxgep->instance, 899 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 900 break; 901 case PORT_1G_FIBER: 902 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 903 nxgep->instance, 904 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 905 break; 906 case PORT_10G_COPPER: 907 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 908 "%s\n", nxgep->instance, 909 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 910 break; 911 case PORT_10G_FIBER: 912 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 913 nxgep->instance, 914 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 915 break; 916 case PORT_10G_SERDES: 917 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 918 "%s\n", nxgep->instance, 919 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 920 break; 921 case PORT_1G_SERDES: 922 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 923 nxgep->instance, 924 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 925 break; 926 case PORT_1G_RGMII_FIBER: 927 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 928 "Fiber %s\n", nxgep->instance, 929 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 930 break; 931 case PORT_HSP_MODE: 932 (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 933 "PHY, Currently NOT present\n", nxgep->instance); 934 break; 935 case PORT_10G_TN1010: 936 (void) mi_mpprintf(mp, "Port mode for nxge%d:" 937 " 10G Copper with TN1010 %s\n", nxgep->instance, 938 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 939 break; 940 case PORT_1G_TN1010: 941 (void) mi_mpprintf(mp, "Port mode for nxge%d:" 942 " 1G Copper with TN1010 %s\n", nxgep->instance, 943 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 944 break; 945 default: 946 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 947 nxgep->instance, 948 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 949 break; 950 } 951 952 (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 953 nxgep->instance, 954 nxgep->soft_lso_enable ? "enable" : "disable"); 955 956 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 957 return (0); 958 } 959 960 /* ARGSUSED */ 961 static int 962 nxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp) 963 { 964 p_nxge_param_t pa = (p_nxge_param_t)cp; 965 966 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time")); 967 968 pa->value = (uint32_t)nxgep->intr_timeout; 969 (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout); 970 971 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time")); 972 return (0); 973 } 974 975 /* ARGSUSED */ 976 static int 977 nxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp) 978 { 979 p_nxge_param_t pa = (p_nxge_param_t)cp; 980 981 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts")); 982 983 pa->value = (uint32_t)nxgep->intr_threshold; 984 (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold); 985 986 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts")); 987 return (0); 988 } 989 990 /* ARGSUSED */ 991 int 992 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 993 { 994 995 uint_t print_len, buf_len; 996 p_mblk_t np; 997 998 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 999 int tdc; 1000 1001 nxge_grp_set_t *set; 1002 1003 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 1004 1005 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 1006 nxgep->function_num); 1007 1008 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1009 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1010 return (0); 1011 } 1012 1013 buf_len = buff_alloc_size; 1014 mp->b_cont = np; 1015 print_len = 0; 1016 1017 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1018 "TDC\t HW TDC\t\n"); 1019 ((mblk_t *)np)->b_wptr += print_len; 1020 buf_len -= print_len; 1021 1022 set = &nxgep->tx_set; 1023 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 1024 if ((1 << tdc) & set->owned.map) { 1025 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1026 buf_len, "%d\n", tdc); 1027 ((mblk_t *)np)->b_wptr += print_len; 1028 buf_len -= print_len; 1029 } 1030 } 1031 1032 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 1033 return (0); 1034 } 1035 1036 /* ARGSUSED */ 1037 int 1038 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1039 { 1040 uint_t print_len, buf_len; 1041 p_mblk_t np; 1042 int rdc; 1043 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1044 p_nxge_hw_pt_cfg_t p_cfgp; 1045 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1046 p_rx_rcr_rings_t rx_rcr_rings; 1047 p_rx_rcr_ring_t *rcr_rings; 1048 p_rx_rbr_rings_t rx_rbr_rings; 1049 p_rx_rbr_ring_t *rbr_rings; 1050 nxge_grp_set_t *set; 1051 1052 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1053 1054 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1055 nxgep->function_num); 1056 1057 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1058 /* The following may work even if we cannot get a large buf. */ 1059 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1060 return (0); 1061 } 1062 1063 buf_len = buff_alloc_size; 1064 mp->b_cont = np; 1065 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1066 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1067 1068 rx_rcr_rings = nxgep->rx_rcr_rings; 1069 rcr_rings = rx_rcr_rings->rcr_rings; 1070 rx_rbr_rings = nxgep->rx_rbr_rings; 1071 rbr_rings = rx_rbr_rings->rbr_rings; 1072 1073 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1074 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 1075 1076 ((mblk_t *)np)->b_wptr += print_len; 1077 buf_len -= print_len; 1078 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1079 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1080 "chunks\t RCR ptr\n"); 1081 1082 ((mblk_t *)np)->b_wptr += print_len; 1083 buf_len -= print_len; 1084 1085 set = &nxgep->rx_set; 1086 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1087 if ((1 << rdc) & set->owned.map) { 1088 print_len = snprintf((char *) 1089 ((mblk_t *)np)->b_wptr, buf_len, 1090 " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1091 rdc, 1092 p_dma_cfgp->rcr_timeout[rdc], 1093 p_dma_cfgp->rcr_threshold[rdc], 1094 (void *)rbr_rings[rdc], 1095 rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]); 1096 ((mblk_t *)np)->b_wptr += print_len; 1097 buf_len -= print_len; 1098 } 1099 } 1100 1101 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1102 return (0); 1103 } 1104 1105 /* ARGSUSED */ 1106 int 1107 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1108 p_mblk_t mp, caddr_t cp) 1109 { 1110 uint_t print_len, buf_len; 1111 p_mblk_t np; 1112 int offset, rdc, i, rdc_grp; 1113 p_nxge_rdc_grp_t rdc_grp_p; 1114 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1115 p_nxge_hw_pt_cfg_t p_cfgp; 1116 1117 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1118 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1119 "==> nxge_param_get_rxdma_rdcgrp_info")); 1120 1121 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1122 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1123 1124 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1125 nxgep->function_num); 1126 1127 rdc_grp = p_cfgp->def_mac_rxdma_grpid; 1128 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1129 /* The following may work even if we cannot get a large buf. */ 1130 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1131 return (0); 1132 } 1133 1134 buf_len = buff_alloc_size; 1135 mp->b_cont = np; 1136 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1137 "Total RDC Groups\t %d \n" 1138 "default RDC group\t %d\n", 1139 p_cfgp->max_rdc_grpids, 1140 p_cfgp->def_mac_rxdma_grpid); 1141 1142 ((mblk_t *)np)->b_wptr += print_len; 1143 buf_len -= print_len; 1144 1145 for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 1146 if (p_cfgp->grpids[i]) { 1147 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1148 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1149 buf_len, 1150 "\nRDC Group Info for Group [%d] %d\n" 1151 "RDC Count %d\tstart RDC %d\n" 1152 "RDC Group Population Information" 1153 " (offsets 0 - 15)\n", 1154 i, rdc_grp, rdc_grp_p->max_rdcs, 1155 rdc_grp_p->start_rdc); 1156 1157 ((mblk_t *)np)->b_wptr += print_len; 1158 buf_len -= print_len; 1159 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1160 buf_len, "\n"); 1161 ((mblk_t *)np)->b_wptr += print_len; 1162 buf_len -= print_len; 1163 1164 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1165 print_len = snprintf( 1166 (char *)((mblk_t *)np)->b_wptr, 1167 buf_len, "[%d]=%d ", rdc, 1168 rdc_grp_p->start_rdc + rdc); 1169 ((mblk_t *)np)->b_wptr += print_len; 1170 buf_len -= print_len; 1171 } 1172 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1173 buf_len, "\n"); 1174 ((mblk_t *)np)->b_wptr += print_len; 1175 buf_len -= print_len; 1176 1177 for (offset = 0; offset < 16; offset++) { 1178 print_len = snprintf( 1179 (char *)((mblk_t *)np)->b_wptr, 1180 buf_len, " %c", 1181 rdc_grp_p->map & (1 << offset) ? 1182 '1' : '0'); 1183 ((mblk_t *)np)->b_wptr += print_len; 1184 buf_len -= print_len; 1185 } 1186 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1187 buf_len, "\n"); 1188 ((mblk_t *)np)->b_wptr += print_len; 1189 buf_len -= print_len; 1190 } 1191 } 1192 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1193 "<== nxge_param_get_rxdma_rdcgrp_info")); 1194 return (0); 1195 } 1196 1197 int 1198 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1199 { 1200 p_mblk_t tmp; 1201 1202 tmp = mp; 1203 while (tmp->b_cont) 1204 tmp = tmp->b_cont; 1205 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1206 tmp->b_cont = allocb(1024, BPRI_HI); 1207 tmp = tmp->b_cont; 1208 if (!tmp) 1209 return (ENOMEM); 1210 } 1211 1212 *nmp = tmp; 1213 return (0); 1214 } 1215 1216 1217 /* ARGSUSED */ 1218 int 1219 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1220 char *value, caddr_t cp) 1221 { 1222 char *end; 1223 uint32_t new_value; 1224 p_nxge_param_t pa = (p_nxge_param_t)cp; 1225 1226 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1227 new_value = (uint32_t)mi_strtol(value, &end, 10); 1228 if (end == value || new_value < pa->minimum || 1229 new_value > pa->maximum) { 1230 return (EINVAL); 1231 } 1232 pa->value = new_value; 1233 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1234 return (0); 1235 } 1236 1237 1238 /* ARGSUSED */ 1239 int 1240 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1241 char *value, caddr_t cp) 1242 { 1243 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1244 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1245 return (0); 1246 } 1247 1248 1249 /* ARGSUSED */ 1250 int 1251 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1252 char *value, caddr_t cp) 1253 { 1254 char *end; 1255 uint32_t new_value; 1256 int status = 0; 1257 p_nxge_param_t pa = (p_nxge_param_t)cp; 1258 1259 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1260 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1261 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1262 return (EINVAL); 1263 } 1264 1265 if (pa->value != new_value) { 1266 pa->old_value = pa->value; 1267 pa->value = new_value; 1268 } 1269 1270 if (!nxge_param_link_update(nxgep)) { 1271 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1272 " false ret from nxge_param_link_update")); 1273 status = EINVAL; 1274 } 1275 1276 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1277 return (status); 1278 } 1279 1280 /* ARGSUSED */ 1281 int 1282 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1283 char *value, caddr_t cp) 1284 { 1285 char *end; 1286 uint32_t cfg_value; 1287 p_nxge_param_t pa = (p_nxge_param_t)cp; 1288 1289 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1290 1291 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1292 1293 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1294 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1295 return (EINVAL); 1296 } 1297 1298 if ((pa->value != cfg_value)) { 1299 pa->old_value = pa->value; 1300 pa->value = cfg_value; 1301 nxgep->intr_threshold = pa->value; 1302 } 1303 1304 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1305 return (0); 1306 } 1307 1308 /* ARGSUSED */ 1309 int 1310 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1311 char *value, caddr_t cp) 1312 { 1313 char *end; 1314 uint32_t cfg_value; 1315 p_nxge_param_t pa = (p_nxge_param_t)cp; 1316 1317 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1318 1319 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1320 1321 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1322 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1323 return (EINVAL); 1324 } 1325 1326 if ((pa->value != cfg_value)) { 1327 pa->old_value = pa->value; 1328 pa->value = cfg_value; 1329 nxgep->intr_timeout = pa->value; 1330 } 1331 1332 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1333 return (0); 1334 } 1335 1336 /* ARGSUSED */ 1337 static int 1338 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1339 mblk_t *mp, char *value, caddr_t cp) 1340 { 1341 char *end; 1342 uint32_t status = 0, cfg_value; 1343 p_nxge_param_t pa = (p_nxge_param_t)cp; 1344 uint32_t cfg_it = B_FALSE; 1345 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1346 p_nxge_hw_pt_cfg_t p_cfgp; 1347 uint32_t *val_ptr, *old_val_ptr; 1348 nxge_param_map_t *mac_map; 1349 p_nxge_class_pt_cfg_t p_class_cfgp; 1350 nxge_mv_cfg_t *mac_host_info; 1351 1352 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1353 1354 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1355 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1356 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1357 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1358 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1359 1360 /* 1361 * now do decoding 1362 */ 1363 mac_map = (nxge_param_map_t *)&cfg_value; 1364 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1365 cfg_value, mac_map->param_id, mac_map->map_to)); 1366 1367 if ((mac_map->param_id < p_cfgp->max_macs) && 1368 p_cfgp->grpids[mac_map->map_to]) { 1369 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1370 " nxge_param_set_mac_rdcgrp mapping" 1371 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1372 #if defined(__i386) 1373 val_ptr = (uint32_t *)(uint32_t)pa->value; 1374 #else 1375 val_ptr = (uint32_t *)pa->value; 1376 #endif 1377 #if defined(__i386) 1378 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1379 #else 1380 old_val_ptr = (uint32_t *)pa->old_value; 1381 #endif 1382 if (val_ptr[mac_map->param_id] != cfg_value) { 1383 old_val_ptr[mac_map->param_id] = 1384 val_ptr[mac_map->param_id]; 1385 val_ptr[mac_map->param_id] = cfg_value; 1386 mac_host_info[mac_map->param_id].mpr_npr = 1387 mac_map->pref; 1388 mac_host_info[mac_map->param_id].flag = 1; 1389 mac_host_info[mac_map->param_id].rdctbl = 1390 mac_map->map_to; 1391 cfg_it = B_TRUE; 1392 } 1393 } else { 1394 return (EINVAL); 1395 } 1396 1397 if (cfg_it == B_TRUE) { 1398 status = nxge_logical_mac_assign_rdc_table(nxgep, 1399 (uint8_t)mac_map->param_id); 1400 if (status != NXGE_OK) 1401 return (EINVAL); 1402 } 1403 1404 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1405 return (0); 1406 } 1407 1408 /* ARGSUSED */ 1409 static int 1410 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1411 mblk_t *mp, char *value, caddr_t cp) 1412 { 1413 char *end; 1414 uint32_t status = 0, cfg_value; 1415 p_nxge_param_t pa = (p_nxge_param_t)cp; 1416 uint32_t cfg_it = B_FALSE; 1417 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1418 p_nxge_hw_pt_cfg_t p_cfgp; 1419 uint32_t *val_ptr, *old_val_ptr; 1420 nxge_param_map_t *vmap, *old_map; 1421 p_nxge_class_pt_cfg_t p_class_cfgp; 1422 uint64_t cfgd_vlans; 1423 int i, inc = 0, cfg_position; 1424 nxge_mv_cfg_t *vlan_tbl; 1425 1426 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1427 1428 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1429 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1430 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1431 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1432 1433 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1434 1435 /* now do decoding */ 1436 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1437 NXGE_PARAM_ARRAY_CNT_SHIFT); 1438 1439 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1440 /* 1441 * for now, we process only upto max 1442 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1443 * In the future, we may want to expand 1444 * the storage array and continue 1445 */ 1446 return (EINVAL); 1447 } 1448 1449 vmap = (nxge_param_map_t *)&cfg_value; 1450 if ((vmap->param_id) && 1451 (vmap->param_id < NXGE_MAX_VLANS) && 1452 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1453 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1454 "nxge_param_set_vlan_rdcgrp mapping" 1455 " id %d grp %d", 1456 vmap->param_id, vmap->map_to)); 1457 #if defined(__i386) 1458 val_ptr = (uint32_t *)(uint32_t)pa->value; 1459 #else 1460 val_ptr = (uint32_t *)pa->value; 1461 #endif 1462 #if defined(__i386) 1463 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1464 #else 1465 old_val_ptr = (uint32_t *)pa->old_value; 1466 #endif 1467 1468 /* search to see if this vlan id is already configured */ 1469 for (i = 0; i < cfgd_vlans; i++) { 1470 old_map = (nxge_param_map_t *)&val_ptr[i]; 1471 if ((old_map->param_id == 0) || 1472 (vmap->param_id == old_map->param_id) || 1473 (vlan_tbl[vmap->param_id].flag)) { 1474 cfg_position = i; 1475 break; 1476 } 1477 } 1478 1479 if (cfgd_vlans == 0) { 1480 cfg_position = 0; 1481 inc++; 1482 } 1483 1484 if (i == cfgd_vlans) { 1485 cfg_position = i; 1486 inc++; 1487 } 1488 1489 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1490 "set_vlan_rdcgrp mapping" 1491 " i %d cfgd_vlans %llx position %d ", 1492 i, cfgd_vlans, cfg_position)); 1493 if (val_ptr[cfg_position] != cfg_value) { 1494 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1495 val_ptr[cfg_position] = cfg_value; 1496 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1497 vlan_tbl[vmap->param_id].flag = 1; 1498 vlan_tbl[vmap->param_id].rdctbl = 1499 vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 1500 cfg_it = B_TRUE; 1501 if (inc) { 1502 cfgd_vlans++; 1503 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1504 pa->type |= (cfgd_vlans << 1505 NXGE_PARAM_ARRAY_CNT_SHIFT); 1506 1507 } 1508 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1509 "after: param_set_vlan_rdcgrp " 1510 " cfg_vlans %llx position %d \n", 1511 cfgd_vlans, cfg_position)); 1512 } 1513 } else { 1514 return (EINVAL); 1515 } 1516 1517 if (cfg_it == B_TRUE) { 1518 status = nxge_fflp_config_vlan_table(nxgep, 1519 (uint16_t)vmap->param_id); 1520 if (status != NXGE_OK) 1521 return (EINVAL); 1522 } 1523 1524 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1525 return (0); 1526 } 1527 1528 /* ARGSUSED */ 1529 static int 1530 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1531 mblk_t *mp, caddr_t cp) 1532 { 1533 1534 uint_t print_len, buf_len; 1535 p_mblk_t np; 1536 int i; 1537 uint32_t *val_ptr; 1538 nxge_param_map_t *vmap; 1539 p_nxge_param_t pa = (p_nxge_param_t)cp; 1540 p_nxge_class_pt_cfg_t p_class_cfgp; 1541 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1542 p_nxge_hw_pt_cfg_t p_cfgp; 1543 uint64_t cfgd_vlans = 0; 1544 nxge_mv_cfg_t *vlan_tbl; 1545 int buff_alloc_size = 1546 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1547 1548 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1549 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1550 nxgep->function_num); 1551 1552 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1553 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1554 return (0); 1555 } 1556 1557 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1558 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1559 1560 buf_len = buff_alloc_size; 1561 mp->b_cont = np; 1562 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1563 NXGE_PARAM_ARRAY_CNT_SHIFT; 1564 1565 i = (int)cfgd_vlans; 1566 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1567 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1568 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1569 "Configured VLANs %d\n" 1570 "VLAN ID\t RDC GRP (Actual/Port)\t" 1571 " Prefernce\n", i); 1572 ((mblk_t *)np)->b_wptr += print_len; 1573 buf_len -= print_len; 1574 #if defined(__i386) 1575 val_ptr = (uint32_t *)(uint32_t)pa->value; 1576 #else 1577 val_ptr = (uint32_t *)pa->value; 1578 #endif 1579 1580 for (i = 0; i < cfgd_vlans; i++) { 1581 vmap = (nxge_param_map_t *)&val_ptr[i]; 1582 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1583 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1584 buf_len, 1585 " %d\t\t %d/%d\t\t %d\n", 1586 vmap->param_id, 1587 vlan_tbl[vmap->param_id].rdctbl, 1588 vlan_tbl[vmap->param_id].rdctbl - 1589 p_cfgp->def_mac_rxdma_grpid, 1590 vlan_tbl[vmap->param_id].mpr_npr); 1591 ((mblk_t *)np)->b_wptr += print_len; 1592 buf_len -= print_len; 1593 } 1594 } 1595 1596 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1597 return (0); 1598 } 1599 1600 /* ARGSUSED */ 1601 static int 1602 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1603 mblk_t *mp, caddr_t cp) 1604 { 1605 uint_t print_len, buf_len; 1606 p_mblk_t np; 1607 int i; 1608 p_nxge_class_pt_cfg_t p_class_cfgp; 1609 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1610 p_nxge_hw_pt_cfg_t p_cfgp; 1611 nxge_mv_cfg_t *mac_host_info; 1612 1613 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1614 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1615 (void) mi_mpprintf(mp, 1616 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1617 nxgep->function_num); 1618 1619 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1620 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1621 return (0); 1622 } 1623 1624 buf_len = buff_alloc_size; 1625 mp->b_cont = np; 1626 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1627 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1628 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1629 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1630 print_len = snprintf((char *)np->b_wptr, buf_len, 1631 "MAC ID\t RDC GRP (Actual/Port)\t" 1632 " Prefernce\n"); 1633 ((mblk_t *)np)->b_wptr += print_len; 1634 buf_len -= print_len; 1635 for (i = 0; i < p_cfgp->max_macs; i++) { 1636 if (mac_host_info[i].flag) { 1637 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1638 buf_len, 1639 " %d\t %d/%d\t\t %d\n", 1640 i, mac_host_info[i].rdctbl, 1641 mac_host_info[i].rdctbl - 1642 p_cfgp->def_mac_rxdma_grpid, 1643 mac_host_info[i].mpr_npr); 1644 ((mblk_t *)np)->b_wptr += print_len; 1645 buf_len -= print_len; 1646 } 1647 } 1648 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1649 "Done Info Dumping \n"); 1650 ((mblk_t *)np)->b_wptr += print_len; 1651 buf_len -= print_len; 1652 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1653 return (0); 1654 } 1655 1656 /* ARGSUSED */ 1657 static int 1658 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1659 mblk_t *mp, char *value, caddr_t cp) 1660 { 1661 uint32_t status = 0, cfg_value; 1662 p_nxge_param_t pa = (p_nxge_param_t)cp; 1663 uint32_t cfg_it = B_FALSE; 1664 char *end; 1665 1666 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1667 1668 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1669 if (pa->value != cfg_value) { 1670 pa->old_value = pa->value; 1671 pa->value = cfg_value; 1672 cfg_it = B_TRUE; 1673 } 1674 1675 if (cfg_it == B_TRUE) { 1676 if (pa->value) 1677 status = nxge_fflp_config_tcam_enable(nxgep); 1678 else 1679 status = nxge_fflp_config_tcam_disable(nxgep); 1680 if (status != NXGE_OK) 1681 return (EINVAL); 1682 } 1683 1684 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1685 return (0); 1686 } 1687 1688 /* ARGSUSED */ 1689 static int 1690 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1691 mblk_t *mp, char *value, caddr_t cp) 1692 { 1693 uint32_t status = 0, cfg_value; 1694 p_nxge_param_t pa = (p_nxge_param_t)cp; 1695 uint32_t cfg_it = B_FALSE; 1696 char *end; 1697 1698 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1699 1700 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1701 if (pa->value != cfg_value) { 1702 pa->old_value = pa->value; 1703 pa->value = cfg_value; 1704 cfg_it = B_TRUE; 1705 } 1706 1707 if (cfg_it == B_TRUE) { 1708 if (pa->value) 1709 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1710 else 1711 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1712 if (status != NXGE_OK) 1713 return (EINVAL); 1714 } 1715 1716 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1717 return (0); 1718 } 1719 1720 /* ARGSUSED */ 1721 static int 1722 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1723 mblk_t *mp, char *value, caddr_t cp) 1724 { 1725 char *end; 1726 uint32_t status = 0, cfg_value; 1727 p_nxge_param_t pa = (p_nxge_param_t)cp; 1728 uint32_t cfg_it = B_FALSE; 1729 1730 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1731 1732 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1733 if (pa->value != cfg_value) { 1734 pa->old_value = pa->value; 1735 pa->value = cfg_value; 1736 cfg_it = B_TRUE; 1737 } 1738 1739 if (cfg_it == B_TRUE) { 1740 if (pa->value) 1741 status = nxge_fflp_config_tcam_enable(nxgep); 1742 else 1743 status = nxge_fflp_config_tcam_disable(nxgep); 1744 if (status != NXGE_OK) 1745 return (EINVAL); 1746 } 1747 1748 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1749 return (0); 1750 } 1751 1752 /* ARGSUSED */ 1753 static int 1754 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1755 mblk_t *mp, char *value, caddr_t cp) 1756 { 1757 char *end; 1758 uint8_t ether_class; 1759 uint32_t status = 0, cfg_value; 1760 p_nxge_param_t pa = (p_nxge_param_t)cp; 1761 uint8_t cfg_it = B_FALSE; 1762 1763 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1764 1765 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1766 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1767 return (EINVAL); 1768 } 1769 1770 if (pa->value != cfg_value) { 1771 pa->old_value = pa->value; 1772 pa->value = cfg_value; 1773 cfg_it = B_TRUE; 1774 } 1775 1776 /* do the actual hw setup */ 1777 if (cfg_it == B_TRUE) { 1778 ether_class = mi_strtol(pa->name, &end, 10); 1779 #ifdef lint 1780 ether_class = ether_class; 1781 #endif 1782 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1783 } 1784 1785 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1786 return (status); 1787 } 1788 1789 /* ARGSUSED */ 1790 static int 1791 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1792 mblk_t *mp, char *value, caddr_t cp) 1793 { 1794 char *end; 1795 tcam_class_t class; 1796 uint32_t status, cfg_value; 1797 p_nxge_param_t pa = (p_nxge_param_t)cp; 1798 uint32_t cfg_it = B_FALSE; 1799 1800 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1801 1802 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1803 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1804 return (EINVAL); 1805 } 1806 1807 if (pa->value != cfg_value) { 1808 pa->old_value = pa->value; 1809 pa->value = cfg_value; 1810 cfg_it = B_TRUE; 1811 } 1812 1813 /* do the actual hw setup with cfg_value. */ 1814 if (cfg_it == B_TRUE) { 1815 class = mi_strtol(pa->name, &end, 10); 1816 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1817 } 1818 1819 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1820 return (status); 1821 } 1822 1823 /* ARGSUSED */ 1824 static int 1825 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1826 { 1827 int i; 1828 int class_instance = param_class_opt_ip_usr4; 1829 p_nxge_param_t param_arr; 1830 1831 param_arr = nxgep->param_arr; 1832 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1833 if (strcmp(param_arr[class_instance].name, name) == 0) 1834 return (i); 1835 class_instance++; 1836 } 1837 return (-1); 1838 } 1839 1840 /* ARGSUSED */ 1841 int 1842 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1843 mblk_t *mp, char *value, caddr_t cp) 1844 { 1845 char *end; 1846 uint32_t status, cfg_value; 1847 p_nxge_param_t pa = (p_nxge_param_t)cp; 1848 tcam_class_t class; 1849 uint32_t cfg_it = B_FALSE; 1850 1851 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1852 1853 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1854 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1855 return (EINVAL); 1856 } 1857 1858 if (pa->value != cfg_value) { 1859 pa->old_value = pa->value; 1860 pa->value = cfg_value; 1861 cfg_it = B_TRUE; 1862 } 1863 1864 if (cfg_it == B_TRUE) { 1865 /* do the actual hw setup */ 1866 class = nxge_class_name_2value(nxgep, pa->name); 1867 if (class == -1) 1868 return (EINVAL); 1869 1870 /* Filter out the allowed bits */ 1871 pa->value &= (NXGE_CLASS_FLOW_USE_PORTNUM | 1872 NXGE_CLASS_FLOW_USE_L2DA | NXGE_CLASS_FLOW_USE_VLAN | 1873 NXGE_CLASS_FLOW_USE_PROTO | NXGE_CLASS_FLOW_USE_IPSRC | 1874 NXGE_CLASS_FLOW_USE_IPDST | NXGE_CLASS_FLOW_USE_SRC_PORT | 1875 NXGE_CLASS_FLOW_USE_DST_PORT); 1876 1877 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1878 if (status != NXGE_OK) 1879 return (EINVAL); 1880 } 1881 1882 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1883 return (0); 1884 } 1885 1886 /* ARGSUSED */ 1887 static int 1888 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1889 mblk_t *mp, caddr_t cp) 1890 { 1891 uint32_t status, cfg_value; 1892 p_nxge_param_t pa = (p_nxge_param_t)cp; 1893 tcam_class_t class; 1894 1895 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1896 1897 /* do the actual hw setup */ 1898 class = nxge_class_name_2value(nxgep, pa->name); 1899 if (class == -1) 1900 return (EINVAL); 1901 1902 cfg_value = 0; 1903 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1904 if (status != NXGE_OK) 1905 return (EINVAL); 1906 1907 /* Filter out the allowed bits */ 1908 cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA | 1909 NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO | 1910 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST | 1911 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT); 1912 1913 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1914 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1915 1916 pa->value = cfg_value; 1917 (void) mi_mpprintf(mp, "%x", cfg_value); 1918 1919 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1920 return (0); 1921 } 1922 1923 /* ARGSUSED */ 1924 static int 1925 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1926 mblk_t *mp, char *value, caddr_t cp) 1927 { 1928 char *end; 1929 uint32_t status, cfg_value; 1930 p_nxge_param_t pa = (p_nxge_param_t)cp; 1931 tcam_class_t class; 1932 uint32_t cfg_it = B_FALSE; 1933 1934 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1935 1936 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1937 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1938 return (EINVAL); 1939 } 1940 1941 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1942 "nxge_param_fflp_hash_init value %x", cfg_value)); 1943 1944 if (pa->value != cfg_value) { 1945 pa->old_value = pa->value; 1946 pa->value = cfg_value; 1947 cfg_it = B_TRUE; 1948 } 1949 1950 if (cfg_it == B_TRUE) { 1951 char *h_name; 1952 1953 /* do the actual hw setup */ 1954 h_name = pa->name; 1955 h_name++; 1956 class = mi_strtol(h_name, &end, 10); 1957 switch (class) { 1958 case 1: 1959 status = nxge_fflp_set_hash1(nxgep, 1960 (uint32_t)pa->value); 1961 break; 1962 case 2: 1963 status = nxge_fflp_set_hash2(nxgep, 1964 (uint16_t)pa->value); 1965 break; 1966 1967 default: 1968 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1969 " nxge_param_fflp_hash_init" 1970 " %s Wrong hash var %d", 1971 pa->name, class)); 1972 return (EINVAL); 1973 } 1974 if (status != NXGE_OK) 1975 return (EINVAL); 1976 } 1977 1978 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1979 return (0); 1980 } 1981 1982 /* ARGSUSED */ 1983 static int 1984 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1985 mblk_t *mp, char *value, caddr_t cp) 1986 { 1987 char *end; 1988 uint32_t status = 0, cfg_value; 1989 p_nxge_param_t pa = (p_nxge_param_t)cp; 1990 uint32_t cfg_it = B_FALSE; 1991 int rdc_grp; 1992 uint8_t real_rdc; 1993 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1994 p_nxge_hw_pt_cfg_t p_cfgp; 1995 p_nxge_rdc_grp_t rdc_grp_p; 1996 1997 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1998 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1999 2000 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 2001 2002 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2003 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2004 return (EINVAL); 2005 } 2006 2007 if (cfg_value >= p_cfgp->max_rdcs) { 2008 return (EINVAL); 2009 } 2010 2011 if (pa->value != cfg_value) { 2012 pa->old_value = pa->value; 2013 pa->value = cfg_value; 2014 cfg_it = B_TRUE; 2015 } 2016 2017 if (cfg_it == B_TRUE) { 2018 char *grp_name; 2019 grp_name = pa->name; 2020 grp_name += strlen("default-grp"); 2021 rdc_grp = mi_strtol(grp_name, &end, 10); 2022 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 2023 real_rdc = rdc_grp_p->start_rdc + cfg_value; 2024 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 2025 cfg_value) == B_FALSE) { 2026 pa->value = pa->old_value; 2027 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2028 " nxge_param_set_grp_rdc" 2029 " %d read %d actual %d outof range", 2030 rdc_grp, cfg_value, real_rdc)); 2031 return (EINVAL); 2032 } 2033 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 2034 real_rdc); 2035 if (status != NXGE_OK) 2036 return (EINVAL); 2037 } 2038 2039 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 2040 return (0); 2041 } 2042 2043 /* ARGSUSED */ 2044 static int 2045 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 2046 mblk_t *mp, char *value, caddr_t cp) 2047 { 2048 char *end; 2049 uint32_t status = B_TRUE, cfg_value; 2050 p_nxge_param_t pa = (p_nxge_param_t)cp; 2051 uint32_t cfg_it = B_FALSE; 2052 2053 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2054 p_nxge_hw_pt_cfg_t p_cfgp; 2055 2056 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 2057 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2058 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2059 2060 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2061 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2062 return (EINVAL); 2063 } 2064 2065 if (pa->value != cfg_value) { 2066 if (cfg_value >= p_cfgp->max_rdcs) 2067 return (EINVAL); 2068 pa->old_value = pa->value; 2069 pa->value = cfg_value; 2070 cfg_it = B_TRUE; 2071 } 2072 2073 if (cfg_it == B_TRUE) { 2074 int rdc; 2075 if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2076 return (EINVAL); 2077 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2078 nxgep->function_num, rdc); 2079 if (status != NXGE_OK) 2080 return (EINVAL); 2081 } 2082 2083 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2084 return (0); 2085 } 2086 2087 /* ARGSUSED */ 2088 static int 2089 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2090 mblk_t *mp, char *value, caddr_t cp) 2091 { 2092 char *end; 2093 uint32_t status = 0; 2094 uint64_t cfg_value = 0; 2095 p_nxge_param_t pa = (p_nxge_param_t)cp; 2096 uint32_t cfg_it = B_FALSE; 2097 2098 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2099 cfg_value = mi_strtol(value, &end, BASE_HEX); 2100 2101 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2102 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2103 " nxge_param_set_nxge_debug_flag" 2104 " outof range %llx", cfg_value)); 2105 return (EINVAL); 2106 } 2107 if (pa->value != cfg_value) { 2108 pa->old_value = pa->value; 2109 pa->value = cfg_value; 2110 cfg_it = B_TRUE; 2111 } 2112 2113 if (cfg_it == B_TRUE) { 2114 nxgep->nxge_debug_level = pa->value; 2115 } 2116 2117 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2118 return (status); 2119 } 2120 2121 /* ARGSUSED */ 2122 static int 2123 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2124 { 2125 int status = 0; 2126 p_nxge_param_t pa = (p_nxge_param_t)cp; 2127 2128 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2129 2130 if (pa->value > 0xffffffff) 2131 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2132 (int)(pa->value & 0xffffffff)); 2133 else 2134 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2135 2136 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2137 return (status); 2138 } 2139 2140 /* ARGSUSED */ 2141 static int 2142 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2143 mblk_t *mp, char *value, caddr_t cp) 2144 { 2145 char *end; 2146 uint32_t status = 0; 2147 uint64_t cfg_value = 0; 2148 p_nxge_param_t pa; 2149 uint32_t cfg_it = B_FALSE; 2150 2151 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2152 cfg_value = mi_strtol(value, &end, BASE_HEX); 2153 pa = (p_nxge_param_t)cp; 2154 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2155 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2156 " outof range %llx", cfg_value)); 2157 return (EINVAL); 2158 } 2159 if (pa->value != cfg_value) { 2160 pa->old_value = pa->value; 2161 pa->value = cfg_value; 2162 cfg_it = B_TRUE; 2163 } 2164 2165 if (cfg_it == B_TRUE) { 2166 npi_debug_level = pa->value; 2167 } 2168 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2169 return (status); 2170 } 2171 2172 /* ARGSUSED */ 2173 static int 2174 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2175 { 2176 nxge_grp_set_t *set = &nxgep->rx_set; 2177 int rdc; 2178 2179 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2180 2181 if (!isLDOMguest(nxgep)) 2182 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2183 2184 for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2185 if ((1 << rdc) & set->owned.map) { 2186 (void) nxge_dump_rxdma_channel(nxgep, rdc); 2187 } 2188 } 2189 2190 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2191 return (0); 2192 } 2193 2194 /* ARGSUSED */ 2195 static int 2196 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2197 { 2198 nxge_grp_set_t *set = &nxgep->tx_set; 2199 int tdc; 2200 2201 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2202 2203 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2204 if ((1 << tdc) & set->owned.map) { 2205 (void) nxge_txdma_regs_dump(nxgep, tdc); 2206 } 2207 } 2208 2209 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2210 return (0); 2211 } 2212 2213 /* ARGSUSED */ 2214 static int 2215 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2216 { 2217 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2218 2219 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2220 2221 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2222 return (0); 2223 } 2224 2225 /* ARGSUSED */ 2226 static int 2227 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2228 { 2229 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2230 2231 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2232 nxgep->function_num); 2233 2234 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2235 return (0); 2236 } 2237 2238 /* ARGSUSED */ 2239 static int 2240 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2241 { 2242 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2243 2244 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2245 nxgep->function_num); 2246 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2247 return (0); 2248 } 2249 2250 /* ARGSUSED */ 2251 static int 2252 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2253 { 2254 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2255 2256 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2257 2258 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2259 return (0); 2260 } 2261 2262 /* ARGSUSED */ 2263 static int 2264 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2265 { 2266 uint8_t table; 2267 2268 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2269 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2270 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2271 table); 2272 } 2273 2274 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2275 return (0); 2276 } 2277 2278 typedef struct block_info { 2279 char *name; 2280 uint32_t offset; 2281 } block_info_t; 2282 2283 block_info_t reg_block[] = { 2284 {"PIO", PIO}, 2285 {"FZC_PIO", FZC_PIO}, 2286 {"FZC_XMAC", FZC_MAC}, 2287 {"FZC_IPP", FZC_IPP}, 2288 {"FFLP", FFLP}, 2289 {"FZC_FFLP", FZC_FFLP}, 2290 {"PIO_VADDR", PIO_VADDR}, 2291 {"ZCP", ZCP}, 2292 {"FZC_ZCP", FZC_ZCP}, 2293 {"DMC", DMC}, 2294 {"FZC_DMC", FZC_DMC}, 2295 {"TXC", TXC}, 2296 {"FZC_TXC", FZC_TXC}, 2297 {"PIO_LDSV", PIO_LDSV}, 2298 {"PIO_LDGIM", PIO_LDGIM}, 2299 {"PIO_IMASK0", PIO_IMASK0}, 2300 {"PIO_IMASK1", PIO_IMASK1}, 2301 {"FZC_PROM", FZC_PROM}, 2302 {"END", ALL_FF_32}, 2303 }; 2304 2305 /* ARGSUSED */ 2306 static int 2307 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2308 { 2309 uint_t print_len, buf_len; 2310 p_mblk_t np; 2311 int rdc, tdc, block; 2312 uint64_t base; 2313 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2314 p_nxge_hw_pt_cfg_t p_cfgp; 2315 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2316 p_tx_ring_t *tx_rings; 2317 p_rx_rcr_rings_t rx_rcr_rings; 2318 p_rx_rcr_ring_t *rcr_rings; 2319 p_rx_rbr_rings_t rx_rbr_rings; 2320 p_rx_rbr_ring_t *rbr_rings; 2321 2322 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2323 "==> nxge_param_dump_ptrs")); 2324 2325 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2326 nxgep->function_num); 2327 2328 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2329 /* The following may work even if we cannot get a large buf. */ 2330 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2331 return (0); 2332 } 2333 2334 buf_len = buff_alloc_size; 2335 mp->b_cont = np; 2336 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2337 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2338 2339 rx_rcr_rings = nxgep->rx_rcr_rings; 2340 rcr_rings = rx_rcr_rings->rcr_rings; 2341 rx_rbr_rings = nxgep->rx_rbr_rings; 2342 rbr_rings = rx_rbr_rings->rbr_rings; 2343 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2344 "nxgep (nxge_t) $%p\n" 2345 "dev_regs (dev_regs_t) $%p\n", 2346 (void *)nxgep, (void *)nxgep->dev_regs); 2347 2348 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2349 2350 /* do register pointers */ 2351 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2352 "reg base (npi_reg_ptr_t) $%p\t " 2353 "pci reg (npi_reg_ptr_t) $%p\n", 2354 (void *)nxgep->dev_regs->nxge_regp, 2355 (void *)nxgep->dev_regs->nxge_pciregp); 2356 2357 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2358 2359 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2360 "\nBlock \t Offset \n"); 2361 2362 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2363 block = 0; 2364 #if defined(__i386) 2365 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2366 #else 2367 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2368 #endif 2369 while (reg_block[block].offset != ALL_FF_32) { 2370 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2371 "%9s\t 0x%llx\n", 2372 reg_block[block].name, 2373 (unsigned long long)(reg_block[block].offset + base)); 2374 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2375 block++; 2376 } 2377 2378 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2379 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2380 "rbrp (rx_rbr_ring_t)\n"); 2381 2382 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2383 2384 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2385 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2386 " %d\t $%p\t\t $%p\n", 2387 rdc, (void *)rcr_rings[rdc], 2388 (void *)rbr_rings[rdc]); 2389 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2390 } 2391 2392 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2393 "\nTDC\t tdcp (tx_ring_t)\n"); 2394 2395 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2396 tx_rings = nxgep->tx_rings->rings; 2397 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 2398 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2399 " %d\t $%p\n", tdc, (void *)tx_rings[tdc]); 2400 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2401 } 2402 2403 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2404 2405 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2406 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2407 return (0); 2408 } 2409 2410 2411 /* ARGSUSED */ 2412 int 2413 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2414 { 2415 ND *nd; 2416 NDE *nde; 2417 char *rwtag; 2418 boolean_t get_ok, set_ok; 2419 size_t param_len; 2420 int status = 0; 2421 2422 nd = (ND *)param; 2423 if (!nd) 2424 return (ENOENT); 2425 2426 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2427 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2428 (nde->nde_get_pfi != NULL); 2429 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2430 (nde->nde_set_pfi != NULL); 2431 if (get_ok) { 2432 if (set_ok) 2433 rwtag = "read and write"; 2434 else 2435 rwtag = "read only"; 2436 } else if (set_ok) 2437 rwtag = "write only"; 2438 else { 2439 continue; 2440 } 2441 param_len = strlen(rwtag); 2442 param_len += strlen(nde->nde_name); 2443 param_len += 4; 2444 2445 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2446 } 2447 return (status); 2448 } 2449 2450 /* ARGSUSED */ 2451 int 2452 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2453 { 2454 return (EACCES); 2455 } 2456 2457 /* ARGSUSED */ 2458 int 2459 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2460 caddr_t data) 2461 { 2462 return (EACCES); 2463 } 2464 2465 boolean_t 2466 nxge_param_link_update(p_nxge_t nxgep) 2467 { 2468 p_nxge_param_t param_arr; 2469 nxge_param_index_t i; 2470 boolean_t update_xcvr; 2471 boolean_t update_dev; 2472 int instance; 2473 boolean_t status = B_TRUE; 2474 2475 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 2476 2477 param_arr = nxgep->param_arr; 2478 instance = nxgep->instance; 2479 update_xcvr = B_FALSE; 2480 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2481 update_xcvr |= param_arr[i].value; 2482 } 2483 2484 if (update_xcvr) { 2485 update_xcvr = B_FALSE; 2486 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2487 update_xcvr |= 2488 (param_arr[i].value != param_arr[i].old_value); 2489 param_arr[i].old_value = param_arr[i].value; 2490 } 2491 if (update_xcvr) { 2492 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2493 "==> nxge_param_link_update: update xcvr")); 2494 RW_ENTER_WRITER(&nxgep->filter_lock); 2495 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2496 (void) nxge_link_init(nxgep); 2497 (void) nxge_mac_init(nxgep); 2498 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2499 RW_EXIT(&nxgep->filter_lock); 2500 } 2501 } else { 2502 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2503 " no link capabilities.", instance); 2504 cmn_err(CE_WARN, " Restoring previous setting."); 2505 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2506 param_arr[i].value = param_arr[i].old_value; 2507 } 2508 2509 update_dev = B_FALSE; 2510 2511 if (update_dev) { 2512 RW_ENTER_WRITER(&nxgep->filter_lock); 2513 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2514 "==> nxge_param_link_update: update dev")); 2515 (void) nxge_rx_mac_disable(nxgep); 2516 (void) nxge_tx_mac_disable(nxgep); 2517 (void) nxge_tx_mac_enable(nxgep); 2518 (void) nxge_rx_mac_enable(nxgep); 2519 RW_EXIT(&nxgep->filter_lock); 2520 } 2521 2522 nxge_param_hw_update_exit: 2523 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2524 "<== nxge_param_link_update status = 0x%08x", status)); 2525 return (status); 2526 } 2527 2528 /* 2529 * synchronize the adv* and en* parameters. 2530 * 2531 * See comments in <sys/dld.h> for details of the *_en_* 2532 * parameters. The usage of ndd for setting adv parameters will 2533 * synchronize all the en parameters with the nxge parameters, 2534 * implicitly disabling any settings made via dladm. 2535 */ 2536 static void 2537 nxge_param_sync(p_nxge_t nxgep) 2538 { 2539 p_nxge_param_t param_arr; 2540 param_arr = nxgep->param_arr; 2541 2542 nxgep->param_en_pause = param_arr[param_anar_pause].value; 2543 nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 2544 nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 2545 nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 2546 } 2547 2548 /* ARGSUSED */ 2549 int 2550 nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 2551 { 2552 uint32_t status, cfg_value; 2553 p_nxge_param_t pa = (p_nxge_param_t)cp; 2554 tcam_class_t class; 2555 2556 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 2557 2558 /* do the actual hw setup */ 2559 class = nxge_class_name_2value(nxgep, pa->name); 2560 if (class == -1) 2561 return (EINVAL); 2562 2563 cfg_value = 0; 2564 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 2565 if (status != NXGE_OK) 2566 return (EINVAL); 2567 2568 /* Filter out the allowed bits */ 2569 cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA | 2570 NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO | 2571 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST | 2572 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT); 2573 2574 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2575 "nxge_param_get_ip_opt_get %x ", cfg_value)); 2576 2577 pa->value = cfg_value; 2578 2579 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 2580 return (0); 2581 } 2582