xref: /titanic_52/usr/src/uts/common/io/nxge/nxge_ipp.c (revision cc7a88b54b4969574f03e1a1225bb13be487f5db)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <nxge_impl.h>
29 #include <nxge_ipp.h>
30 
31 #define	NXGE_IPP_FIFO_SYNC_TRY_COUNT 100
32 
33 /* ARGSUSED */
34 nxge_status_t
35 nxge_ipp_init(p_nxge_t nxgep)
36 {
37 	uint8_t portn;
38 	uint32_t config;
39 	npi_handle_t handle;
40 	uint32_t pkt_size;
41 	ipp_status_t istatus;
42 	npi_status_t rs = NPI_SUCCESS;
43 	uint64_t val;
44 	uint32_t d0, d1, d2, d3, d4;
45 	int i;
46 	uint32_t dfifo_entries;
47 
48 	handle = nxgep->npi_handle;
49 	portn = NXGE_GET_PORT_NUM(nxgep->function_num);
50 
51 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "==> nxge_ipp_init: port%d", portn));
52 
53 	/* Initialize ECC and parity in SRAM of DFIFO and PFIFO */
54 	if (nxgep->niu_type == N2_NIU) {
55 		dfifo_entries = IPP_NIU_DFIFO_ENTRIES;
56 	} else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
57 		if (portn < 2)
58 			dfifo_entries = IPP_P0_P1_DFIFO_ENTRIES;
59 		else
60 			dfifo_entries = IPP_P2_P3_DFIFO_ENTRIES;
61 	} else {
62 		goto fail;
63 	}
64 
65 	for (i = 0; i < dfifo_entries; i++) {
66 		if ((rs = npi_ipp_write_dfifo(handle,
67 				portn, i, 0, 0, 0, 0, 0)) != NPI_SUCCESS)
68 			goto fail;
69 		if ((rs = npi_ipp_read_dfifo(handle, portn,
70 				i, &d0, &d1, &d2, &d3, &d4)) != NPI_SUCCESS)
71 			goto fail;
72 	}
73 
74 	/* Clear PFIFO DFIFO status bits */
75 	if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS)
76 		goto fail;
77 	if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS)
78 		goto fail;
79 
80 	/*
81 	 * Soft reset to make sure we bring the FIFO pointers back to the
82 	 * original initial position.
83 	 */
84 	if ((rs = npi_ipp_reset(handle, portn)) != NPI_SUCCESS)
85 		goto fail;
86 
87 	/* Clean up ECC counter */
88 	IPP_REG_RD(nxgep->npi_handle, portn, IPP_ECC_ERR_COUNTER_REG, &val);
89 	IPP_REG_RD(nxgep->npi_handle, portn, IPP_BAD_CKSUM_ERR_CNT_REG, &val);
90 	IPP_REG_RD(nxgep->npi_handle, portn, IPP_DISCARD_PKT_CNT_REG, &val);
91 
92 	if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS)
93 		goto fail;
94 
95 	/* Configure IPP port */
96 	if ((rs = npi_ipp_iconfig(handle, INIT, portn, ICFG_IPP_ALL))
97 			!= NPI_SUCCESS)
98 		goto fail;
99 	nxgep->ipp.iconfig = ICFG_IPP_ALL;
100 
101 	config = CFG_IPP | CFG_IPP_DFIFO_ECC_CORRECT | CFG_IPP_DROP_BAD_CRC |
102 		CFG_IPP_TCP_UDP_CKSUM;
103 	if ((rs = npi_ipp_config(handle, INIT, portn, config)) != NPI_SUCCESS)
104 		goto fail;
105 	nxgep->ipp.config = config;
106 
107 	/* Set max packet size */
108 	pkt_size = IPP_MAX_PKT_SIZE;
109 	if ((rs = npi_ipp_set_max_pktsize(handle, portn,
110 			IPP_MAX_PKT_SIZE)) != NPI_SUCCESS)
111 		goto fail;
112 	nxgep->ipp.max_pkt_size = pkt_size;
113 
114 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "<== nxge_ipp_init: port%d", portn));
115 
116 	return (NXGE_OK);
117 fail:
118 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
119 			"nxge_ipp_init: Fail to initialize IPP Port #%d\n",
120 			portn));
121 	return (NXGE_ERROR | rs);
122 }
123 
124 /* ARGSUSED */
125 nxge_status_t
126 nxge_ipp_disable(p_nxge_t nxgep)
127 {
128 	uint8_t portn;
129 	uint32_t config;
130 	npi_handle_t handle;
131 	npi_status_t rs = NPI_SUCCESS;
132 	uint16_t wr_ptr, rd_ptr;
133 	uint32_t try_count;
134 
135 	handle = nxgep->npi_handle;
136 	portn = NXGE_GET_PORT_NUM(nxgep->function_num);
137 
138 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "==> nxge_ipp_disable: port%d", portn));
139 	(void) nxge_rx_mac_disable(nxgep);
140 
141 	/*
142 	 * Wait until ip read and write fifo pointers are equal
143 	 */
144 	(void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr);
145 	(void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr);
146 	try_count = NXGE_IPP_FIFO_SYNC_TRY_COUNT;
147 
148 	while ((try_count > 0) && (rd_ptr != wr_ptr)) {
149 		(void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr);
150 		(void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr);
151 		try_count--;
152 	}
153 
154 	if (try_count == 0) {
155 		if ((rd_ptr != 0) && (wr_ptr != 1)) {
156 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
157 				" nxge_ipp_disable: port%d failed"
158 				" rd_fifo != wr_fifo", portn));
159 			goto fail;
160 		}
161 	}
162 	/* disable the IPP */
163 	config = nxgep->ipp.config;
164 	if ((rs = npi_ipp_config(handle, DISABLE,
165 			portn, config)) != NPI_SUCCESS)
166 		goto fail;
167 
168 	/* IPP soft reset */
169 	if ((rs = npi_ipp_reset(handle, portn)) != NPI_SUCCESS)
170 		goto fail;
171 
172 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "<== nxge_ipp_disable: port%d", portn));
173 	return (NXGE_OK);
174 fail:
175 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
176 		"nxge_ipp_disable: Fail to disable IPP Port #%d\n", portn));
177 	return (NXGE_ERROR | rs);
178 }
179 
180 /* ARGSUSED */
181 nxge_status_t
182 nxge_ipp_reset(p_nxge_t nxgep)
183 {
184 	uint8_t portn;
185 	uint32_t config;
186 	npi_handle_t handle;
187 	npi_status_t rs = NPI_SUCCESS;
188 	uint16_t wr_ptr, rd_ptr;
189 	uint32_t try_count;
190 
191 	handle = nxgep->npi_handle;
192 	portn = NXGE_GET_PORT_NUM(nxgep->function_num);
193 
194 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "==> nxge_ipp_reset: port%d", portn));
195 
196 	/* disable the IPP */
197 	config = nxgep->ipp.config;
198 	if ((rs = npi_ipp_config(handle, DISABLE,
199 			portn, config)) != NPI_SUCCESS)
200 		goto fail;
201 
202 	/*
203 	 * Wait until ip read and write fifo pointers are equal
204 	 */
205 	(void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr);
206 	(void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr);
207 	try_count = NXGE_IPP_FIFO_SYNC_TRY_COUNT;
208 
209 	while ((try_count > 0) && (rd_ptr != wr_ptr)) {
210 		(void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr);
211 		(void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr);
212 		try_count--;
213 	}
214 
215 	if (try_count == 0) {
216 		if ((rd_ptr != 0) && (wr_ptr != 1)) {
217 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
218 				" nxge_ipp_disable: port%d failed"
219 				" rd_fifo != wr_fifo", portn));
220 			goto fail;
221 		}
222 	}
223 
224 	/* IPP soft reset */
225 	if ((rs = npi_ipp_reset(handle, portn)) != NPI_SUCCESS) {
226 		goto fail;
227 	}
228 
229 	/* to reset control FIFO */
230 	if ((rs = npi_zcp_rest_cfifo_port(handle, portn)) != NPI_SUCCESS)
231 		goto fail;
232 
233 	/*
234 	 * Making sure that error source is cleared if this is an injected
235 	 * error.
236 	 */
237 	IPP_REG_WR(handle, portn, IPP_ECC_CTRL_REG, 0);
238 
239 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "<== nxge_ipp_reset: port%d", portn));
240 	return (NXGE_OK);
241 fail:
242 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
243 			"nxge_ipp_init: Fail to Reset IPP Port #%d\n",
244 			portn));
245 	return (NXGE_ERROR | rs);
246 }
247 
248 /* ARGSUSED */
249 nxge_status_t
250 nxge_ipp_enable(p_nxge_t nxgep)
251 {
252 	uint8_t portn;
253 	uint32_t config;
254 	npi_handle_t handle;
255 	uint32_t pkt_size;
256 	npi_status_t rs = NPI_SUCCESS;
257 
258 	handle = nxgep->npi_handle;
259 	portn = NXGE_GET_PORT_NUM(nxgep->function_num);
260 
261 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "==> nxge_ipp_enable: port%d", portn));
262 
263 	config = CFG_IPP | CFG_IPP_DFIFO_ECC_CORRECT | CFG_IPP_DROP_BAD_CRC |
264 		CFG_IPP_TCP_UDP_CKSUM;
265 	if ((rs = npi_ipp_config(handle, INIT, portn, config)) != NPI_SUCCESS)
266 		goto fail;
267 	nxgep->ipp.config = config;
268 
269 	/* Set max packet size */
270 	pkt_size = IPP_MAX_PKT_SIZE;
271 	if ((rs = npi_ipp_set_max_pktsize(handle, portn,
272 			IPP_MAX_PKT_SIZE)) != NPI_SUCCESS)
273 		goto fail;
274 	nxgep->ipp.max_pkt_size = pkt_size;
275 
276 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "<== nxge_ipp_enable: port%d", portn));
277 	return (NXGE_OK);
278 fail:
279 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
280 		"nxge_ipp_init: Fail to Enable IPP Port #%d\n", portn));
281 	return (NXGE_ERROR | rs);
282 }
283 
284 /* ARGSUSED */
285 nxge_status_t
286 nxge_ipp_handle_sys_errors(p_nxge_t nxgep)
287 {
288 	npi_handle_t handle;
289 	npi_status_t rs = NPI_SUCCESS;
290 	p_nxge_ipp_stats_t statsp;
291 	ipp_status_t istatus;
292 	uint8_t portn;
293 	p_ipp_errlog_t errlogp;
294 	boolean_t rxport_fatal = B_FALSE;
295 	nxge_status_t status = NXGE_OK;
296 	uint8_t cnt8;
297 	uint16_t cnt16;
298 
299 	handle = nxgep->npi_handle;
300 	statsp = (p_nxge_ipp_stats_t)&nxgep->statsp->ipp_stats;
301 	portn = nxgep->mac.portnum;
302 
303 	errlogp = (p_ipp_errlog_t)&statsp->errlog;
304 
305 	if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS)
306 		return (NXGE_ERROR | rs);
307 
308 	if (istatus.value == 0) {
309 		/*
310 		 * The error is not initiated from this port, so just exit.
311 		 */
312 		return (NXGE_OK);
313 	}
314 
315 	if (istatus.bits.w0.dfifo_missed_sop) {
316 		statsp->sop_miss++;
317 		if ((rs = npi_ipp_get_dfifo_eopm_rdptr(handle, portn,
318 					&errlogp->dfifo_rd_ptr)) != NPI_SUCCESS)
319 			return (NXGE_ERROR | rs);
320 		if ((rs = npi_ipp_get_state_mach(handle, portn,
321 				&errlogp->state_mach)) != NPI_SUCCESS)
322 			return (NXGE_ERROR | rs);
323 		NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
324 			NXGE_FM_EREPORT_IPP_SOP_MISS);
325 		if (statsp->sop_miss < IPP_MAX_ERR_SHOW)
326 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
327 				"nxge_ipp_err_evnts: fatal error: sop_miss\n"));
328 		rxport_fatal = B_TRUE;
329 	}
330 	if (istatus.bits.w0.dfifo_missed_eop) {
331 		statsp->eop_miss++;
332 		if ((rs = npi_ipp_get_dfifo_eopm_rdptr(handle, portn,
333 				&errlogp->dfifo_rd_ptr)) != NPI_SUCCESS)
334 			return (NXGE_ERROR | rs);
335 		if ((rs = npi_ipp_get_state_mach(handle, portn,
336 				&errlogp->state_mach)) != NPI_SUCCESS)
337 			return (NXGE_ERROR | rs);
338 		NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
339 			NXGE_FM_EREPORT_IPP_EOP_MISS);
340 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
341 			"nxge_ipp_err_evnts: fatal error: eop_miss\n"));
342 		rxport_fatal = B_TRUE;
343 	}
344 	if (istatus.bits.w0.dfifo_uncorr_ecc_err) {
345 		boolean_t ue_ecc_valid;
346 
347 		if ((status = nxge_ipp_eccue_valid_check(nxgep,
348 				&ue_ecc_valid)) != NXGE_OK)
349 			return (status);
350 
351 		if (ue_ecc_valid) {
352 			statsp->dfifo_ue++;
353 			if ((rs = npi_ipp_get_ecc_syndrome(handle, portn,
354 					&errlogp->ecc_syndrome)) != NPI_SUCCESS)
355 				return (NXGE_ERROR | rs);
356 			NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
357 				NXGE_FM_EREPORT_IPP_DFIFO_UE);
358 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
359 				"nxge_ipp_err_evnts: fatal error: dfifo_ue\n"));
360 			rxport_fatal = B_TRUE;
361 		}
362 	}
363 	if (istatus.bits.w0.pre_fifo_perr) {
364 		statsp->pfifo_perr++;
365 		NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
366 			NXGE_FM_EREPORT_IPP_PFIFO_PERR);
367 		if (statsp->pfifo_perr < IPP_MAX_ERR_SHOW)
368 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
369 				"nxge_ipp_err_evnts: "
370 				"fatal error: pre_pifo_perr\n"));
371 		rxport_fatal = B_TRUE;
372 	}
373 	if (istatus.bits.w0.pre_fifo_overrun) {
374 		statsp->pfifo_over++;
375 		NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
376 			NXGE_FM_EREPORT_IPP_PFIFO_OVER);
377 		if (statsp->pfifo_over < IPP_MAX_ERR_SHOW)
378 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
379 				"nxge_ipp_err_evnts: "
380 				"fatal error: pfifo_over\n"));
381 		rxport_fatal = B_TRUE;
382 	}
383 	if (istatus.bits.w0.pre_fifo_underrun) {
384 		statsp->pfifo_und++;
385 		NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
386 			NXGE_FM_EREPORT_IPP_PFIFO_UND);
387 		if (statsp->pfifo_und < IPP_MAX_ERR_SHOW)
388 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
389 				"nxge_ipp_err_evnts: "
390 				"fatal error: pfifo_und\n"));
391 		rxport_fatal = B_TRUE;
392 	}
393 	if (istatus.bits.w0.bad_cksum_cnt_ovfl) {
394 		/*
395 		 * Do not send FMA ereport or log error message
396 		 * in /var/adm/messages because this error does not
397 		 * indicate a HW failure.
398 		 *
399 		 * Clear bit BAD_CS_MX of register IPP_INT_STAT
400 		 * by reading register IPP_BAD_CS_CNT
401 		 */
402 		(void) npi_ipp_get_cs_err_count(handle, portn, &cnt16);
403 		statsp->bad_cs_cnt += IPP_BAD_CS_CNT_MASK;
404 	}
405 	if (istatus.bits.w0.pkt_discard_cnt_ovfl) {
406 		/*
407 		 * Do not send FMA ereport or log error message
408 		 * in /var/adm/messages because this error does not
409 		 * indicate a HW failure.
410 		 *
411 		 * Clear bit PKT_DIS_MX of register IPP_INT_STAT
412 		 * by reading register IPP_PKT_DIS
413 		 */
414 		(void) npi_ipp_get_pkt_dis_count(handle, portn, &cnt16);
415 		statsp->pkt_dis_cnt += IPP_PKT_DIS_CNT_MASK;
416 	}
417 	if (istatus.bits.w0.ecc_err_cnt_ovfl) {
418 		/*
419 		 * Clear bit ECC_ERR_MAX of register IPP_INI_STAT
420 		 * by reading register IPP_ECC
421 		 */
422 		(void) npi_ipp_get_ecc_err_count(handle, portn, &cnt8);
423 		statsp->ecc_err_cnt += IPP_ECC_CNT_MASK;
424 		/*
425 		 * A defect in Neptune port2's IPP module could generate
426 		 * many fake but harmless ECC errors under stress and cause
427 		 * the ecc-error-counter register IPP_ECC to reach its
428 		 * maximum value in a few seconds. To avoid false alarm, do
429 		 * not report the error if it is port2.
430 		 */
431 		if (portn != 2) {
432 			NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
433 			    NXGE_FM_EREPORT_IPP_ECC_ERR_MAX);
434 			if (statsp->ecc_err_cnt < (IPP_MAX_ERR_SHOW *
435 			    IPP_ECC_CNT_MASK)) {
436 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
437 				    "nxge_ipp_err_evnts: pkt_ecc_err_max\n"));
438 			}
439 		}
440 	}
441 	/*
442 	 * Making sure that error source is cleared if this is an injected
443 	 * error.
444 	 */
445 	IPP_REG_WR(handle, portn, IPP_ECC_CTRL_REG, 0);
446 
447 	if (rxport_fatal) {
448 		NXGE_DEBUG_MSG((nxgep, IPP_CTL,
449 			" nxge_ipp_handle_sys_errors:"
450 			" fatal Error on  Port #%d\n", portn));
451 		status = nxge_ipp_fatal_err_recover(nxgep);
452 		if (status == NXGE_OK) {
453 			FM_SERVICE_RESTORED(nxgep);
454 		}
455 	}
456 	return (status);
457 }
458 
459 /* ARGSUSED */
460 void
461 nxge_ipp_inject_err(p_nxge_t nxgep, uint32_t err_id)
462 {
463 	ipp_status_t ipps;
464 	ipp_ecc_ctrl_t ecc_ctrl;
465 	uint8_t portn = nxgep->mac.portnum;
466 
467 	switch (err_id) {
468 	case NXGE_FM_EREPORT_IPP_DFIFO_UE:
469 		ecc_ctrl.value = 0;
470 		ecc_ctrl.bits.w0.cor_dbl = 1;
471 		ecc_ctrl.bits.w0.cor_1 = 1;
472 		ecc_ctrl.bits.w0.cor_lst = 1;
473 		cmn_err(CE_NOTE, "!Write 0x%llx to IPP_ECC_CTRL_REG\n",
474 			(unsigned long long) ecc_ctrl.value);
475 		IPP_REG_WR(nxgep->npi_handle, portn, IPP_ECC_CTRL_REG,
476 			ecc_ctrl.value);
477 		break;
478 
479 	case NXGE_FM_EREPORT_IPP_DFIFO_CE:
480 		ecc_ctrl.value = 0;
481 		ecc_ctrl.bits.w0.cor_sng = 1;
482 		ecc_ctrl.bits.w0.cor_1 = 1;
483 		ecc_ctrl.bits.w0.cor_snd = 1;
484 		cmn_err(CE_NOTE, "!Write 0x%llx to IPP_ECC_CTRL_REG\n",
485 			(unsigned long long) ecc_ctrl.value);
486 		IPP_REG_WR(nxgep->npi_handle, portn, IPP_ECC_CTRL_REG,
487 			ecc_ctrl.value);
488 		break;
489 
490 	case NXGE_FM_EREPORT_IPP_EOP_MISS:
491 	case NXGE_FM_EREPORT_IPP_SOP_MISS:
492 	case NXGE_FM_EREPORT_IPP_PFIFO_PERR:
493 	case NXGE_FM_EREPORT_IPP_ECC_ERR_MAX:
494 	case NXGE_FM_EREPORT_IPP_PFIFO_OVER:
495 	case NXGE_FM_EREPORT_IPP_PFIFO_UND:
496 	case NXGE_FM_EREPORT_IPP_BAD_CS_MX:
497 	case NXGE_FM_EREPORT_IPP_PKT_DIS_MX:
498 	case NXGE_FM_EREPORT_IPP_RESET_FAIL:
499 		IPP_REG_RD(nxgep->npi_handle, portn, IPP_INT_STATUS_REG,
500 			&ipps.value);
501 		if (err_id == NXGE_FM_EREPORT_IPP_EOP_MISS)
502 			ipps.bits.w0.dfifo_missed_eop = 1;
503 		else if (err_id == NXGE_FM_EREPORT_IPP_SOP_MISS)
504 			ipps.bits.w0.dfifo_missed_sop = 1;
505 		else if (err_id == NXGE_FM_EREPORT_IPP_DFIFO_UE)
506 			ipps.bits.w0.dfifo_uncorr_ecc_err = 1;
507 		else if (err_id == NXGE_FM_EREPORT_IPP_DFIFO_CE)
508 			ipps.bits.w0.dfifo_corr_ecc_err = 1;
509 		else if (err_id == NXGE_FM_EREPORT_IPP_PFIFO_PERR)
510 			ipps.bits.w0.pre_fifo_perr = 1;
511 		else if (err_id == NXGE_FM_EREPORT_IPP_ECC_ERR_MAX) {
512 			/*
513 			 * Fill register IPP_ECC with max ECC-error-
514 			 * counter value (0xff) to set the ECC_ERR_MAX bit
515 			 * of the IPP_INT_STAT register and trigger an
516 			 * FMA ereport.
517 			 */
518 			IPP_REG_WR(nxgep->npi_handle, portn,
519 			    IPP_ECC_ERR_COUNTER_REG, IPP_ECC_CNT_MASK);
520 		} else if (err_id == NXGE_FM_EREPORT_IPP_PFIFO_OVER)
521 			ipps.bits.w0.pre_fifo_overrun = 1;
522 		else if (err_id == NXGE_FM_EREPORT_IPP_PFIFO_UND)
523 			ipps.bits.w0.pre_fifo_underrun = 1;
524 		else if (err_id == NXGE_FM_EREPORT_IPP_BAD_CS_MX) {
525 			/*
526 			 * Fill IPP_BAD_CS_CNT with max bad-checksum-counter
527 			 * value (0x3fff) to set the BAD_CS_MX bit of
528 			 * IPP_INT_STAT and trigger an FMA ereport.
529 			 */
530 			IPP_REG_WR(nxgep->npi_handle, portn,
531 			    IPP_BAD_CKSUM_ERR_CNT_REG, IPP_BAD_CS_CNT_MASK);
532 		} else if (err_id == NXGE_FM_EREPORT_IPP_PKT_DIS_MX) {
533 			/*
534 			 * Fill IPP_PKT_DIS with max packet-discard-counter
535 			 * value (0x3fff) to set the PKT_DIS_MX bit of
536 			 * IPP_INT_STAT and trigger an FMA ereport.
537 			 */
538 			IPP_REG_WR(nxgep->npi_handle, portn,
539 			    IPP_DISCARD_PKT_CNT_REG, IPP_PKT_DIS_CNT_MASK);
540 		}
541 		cmn_err(CE_NOTE, "!Write 0x%llx to IPP_INT_STATUS_REG\n",
542 			(unsigned long long) ipps.value);
543 		IPP_REG_WR(nxgep->npi_handle, portn, IPP_INT_STATUS_REG,
544 			ipps.value);
545 		break;
546 	}
547 }
548 
549 /* ARGSUSED */
550 nxge_status_t
551 nxge_ipp_fatal_err_recover(p_nxge_t nxgep)
552 {
553 	npi_handle_t handle;
554 	npi_status_t rs = NPI_SUCCESS;
555 	nxge_status_t status = NXGE_OK;
556 	uint8_t portn;
557 	uint16_t wr_ptr;
558 	uint16_t rd_ptr;
559 	uint32_t try_count;
560 	uint32_t dfifo_entries;
561 	ipp_status_t istatus;
562 	uint32_t d0, d1, d2, d3, d4;
563 	int i;
564 
565 	NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_ipp_fatal_err_recover"));
566 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
567 		"Recovering from RxPort error..."));
568 
569 	handle = nxgep->npi_handle;
570 	portn = nxgep->mac.portnum;
571 
572 	/*
573 	 * Making sure that error source is cleared if this is an injected
574 	 * error.
575 	 */
576 	IPP_REG_WR(handle, portn, IPP_ECC_CTRL_REG, 0);
577 
578 	/* Disable RxMAC */
579 	if (nxge_rx_mac_disable(nxgep) != NXGE_OK)
580 		goto fail;
581 
582 	/* When recovering from IPP, RxDMA channel resets are not necessary */
583 	/* Reset ZCP CFIFO */
584 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Reset ZCP CFIFO...", portn));
585 	if ((rs = npi_zcp_rest_cfifo_port(handle, portn)) != NPI_SUCCESS)
586 		goto fail;
587 
588 	/*
589 	 * Wait until ip read and write fifo pointers are equal
590 	 */
591 	(void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr);
592 	(void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr);
593 	try_count = 512;
594 
595 	while ((try_count > 0) && (rd_ptr != wr_ptr)) {
596 		(void) npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr);
597 		(void) npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr);
598 		try_count--;
599 	}
600 
601 	if (try_count == 0) {
602 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
603 			" nxge_ipp_reset: port%d IPP stalled..."
604 			" rd_fifo_ptr = 0x%x wr_fifo_ptr = 0x%x",
605 			portn, rd_ptr, wr_ptr));
606 		/*
607 		 * This means the fatal error occurred on the first line of the
608 		 * fifo. In this case, just reset the IPP without draining the
609 		 * PFIFO.
610 		 */
611 	}
612 
613 	if (nxgep->niu_type == N2_NIU) {
614 		dfifo_entries = IPP_NIU_DFIFO_ENTRIES;
615 	} else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
616 		if (portn < 2)
617 			dfifo_entries = IPP_P0_P1_DFIFO_ENTRIES;
618 		else
619 			dfifo_entries = IPP_P2_P3_DFIFO_ENTRIES;
620 	} else {
621 		goto fail;
622 	}
623 
624 	/* Clean up DFIFO SRAM entries */
625 	for (i = 0; i < dfifo_entries; i++) {
626 		if ((rs = npi_ipp_write_dfifo(handle, portn,
627 				i, 0, 0, 0, 0, 0)) != NPI_SUCCESS)
628 			goto fail;
629 		if ((rs = npi_ipp_read_dfifo(handle, portn, i,
630 				&d0, &d1, &d2, &d3, &d4)) != NPI_SUCCESS)
631 			goto fail;
632 	}
633 
634 	/* Clear PFIFO DFIFO status bits */
635 	if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS)
636 		goto fail;
637 	if ((rs = npi_ipp_get_status(handle, portn, &istatus)) != NPI_SUCCESS)
638 		goto fail;
639 
640 	/* Reset IPP */
641 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Reset IPP...", portn));
642 	if ((rs = npi_ipp_reset(handle, portn)) != NPI_SUCCESS)
643 		goto fail;
644 
645 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Reset RxMAC...", portn));
646 	if (nxge_rx_mac_reset(nxgep) != NXGE_OK)
647 		goto fail;
648 
649 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Initialize RxMAC...", portn));
650 	if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK)
651 		goto fail;
652 
653 	NXGE_DEBUG_MSG((nxgep, IPP_CTL, "port%d Enable RxMAC...", portn));
654 	if (nxge_rx_mac_enable(nxgep) != NXGE_OK)
655 		goto fail;
656 
657 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
658 		"Recovery successful, RxPort restored"));
659 	NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_ipp_fatal_err_recover"));
660 
661 	return (NXGE_OK);
662 fail:
663 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed"));
664 	return (status | rs);
665 }
666 
667 /* ARGSUSED */
668 /*
669  *    A hardware bug may cause fake ECCUEs (ECC Uncorrectable Error).
670  * This function checks if a ECCUE is real(valid) or not.  It is not
671  * real if rd_ptr == wr_ptr.
672  *    The hardware module that has the bug is used not only by the IPP
673  * FIFO but also by the ZCP FIFO, therefore this function is also
674  * called by nxge_zcp_handle_sys_errors for validating the ZCP FIFO
675  * error.
676  */
677 nxge_status_t
678 nxge_ipp_eccue_valid_check(p_nxge_t nxgep, boolean_t *valid)
679 {
680 	npi_handle_t handle;
681 	npi_status_t rs = NPI_SUCCESS;
682 	uint8_t portn;
683 	uint16_t rd_ptr;
684 	uint16_t wr_ptr;
685 	uint16_t curr_rd_ptr;
686 	uint16_t curr_wr_ptr;
687 	uint32_t stall_cnt;
688 	uint32_t d0, d1, d2, d3, d4;
689 
690 	handle = nxgep->npi_handle;
691 	portn = nxgep->mac.portnum;
692 	*valid = B_TRUE;
693 
694 	if ((rs = npi_ipp_get_dfifo_rd_ptr(handle, portn, &rd_ptr))
695 		!= NPI_SUCCESS)
696 		goto fail;
697 	if ((rs = npi_ipp_get_dfifo_wr_ptr(handle, portn, &wr_ptr))
698 		!= NPI_SUCCESS)
699 		goto fail;
700 
701 	if (rd_ptr == wr_ptr) {
702 		*valid = B_FALSE; /* FIFO not stuck, so it's not a real ECCUE */
703 	} else {
704 		stall_cnt = 0;
705 		/*
706 		 * Check if the two pointers are moving, the ECCUE is invali
707 		 * if either pointer is moving, which indicates that the FIFO
708 		 * is functional.
709 		 */
710 		while (stall_cnt < 16) {
711 			if ((rs = npi_ipp_get_dfifo_rd_ptr(handle,
712 					portn, &curr_rd_ptr)) != NPI_SUCCESS)
713 				goto fail;
714 			if ((rs = npi_ipp_get_dfifo_wr_ptr(handle,
715 					portn, &curr_wr_ptr)) != NPI_SUCCESS)
716 				goto fail;
717 
718 			if (rd_ptr == curr_rd_ptr && wr_ptr == curr_wr_ptr) {
719 				stall_cnt++;
720 			} else {
721 				*valid = B_FALSE;
722 				break;
723 			}
724 		}
725 
726 		if (valid) {
727 			/*
728 			 * Further check to see if the ECCUE is valid. The
729 			 * error is real if the LSB of d4 is 1, which
730 			 * indicates that the data that has set the ECC
731 			 * error flag is the 16-byte internal control word.
732 			 */
733 			if ((rs = npi_ipp_read_dfifo(handle, portn, rd_ptr,
734 			    &d0, &d1, &d2, &d3, &d4)) != NPI_SUCCESS)
735 				goto fail;
736 			if ((d4 & 0x1) == 0)	/* Not the 1st line */
737 				*valid = B_FALSE;
738 		}
739 	}
740 	return (NXGE_OK);
741 fail:
742 	return (NXGE_ERROR | rs);
743 }
744