1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.18"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 static void e1000g_pch_limits(struct e1000g *); 98 static uint32_t e1000g_mtu2maxframe(uint32_t); 99 100 /* 101 * Local routines 102 */ 103 static boolean_t e1000g_reset_adapter(struct e1000g *); 104 static void e1000g_tx_clean(struct e1000g *); 105 static void e1000g_rx_clean(struct e1000g *); 106 static void e1000g_link_timer(void *); 107 static void e1000g_local_timer(void *); 108 static boolean_t e1000g_link_check(struct e1000g *); 109 static boolean_t e1000g_stall_check(struct e1000g *); 110 static void e1000g_smartspeed(struct e1000g *); 111 static void e1000g_get_conf(struct e1000g *); 112 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 113 static void enable_watchdog_timer(struct e1000g *); 114 static void disable_watchdog_timer(struct e1000g *); 115 static void start_watchdog_timer(struct e1000g *); 116 static void restart_watchdog_timer(struct e1000g *); 117 static void stop_watchdog_timer(struct e1000g *); 118 static void stop_link_timer(struct e1000g *); 119 static void stop_82547_timer(e1000g_tx_ring_t *); 120 static void e1000g_force_speed_duplex(struct e1000g *); 121 static void e1000g_setup_max_mtu(struct e1000g *); 122 static void e1000g_get_max_frame_size(struct e1000g *); 123 static boolean_t is_valid_mac_addr(uint8_t *); 124 static void e1000g_unattach(dev_info_t *, struct e1000g *); 125 #ifdef E1000G_DEBUG 126 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 127 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 128 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 130 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 131 struct iocblk *, mblk_t *); 132 #endif 133 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 134 struct iocblk *, mblk_t *); 135 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 136 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 137 static void e1000g_set_internal_loopback(struct e1000g *); 138 static void e1000g_set_external_loopback_1000(struct e1000g *); 139 static void e1000g_set_external_loopback_100(struct e1000g *); 140 static void e1000g_set_external_loopback_10(struct e1000g *); 141 static int e1000g_add_intrs(struct e1000g *); 142 static int e1000g_intr_add(struct e1000g *, int); 143 static int e1000g_rem_intrs(struct e1000g *); 144 static int e1000g_enable_intrs(struct e1000g *); 145 static int e1000g_disable_intrs(struct e1000g *); 146 static boolean_t e1000g_link_up(struct e1000g *); 147 #ifdef __sparc 148 static boolean_t e1000g_find_mac_address(struct e1000g *); 149 #endif 150 static void e1000g_get_phy_state(struct e1000g *); 151 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 152 const void *impl_data); 153 static void e1000g_fm_init(struct e1000g *Adapter); 154 static void e1000g_fm_fini(struct e1000g *Adapter); 155 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 156 static void e1000g_param_sync(struct e1000g *); 157 static void e1000g_get_driver_control(struct e1000_hw *); 158 static void e1000g_release_driver_control(struct e1000_hw *); 159 static void e1000g_restore_promisc(struct e1000g *Adapter); 160 161 mac_priv_prop_t e1000g_priv_props[] = { 162 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 164 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 167 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 168 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 169 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 170 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 171 {"_intr_adaptive", MAC_PROP_PERM_RW}, 172 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 173 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 174 }; 175 #define E1000G_MAX_PRIV_PROPS \ 176 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 177 178 179 static struct cb_ops cb_ws_ops = { 180 nulldev, /* cb_open */ 181 nulldev, /* cb_close */ 182 nodev, /* cb_strategy */ 183 nodev, /* cb_print */ 184 nodev, /* cb_dump */ 185 nodev, /* cb_read */ 186 nodev, /* cb_write */ 187 nodev, /* cb_ioctl */ 188 nodev, /* cb_devmap */ 189 nodev, /* cb_mmap */ 190 nodev, /* cb_segmap */ 191 nochpoll, /* cb_chpoll */ 192 ddi_prop_op, /* cb_prop_op */ 193 NULL, /* cb_stream */ 194 D_MP | D_HOTPLUG, /* cb_flag */ 195 CB_REV, /* cb_rev */ 196 nodev, /* cb_aread */ 197 nodev /* cb_awrite */ 198 }; 199 200 static struct dev_ops ws_ops = { 201 DEVO_REV, /* devo_rev */ 202 0, /* devo_refcnt */ 203 NULL, /* devo_getinfo */ 204 nulldev, /* devo_identify */ 205 nulldev, /* devo_probe */ 206 e1000g_attach, /* devo_attach */ 207 e1000g_detach, /* devo_detach */ 208 nodev, /* devo_reset */ 209 &cb_ws_ops, /* devo_cb_ops */ 210 NULL, /* devo_bus_ops */ 211 ddi_power, /* devo_power */ 212 e1000g_quiesce /* devo_quiesce */ 213 }; 214 215 static struct modldrv modldrv = { 216 &mod_driverops, /* Type of module. This one is a driver */ 217 ident, /* Discription string */ 218 &ws_ops, /* driver ops */ 219 }; 220 221 static struct modlinkage modlinkage = { 222 MODREV_1, &modldrv, NULL 223 }; 224 225 /* Access attributes for register mapping */ 226 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 227 DDI_DEVICE_ATTR_V1, 228 DDI_STRUCTURE_LE_ACC, 229 DDI_STRICTORDER_ACC, 230 DDI_FLAGERR_ACC 231 }; 232 233 #define E1000G_M_CALLBACK_FLAGS \ 234 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 235 236 static mac_callbacks_t e1000g_m_callbacks = { 237 E1000G_M_CALLBACK_FLAGS, 238 e1000g_m_stat, 239 e1000g_m_start, 240 e1000g_m_stop, 241 e1000g_m_promisc, 242 e1000g_m_multicst, 243 NULL, 244 e1000g_m_tx, 245 e1000g_m_ioctl, 246 e1000g_m_getcapab, 247 NULL, 248 NULL, 249 e1000g_m_setprop, 250 e1000g_m_getprop 251 }; 252 253 /* 254 * Global variables 255 */ 256 uint32_t e1000g_mblks_pending = 0; 257 /* 258 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 259 * Here we maintain a private dev_info list if e1000g_force_detach is 260 * enabled. If we force the driver to detach while there are still some 261 * rx buffers retained in the upper layer, we have to keep a copy of the 262 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 263 * structure will be freed after the driver is detached. However when we 264 * finally free those rx buffers released by the upper layer, we need to 265 * refer to the dev_info to free the dma buffers. So we save a copy of 266 * the dev_info for this purpose. On x86 platform, we assume this copy 267 * of dev_info is always valid, but on SPARC platform, it could be invalid 268 * after the system board level DR operation. For this reason, the global 269 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 270 */ 271 #ifdef __sparc 272 boolean_t e1000g_force_detach = B_FALSE; 273 #else 274 boolean_t e1000g_force_detach = B_TRUE; 275 #endif 276 private_devi_list_t *e1000g_private_devi_list = NULL; 277 278 /* 279 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 280 * the private dev_info list, and to serialize the processing of rx buffer 281 * freeing and rx buffer recycling. 282 */ 283 kmutex_t e1000g_rx_detach_lock; 284 /* 285 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 286 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 287 * If there are many e1000g instances, the system may run out of DVMA 288 * resources during the initialization of the instances, then the flag will 289 * be changed to "USE_DMA". Because different e1000g instances are initialized 290 * in parallel, we need to use this lock to protect the flag. 291 */ 292 krwlock_t e1000g_dma_type_lock; 293 294 /* 295 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 296 * Based on the information from Intel, the 82546 chipset has some hardware 297 * problem. When one port is being reset and the other port is trying to 298 * access the eeprom, it could cause system hang or panic. To workaround this 299 * hardware problem, we use a global mutex to prevent such operations from 300 * happening simultaneously on different instances. This workaround is applied 301 * to all the devices supported by this driver. 302 */ 303 kmutex_t e1000g_nvm_lock; 304 305 /* 306 * Loadable module configuration entry points for the driver 307 */ 308 309 /* 310 * _init - module initialization 311 */ 312 int 313 _init(void) 314 { 315 int status; 316 317 mac_init_ops(&ws_ops, WSNAME); 318 status = mod_install(&modlinkage); 319 if (status != DDI_SUCCESS) 320 mac_fini_ops(&ws_ops); 321 else { 322 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 323 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 324 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 325 } 326 327 return (status); 328 } 329 330 /* 331 * _fini - module finalization 332 */ 333 int 334 _fini(void) 335 { 336 int status; 337 338 if (e1000g_mblks_pending != 0) 339 return (EBUSY); 340 341 status = mod_remove(&modlinkage); 342 if (status == DDI_SUCCESS) { 343 mac_fini_ops(&ws_ops); 344 345 if (e1000g_force_detach) { 346 private_devi_list_t *devi_node; 347 348 mutex_enter(&e1000g_rx_detach_lock); 349 while (e1000g_private_devi_list != NULL) { 350 devi_node = e1000g_private_devi_list; 351 e1000g_private_devi_list = 352 e1000g_private_devi_list->next; 353 354 kmem_free(devi_node->priv_dip, 355 sizeof (struct dev_info)); 356 kmem_free(devi_node, 357 sizeof (private_devi_list_t)); 358 } 359 mutex_exit(&e1000g_rx_detach_lock); 360 } 361 362 mutex_destroy(&e1000g_rx_detach_lock); 363 rw_destroy(&e1000g_dma_type_lock); 364 mutex_destroy(&e1000g_nvm_lock); 365 } 366 367 return (status); 368 } 369 370 /* 371 * _info - module information 372 */ 373 int 374 _info(struct modinfo *modinfop) 375 { 376 return (mod_info(&modlinkage, modinfop)); 377 } 378 379 /* 380 * e1000g_attach - driver attach 381 * 382 * This function is the device-specific initialization entry 383 * point. This entry point is required and must be written. 384 * The DDI_ATTACH command must be provided in the attach entry 385 * point. When attach() is called with cmd set to DDI_ATTACH, 386 * all normal kernel services (such as kmem_alloc(9F)) are 387 * available for use by the driver. 388 * 389 * The attach() function will be called once for each instance 390 * of the device on the system with cmd set to DDI_ATTACH. 391 * Until attach() succeeds, the only driver entry points which 392 * may be called are open(9E) and getinfo(9E). 393 */ 394 static int 395 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 396 { 397 struct e1000g *Adapter; 398 struct e1000_hw *hw; 399 struct e1000g_osdep *osdep; 400 int instance; 401 402 switch (cmd) { 403 default: 404 e1000g_log(NULL, CE_WARN, 405 "Unsupported command send to e1000g_attach... "); 406 return (DDI_FAILURE); 407 408 case DDI_RESUME: 409 return (e1000g_resume(devinfo)); 410 411 case DDI_ATTACH: 412 break; 413 } 414 415 /* 416 * get device instance number 417 */ 418 instance = ddi_get_instance(devinfo); 419 420 /* 421 * Allocate soft data structure 422 */ 423 Adapter = 424 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 425 426 Adapter->dip = devinfo; 427 Adapter->instance = instance; 428 Adapter->tx_ring->adapter = Adapter; 429 Adapter->rx_ring->adapter = Adapter; 430 431 hw = &Adapter->shared; 432 osdep = &Adapter->osdep; 433 hw->back = osdep; 434 osdep->adapter = Adapter; 435 436 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 437 438 /* 439 * Initialize for fma support 440 */ 441 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 442 0, 0x0f, 443 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 444 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 445 e1000g_fm_init(Adapter); 446 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 447 448 /* 449 * PCI Configure 450 */ 451 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 452 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 453 goto attach_fail; 454 } 455 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 456 457 /* 458 * Setup hardware 459 */ 460 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 461 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 462 goto attach_fail; 463 } 464 465 /* 466 * Map in the device registers. 467 */ 468 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 469 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 470 goto attach_fail; 471 } 472 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 473 474 /* 475 * Initialize driver parameters 476 */ 477 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 478 goto attach_fail; 479 } 480 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 481 482 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 483 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 484 goto attach_fail; 485 } 486 487 /* 488 * Initialize interrupts 489 */ 490 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 491 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 492 goto attach_fail; 493 } 494 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 495 496 /* 497 * Initialize mutex's for this device. 498 * Do this before enabling the interrupt handler and 499 * register the softint to avoid the condition where 500 * interrupt handler can try using uninitialized mutex 501 */ 502 e1000g_init_locks(Adapter); 503 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 504 505 /* 506 * Initialize Driver Counters 507 */ 508 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 509 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 510 goto attach_fail; 511 } 512 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 513 514 /* 515 * Initialize chip hardware and software structures 516 */ 517 rw_enter(&Adapter->chip_lock, RW_WRITER); 518 if (e1000g_init(Adapter) != DDI_SUCCESS) { 519 rw_exit(&Adapter->chip_lock); 520 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 521 goto attach_fail; 522 } 523 rw_exit(&Adapter->chip_lock); 524 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 525 526 /* 527 * Register the driver to the MAC 528 */ 529 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 530 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 531 goto attach_fail; 532 } 533 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 534 535 /* 536 * Now that mutex locks are initialized, and the chip is also 537 * initialized, enable interrupts. 538 */ 539 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 540 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 541 goto attach_fail; 542 } 543 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 544 545 /* 546 * If e1000g_force_detach is enabled, in global private dip list, 547 * we will create a new entry, which maintains the priv_dip for DR 548 * supports after driver detached. 549 */ 550 if (e1000g_force_detach) { 551 private_devi_list_t *devi_node; 552 553 Adapter->priv_dip = 554 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 555 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 556 sizeof (struct dev_info)); 557 558 devi_node = 559 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 560 561 mutex_enter(&e1000g_rx_detach_lock); 562 devi_node->priv_dip = Adapter->priv_dip; 563 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 564 devi_node->pending_rx_count = 0; 565 566 Adapter->priv_devi_node = devi_node; 567 568 if (e1000g_private_devi_list == NULL) { 569 devi_node->prev = NULL; 570 devi_node->next = NULL; 571 e1000g_private_devi_list = devi_node; 572 } else { 573 devi_node->prev = NULL; 574 devi_node->next = e1000g_private_devi_list; 575 e1000g_private_devi_list->prev = devi_node; 576 e1000g_private_devi_list = devi_node; 577 } 578 mutex_exit(&e1000g_rx_detach_lock); 579 } 580 581 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 582 Adapter->e1000g_state = E1000G_INITIALIZED; 583 584 return (DDI_SUCCESS); 585 586 attach_fail: 587 e1000g_unattach(devinfo, Adapter); 588 return (DDI_FAILURE); 589 } 590 591 static int 592 e1000g_register_mac(struct e1000g *Adapter) 593 { 594 struct e1000_hw *hw = &Adapter->shared; 595 mac_register_t *mac; 596 int err; 597 598 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 599 return (DDI_FAILURE); 600 601 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 602 mac->m_driver = Adapter; 603 mac->m_dip = Adapter->dip; 604 mac->m_src_addr = hw->mac.addr; 605 mac->m_callbacks = &e1000g_m_callbacks; 606 mac->m_min_sdu = 0; 607 mac->m_max_sdu = Adapter->default_mtu; 608 mac->m_margin = VLAN_TAGSZ; 609 mac->m_priv_props = e1000g_priv_props; 610 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 611 mac->m_v12n = MAC_VIRT_LEVEL1; 612 613 err = mac_register(mac, &Adapter->mh); 614 mac_free(mac); 615 616 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 617 } 618 619 static int 620 e1000g_identify_hardware(struct e1000g *Adapter) 621 { 622 struct e1000_hw *hw = &Adapter->shared; 623 struct e1000g_osdep *osdep = &Adapter->osdep; 624 625 /* Get the device id */ 626 hw->vendor_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 628 hw->device_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 630 hw->revision_id = 631 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 632 hw->subsystem_device_id = 633 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 634 hw->subsystem_vendor_id = 635 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 636 637 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 638 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 639 "MAC type could not be set properly."); 640 return (DDI_FAILURE); 641 } 642 643 return (DDI_SUCCESS); 644 } 645 646 static int 647 e1000g_regs_map(struct e1000g *Adapter) 648 { 649 dev_info_t *devinfo = Adapter->dip; 650 struct e1000_hw *hw = &Adapter->shared; 651 struct e1000g_osdep *osdep = &Adapter->osdep; 652 off_t mem_size; 653 654 /* Get size of adapter register memory */ 655 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 656 DDI_SUCCESS) { 657 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 658 "ddi_dev_regsize for registers failed"); 659 return (DDI_FAILURE); 660 } 661 662 /* Map adapter register memory */ 663 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 664 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 665 &osdep->reg_handle)) != DDI_SUCCESS) { 666 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 667 "ddi_regs_map_setup for registers failed"); 668 goto regs_map_fail; 669 } 670 671 /* ICH needs to map flash memory */ 672 if (hw->mac.type == e1000_ich8lan || 673 hw->mac.type == e1000_ich9lan || 674 hw->mac.type == e1000_ich10lan || 675 hw->mac.type == e1000_pchlan) { 676 /* get flash size */ 677 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 678 &mem_size) != DDI_SUCCESS) { 679 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 680 "ddi_dev_regsize for ICH flash failed"); 681 goto regs_map_fail; 682 } 683 684 /* map flash in */ 685 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 686 (caddr_t *)&hw->flash_address, 0, 687 mem_size, &e1000g_regs_acc_attr, 688 &osdep->ich_flash_handle) != DDI_SUCCESS) { 689 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 690 "ddi_regs_map_setup for ICH flash failed"); 691 goto regs_map_fail; 692 } 693 } 694 695 return (DDI_SUCCESS); 696 697 regs_map_fail: 698 if (osdep->reg_handle != NULL) 699 ddi_regs_map_free(&osdep->reg_handle); 700 701 return (DDI_FAILURE); 702 } 703 704 static int 705 e1000g_set_driver_params(struct e1000g *Adapter) 706 { 707 struct e1000_hw *hw; 708 uint32_t mem_bar, io_bar, bar64; 709 710 hw = &Adapter->shared; 711 712 /* Set MAC type and initialize hardware functions */ 713 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 714 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 715 "Could not setup hardware functions"); 716 return (DDI_FAILURE); 717 } 718 719 /* Get bus information */ 720 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 721 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 722 "Could not get bus information"); 723 return (DDI_FAILURE); 724 } 725 726 /* get mem_base addr */ 727 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 728 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 729 730 /* get io_base addr */ 731 if (hw->mac.type >= e1000_82544) { 732 if (bar64) { 733 /* IO BAR is different for 64 bit BAR mode */ 734 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 735 PCI_CONF_BASE4); 736 } else { 737 /* normal 32-bit BAR mode */ 738 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 739 PCI_CONF_BASE2); 740 } 741 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 742 } else { 743 /* no I/O access for adapters prior to 82544 */ 744 hw->io_base = 0x0; 745 } 746 747 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 748 749 hw->mac.autoneg_failed = B_TRUE; 750 751 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 752 hw->phy.autoneg_wait_to_complete = B_FALSE; 753 754 /* Adaptive IFS related changes */ 755 hw->mac.adaptive_ifs = B_TRUE; 756 757 /* Enable phy init script for IGP phy of 82541/82547 */ 758 if ((hw->mac.type == e1000_82547) || 759 (hw->mac.type == e1000_82541) || 760 (hw->mac.type == e1000_82547_rev_2) || 761 (hw->mac.type == e1000_82541_rev_2)) 762 e1000_init_script_state_82541(hw, B_TRUE); 763 764 /* Enable the TTL workaround for 82541/82547 */ 765 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 766 767 #ifdef __sparc 768 Adapter->strip_crc = B_TRUE; 769 #else 770 Adapter->strip_crc = B_FALSE; 771 #endif 772 773 /* setup the maximum MTU size of the chip */ 774 e1000g_setup_max_mtu(Adapter); 775 776 /* Get conf file properties */ 777 e1000g_get_conf(Adapter); 778 779 /* Get speed/duplex settings in conf file */ 780 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 781 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 782 e1000g_force_speed_duplex(Adapter); 783 784 /* Get Jumbo Frames settings in conf file */ 785 e1000g_get_max_frame_size(Adapter); 786 787 /* enforce PCH limits */ 788 e1000g_pch_limits(Adapter); 789 790 /* Set Rx/Tx buffer size */ 791 e1000g_set_bufsize(Adapter); 792 793 /* Master Latency Timer */ 794 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 795 796 /* copper options */ 797 if (hw->phy.media_type == e1000_media_type_copper) { 798 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 799 hw->phy.disable_polarity_correction = B_FALSE; 800 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 801 } 802 803 /* The initial link state should be "unknown" */ 804 Adapter->link_state = LINK_STATE_UNKNOWN; 805 806 /* Initialize rx parameters */ 807 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 808 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 809 810 /* Initialize tx parameters */ 811 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 812 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 813 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 814 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 815 816 /* Initialize rx parameters */ 817 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 818 819 return (DDI_SUCCESS); 820 } 821 822 static void 823 e1000g_setup_max_mtu(struct e1000g *Adapter) 824 { 825 struct e1000_mac_info *mac = &Adapter->shared.mac; 826 struct e1000_phy_info *phy = &Adapter->shared.phy; 827 828 switch (mac->type) { 829 /* types that do not support jumbo frames */ 830 case e1000_ich8lan: 831 case e1000_82573: 832 case e1000_82583: 833 Adapter->max_mtu = ETHERMTU; 834 break; 835 /* ich9 supports jumbo frames except on one phy type */ 836 case e1000_ich9lan: 837 if (phy->type == e1000_phy_ife) 838 Adapter->max_mtu = ETHERMTU; 839 else 840 Adapter->max_mtu = MAXIMUM_MTU_9K; 841 break; 842 /* pch can do jumbo frames up to 4K */ 843 case e1000_pchlan: 844 Adapter->max_mtu = MAXIMUM_MTU_4K; 845 break; 846 /* types with a special limit */ 847 case e1000_82571: 848 case e1000_82572: 849 case e1000_82574: 850 case e1000_80003es2lan: 851 case e1000_ich10lan: 852 Adapter->max_mtu = MAXIMUM_MTU_9K; 853 break; 854 /* default limit is 16K */ 855 default: 856 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 857 sizeof (struct ether_vlan_header) - ETHERFCSL - 858 E1000G_IPALIGNPRESERVEROOM; 859 break; 860 } 861 } 862 863 static void 864 e1000g_set_bufsize(struct e1000g *Adapter) 865 { 866 struct e1000_mac_info *mac = &Adapter->shared.mac; 867 uint64_t rx_size; 868 uint64_t tx_size; 869 870 dev_info_t *devinfo = Adapter->dip; 871 #ifdef __sparc 872 ulong_t iommu_pagesize; 873 #endif 874 /* Get the system page size */ 875 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 876 877 #ifdef __sparc 878 iommu_pagesize = dvma_pagesize(devinfo); 879 if (iommu_pagesize != 0) { 880 if (Adapter->sys_page_sz == iommu_pagesize) { 881 if (iommu_pagesize > 0x4000) 882 Adapter->sys_page_sz = 0x4000; 883 } else { 884 if (Adapter->sys_page_sz > iommu_pagesize) 885 Adapter->sys_page_sz = iommu_pagesize; 886 } 887 } 888 if (Adapter->lso_enable) { 889 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 890 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 891 } else { 892 Adapter->dvma_page_num = Adapter->max_frame_size / 893 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 894 } 895 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 896 #endif 897 898 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 899 900 if (Adapter->mem_workaround_82546 && 901 ((mac->type == e1000_82545) || 902 (mac->type == e1000_82546) || 903 (mac->type == e1000_82546_rev_3))) { 904 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 905 } else { 906 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 907 if ((rx_size > FRAME_SIZE_UPTO_2K) && 908 (rx_size <= FRAME_SIZE_UPTO_4K)) 909 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 910 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 911 (rx_size <= FRAME_SIZE_UPTO_8K)) 912 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 913 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 914 (rx_size <= FRAME_SIZE_UPTO_16K)) 915 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 916 else 917 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 918 } 919 920 tx_size = Adapter->max_frame_size; 921 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 922 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 923 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 924 (tx_size <= FRAME_SIZE_UPTO_8K)) 925 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 926 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 927 (tx_size <= FRAME_SIZE_UPTO_16K)) 928 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 929 else 930 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 931 932 /* 933 * For Wiseman adapters we have an requirement of having receive 934 * buffers aligned at 256 byte boundary. Since Livengood does not 935 * require this and forcing it for all hardwares will have 936 * performance implications, I am making it applicable only for 937 * Wiseman and for Jumbo frames enabled mode as rest of the time, 938 * it is okay to have normal frames...but it does involve a 939 * potential risk where we may loose data if buffer is not 940 * aligned...so all wiseman boards to have 256 byte aligned 941 * buffers 942 */ 943 if (mac->type < e1000_82543) 944 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 945 else 946 Adapter->rx_buf_align = 1; 947 } 948 949 /* 950 * e1000g_detach - driver detach 951 * 952 * The detach() function is the complement of the attach routine. 953 * If cmd is set to DDI_DETACH, detach() is used to remove the 954 * state associated with a given instance of a device node 955 * prior to the removal of that instance from the system. 956 * 957 * The detach() function will be called once for each instance 958 * of the device for which there has been a successful attach() 959 * once there are no longer any opens on the device. 960 * 961 * Interrupts routine are disabled, All memory allocated by this 962 * driver are freed. 963 */ 964 static int 965 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 966 { 967 struct e1000g *Adapter; 968 boolean_t rx_drain; 969 970 switch (cmd) { 971 default: 972 return (DDI_FAILURE); 973 974 case DDI_SUSPEND: 975 return (e1000g_suspend(devinfo)); 976 977 case DDI_DETACH: 978 break; 979 } 980 981 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 982 if (Adapter == NULL) 983 return (DDI_FAILURE); 984 985 rx_drain = e1000g_rx_drain(Adapter); 986 if (!rx_drain && !e1000g_force_detach) 987 return (DDI_FAILURE); 988 989 if (mac_unregister(Adapter->mh) != 0) { 990 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 991 return (DDI_FAILURE); 992 } 993 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 994 995 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 996 997 if (!e1000g_force_detach && !rx_drain) 998 return (DDI_FAILURE); 999 1000 e1000g_unattach(devinfo, Adapter); 1001 1002 return (DDI_SUCCESS); 1003 } 1004 1005 /* 1006 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1007 */ 1008 void 1009 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1010 { 1011 ASSERT(e1000g_private_devi_list != NULL); 1012 ASSERT(devi_node != NULL); 1013 1014 if (devi_node->prev != NULL) 1015 devi_node->prev->next = devi_node->next; 1016 if (devi_node->next != NULL) 1017 devi_node->next->prev = devi_node->prev; 1018 if (devi_node == e1000g_private_devi_list) 1019 e1000g_private_devi_list = devi_node->next; 1020 1021 kmem_free(devi_node->priv_dip, 1022 sizeof (struct dev_info)); 1023 kmem_free(devi_node, 1024 sizeof (private_devi_list_t)); 1025 } 1026 1027 static void 1028 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1029 { 1030 private_devi_list_t *devi_node; 1031 int result; 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1034 (void) e1000g_disable_intrs(Adapter); 1035 } 1036 1037 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1038 (void) mac_unregister(Adapter->mh); 1039 } 1040 1041 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1042 (void) e1000g_rem_intrs(Adapter); 1043 } 1044 1045 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1046 (void) ddi_prop_remove_all(devinfo); 1047 } 1048 1049 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1050 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1051 } 1052 1053 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1054 stop_link_timer(Adapter); 1055 1056 mutex_enter(&e1000g_nvm_lock); 1057 result = e1000_reset_hw(&Adapter->shared); 1058 mutex_exit(&e1000g_nvm_lock); 1059 1060 if (result != E1000_SUCCESS) { 1061 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1062 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1063 } 1064 } 1065 1066 e1000g_release_multicast(Adapter); 1067 1068 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1069 if (Adapter->osdep.reg_handle != NULL) 1070 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1071 if (Adapter->osdep.ich_flash_handle != NULL) 1072 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1073 } 1074 1075 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1076 if (Adapter->osdep.cfg_handle != NULL) 1077 pci_config_teardown(&Adapter->osdep.cfg_handle); 1078 } 1079 1080 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1081 e1000g_destroy_locks(Adapter); 1082 } 1083 1084 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1085 e1000g_fm_fini(Adapter); 1086 } 1087 1088 mutex_enter(&e1000g_rx_detach_lock); 1089 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1090 devi_node = Adapter->priv_devi_node; 1091 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1092 1093 if (devi_node->pending_rx_count == 0) { 1094 e1000g_free_priv_devi_node(devi_node); 1095 } 1096 } 1097 mutex_exit(&e1000g_rx_detach_lock); 1098 1099 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1100 1101 /* 1102 * Another hotplug spec requirement, 1103 * run ddi_set_driver_private(devinfo, null); 1104 */ 1105 ddi_set_driver_private(devinfo, NULL); 1106 } 1107 1108 static void 1109 e1000g_init_locks(struct e1000g *Adapter) 1110 { 1111 e1000g_tx_ring_t *tx_ring; 1112 e1000g_rx_ring_t *rx_ring; 1113 1114 rw_init(&Adapter->chip_lock, NULL, 1115 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1116 mutex_init(&Adapter->link_lock, NULL, 1117 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1118 mutex_init(&Adapter->watchdog_lock, NULL, 1119 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1120 1121 tx_ring = Adapter->tx_ring; 1122 1123 mutex_init(&tx_ring->tx_lock, NULL, 1124 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1125 mutex_init(&tx_ring->usedlist_lock, NULL, 1126 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1127 mutex_init(&tx_ring->freelist_lock, NULL, 1128 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1129 1130 rx_ring = Adapter->rx_ring; 1131 1132 mutex_init(&rx_ring->rx_lock, NULL, 1133 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1134 } 1135 1136 static void 1137 e1000g_destroy_locks(struct e1000g *Adapter) 1138 { 1139 e1000g_tx_ring_t *tx_ring; 1140 e1000g_rx_ring_t *rx_ring; 1141 1142 tx_ring = Adapter->tx_ring; 1143 mutex_destroy(&tx_ring->tx_lock); 1144 mutex_destroy(&tx_ring->usedlist_lock); 1145 mutex_destroy(&tx_ring->freelist_lock); 1146 1147 rx_ring = Adapter->rx_ring; 1148 mutex_destroy(&rx_ring->rx_lock); 1149 1150 mutex_destroy(&Adapter->link_lock); 1151 mutex_destroy(&Adapter->watchdog_lock); 1152 rw_destroy(&Adapter->chip_lock); 1153 1154 /* destory mutex initialized in shared code */ 1155 e1000_destroy_hw_mutex(&Adapter->shared); 1156 } 1157 1158 static int 1159 e1000g_resume(dev_info_t *devinfo) 1160 { 1161 struct e1000g *Adapter; 1162 1163 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1164 if (Adapter == NULL) 1165 e1000g_log(Adapter, CE_PANIC, 1166 "Instance pointer is null\n"); 1167 1168 if (Adapter->dip != devinfo) 1169 e1000g_log(Adapter, CE_PANIC, 1170 "Devinfo is not the same as saved devinfo\n"); 1171 1172 rw_enter(&Adapter->chip_lock, RW_WRITER); 1173 1174 if (Adapter->e1000g_state & E1000G_STARTED) { 1175 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1176 rw_exit(&Adapter->chip_lock); 1177 /* 1178 * We note the failure, but return success, as the 1179 * system is still usable without this controller. 1180 */ 1181 e1000g_log(Adapter, CE_WARN, 1182 "e1000g_resume: failed to restart controller\n"); 1183 return (DDI_SUCCESS); 1184 } 1185 /* Enable and start the watchdog timer */ 1186 enable_watchdog_timer(Adapter); 1187 } 1188 1189 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1190 1191 rw_exit(&Adapter->chip_lock); 1192 1193 return (DDI_SUCCESS); 1194 } 1195 1196 static int 1197 e1000g_suspend(dev_info_t *devinfo) 1198 { 1199 struct e1000g *Adapter; 1200 1201 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1202 if (Adapter == NULL) 1203 return (DDI_FAILURE); 1204 1205 rw_enter(&Adapter->chip_lock, RW_WRITER); 1206 1207 Adapter->e1000g_state |= E1000G_SUSPENDED; 1208 1209 /* if the port isn't plumbed, we can simply return */ 1210 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1211 rw_exit(&Adapter->chip_lock); 1212 return (DDI_SUCCESS); 1213 } 1214 1215 e1000g_stop(Adapter, B_FALSE); 1216 1217 rw_exit(&Adapter->chip_lock); 1218 1219 /* Disable and stop all the timers */ 1220 disable_watchdog_timer(Adapter); 1221 stop_link_timer(Adapter); 1222 stop_82547_timer(Adapter->tx_ring); 1223 1224 return (DDI_SUCCESS); 1225 } 1226 1227 static int 1228 e1000g_init(struct e1000g *Adapter) 1229 { 1230 uint32_t pba; 1231 uint32_t high_water; 1232 struct e1000_hw *hw; 1233 clock_t link_timeout; 1234 int result; 1235 1236 hw = &Adapter->shared; 1237 1238 /* 1239 * reset to put the hardware in a known state 1240 * before we try to do anything with the eeprom 1241 */ 1242 mutex_enter(&e1000g_nvm_lock); 1243 result = e1000_reset_hw(hw); 1244 mutex_exit(&e1000g_nvm_lock); 1245 1246 if (result != E1000_SUCCESS) { 1247 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1248 goto init_fail; 1249 } 1250 1251 mutex_enter(&e1000g_nvm_lock); 1252 result = e1000_validate_nvm_checksum(hw); 1253 if (result < E1000_SUCCESS) { 1254 /* 1255 * Some PCI-E parts fail the first check due to 1256 * the link being in sleep state. Call it again, 1257 * if it fails a second time its a real issue. 1258 */ 1259 result = e1000_validate_nvm_checksum(hw); 1260 } 1261 mutex_exit(&e1000g_nvm_lock); 1262 1263 if (result < E1000_SUCCESS) { 1264 e1000g_log(Adapter, CE_WARN, 1265 "Invalid NVM checksum. Please contact " 1266 "the vendor to update the NVM."); 1267 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1268 goto init_fail; 1269 } 1270 1271 result = 0; 1272 #ifdef __sparc 1273 /* 1274 * First, we try to get the local ethernet address from OBP. If 1275 * failed, then we get it from the EEPROM of NIC card. 1276 */ 1277 result = e1000g_find_mac_address(Adapter); 1278 #endif 1279 /* Get the local ethernet address. */ 1280 if (!result) { 1281 mutex_enter(&e1000g_nvm_lock); 1282 result = e1000_read_mac_addr(hw); 1283 mutex_exit(&e1000g_nvm_lock); 1284 } 1285 1286 if (result < E1000_SUCCESS) { 1287 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1288 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1289 goto init_fail; 1290 } 1291 1292 /* check for valid mac address */ 1293 if (!is_valid_mac_addr(hw->mac.addr)) { 1294 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1295 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1296 goto init_fail; 1297 } 1298 1299 /* Set LAA state for 82571 chipset */ 1300 e1000_set_laa_state_82571(hw, B_TRUE); 1301 1302 /* Master Latency Timer implementation */ 1303 if (Adapter->master_latency_timer) { 1304 pci_config_put8(Adapter->osdep.cfg_handle, 1305 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1306 } 1307 1308 if (hw->mac.type < e1000_82547) { 1309 /* 1310 * Total FIFO is 64K 1311 */ 1312 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1313 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1314 else 1315 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1316 } else if ((hw->mac.type == e1000_82571) || 1317 (hw->mac.type == e1000_82572) || 1318 (hw->mac.type == e1000_80003es2lan)) { 1319 /* 1320 * Total FIFO is 48K 1321 */ 1322 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1323 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1324 else 1325 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1326 } else if (hw->mac.type == e1000_82573) { 1327 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1328 } else if (hw->mac.type == e1000_82574) { 1329 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1330 pba = E1000_READ_REG(hw, E1000_PBA); 1331 } else if (hw->mac.type == e1000_ich8lan) { 1332 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1333 } else if (hw->mac.type == e1000_ich9lan) { 1334 pba = E1000_PBA_10K; 1335 } else if (hw->mac.type == e1000_ich10lan) { 1336 pba = E1000_PBA_10K; 1337 } else if (hw->mac.type == e1000_pchlan) { 1338 pba = E1000_PBA_26K; 1339 } else { 1340 /* 1341 * Total FIFO is 40K 1342 */ 1343 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1344 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1345 else 1346 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1347 } 1348 E1000_WRITE_REG(hw, E1000_PBA, pba); 1349 1350 /* 1351 * These parameters set thresholds for the adapter's generation(Tx) 1352 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1353 * settings. Flow control is enabled or disabled in the configuration 1354 * file. 1355 * High-water mark is set down from the top of the rx fifo (not 1356 * sensitive to max_frame_size) and low-water is set just below 1357 * high-water mark. 1358 * The high water mark must be low enough to fit one full frame above 1359 * it in the rx FIFO. Should be the lower of: 1360 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1361 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1362 * Rx FIFO size minus one full frame. 1363 */ 1364 high_water = min(((pba << 10) * 9 / 10), 1365 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1366 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1367 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1368 ((pba << 10) - Adapter->max_frame_size))); 1369 1370 hw->fc.high_water = high_water & 0xFFF8; 1371 hw->fc.low_water = hw->fc.high_water - 8; 1372 1373 if (hw->mac.type == e1000_80003es2lan) 1374 hw->fc.pause_time = 0xFFFF; 1375 else 1376 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1377 hw->fc.send_xon = B_TRUE; 1378 1379 /* 1380 * Reset the adapter hardware the second time. 1381 */ 1382 mutex_enter(&e1000g_nvm_lock); 1383 result = e1000_reset_hw(hw); 1384 mutex_exit(&e1000g_nvm_lock); 1385 1386 if (result != E1000_SUCCESS) { 1387 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1388 goto init_fail; 1389 } 1390 1391 /* disable wakeup control by default */ 1392 if (hw->mac.type >= e1000_82544) 1393 E1000_WRITE_REG(hw, E1000_WUC, 0); 1394 1395 /* 1396 * MWI should be disabled on 82546. 1397 */ 1398 if (hw->mac.type == e1000_82546) 1399 e1000_pci_clear_mwi(hw); 1400 else 1401 e1000_pci_set_mwi(hw); 1402 1403 /* 1404 * Configure/Initialize hardware 1405 */ 1406 mutex_enter(&e1000g_nvm_lock); 1407 result = e1000_init_hw(hw); 1408 mutex_exit(&e1000g_nvm_lock); 1409 1410 if (result < E1000_SUCCESS) { 1411 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1412 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1413 goto init_fail; 1414 } 1415 1416 /* 1417 * Restore LED settings to the default from EEPROM 1418 * to meet the standard for Sun platforms. 1419 */ 1420 (void) e1000_cleanup_led(hw); 1421 1422 /* Disable Smart Power Down */ 1423 phy_spd_state(hw, B_FALSE); 1424 1425 /* Make sure driver has control */ 1426 e1000g_get_driver_control(hw); 1427 1428 /* 1429 * Initialize unicast addresses. 1430 */ 1431 e1000g_init_unicst(Adapter); 1432 1433 /* 1434 * Setup and initialize the mctable structures. After this routine 1435 * completes Multicast table will be set 1436 */ 1437 e1000_update_mc_addr_list(hw, 1438 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1439 msec_delay(5); 1440 1441 /* 1442 * Implement Adaptive IFS 1443 */ 1444 e1000_reset_adaptive(hw); 1445 1446 /* Setup Interrupt Throttling Register */ 1447 if (hw->mac.type >= e1000_82540) { 1448 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1449 } else 1450 Adapter->intr_adaptive = B_FALSE; 1451 1452 /* Start the timer for link setup */ 1453 if (hw->mac.autoneg) 1454 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1455 else 1456 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1457 1458 mutex_enter(&Adapter->link_lock); 1459 if (hw->phy.autoneg_wait_to_complete) { 1460 Adapter->link_complete = B_TRUE; 1461 } else { 1462 Adapter->link_complete = B_FALSE; 1463 Adapter->link_tid = timeout(e1000g_link_timer, 1464 (void *)Adapter, link_timeout); 1465 } 1466 mutex_exit(&Adapter->link_lock); 1467 1468 /* Save the state of the phy */ 1469 e1000g_get_phy_state(Adapter); 1470 1471 e1000g_param_sync(Adapter); 1472 1473 Adapter->init_count++; 1474 1475 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1476 goto init_fail; 1477 } 1478 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1479 goto init_fail; 1480 } 1481 1482 Adapter->poll_mode = e1000g_poll_mode; 1483 1484 return (DDI_SUCCESS); 1485 1486 init_fail: 1487 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1488 return (DDI_FAILURE); 1489 } 1490 1491 static int 1492 e1000g_alloc_rx_data(struct e1000g *Adapter) 1493 { 1494 e1000g_rx_ring_t *rx_ring; 1495 e1000g_rx_data_t *rx_data; 1496 1497 rx_ring = Adapter->rx_ring; 1498 1499 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1500 1501 if (rx_data == NULL) 1502 return (DDI_FAILURE); 1503 1504 rx_data->priv_devi_node = Adapter->priv_devi_node; 1505 rx_data->rx_ring = rx_ring; 1506 1507 mutex_init(&rx_data->freelist_lock, NULL, 1508 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1509 mutex_init(&rx_data->recycle_lock, NULL, 1510 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1511 1512 rx_ring->rx_data = rx_data; 1513 1514 return (DDI_SUCCESS); 1515 } 1516 1517 void 1518 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1519 { 1520 rx_sw_packet_t *packet, *next_packet; 1521 1522 if (rx_data == NULL) 1523 return; 1524 1525 packet = rx_data->packet_area; 1526 while (packet != NULL) { 1527 next_packet = packet->next; 1528 e1000g_free_rx_sw_packet(packet, B_TRUE); 1529 packet = next_packet; 1530 } 1531 rx_data->packet_area = NULL; 1532 } 1533 1534 void 1535 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1536 { 1537 if (rx_data == NULL) 1538 return; 1539 1540 mutex_destroy(&rx_data->freelist_lock); 1541 mutex_destroy(&rx_data->recycle_lock); 1542 1543 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1544 } 1545 1546 /* 1547 * Check if the link is up 1548 */ 1549 static boolean_t 1550 e1000g_link_up(struct e1000g *Adapter) 1551 { 1552 struct e1000_hw *hw = &Adapter->shared; 1553 boolean_t link_up = B_FALSE; 1554 1555 /* 1556 * get_link_status is set in the interrupt handler on link-status-change 1557 * or rx sequence error interrupt. get_link_status will stay 1558 * false until the e1000_check_for_link establishes link only 1559 * for copper adapters. 1560 */ 1561 switch (hw->phy.media_type) { 1562 case e1000_media_type_copper: 1563 if (hw->mac.get_link_status) { 1564 (void) e1000_check_for_link(hw); 1565 link_up = !hw->mac.get_link_status; 1566 } else { 1567 link_up = B_TRUE; 1568 } 1569 break; 1570 case e1000_media_type_fiber: 1571 (void) e1000_check_for_link(hw); 1572 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1573 E1000_STATUS_LU); 1574 break; 1575 case e1000_media_type_internal_serdes: 1576 (void) e1000_check_for_link(hw); 1577 link_up = hw->mac.serdes_has_link; 1578 break; 1579 } 1580 1581 return (link_up); 1582 } 1583 1584 static void 1585 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1586 { 1587 struct iocblk *iocp; 1588 struct e1000g *e1000gp; 1589 enum ioc_reply status; 1590 1591 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1592 iocp->ioc_error = 0; 1593 e1000gp = (struct e1000g *)arg; 1594 1595 ASSERT(e1000gp); 1596 if (e1000gp == NULL) { 1597 miocnak(q, mp, 0, EINVAL); 1598 return; 1599 } 1600 1601 rw_enter(&e1000gp->chip_lock, RW_READER); 1602 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1603 rw_exit(&e1000gp->chip_lock); 1604 miocnak(q, mp, 0, EINVAL); 1605 return; 1606 } 1607 rw_exit(&e1000gp->chip_lock); 1608 1609 switch (iocp->ioc_cmd) { 1610 1611 case LB_GET_INFO_SIZE: 1612 case LB_GET_INFO: 1613 case LB_GET_MODE: 1614 case LB_SET_MODE: 1615 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1616 break; 1617 1618 1619 #ifdef E1000G_DEBUG 1620 case E1000G_IOC_REG_PEEK: 1621 case E1000G_IOC_REG_POKE: 1622 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1623 break; 1624 case E1000G_IOC_CHIP_RESET: 1625 e1000gp->reset_count++; 1626 if (e1000g_reset_adapter(e1000gp)) 1627 status = IOC_ACK; 1628 else 1629 status = IOC_INVAL; 1630 break; 1631 #endif 1632 default: 1633 status = IOC_INVAL; 1634 break; 1635 } 1636 1637 /* 1638 * Decide how to reply 1639 */ 1640 switch (status) { 1641 default: 1642 case IOC_INVAL: 1643 /* 1644 * Error, reply with a NAK and EINVAL or the specified error 1645 */ 1646 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1647 EINVAL : iocp->ioc_error); 1648 break; 1649 1650 case IOC_DONE: 1651 /* 1652 * OK, reply already sent 1653 */ 1654 break; 1655 1656 case IOC_ACK: 1657 /* 1658 * OK, reply with an ACK 1659 */ 1660 miocack(q, mp, 0, 0); 1661 break; 1662 1663 case IOC_REPLY: 1664 /* 1665 * OK, send prepared reply as ACK or NAK 1666 */ 1667 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1668 M_IOCACK : M_IOCNAK; 1669 qreply(q, mp); 1670 break; 1671 } 1672 } 1673 1674 /* 1675 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1676 * capable of supporting only one interrupt and we shouldn't disable 1677 * the physical interrupt. In this case we let the interrupt come and 1678 * we queue the packets in the rx ring itself in case we are in polling 1679 * mode (better latency but slightly lower performance and a very 1680 * high intrrupt count in mpstat which is harmless). 1681 * 1682 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1683 * which can be disabled in poll mode. This gives better overall 1684 * throughput (compared to the mode above), shows very low interrupt 1685 * count but has slightly higher latency since we pick the packets when 1686 * the poll thread does polling. 1687 * 1688 * Currently, this flag should be enabled only while doing performance 1689 * measurement or when it can be guaranteed that entire NIC going 1690 * in poll mode will not harm any traffic like cluster heartbeat etc. 1691 */ 1692 int e1000g_poll_mode = 0; 1693 1694 /* 1695 * Called from the upper layers when driver is in polling mode to 1696 * pick up any queued packets. Care should be taken to not block 1697 * this thread. 1698 */ 1699 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1700 { 1701 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1702 mblk_t *mp = NULL; 1703 mblk_t *tail; 1704 struct e1000g *adapter; 1705 1706 adapter = rx_ring->adapter; 1707 1708 rw_enter(&adapter->chip_lock, RW_READER); 1709 1710 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1711 rw_exit(&adapter->chip_lock); 1712 return (NULL); 1713 } 1714 1715 mutex_enter(&rx_ring->rx_lock); 1716 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1717 mutex_exit(&rx_ring->rx_lock); 1718 rw_exit(&adapter->chip_lock); 1719 return (mp); 1720 } 1721 1722 static int 1723 e1000g_m_start(void *arg) 1724 { 1725 struct e1000g *Adapter = (struct e1000g *)arg; 1726 1727 rw_enter(&Adapter->chip_lock, RW_WRITER); 1728 1729 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1730 rw_exit(&Adapter->chip_lock); 1731 return (ECANCELED); 1732 } 1733 1734 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1735 rw_exit(&Adapter->chip_lock); 1736 return (ENOTACTIVE); 1737 } 1738 1739 Adapter->e1000g_state |= E1000G_STARTED; 1740 1741 rw_exit(&Adapter->chip_lock); 1742 1743 /* Enable and start the watchdog timer */ 1744 enable_watchdog_timer(Adapter); 1745 1746 return (0); 1747 } 1748 1749 static int 1750 e1000g_start(struct e1000g *Adapter, boolean_t global) 1751 { 1752 e1000g_rx_data_t *rx_data; 1753 1754 if (global) { 1755 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1756 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1757 goto start_fail; 1758 } 1759 1760 /* Allocate dma resources for descriptors and buffers */ 1761 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1762 e1000g_log(Adapter, CE_WARN, 1763 "Alloc DMA resources failed"); 1764 goto start_fail; 1765 } 1766 Adapter->rx_buffer_setup = B_FALSE; 1767 } 1768 1769 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1770 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1771 e1000g_log(Adapter, CE_WARN, 1772 "Adapter initialization failed"); 1773 goto start_fail; 1774 } 1775 } 1776 1777 /* Setup and initialize the transmit structures */ 1778 e1000g_tx_setup(Adapter); 1779 msec_delay(5); 1780 1781 /* Setup and initialize the receive structures */ 1782 e1000g_rx_setup(Adapter); 1783 msec_delay(5); 1784 1785 /* Restore the e1000g promiscuous mode */ 1786 e1000g_restore_promisc(Adapter); 1787 1788 e1000g_mask_interrupt(Adapter); 1789 1790 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1791 1792 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1793 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1794 goto start_fail; 1795 } 1796 1797 return (DDI_SUCCESS); 1798 1799 start_fail: 1800 rx_data = Adapter->rx_ring->rx_data; 1801 1802 if (global) { 1803 e1000g_release_dma_resources(Adapter); 1804 e1000g_free_rx_pending_buffers(rx_data); 1805 e1000g_free_rx_data(rx_data); 1806 } 1807 1808 mutex_enter(&e1000g_nvm_lock); 1809 (void) e1000_reset_hw(&Adapter->shared); 1810 mutex_exit(&e1000g_nvm_lock); 1811 1812 return (DDI_FAILURE); 1813 } 1814 1815 static void 1816 e1000g_m_stop(void *arg) 1817 { 1818 struct e1000g *Adapter = (struct e1000g *)arg; 1819 1820 /* Drain tx sessions */ 1821 (void) e1000g_tx_drain(Adapter); 1822 1823 rw_enter(&Adapter->chip_lock, RW_WRITER); 1824 1825 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1826 rw_exit(&Adapter->chip_lock); 1827 return; 1828 } 1829 Adapter->e1000g_state &= ~E1000G_STARTED; 1830 e1000g_stop(Adapter, B_TRUE); 1831 1832 rw_exit(&Adapter->chip_lock); 1833 1834 /* Disable and stop all the timers */ 1835 disable_watchdog_timer(Adapter); 1836 stop_link_timer(Adapter); 1837 stop_82547_timer(Adapter->tx_ring); 1838 } 1839 1840 static void 1841 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1842 { 1843 private_devi_list_t *devi_node; 1844 e1000g_rx_data_t *rx_data; 1845 int result; 1846 1847 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1848 1849 /* Stop the chip and release pending resources */ 1850 1851 /* Tell firmware driver is no longer in control */ 1852 e1000g_release_driver_control(&Adapter->shared); 1853 1854 e1000g_clear_all_interrupts(Adapter); 1855 1856 mutex_enter(&e1000g_nvm_lock); 1857 result = e1000_reset_hw(&Adapter->shared); 1858 mutex_exit(&e1000g_nvm_lock); 1859 1860 if (result != E1000_SUCCESS) { 1861 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1862 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1863 } 1864 1865 /* Release resources still held by the TX descriptors */ 1866 e1000g_tx_clean(Adapter); 1867 1868 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1869 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1870 1871 /* Clean the pending rx jumbo packet fragment */ 1872 e1000g_rx_clean(Adapter); 1873 1874 if (global) { 1875 e1000g_release_dma_resources(Adapter); 1876 1877 mutex_enter(&e1000g_rx_detach_lock); 1878 rx_data = Adapter->rx_ring->rx_data; 1879 rx_data->flag |= E1000G_RX_STOPPED; 1880 1881 if (rx_data->pending_count == 0) { 1882 e1000g_free_rx_pending_buffers(rx_data); 1883 e1000g_free_rx_data(rx_data); 1884 } else { 1885 devi_node = rx_data->priv_devi_node; 1886 if (devi_node != NULL) 1887 atomic_inc_32(&devi_node->pending_rx_count); 1888 else 1889 atomic_inc_32(&Adapter->pending_rx_count); 1890 } 1891 mutex_exit(&e1000g_rx_detach_lock); 1892 } 1893 1894 if (Adapter->link_state == LINK_STATE_UP) { 1895 Adapter->link_state = LINK_STATE_UNKNOWN; 1896 mac_link_update(Adapter->mh, Adapter->link_state); 1897 } 1898 } 1899 1900 static void 1901 e1000g_rx_clean(struct e1000g *Adapter) 1902 { 1903 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 1904 1905 if (rx_data == NULL) 1906 return; 1907 1908 if (rx_data->rx_mblk != NULL) { 1909 freemsg(rx_data->rx_mblk); 1910 rx_data->rx_mblk = NULL; 1911 rx_data->rx_mblk_tail = NULL; 1912 rx_data->rx_mblk_len = 0; 1913 } 1914 } 1915 1916 static void 1917 e1000g_tx_clean(struct e1000g *Adapter) 1918 { 1919 e1000g_tx_ring_t *tx_ring; 1920 p_tx_sw_packet_t packet; 1921 mblk_t *mp; 1922 mblk_t *nmp; 1923 uint32_t packet_count; 1924 1925 tx_ring = Adapter->tx_ring; 1926 1927 /* 1928 * Here we don't need to protect the lists using 1929 * the usedlist_lock and freelist_lock, for they 1930 * have been protected by the chip_lock. 1931 */ 1932 mp = NULL; 1933 nmp = NULL; 1934 packet_count = 0; 1935 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1936 while (packet != NULL) { 1937 if (packet->mp != NULL) { 1938 /* Assemble the message chain */ 1939 if (mp == NULL) { 1940 mp = packet->mp; 1941 nmp = packet->mp; 1942 } else { 1943 nmp->b_next = packet->mp; 1944 nmp = packet->mp; 1945 } 1946 /* Disconnect the message from the sw packet */ 1947 packet->mp = NULL; 1948 } 1949 1950 e1000g_free_tx_swpkt(packet); 1951 packet_count++; 1952 1953 packet = (p_tx_sw_packet_t) 1954 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1955 } 1956 1957 if (mp != NULL) 1958 freemsgchain(mp); 1959 1960 if (packet_count > 0) { 1961 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1962 QUEUE_INIT_LIST(&tx_ring->used_list); 1963 1964 /* Setup TX descriptor pointers */ 1965 tx_ring->tbd_next = tx_ring->tbd_first; 1966 tx_ring->tbd_oldest = tx_ring->tbd_first; 1967 1968 /* Setup our HW Tx Head & Tail descriptor pointers */ 1969 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1970 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1971 } 1972 } 1973 1974 static boolean_t 1975 e1000g_tx_drain(struct e1000g *Adapter) 1976 { 1977 int i; 1978 boolean_t done; 1979 e1000g_tx_ring_t *tx_ring; 1980 1981 tx_ring = Adapter->tx_ring; 1982 1983 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1984 for (i = 0; i < TX_DRAIN_TIME; i++) { 1985 mutex_enter(&tx_ring->usedlist_lock); 1986 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1987 mutex_exit(&tx_ring->usedlist_lock); 1988 1989 if (done) 1990 break; 1991 1992 msec_delay(1); 1993 } 1994 1995 return (done); 1996 } 1997 1998 static boolean_t 1999 e1000g_rx_drain(struct e1000g *Adapter) 2000 { 2001 int i; 2002 boolean_t done; 2003 2004 /* 2005 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2006 */ 2007 for (i = 0; i < RX_DRAIN_TIME; i++) { 2008 done = (Adapter->pending_rx_count == 0); 2009 2010 if (done) 2011 break; 2012 2013 msec_delay(1); 2014 } 2015 2016 return (done); 2017 } 2018 2019 static boolean_t 2020 e1000g_reset_adapter(struct e1000g *Adapter) 2021 { 2022 /* Disable and stop all the timers */ 2023 disable_watchdog_timer(Adapter); 2024 stop_link_timer(Adapter); 2025 stop_82547_timer(Adapter->tx_ring); 2026 2027 rw_enter(&Adapter->chip_lock, RW_WRITER); 2028 2029 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2030 rw_exit(&Adapter->chip_lock); 2031 return (B_TRUE); 2032 } 2033 2034 e1000g_stop(Adapter, B_FALSE); 2035 2036 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2037 rw_exit(&Adapter->chip_lock); 2038 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2039 return (B_FALSE); 2040 } 2041 2042 rw_exit(&Adapter->chip_lock); 2043 2044 /* Enable and start the watchdog timer */ 2045 enable_watchdog_timer(Adapter); 2046 2047 return (B_TRUE); 2048 } 2049 2050 boolean_t 2051 e1000g_global_reset(struct e1000g *Adapter) 2052 { 2053 /* Disable and stop all the timers */ 2054 disable_watchdog_timer(Adapter); 2055 stop_link_timer(Adapter); 2056 stop_82547_timer(Adapter->tx_ring); 2057 2058 rw_enter(&Adapter->chip_lock, RW_WRITER); 2059 2060 e1000g_stop(Adapter, B_TRUE); 2061 2062 Adapter->init_count = 0; 2063 2064 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2065 rw_exit(&Adapter->chip_lock); 2066 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2067 return (B_FALSE); 2068 } 2069 2070 rw_exit(&Adapter->chip_lock); 2071 2072 /* Enable and start the watchdog timer */ 2073 enable_watchdog_timer(Adapter); 2074 2075 return (B_TRUE); 2076 } 2077 2078 /* 2079 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2080 * 2081 * This interrupt service routine is for PCI-Express adapters. 2082 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2083 * bit is set. 2084 */ 2085 static uint_t 2086 e1000g_intr_pciexpress(caddr_t arg) 2087 { 2088 struct e1000g *Adapter; 2089 uint32_t icr; 2090 2091 Adapter = (struct e1000g *)(uintptr_t)arg; 2092 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2093 2094 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2095 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2096 return (DDI_INTR_CLAIMED); 2097 } 2098 2099 if (icr & E1000_ICR_INT_ASSERTED) { 2100 /* 2101 * E1000_ICR_INT_ASSERTED bit was set: 2102 * Read(Clear) the ICR, claim this interrupt, 2103 * look for work to do. 2104 */ 2105 e1000g_intr_work(Adapter, icr); 2106 return (DDI_INTR_CLAIMED); 2107 } else { 2108 /* 2109 * E1000_ICR_INT_ASSERTED bit was not set: 2110 * Don't claim this interrupt, return immediately. 2111 */ 2112 return (DDI_INTR_UNCLAIMED); 2113 } 2114 } 2115 2116 /* 2117 * e1000g_intr - ISR for PCI/PCI-X chipsets 2118 * 2119 * This interrupt service routine is for PCI/PCI-X adapters. 2120 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2121 * bit is set or not. 2122 */ 2123 static uint_t 2124 e1000g_intr(caddr_t arg) 2125 { 2126 struct e1000g *Adapter; 2127 uint32_t icr; 2128 2129 Adapter = (struct e1000g *)(uintptr_t)arg; 2130 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2131 2132 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2133 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2134 return (DDI_INTR_CLAIMED); 2135 } 2136 2137 if (icr) { 2138 /* 2139 * Any bit was set in ICR: 2140 * Read(Clear) the ICR, claim this interrupt, 2141 * look for work to do. 2142 */ 2143 e1000g_intr_work(Adapter, icr); 2144 return (DDI_INTR_CLAIMED); 2145 } else { 2146 /* 2147 * No bit was set in ICR: 2148 * Don't claim this interrupt, return immediately. 2149 */ 2150 return (DDI_INTR_UNCLAIMED); 2151 } 2152 } 2153 2154 /* 2155 * e1000g_intr_work - actual processing of ISR 2156 * 2157 * Read(clear) the ICR contents and call appropriate interrupt 2158 * processing routines. 2159 */ 2160 static void 2161 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2162 { 2163 struct e1000_hw *hw; 2164 hw = &Adapter->shared; 2165 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2166 2167 Adapter->rx_pkt_cnt = 0; 2168 Adapter->tx_pkt_cnt = 0; 2169 2170 rw_enter(&Adapter->chip_lock, RW_READER); 2171 2172 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2173 rw_exit(&Adapter->chip_lock); 2174 return; 2175 } 2176 /* 2177 * Here we need to check the "e1000g_state" flag within the chip_lock to 2178 * ensure the receive routine will not execute when the adapter is 2179 * being reset. 2180 */ 2181 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2182 rw_exit(&Adapter->chip_lock); 2183 return; 2184 } 2185 2186 if (icr & E1000_ICR_RXT0) { 2187 mblk_t *mp = NULL; 2188 mblk_t *tail = NULL; 2189 e1000g_rx_ring_t *rx_ring; 2190 2191 rx_ring = Adapter->rx_ring; 2192 mutex_enter(&rx_ring->rx_lock); 2193 /* 2194 * Sometimes with legacy interrupts, it possible that 2195 * there is a single interrupt for Rx/Tx. In which 2196 * case, if poll flag is set, we shouldn't really 2197 * be doing Rx processing. 2198 */ 2199 if (!rx_ring->poll_flag) 2200 mp = e1000g_receive(rx_ring, &tail, 2201 E1000G_CHAIN_NO_LIMIT); 2202 mutex_exit(&rx_ring->rx_lock); 2203 rw_exit(&Adapter->chip_lock); 2204 if (mp != NULL) 2205 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2206 mp, rx_ring->ring_gen_num); 2207 } else 2208 rw_exit(&Adapter->chip_lock); 2209 2210 if (icr & E1000_ICR_TXDW) { 2211 if (!Adapter->tx_intr_enable) 2212 e1000g_clear_tx_interrupt(Adapter); 2213 2214 /* Recycle the tx descriptors */ 2215 rw_enter(&Adapter->chip_lock, RW_READER); 2216 (void) e1000g_recycle(tx_ring); 2217 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2218 rw_exit(&Adapter->chip_lock); 2219 2220 if (tx_ring->resched_needed && 2221 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2222 tx_ring->resched_needed = B_FALSE; 2223 mac_tx_update(Adapter->mh); 2224 E1000G_STAT(tx_ring->stat_reschedule); 2225 } 2226 } 2227 2228 /* 2229 * The Receive Sequence errors RXSEQ and the link status change LSC 2230 * are checked to detect that the cable has been pulled out. For 2231 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2232 * are an indication that cable is not connected. 2233 */ 2234 if ((icr & E1000_ICR_RXSEQ) || 2235 (icr & E1000_ICR_LSC) || 2236 (icr & E1000_ICR_GPI_EN1)) { 2237 boolean_t link_changed; 2238 timeout_id_t tid = 0; 2239 2240 stop_watchdog_timer(Adapter); 2241 2242 rw_enter(&Adapter->chip_lock, RW_WRITER); 2243 2244 /* 2245 * Because we got a link-status-change interrupt, force 2246 * e1000_check_for_link() to look at phy 2247 */ 2248 Adapter->shared.mac.get_link_status = B_TRUE; 2249 2250 /* e1000g_link_check takes care of link status change */ 2251 link_changed = e1000g_link_check(Adapter); 2252 2253 /* Get new phy state */ 2254 e1000g_get_phy_state(Adapter); 2255 2256 /* 2257 * If the link timer has not timed out, we'll not notify 2258 * the upper layer with any link state until the link is up. 2259 */ 2260 if (link_changed && !Adapter->link_complete) { 2261 if (Adapter->link_state == LINK_STATE_UP) { 2262 mutex_enter(&Adapter->link_lock); 2263 Adapter->link_complete = B_TRUE; 2264 tid = Adapter->link_tid; 2265 Adapter->link_tid = 0; 2266 mutex_exit(&Adapter->link_lock); 2267 } else { 2268 link_changed = B_FALSE; 2269 } 2270 } 2271 rw_exit(&Adapter->chip_lock); 2272 2273 if (link_changed) { 2274 if (tid != 0) 2275 (void) untimeout(tid); 2276 2277 /* 2278 * Workaround for esb2. Data stuck in fifo on a link 2279 * down event. Stop receiver here and reset in watchdog. 2280 */ 2281 if ((Adapter->link_state == LINK_STATE_DOWN) && 2282 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2283 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2284 E1000_WRITE_REG(hw, E1000_RCTL, 2285 rctl & ~E1000_RCTL_EN); 2286 e1000g_log(Adapter, CE_WARN, 2287 "ESB2 receiver disabled"); 2288 Adapter->esb2_workaround = B_TRUE; 2289 } 2290 if (!Adapter->reset_flag) 2291 mac_link_update(Adapter->mh, 2292 Adapter->link_state); 2293 if (Adapter->link_state == LINK_STATE_UP) 2294 Adapter->reset_flag = B_FALSE; 2295 } 2296 2297 start_watchdog_timer(Adapter); 2298 } 2299 } 2300 2301 static void 2302 e1000g_init_unicst(struct e1000g *Adapter) 2303 { 2304 struct e1000_hw *hw; 2305 int slot; 2306 2307 hw = &Adapter->shared; 2308 2309 if (Adapter->init_count == 0) { 2310 /* Initialize the multiple unicast addresses */ 2311 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2312 2313 /* Workaround for an erratum of 82571 chipst */ 2314 if ((hw->mac.type == e1000_82571) && 2315 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2316 Adapter->unicst_total--; 2317 2318 Adapter->unicst_avail = Adapter->unicst_total; 2319 2320 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2321 /* Clear both the flag and MAC address */ 2322 Adapter->unicst_addr[slot].reg.high = 0; 2323 Adapter->unicst_addr[slot].reg.low = 0; 2324 } 2325 } else { 2326 /* Workaround for an erratum of 82571 chipst */ 2327 if ((hw->mac.type == e1000_82571) && 2328 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2329 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2330 2331 /* Re-configure the RAR registers */ 2332 for (slot = 0; slot < Adapter->unicst_total; slot++) 2333 if (Adapter->unicst_addr[slot].mac.set == 1) 2334 e1000_rar_set(hw, 2335 Adapter->unicst_addr[slot].mac.addr, slot); 2336 } 2337 2338 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2339 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2340 } 2341 2342 static int 2343 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2344 int slot) 2345 { 2346 struct e1000_hw *hw; 2347 2348 hw = &Adapter->shared; 2349 2350 /* 2351 * The first revision of Wiseman silicon (rev 2.0) has an errata 2352 * that requires the receiver to be in reset when any of the 2353 * receive address registers (RAR regs) are accessed. The first 2354 * rev of Wiseman silicon also requires MWI to be disabled when 2355 * a global reset or a receive reset is issued. So before we 2356 * initialize the RARs, we check the rev of the Wiseman controller 2357 * and work around any necessary HW errata. 2358 */ 2359 if ((hw->mac.type == e1000_82542) && 2360 (hw->revision_id == E1000_REVISION_2)) { 2361 e1000_pci_clear_mwi(hw); 2362 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2363 msec_delay(5); 2364 } 2365 if (mac_addr == NULL) { 2366 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2367 E1000_WRITE_FLUSH(hw); 2368 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2369 E1000_WRITE_FLUSH(hw); 2370 /* Clear both the flag and MAC address */ 2371 Adapter->unicst_addr[slot].reg.high = 0; 2372 Adapter->unicst_addr[slot].reg.low = 0; 2373 } else { 2374 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2375 ETHERADDRL); 2376 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2377 Adapter->unicst_addr[slot].mac.set = 1; 2378 } 2379 2380 /* Workaround for an erratum of 82571 chipst */ 2381 if (slot == 0) { 2382 if ((hw->mac.type == e1000_82571) && 2383 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2384 if (mac_addr == NULL) { 2385 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2386 slot << 1, 0); 2387 E1000_WRITE_FLUSH(hw); 2388 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2389 (slot << 1) + 1, 0); 2390 E1000_WRITE_FLUSH(hw); 2391 } else { 2392 e1000_rar_set(hw, (uint8_t *)mac_addr, 2393 LAST_RAR_ENTRY); 2394 } 2395 } 2396 2397 /* 2398 * If we are using Wiseman rev 2.0 silicon, we will have previously 2399 * put the receive in reset, and disabled MWI, to work around some 2400 * HW errata. Now we should take the receiver out of reset, and 2401 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2402 */ 2403 if ((hw->mac.type == e1000_82542) && 2404 (hw->revision_id == E1000_REVISION_2)) { 2405 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2406 msec_delay(1); 2407 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2408 e1000_pci_set_mwi(hw); 2409 e1000g_rx_setup(Adapter); 2410 } 2411 2412 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2413 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2414 return (EIO); 2415 } 2416 2417 return (0); 2418 } 2419 2420 static int 2421 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2422 { 2423 struct e1000_hw *hw = &Adapter->shared; 2424 struct ether_addr *newtable; 2425 size_t new_len; 2426 size_t old_len; 2427 int res = 0; 2428 2429 if ((multiaddr[0] & 01) == 0) { 2430 res = EINVAL; 2431 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2432 goto done; 2433 } 2434 2435 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2436 res = ENOENT; 2437 e1000g_log(Adapter, CE_WARN, 2438 "Adapter requested more than %d mcast addresses", 2439 Adapter->mcast_max_num); 2440 goto done; 2441 } 2442 2443 2444 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2445 old_len = Adapter->mcast_alloc_count * 2446 sizeof (struct ether_addr); 2447 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2448 sizeof (struct ether_addr); 2449 2450 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2451 if (newtable == NULL) { 2452 res = ENOMEM; 2453 e1000g_log(Adapter, CE_WARN, 2454 "Not enough memory to alloc mcast table"); 2455 goto done; 2456 } 2457 2458 if (Adapter->mcast_table != NULL) { 2459 bcopy(Adapter->mcast_table, newtable, old_len); 2460 kmem_free(Adapter->mcast_table, old_len); 2461 } 2462 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2463 Adapter->mcast_table = newtable; 2464 } 2465 2466 bcopy(multiaddr, 2467 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2468 Adapter->mcast_count++; 2469 2470 /* 2471 * Update the MC table in the hardware 2472 */ 2473 e1000g_clear_interrupt(Adapter); 2474 2475 e1000_update_mc_addr_list(hw, 2476 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2477 2478 e1000g_mask_interrupt(Adapter); 2479 2480 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2481 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2482 res = EIO; 2483 } 2484 2485 done: 2486 return (res); 2487 } 2488 2489 static int 2490 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2491 { 2492 struct e1000_hw *hw = &Adapter->shared; 2493 struct ether_addr *newtable; 2494 size_t new_len; 2495 size_t old_len; 2496 unsigned i; 2497 2498 for (i = 0; i < Adapter->mcast_count; i++) { 2499 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2500 ETHERADDRL) == 0) { 2501 for (i++; i < Adapter->mcast_count; i++) { 2502 Adapter->mcast_table[i - 1] = 2503 Adapter->mcast_table[i]; 2504 } 2505 Adapter->mcast_count--; 2506 break; 2507 } 2508 } 2509 2510 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2511 MCAST_ALLOC_SIZE) { 2512 old_len = Adapter->mcast_alloc_count * 2513 sizeof (struct ether_addr); 2514 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2515 sizeof (struct ether_addr); 2516 2517 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2518 if (newtable != NULL) { 2519 bcopy(Adapter->mcast_table, newtable, new_len); 2520 kmem_free(Adapter->mcast_table, old_len); 2521 2522 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2523 Adapter->mcast_table = newtable; 2524 } 2525 } 2526 2527 /* 2528 * Update the MC table in the hardware 2529 */ 2530 e1000g_clear_interrupt(Adapter); 2531 2532 e1000_update_mc_addr_list(hw, 2533 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2534 2535 e1000g_mask_interrupt(Adapter); 2536 2537 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2538 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2539 return (EIO); 2540 } 2541 2542 return (0); 2543 } 2544 2545 static void 2546 e1000g_release_multicast(struct e1000g *Adapter) 2547 { 2548 if (Adapter->mcast_table != NULL) { 2549 kmem_free(Adapter->mcast_table, 2550 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2551 Adapter->mcast_table = NULL; 2552 } 2553 } 2554 2555 int 2556 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2557 { 2558 struct e1000g *Adapter = (struct e1000g *)arg; 2559 int result; 2560 2561 rw_enter(&Adapter->chip_lock, RW_WRITER); 2562 2563 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2564 result = ECANCELED; 2565 goto done; 2566 } 2567 2568 result = (add) ? multicst_add(Adapter, addr) 2569 : multicst_remove(Adapter, addr); 2570 2571 done: 2572 rw_exit(&Adapter->chip_lock); 2573 return (result); 2574 2575 } 2576 2577 int 2578 e1000g_m_promisc(void *arg, boolean_t on) 2579 { 2580 struct e1000g *Adapter = (struct e1000g *)arg; 2581 uint32_t rctl; 2582 2583 rw_enter(&Adapter->chip_lock, RW_WRITER); 2584 2585 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2586 rw_exit(&Adapter->chip_lock); 2587 return (ECANCELED); 2588 } 2589 2590 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2591 2592 if (on) 2593 rctl |= 2594 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2595 else 2596 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2597 2598 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2599 2600 Adapter->e1000g_promisc = on; 2601 2602 rw_exit(&Adapter->chip_lock); 2603 2604 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2605 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2606 return (EIO); 2607 } 2608 2609 return (0); 2610 } 2611 2612 /* 2613 * Entry points to enable and disable interrupts at the granularity of 2614 * a group. 2615 * Turns the poll_mode for the whole adapter on and off to enable or 2616 * override the ring level polling control over the hardware interrupts. 2617 */ 2618 static int 2619 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2620 { 2621 struct e1000g *adapter = (struct e1000g *)arg; 2622 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2623 2624 /* 2625 * Later interrupts at the granularity of the this ring will 2626 * invoke mac_rx() with NULL, indicating the need for another 2627 * software classification. 2628 * We have a single ring usable per adapter now, so we only need to 2629 * reset the rx handle for that one. 2630 * When more RX rings can be used, we should update each one of them. 2631 */ 2632 mutex_enter(&rx_ring->rx_lock); 2633 rx_ring->mrh = NULL; 2634 adapter->poll_mode = B_FALSE; 2635 mutex_exit(&rx_ring->rx_lock); 2636 return (0); 2637 } 2638 2639 static int 2640 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2641 { 2642 struct e1000g *adapter = (struct e1000g *)arg; 2643 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2644 2645 mutex_enter(&rx_ring->rx_lock); 2646 2647 /* 2648 * Later interrupts at the granularity of the this ring will 2649 * invoke mac_rx() with the handle for this ring; 2650 */ 2651 adapter->poll_mode = B_TRUE; 2652 rx_ring->mrh = rx_ring->mrh_init; 2653 mutex_exit(&rx_ring->rx_lock); 2654 return (0); 2655 } 2656 2657 /* 2658 * Entry points to enable and disable interrupts at the granularity of 2659 * a ring. 2660 * adapter poll_mode controls whether we actually proceed with hardware 2661 * interrupt toggling. 2662 */ 2663 static int 2664 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2665 { 2666 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2667 struct e1000g *adapter = rx_ring->adapter; 2668 struct e1000_hw *hw = &adapter->shared; 2669 uint32_t intr_mask; 2670 2671 rw_enter(&adapter->chip_lock, RW_READER); 2672 2673 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2674 rw_exit(&adapter->chip_lock); 2675 return (0); 2676 } 2677 2678 mutex_enter(&rx_ring->rx_lock); 2679 rx_ring->poll_flag = 0; 2680 mutex_exit(&rx_ring->rx_lock); 2681 2682 /* Rx interrupt enabling for MSI and legacy */ 2683 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2684 intr_mask |= E1000_IMS_RXT0; 2685 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2686 E1000_WRITE_FLUSH(hw); 2687 2688 /* Trigger a Rx interrupt to check Rx ring */ 2689 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2690 E1000_WRITE_FLUSH(hw); 2691 2692 rw_exit(&adapter->chip_lock); 2693 return (0); 2694 } 2695 2696 static int 2697 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2698 { 2699 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2700 struct e1000g *adapter = rx_ring->adapter; 2701 struct e1000_hw *hw = &adapter->shared; 2702 2703 rw_enter(&adapter->chip_lock, RW_READER); 2704 2705 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2706 rw_exit(&adapter->chip_lock); 2707 return (0); 2708 } 2709 mutex_enter(&rx_ring->rx_lock); 2710 rx_ring->poll_flag = 1; 2711 mutex_exit(&rx_ring->rx_lock); 2712 2713 /* Rx interrupt disabling for MSI and legacy */ 2714 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2715 E1000_WRITE_FLUSH(hw); 2716 2717 rw_exit(&adapter->chip_lock); 2718 return (0); 2719 } 2720 2721 /* 2722 * e1000g_unicst_find - Find the slot for the specified unicast address 2723 */ 2724 static int 2725 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2726 { 2727 int slot; 2728 2729 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2730 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2731 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2732 mac_addr, ETHERADDRL) == 0)) 2733 return (slot); 2734 } 2735 2736 return (-1); 2737 } 2738 2739 /* 2740 * Entry points to add and remove a MAC address to a ring group. 2741 * The caller takes care of adding and removing the MAC addresses 2742 * to the filter via these two routines. 2743 */ 2744 2745 static int 2746 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2747 { 2748 struct e1000g *Adapter = (struct e1000g *)arg; 2749 int slot, err; 2750 2751 rw_enter(&Adapter->chip_lock, RW_WRITER); 2752 2753 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2754 rw_exit(&Adapter->chip_lock); 2755 return (ECANCELED); 2756 } 2757 2758 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2759 /* The same address is already in slot */ 2760 rw_exit(&Adapter->chip_lock); 2761 return (0); 2762 } 2763 2764 if (Adapter->unicst_avail == 0) { 2765 /* no slots available */ 2766 rw_exit(&Adapter->chip_lock); 2767 return (ENOSPC); 2768 } 2769 2770 /* Search for a free slot */ 2771 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2772 if (Adapter->unicst_addr[slot].mac.set == 0) 2773 break; 2774 } 2775 ASSERT(slot < Adapter->unicst_total); 2776 2777 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2778 if (err == 0) 2779 Adapter->unicst_avail--; 2780 2781 rw_exit(&Adapter->chip_lock); 2782 2783 return (err); 2784 } 2785 2786 static int 2787 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2788 { 2789 struct e1000g *Adapter = (struct e1000g *)arg; 2790 int slot, err; 2791 2792 rw_enter(&Adapter->chip_lock, RW_WRITER); 2793 2794 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2795 rw_exit(&Adapter->chip_lock); 2796 return (ECANCELED); 2797 } 2798 2799 slot = e1000g_unicst_find(Adapter, mac_addr); 2800 if (slot == -1) { 2801 rw_exit(&Adapter->chip_lock); 2802 return (EINVAL); 2803 } 2804 2805 ASSERT(Adapter->unicst_addr[slot].mac.set); 2806 2807 /* Clear this slot */ 2808 err = e1000g_unicst_set(Adapter, NULL, slot); 2809 if (err == 0) 2810 Adapter->unicst_avail++; 2811 2812 rw_exit(&Adapter->chip_lock); 2813 2814 return (err); 2815 } 2816 2817 static int 2818 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2819 { 2820 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2821 2822 mutex_enter(&rx_ring->rx_lock); 2823 rx_ring->ring_gen_num = mr_gen_num; 2824 mutex_exit(&rx_ring->rx_lock); 2825 return (0); 2826 } 2827 2828 /* 2829 * Callback funtion for MAC layer to register all rings. 2830 * 2831 * The hardware supports a single group with currently only one ring 2832 * available. 2833 * Though not offering virtualization ability per se, exposing the 2834 * group/ring still enables the polling and interrupt toggling. 2835 */ 2836 /* ARGSUSED */ 2837 void 2838 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2839 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2840 { 2841 struct e1000g *Adapter = (struct e1000g *)arg; 2842 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2843 mac_intr_t *mintr; 2844 2845 /* 2846 * We advertised only RX group/rings, so the MAC framework shouldn't 2847 * ask for any thing else. 2848 */ 2849 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2850 2851 rx_ring->mrh = rx_ring->mrh_init = rh; 2852 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2853 infop->mri_start = e1000g_ring_start; 2854 infop->mri_stop = NULL; 2855 infop->mri_poll = e1000g_poll_ring; 2856 2857 /* Ring level interrupts */ 2858 mintr = &infop->mri_intr; 2859 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2860 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2861 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2862 } 2863 2864 /* ARGSUSED */ 2865 static void 2866 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2867 mac_group_info_t *infop, mac_group_handle_t gh) 2868 { 2869 struct e1000g *Adapter = (struct e1000g *)arg; 2870 mac_intr_t *mintr; 2871 2872 /* 2873 * We advertised a single RX ring. Getting a request for anything else 2874 * signifies a bug in the MAC framework. 2875 */ 2876 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2877 2878 Adapter->rx_group = gh; 2879 2880 infop->mgi_driver = (mac_group_driver_t)Adapter; 2881 infop->mgi_start = NULL; 2882 infop->mgi_stop = NULL; 2883 infop->mgi_addmac = e1000g_addmac; 2884 infop->mgi_remmac = e1000g_remmac; 2885 infop->mgi_count = 1; 2886 2887 /* Group level interrupts */ 2888 mintr = &infop->mgi_intr; 2889 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2890 mintr->mi_enable = e1000g_rx_group_intr_enable; 2891 mintr->mi_disable = e1000g_rx_group_intr_disable; 2892 } 2893 2894 static boolean_t 2895 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2896 { 2897 struct e1000g *Adapter = (struct e1000g *)arg; 2898 2899 switch (cap) { 2900 case MAC_CAPAB_HCKSUM: { 2901 uint32_t *txflags = cap_data; 2902 2903 if (Adapter->tx_hcksum_enable) 2904 *txflags = HCKSUM_IPHDRCKSUM | 2905 HCKSUM_INET_PARTIAL; 2906 else 2907 return (B_FALSE); 2908 break; 2909 } 2910 2911 case MAC_CAPAB_LSO: { 2912 mac_capab_lso_t *cap_lso = cap_data; 2913 2914 if (Adapter->lso_enable) { 2915 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2916 cap_lso->lso_basic_tcp_ipv4.lso_max = 2917 E1000_LSO_MAXLEN; 2918 } else 2919 return (B_FALSE); 2920 break; 2921 } 2922 case MAC_CAPAB_RINGS: { 2923 mac_capab_rings_t *cap_rings = cap_data; 2924 2925 /* No TX rings exposed yet */ 2926 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2927 return (B_FALSE); 2928 2929 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2930 cap_rings->mr_rnum = 1; 2931 cap_rings->mr_gnum = 1; 2932 cap_rings->mr_rget = e1000g_fill_ring; 2933 cap_rings->mr_gget = e1000g_fill_group; 2934 break; 2935 } 2936 default: 2937 return (B_FALSE); 2938 } 2939 return (B_TRUE); 2940 } 2941 2942 static boolean_t 2943 e1000g_param_locked(mac_prop_id_t pr_num) 2944 { 2945 /* 2946 * All en_* parameters are locked (read-only) while 2947 * the device is in any sort of loopback mode ... 2948 */ 2949 switch (pr_num) { 2950 case MAC_PROP_EN_1000FDX_CAP: 2951 case MAC_PROP_EN_1000HDX_CAP: 2952 case MAC_PROP_EN_100FDX_CAP: 2953 case MAC_PROP_EN_100HDX_CAP: 2954 case MAC_PROP_EN_10FDX_CAP: 2955 case MAC_PROP_EN_10HDX_CAP: 2956 case MAC_PROP_AUTONEG: 2957 case MAC_PROP_FLOWCTRL: 2958 return (B_TRUE); 2959 } 2960 return (B_FALSE); 2961 } 2962 2963 /* 2964 * callback function for set/get of properties 2965 */ 2966 static int 2967 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2968 uint_t pr_valsize, const void *pr_val) 2969 { 2970 struct e1000g *Adapter = arg; 2971 struct e1000_hw *hw = &Adapter->shared; 2972 struct e1000_fc_info *fc = &Adapter->shared.fc; 2973 int err = 0; 2974 link_flowctrl_t flowctrl; 2975 uint32_t cur_mtu, new_mtu; 2976 2977 rw_enter(&Adapter->chip_lock, RW_WRITER); 2978 2979 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2980 rw_exit(&Adapter->chip_lock); 2981 return (ECANCELED); 2982 } 2983 2984 if (Adapter->loopback_mode != E1000G_LB_NONE && 2985 e1000g_param_locked(pr_num)) { 2986 /* 2987 * All en_* parameters are locked (read-only) 2988 * while the device is in any sort of loopback mode. 2989 */ 2990 rw_exit(&Adapter->chip_lock); 2991 return (EBUSY); 2992 } 2993 2994 switch (pr_num) { 2995 case MAC_PROP_EN_1000FDX_CAP: 2996 if (hw->phy.media_type != e1000_media_type_copper) { 2997 err = ENOTSUP; 2998 break; 2999 } 3000 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3001 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3002 goto reset; 3003 case MAC_PROP_EN_100FDX_CAP: 3004 if (hw->phy.media_type != e1000_media_type_copper) { 3005 err = ENOTSUP; 3006 break; 3007 } 3008 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3009 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3010 goto reset; 3011 case MAC_PROP_EN_100HDX_CAP: 3012 if (hw->phy.media_type != e1000_media_type_copper) { 3013 err = ENOTSUP; 3014 break; 3015 } 3016 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3017 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3018 goto reset; 3019 case MAC_PROP_EN_10FDX_CAP: 3020 if (hw->phy.media_type != e1000_media_type_copper) { 3021 err = ENOTSUP; 3022 break; 3023 } 3024 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3025 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3026 goto reset; 3027 case MAC_PROP_EN_10HDX_CAP: 3028 if (hw->phy.media_type != e1000_media_type_copper) { 3029 err = ENOTSUP; 3030 break; 3031 } 3032 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3033 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3034 goto reset; 3035 case MAC_PROP_AUTONEG: 3036 if (hw->phy.media_type != e1000_media_type_copper) { 3037 err = ENOTSUP; 3038 break; 3039 } 3040 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3041 goto reset; 3042 case MAC_PROP_FLOWCTRL: 3043 fc->send_xon = B_TRUE; 3044 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3045 3046 switch (flowctrl) { 3047 default: 3048 err = EINVAL; 3049 break; 3050 case LINK_FLOWCTRL_NONE: 3051 fc->requested_mode = e1000_fc_none; 3052 break; 3053 case LINK_FLOWCTRL_RX: 3054 fc->requested_mode = e1000_fc_rx_pause; 3055 break; 3056 case LINK_FLOWCTRL_TX: 3057 fc->requested_mode = e1000_fc_tx_pause; 3058 break; 3059 case LINK_FLOWCTRL_BI: 3060 fc->requested_mode = e1000_fc_full; 3061 break; 3062 } 3063 reset: 3064 if (err == 0) { 3065 /* check PCH limits & reset the link */ 3066 e1000g_pch_limits(Adapter); 3067 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3068 err = EINVAL; 3069 } 3070 break; 3071 case MAC_PROP_ADV_1000FDX_CAP: 3072 case MAC_PROP_ADV_1000HDX_CAP: 3073 case MAC_PROP_ADV_100FDX_CAP: 3074 case MAC_PROP_ADV_100HDX_CAP: 3075 case MAC_PROP_ADV_10FDX_CAP: 3076 case MAC_PROP_ADV_10HDX_CAP: 3077 case MAC_PROP_EN_1000HDX_CAP: 3078 case MAC_PROP_STATUS: 3079 case MAC_PROP_SPEED: 3080 case MAC_PROP_DUPLEX: 3081 err = ENOTSUP; /* read-only prop. Can't set this. */ 3082 break; 3083 case MAC_PROP_MTU: 3084 /* adapter must be stopped for an MTU change */ 3085 if (Adapter->e1000g_state & E1000G_STARTED) { 3086 err = EBUSY; 3087 break; 3088 } 3089 3090 cur_mtu = Adapter->default_mtu; 3091 3092 /* get new requested MTU */ 3093 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3094 if (new_mtu == cur_mtu) { 3095 err = 0; 3096 break; 3097 } 3098 3099 if ((new_mtu < DEFAULT_MTU) || 3100 (new_mtu > Adapter->max_mtu)) { 3101 err = EINVAL; 3102 break; 3103 } 3104 3105 /* inform MAC framework of new MTU */ 3106 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3107 3108 if (err == 0) { 3109 Adapter->default_mtu = new_mtu; 3110 Adapter->max_frame_size = 3111 e1000g_mtu2maxframe(new_mtu); 3112 3113 /* 3114 * check PCH limits & set buffer sizes to 3115 * match new MTU 3116 */ 3117 e1000g_pch_limits(Adapter); 3118 e1000g_set_bufsize(Adapter); 3119 } 3120 break; 3121 case MAC_PROP_PRIVATE: 3122 err = e1000g_set_priv_prop(Adapter, pr_name, 3123 pr_valsize, pr_val); 3124 break; 3125 default: 3126 err = ENOTSUP; 3127 break; 3128 } 3129 rw_exit(&Adapter->chip_lock); 3130 return (err); 3131 } 3132 3133 static int 3134 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3135 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3136 { 3137 struct e1000g *Adapter = arg; 3138 struct e1000_fc_info *fc = &Adapter->shared.fc; 3139 struct e1000_hw *hw = &Adapter->shared; 3140 int err = 0; 3141 link_flowctrl_t flowctrl; 3142 uint64_t tmp = 0; 3143 3144 if (pr_valsize == 0) 3145 return (EINVAL); 3146 3147 *perm = MAC_PROP_PERM_RW; 3148 3149 bzero(pr_val, pr_valsize); 3150 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3151 return (e1000g_get_def_val(Adapter, pr_num, 3152 pr_valsize, pr_val)); 3153 } 3154 3155 switch (pr_num) { 3156 case MAC_PROP_DUPLEX: 3157 *perm = MAC_PROP_PERM_READ; 3158 if (pr_valsize >= sizeof (link_duplex_t)) { 3159 bcopy(&Adapter->link_duplex, pr_val, 3160 sizeof (link_duplex_t)); 3161 } else 3162 err = EINVAL; 3163 break; 3164 case MAC_PROP_SPEED: 3165 *perm = MAC_PROP_PERM_READ; 3166 if (pr_valsize >= sizeof (uint64_t)) { 3167 tmp = Adapter->link_speed * 1000000ull; 3168 bcopy(&tmp, pr_val, sizeof (tmp)); 3169 } else 3170 err = EINVAL; 3171 break; 3172 case MAC_PROP_AUTONEG: 3173 if (hw->phy.media_type != e1000_media_type_copper) 3174 *perm = MAC_PROP_PERM_READ; 3175 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3176 break; 3177 case MAC_PROP_FLOWCTRL: 3178 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3179 switch (fc->current_mode) { 3180 case e1000_fc_none: 3181 flowctrl = LINK_FLOWCTRL_NONE; 3182 break; 3183 case e1000_fc_rx_pause: 3184 flowctrl = LINK_FLOWCTRL_RX; 3185 break; 3186 case e1000_fc_tx_pause: 3187 flowctrl = LINK_FLOWCTRL_TX; 3188 break; 3189 case e1000_fc_full: 3190 flowctrl = LINK_FLOWCTRL_BI; 3191 break; 3192 } 3193 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3194 } else 3195 err = EINVAL; 3196 break; 3197 case MAC_PROP_ADV_1000FDX_CAP: 3198 *perm = MAC_PROP_PERM_READ; 3199 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3200 break; 3201 case MAC_PROP_EN_1000FDX_CAP: 3202 if (hw->phy.media_type != e1000_media_type_copper) 3203 *perm = MAC_PROP_PERM_READ; 3204 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3205 break; 3206 case MAC_PROP_ADV_1000HDX_CAP: 3207 *perm = MAC_PROP_PERM_READ; 3208 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3209 break; 3210 case MAC_PROP_EN_1000HDX_CAP: 3211 *perm = MAC_PROP_PERM_READ; 3212 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3213 break; 3214 case MAC_PROP_ADV_100FDX_CAP: 3215 *perm = MAC_PROP_PERM_READ; 3216 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3217 break; 3218 case MAC_PROP_EN_100FDX_CAP: 3219 if (hw->phy.media_type != e1000_media_type_copper) 3220 *perm = MAC_PROP_PERM_READ; 3221 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3222 break; 3223 case MAC_PROP_ADV_100HDX_CAP: 3224 *perm = MAC_PROP_PERM_READ; 3225 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3226 break; 3227 case MAC_PROP_EN_100HDX_CAP: 3228 if (hw->phy.media_type != e1000_media_type_copper) 3229 *perm = MAC_PROP_PERM_READ; 3230 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3231 break; 3232 case MAC_PROP_ADV_10FDX_CAP: 3233 *perm = MAC_PROP_PERM_READ; 3234 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3235 break; 3236 case MAC_PROP_EN_10FDX_CAP: 3237 if (hw->phy.media_type != e1000_media_type_copper) 3238 *perm = MAC_PROP_PERM_READ; 3239 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3240 break; 3241 case MAC_PROP_ADV_10HDX_CAP: 3242 *perm = MAC_PROP_PERM_READ; 3243 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3244 break; 3245 case MAC_PROP_EN_10HDX_CAP: 3246 if (hw->phy.media_type != e1000_media_type_copper) 3247 *perm = MAC_PROP_PERM_READ; 3248 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3249 break; 3250 case MAC_PROP_ADV_100T4_CAP: 3251 case MAC_PROP_EN_100T4_CAP: 3252 *perm = MAC_PROP_PERM_READ; 3253 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3254 break; 3255 case MAC_PROP_PRIVATE: 3256 err = e1000g_get_priv_prop(Adapter, pr_name, 3257 pr_flags, pr_valsize, pr_val, perm); 3258 break; 3259 case MAC_PROP_MTU: { 3260 struct e1000_mac_info *mac = &Adapter->shared.mac; 3261 struct e1000_phy_info *phy = &Adapter->shared.phy; 3262 mac_propval_range_t range; 3263 3264 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3265 return (ENOTSUP); 3266 if (pr_valsize < sizeof (mac_propval_range_t)) 3267 return (EINVAL); 3268 range.mpr_count = 1; 3269 range.mpr_type = MAC_PROPVAL_UINT32; 3270 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3271 range.range_uint32[0].mpur_max = Adapter->max_mtu; 3272 /* following MAC type do not support jumbo frames */ 3273 if ((mac->type == e1000_ich8lan) || 3274 ((mac->type == e1000_ich9lan) && (phy->type == 3275 e1000_phy_ife))) { 3276 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3277 } 3278 bcopy(&range, pr_val, sizeof (range)); 3279 break; 3280 } 3281 default: 3282 err = ENOTSUP; 3283 break; 3284 } 3285 return (err); 3286 } 3287 3288 /* ARGSUSED2 */ 3289 static int 3290 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3291 uint_t pr_valsize, const void *pr_val) 3292 { 3293 int err = 0; 3294 long result; 3295 struct e1000_hw *hw = &Adapter->shared; 3296 3297 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3298 if (pr_val == NULL) { 3299 err = EINVAL; 3300 return (err); 3301 } 3302 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3303 if (result < MIN_TX_BCOPY_THRESHOLD || 3304 result > MAX_TX_BCOPY_THRESHOLD) 3305 err = EINVAL; 3306 else { 3307 Adapter->tx_bcopy_thresh = (uint32_t)result; 3308 } 3309 return (err); 3310 } 3311 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3312 if (pr_val == NULL) { 3313 err = EINVAL; 3314 return (err); 3315 } 3316 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3317 if (result < 0 || result > 1) 3318 err = EINVAL; 3319 else { 3320 Adapter->tx_intr_enable = (result == 1) ? 3321 B_TRUE: B_FALSE; 3322 if (Adapter->tx_intr_enable) 3323 e1000g_mask_tx_interrupt(Adapter); 3324 else 3325 e1000g_clear_tx_interrupt(Adapter); 3326 if (e1000g_check_acc_handle( 3327 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3328 ddi_fm_service_impact(Adapter->dip, 3329 DDI_SERVICE_DEGRADED); 3330 err = EIO; 3331 } 3332 } 3333 return (err); 3334 } 3335 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3336 if (pr_val == NULL) { 3337 err = EINVAL; 3338 return (err); 3339 } 3340 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3341 if (result < MIN_TX_INTR_DELAY || 3342 result > MAX_TX_INTR_DELAY) 3343 err = EINVAL; 3344 else { 3345 Adapter->tx_intr_delay = (uint32_t)result; 3346 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3347 if (e1000g_check_acc_handle( 3348 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3349 ddi_fm_service_impact(Adapter->dip, 3350 DDI_SERVICE_DEGRADED); 3351 err = EIO; 3352 } 3353 } 3354 return (err); 3355 } 3356 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3357 if (pr_val == NULL) { 3358 err = EINVAL; 3359 return (err); 3360 } 3361 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3362 if (result < MIN_TX_INTR_ABS_DELAY || 3363 result > MAX_TX_INTR_ABS_DELAY) 3364 err = EINVAL; 3365 else { 3366 Adapter->tx_intr_abs_delay = (uint32_t)result; 3367 E1000_WRITE_REG(hw, E1000_TADV, 3368 Adapter->tx_intr_abs_delay); 3369 if (e1000g_check_acc_handle( 3370 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3371 ddi_fm_service_impact(Adapter->dip, 3372 DDI_SERVICE_DEGRADED); 3373 err = EIO; 3374 } 3375 } 3376 return (err); 3377 } 3378 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3379 if (pr_val == NULL) { 3380 err = EINVAL; 3381 return (err); 3382 } 3383 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3384 if (result < MIN_RX_BCOPY_THRESHOLD || 3385 result > MAX_RX_BCOPY_THRESHOLD) 3386 err = EINVAL; 3387 else 3388 Adapter->rx_bcopy_thresh = (uint32_t)result; 3389 return (err); 3390 } 3391 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3392 if (pr_val == NULL) { 3393 err = EINVAL; 3394 return (err); 3395 } 3396 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3397 if (result < MIN_RX_LIMIT_ON_INTR || 3398 result > MAX_RX_LIMIT_ON_INTR) 3399 err = EINVAL; 3400 else 3401 Adapter->rx_limit_onintr = (uint32_t)result; 3402 return (err); 3403 } 3404 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3405 if (pr_val == NULL) { 3406 err = EINVAL; 3407 return (err); 3408 } 3409 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3410 if (result < MIN_RX_INTR_DELAY || 3411 result > MAX_RX_INTR_DELAY) 3412 err = EINVAL; 3413 else { 3414 Adapter->rx_intr_delay = (uint32_t)result; 3415 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3416 if (e1000g_check_acc_handle( 3417 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3418 ddi_fm_service_impact(Adapter->dip, 3419 DDI_SERVICE_DEGRADED); 3420 err = EIO; 3421 } 3422 } 3423 return (err); 3424 } 3425 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3426 if (pr_val == NULL) { 3427 err = EINVAL; 3428 return (err); 3429 } 3430 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3431 if (result < MIN_RX_INTR_ABS_DELAY || 3432 result > MAX_RX_INTR_ABS_DELAY) 3433 err = EINVAL; 3434 else { 3435 Adapter->rx_intr_abs_delay = (uint32_t)result; 3436 E1000_WRITE_REG(hw, E1000_RADV, 3437 Adapter->rx_intr_abs_delay); 3438 if (e1000g_check_acc_handle( 3439 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3440 ddi_fm_service_impact(Adapter->dip, 3441 DDI_SERVICE_DEGRADED); 3442 err = EIO; 3443 } 3444 } 3445 return (err); 3446 } 3447 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3448 if (pr_val == NULL) { 3449 err = EINVAL; 3450 return (err); 3451 } 3452 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3453 if (result < MIN_INTR_THROTTLING || 3454 result > MAX_INTR_THROTTLING) 3455 err = EINVAL; 3456 else { 3457 if (hw->mac.type >= e1000_82540) { 3458 Adapter->intr_throttling_rate = 3459 (uint32_t)result; 3460 E1000_WRITE_REG(hw, E1000_ITR, 3461 Adapter->intr_throttling_rate); 3462 if (e1000g_check_acc_handle( 3463 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3464 ddi_fm_service_impact(Adapter->dip, 3465 DDI_SERVICE_DEGRADED); 3466 err = EIO; 3467 } 3468 } else 3469 err = EINVAL; 3470 } 3471 return (err); 3472 } 3473 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3474 if (pr_val == NULL) { 3475 err = EINVAL; 3476 return (err); 3477 } 3478 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3479 if (result < 0 || result > 1) 3480 err = EINVAL; 3481 else { 3482 if (hw->mac.type >= e1000_82540) { 3483 Adapter->intr_adaptive = (result == 1) ? 3484 B_TRUE : B_FALSE; 3485 } else { 3486 err = EINVAL; 3487 } 3488 } 3489 return (err); 3490 } 3491 return (ENOTSUP); 3492 } 3493 3494 static int 3495 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3496 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3497 { 3498 int err = ENOTSUP; 3499 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3500 int value; 3501 3502 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3503 *perm = MAC_PROP_PERM_READ; 3504 if (is_default) 3505 goto done; 3506 value = Adapter->param_adv_pause; 3507 err = 0; 3508 goto done; 3509 } 3510 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3511 *perm = MAC_PROP_PERM_READ; 3512 if (is_default) 3513 goto done; 3514 value = Adapter->param_adv_asym_pause; 3515 err = 0; 3516 goto done; 3517 } 3518 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3519 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3520 Adapter->tx_bcopy_thresh); 3521 err = 0; 3522 goto done; 3523 } 3524 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3525 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3526 Adapter->tx_intr_enable); 3527 err = 0; 3528 goto done; 3529 } 3530 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3531 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3532 Adapter->tx_intr_delay); 3533 err = 0; 3534 goto done; 3535 } 3536 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3537 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3538 Adapter->tx_intr_abs_delay); 3539 err = 0; 3540 goto done; 3541 } 3542 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3543 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3544 Adapter->rx_bcopy_thresh); 3545 err = 0; 3546 goto done; 3547 } 3548 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3549 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3550 Adapter->rx_limit_onintr); 3551 err = 0; 3552 goto done; 3553 } 3554 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3555 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3556 Adapter->rx_intr_delay); 3557 err = 0; 3558 goto done; 3559 } 3560 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3561 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3562 Adapter->rx_intr_abs_delay); 3563 err = 0; 3564 goto done; 3565 } 3566 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3567 value = (is_default ? DEFAULT_INTR_THROTTLING : 3568 Adapter->intr_throttling_rate); 3569 err = 0; 3570 goto done; 3571 } 3572 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3573 value = (is_default ? 1 : Adapter->intr_adaptive); 3574 err = 0; 3575 goto done; 3576 } 3577 done: 3578 if (err == 0) { 3579 (void) snprintf(pr_val, pr_valsize, "%d", value); 3580 } 3581 return (err); 3582 } 3583 3584 /* 3585 * e1000g_get_conf - get configurations set in e1000g.conf 3586 * This routine gets user-configured values out of the configuration 3587 * file e1000g.conf. 3588 * 3589 * For each configurable value, there is a minimum, a maximum, and a 3590 * default. 3591 * If user does not configure a value, use the default. 3592 * If user configures below the minimum, use the minumum. 3593 * If user configures above the maximum, use the maxumum. 3594 */ 3595 static void 3596 e1000g_get_conf(struct e1000g *Adapter) 3597 { 3598 struct e1000_hw *hw = &Adapter->shared; 3599 boolean_t tbi_compatibility = B_FALSE; 3600 3601 /* 3602 * get each configurable property from e1000g.conf 3603 */ 3604 3605 /* 3606 * NumTxDescriptors 3607 */ 3608 Adapter->tx_desc_num = 3609 e1000g_get_prop(Adapter, "NumTxDescriptors", 3610 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3611 DEFAULT_NUM_TX_DESCRIPTOR); 3612 3613 /* 3614 * NumRxDescriptors 3615 */ 3616 Adapter->rx_desc_num = 3617 e1000g_get_prop(Adapter, "NumRxDescriptors", 3618 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3619 DEFAULT_NUM_RX_DESCRIPTOR); 3620 3621 /* 3622 * NumRxFreeList 3623 */ 3624 Adapter->rx_freelist_num = 3625 e1000g_get_prop(Adapter, "NumRxFreeList", 3626 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3627 DEFAULT_NUM_RX_FREELIST); 3628 3629 /* 3630 * NumTxPacketList 3631 */ 3632 Adapter->tx_freelist_num = 3633 e1000g_get_prop(Adapter, "NumTxPacketList", 3634 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3635 DEFAULT_NUM_TX_FREELIST); 3636 3637 /* 3638 * FlowControl 3639 */ 3640 hw->fc.send_xon = B_TRUE; 3641 hw->fc.requested_mode = 3642 e1000g_get_prop(Adapter, "FlowControl", 3643 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3644 /* 4 is the setting that says "let the eeprom decide" */ 3645 if (hw->fc.requested_mode == 4) 3646 hw->fc.requested_mode = e1000_fc_default; 3647 3648 /* 3649 * Max Num Receive Packets on Interrupt 3650 */ 3651 Adapter->rx_limit_onintr = 3652 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3653 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3654 DEFAULT_RX_LIMIT_ON_INTR); 3655 3656 /* 3657 * PHY master slave setting 3658 */ 3659 hw->phy.ms_type = 3660 e1000g_get_prop(Adapter, "SetMasterSlave", 3661 e1000_ms_hw_default, e1000_ms_auto, 3662 e1000_ms_hw_default); 3663 3664 /* 3665 * Parameter which controls TBI mode workaround, which is only 3666 * needed on certain switches such as Cisco 6500/Foundry 3667 */ 3668 tbi_compatibility = 3669 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3670 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3671 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3672 3673 /* 3674 * MSI Enable 3675 */ 3676 Adapter->msi_enable = 3677 e1000g_get_prop(Adapter, "MSIEnable", 3678 0, 1, DEFAULT_MSI_ENABLE); 3679 3680 /* 3681 * Interrupt Throttling Rate 3682 */ 3683 Adapter->intr_throttling_rate = 3684 e1000g_get_prop(Adapter, "intr_throttling_rate", 3685 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3686 DEFAULT_INTR_THROTTLING); 3687 3688 /* 3689 * Adaptive Interrupt Blanking Enable/Disable 3690 * It is enabled by default 3691 */ 3692 Adapter->intr_adaptive = 3693 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3694 B_TRUE : B_FALSE; 3695 3696 /* 3697 * Hardware checksum enable/disable parameter 3698 */ 3699 Adapter->tx_hcksum_enable = 3700 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3701 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3702 /* 3703 * Checksum on/off selection via global parameters. 3704 * 3705 * If the chip is flagged as not capable of (correctly) 3706 * handling checksumming, we don't enable it on either 3707 * Rx or Tx side. Otherwise, we take this chip's settings 3708 * from the patchable global defaults. 3709 * 3710 * We advertise our capabilities only if TX offload is 3711 * enabled. On receive, the stack will accept checksummed 3712 * packets anyway, even if we haven't said we can deliver 3713 * them. 3714 */ 3715 switch (hw->mac.type) { 3716 case e1000_82540: 3717 case e1000_82544: 3718 case e1000_82545: 3719 case e1000_82545_rev_3: 3720 case e1000_82546: 3721 case e1000_82546_rev_3: 3722 case e1000_82571: 3723 case e1000_82572: 3724 case e1000_82573: 3725 case e1000_80003es2lan: 3726 break; 3727 /* 3728 * For the following Intel PRO/1000 chipsets, we have not 3729 * tested the hardware checksum offload capability, so we 3730 * disable the capability for them. 3731 * e1000_82542, 3732 * e1000_82543, 3733 * e1000_82541, 3734 * e1000_82541_rev_2, 3735 * e1000_82547, 3736 * e1000_82547_rev_2, 3737 */ 3738 default: 3739 Adapter->tx_hcksum_enable = B_FALSE; 3740 } 3741 3742 /* 3743 * Large Send Offloading(LSO) Enable/Disable 3744 * If the tx hardware checksum is not enabled, LSO should be 3745 * disabled. 3746 */ 3747 Adapter->lso_enable = 3748 e1000g_get_prop(Adapter, "lso_enable", 3749 0, 1, DEFAULT_LSO_ENABLE); 3750 3751 switch (hw->mac.type) { 3752 case e1000_82546: 3753 case e1000_82546_rev_3: 3754 if (Adapter->lso_enable) 3755 Adapter->lso_premature_issue = B_TRUE; 3756 /* FALLTHRU */ 3757 case e1000_82571: 3758 case e1000_82572: 3759 case e1000_82573: 3760 case e1000_80003es2lan: 3761 break; 3762 default: 3763 Adapter->lso_enable = B_FALSE; 3764 } 3765 3766 if (!Adapter->tx_hcksum_enable) { 3767 Adapter->lso_premature_issue = B_FALSE; 3768 Adapter->lso_enable = B_FALSE; 3769 } 3770 3771 /* 3772 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3773 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3774 * will not cross 64k boundary. 3775 */ 3776 Adapter->mem_workaround_82546 = 3777 e1000g_get_prop(Adapter, "mem_workaround_82546", 3778 0, 1, DEFAULT_MEM_WORKAROUND_82546); 3779 3780 /* 3781 * Max number of multicast addresses 3782 */ 3783 Adapter->mcast_max_num = 3784 e1000g_get_prop(Adapter, "mcast_max_num", 3785 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32); 3786 } 3787 3788 /* 3789 * e1000g_get_prop - routine to read properties 3790 * 3791 * Get a user-configure property value out of the configuration 3792 * file e1000g.conf. 3793 * 3794 * Caller provides name of the property, a default value, a minimum 3795 * value, and a maximum value. 3796 * 3797 * Return configured value of the property, with default, minimum and 3798 * maximum properly applied. 3799 */ 3800 static int 3801 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3802 char *propname, /* name of the property */ 3803 int minval, /* minimum acceptable value */ 3804 int maxval, /* maximim acceptable value */ 3805 int defval) /* default value */ 3806 { 3807 int propval; /* value returned for requested property */ 3808 int *props; /* point to array of properties returned */ 3809 uint_t nprops; /* number of property value returned */ 3810 3811 /* 3812 * get the array of properties from the config file 3813 */ 3814 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3815 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3816 /* got some properties, test if we got enough */ 3817 if (Adapter->instance < nprops) { 3818 propval = props[Adapter->instance]; 3819 } else { 3820 /* not enough properties configured */ 3821 propval = defval; 3822 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3823 "Not Enough %s values found in e1000g.conf" 3824 " - set to %d\n", 3825 propname, propval); 3826 } 3827 3828 /* free memory allocated for properties */ 3829 ddi_prop_free(props); 3830 3831 } else { 3832 propval = defval; 3833 } 3834 3835 /* 3836 * enforce limits 3837 */ 3838 if (propval > maxval) { 3839 propval = maxval; 3840 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3841 "Too High %s value in e1000g.conf - set to %d\n", 3842 propname, propval); 3843 } 3844 3845 if (propval < minval) { 3846 propval = minval; 3847 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3848 "Too Low %s value in e1000g.conf - set to %d\n", 3849 propname, propval); 3850 } 3851 3852 return (propval); 3853 } 3854 3855 static boolean_t 3856 e1000g_link_check(struct e1000g *Adapter) 3857 { 3858 uint16_t speed, duplex, phydata; 3859 boolean_t link_changed = B_FALSE; 3860 struct e1000_hw *hw; 3861 uint32_t reg_tarc; 3862 3863 hw = &Adapter->shared; 3864 3865 if (e1000g_link_up(Adapter)) { 3866 /* 3867 * The Link is up, check whether it was marked as down earlier 3868 */ 3869 if (Adapter->link_state != LINK_STATE_UP) { 3870 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3871 Adapter->link_speed = speed; 3872 Adapter->link_duplex = duplex; 3873 Adapter->link_state = LINK_STATE_UP; 3874 link_changed = B_TRUE; 3875 3876 if (Adapter->link_speed == SPEED_1000) 3877 Adapter->stall_threshold = TX_STALL_TIME_2S; 3878 else 3879 Adapter->stall_threshold = TX_STALL_TIME_8S; 3880 3881 Adapter->tx_link_down_timeout = 0; 3882 3883 if ((hw->mac.type == e1000_82571) || 3884 (hw->mac.type == e1000_82572)) { 3885 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3886 if (speed == SPEED_1000) 3887 reg_tarc |= (1 << 21); 3888 else 3889 reg_tarc &= ~(1 << 21); 3890 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3891 } 3892 } 3893 Adapter->smartspeed = 0; 3894 } else { 3895 if (Adapter->link_state != LINK_STATE_DOWN) { 3896 Adapter->link_speed = 0; 3897 Adapter->link_duplex = 0; 3898 Adapter->link_state = LINK_STATE_DOWN; 3899 link_changed = B_TRUE; 3900 3901 /* 3902 * SmartSpeed workaround for Tabor/TanaX, When the 3903 * driver loses link disable auto master/slave 3904 * resolution. 3905 */ 3906 if (hw->phy.type == e1000_phy_igp) { 3907 (void) e1000_read_phy_reg(hw, 3908 PHY_1000T_CTRL, &phydata); 3909 phydata |= CR_1000T_MS_ENABLE; 3910 (void) e1000_write_phy_reg(hw, 3911 PHY_1000T_CTRL, phydata); 3912 } 3913 } else { 3914 e1000g_smartspeed(Adapter); 3915 } 3916 3917 if (Adapter->e1000g_state & E1000G_STARTED) { 3918 if (Adapter->tx_link_down_timeout < 3919 MAX_TX_LINK_DOWN_TIMEOUT) { 3920 Adapter->tx_link_down_timeout++; 3921 } else if (Adapter->tx_link_down_timeout == 3922 MAX_TX_LINK_DOWN_TIMEOUT) { 3923 e1000g_tx_clean(Adapter); 3924 Adapter->tx_link_down_timeout++; 3925 } 3926 } 3927 } 3928 3929 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3930 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3931 3932 return (link_changed); 3933 } 3934 3935 /* 3936 * e1000g_reset_link - Using the link properties to setup the link 3937 */ 3938 int 3939 e1000g_reset_link(struct e1000g *Adapter) 3940 { 3941 struct e1000_mac_info *mac; 3942 struct e1000_phy_info *phy; 3943 struct e1000_hw *hw; 3944 boolean_t invalid; 3945 3946 mac = &Adapter->shared.mac; 3947 phy = &Adapter->shared.phy; 3948 hw = &Adapter->shared; 3949 invalid = B_FALSE; 3950 3951 if (hw->phy.media_type != e1000_media_type_copper) 3952 goto out; 3953 3954 if (Adapter->param_adv_autoneg == 1) { 3955 mac->autoneg = B_TRUE; 3956 phy->autoneg_advertised = 0; 3957 3958 /* 3959 * 1000hdx is not supported for autonegotiation 3960 */ 3961 if (Adapter->param_adv_1000fdx == 1) 3962 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3963 3964 if (Adapter->param_adv_100fdx == 1) 3965 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3966 3967 if (Adapter->param_adv_100hdx == 1) 3968 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3969 3970 if (Adapter->param_adv_10fdx == 1) 3971 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3972 3973 if (Adapter->param_adv_10hdx == 1) 3974 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3975 3976 if (phy->autoneg_advertised == 0) 3977 invalid = B_TRUE; 3978 } else { 3979 mac->autoneg = B_FALSE; 3980 3981 /* 3982 * For Intel copper cards, 1000fdx and 1000hdx are not 3983 * supported for forced link 3984 */ 3985 if (Adapter->param_adv_100fdx == 1) 3986 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3987 else if (Adapter->param_adv_100hdx == 1) 3988 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3989 else if (Adapter->param_adv_10fdx == 1) 3990 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3991 else if (Adapter->param_adv_10hdx == 1) 3992 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3993 else 3994 invalid = B_TRUE; 3995 3996 } 3997 3998 if (invalid) { 3999 e1000g_log(Adapter, CE_WARN, 4000 "Invalid link settings. Setup link to " 4001 "support autonegotiation with all link capabilities."); 4002 mac->autoneg = B_TRUE; 4003 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4004 } 4005 4006 out: 4007 return (e1000_setup_link(&Adapter->shared)); 4008 } 4009 4010 static void 4011 e1000g_timer_tx_resched(struct e1000g *Adapter) 4012 { 4013 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4014 4015 rw_enter(&Adapter->chip_lock, RW_READER); 4016 4017 if (tx_ring->resched_needed && 4018 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4019 drv_usectohz(1000000)) && 4020 (Adapter->e1000g_state & E1000G_STARTED) && 4021 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4022 tx_ring->resched_needed = B_FALSE; 4023 mac_tx_update(Adapter->mh); 4024 E1000G_STAT(tx_ring->stat_reschedule); 4025 E1000G_STAT(tx_ring->stat_timer_reschedule); 4026 } 4027 4028 rw_exit(&Adapter->chip_lock); 4029 } 4030 4031 static void 4032 e1000g_local_timer(void *ws) 4033 { 4034 struct e1000g *Adapter = (struct e1000g *)ws; 4035 struct e1000_hw *hw; 4036 e1000g_ether_addr_t ether_addr; 4037 boolean_t link_changed; 4038 4039 hw = &Adapter->shared; 4040 4041 if (Adapter->e1000g_state & E1000G_ERROR) { 4042 rw_enter(&Adapter->chip_lock, RW_WRITER); 4043 Adapter->e1000g_state &= ~E1000G_ERROR; 4044 rw_exit(&Adapter->chip_lock); 4045 4046 Adapter->reset_count++; 4047 if (e1000g_global_reset(Adapter)) { 4048 ddi_fm_service_impact(Adapter->dip, 4049 DDI_SERVICE_RESTORED); 4050 e1000g_timer_tx_resched(Adapter); 4051 } else 4052 ddi_fm_service_impact(Adapter->dip, 4053 DDI_SERVICE_LOST); 4054 return; 4055 } 4056 4057 if (e1000g_stall_check(Adapter)) { 4058 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4059 "Tx stall detected. Activate automatic recovery.\n"); 4060 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4061 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4062 Adapter->reset_count++; 4063 if (e1000g_reset_adapter(Adapter)) { 4064 ddi_fm_service_impact(Adapter->dip, 4065 DDI_SERVICE_RESTORED); 4066 e1000g_timer_tx_resched(Adapter); 4067 } 4068 return; 4069 } 4070 4071 link_changed = B_FALSE; 4072 rw_enter(&Adapter->chip_lock, RW_READER); 4073 if (Adapter->link_complete) 4074 link_changed = e1000g_link_check(Adapter); 4075 rw_exit(&Adapter->chip_lock); 4076 4077 if (link_changed) { 4078 if (!Adapter->reset_flag) 4079 mac_link_update(Adapter->mh, Adapter->link_state); 4080 if (Adapter->link_state == LINK_STATE_UP) 4081 Adapter->reset_flag = B_FALSE; 4082 } 4083 /* 4084 * Workaround for esb2. Data stuck in fifo on a link 4085 * down event. Reset the adapter to recover it. 4086 */ 4087 if (Adapter->esb2_workaround) { 4088 Adapter->esb2_workaround = B_FALSE; 4089 (void) e1000g_reset_adapter(Adapter); 4090 return; 4091 } 4092 4093 /* 4094 * With 82571 controllers, any locally administered address will 4095 * be overwritten when there is a reset on the other port. 4096 * Detect this circumstance and correct it. 4097 */ 4098 if ((hw->mac.type == e1000_82571) && 4099 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4100 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4101 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4102 4103 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4104 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4105 4106 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4107 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4108 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4109 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4110 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4111 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4112 e1000_rar_set(hw, hw->mac.addr, 0); 4113 } 4114 } 4115 4116 /* 4117 * Long TTL workaround for 82541/82547 4118 */ 4119 (void) e1000_igp_ttl_workaround_82547(hw); 4120 4121 /* 4122 * Check for Adaptive IFS settings If there are lots of collisions 4123 * change the value in steps... 4124 * These properties should only be set for 10/100 4125 */ 4126 if ((hw->phy.media_type == e1000_media_type_copper) && 4127 ((Adapter->link_speed == SPEED_100) || 4128 (Adapter->link_speed == SPEED_10))) { 4129 e1000_update_adaptive(hw); 4130 } 4131 /* 4132 * Set Timer Interrupts 4133 */ 4134 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4135 4136 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4137 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4138 else 4139 e1000g_timer_tx_resched(Adapter); 4140 4141 restart_watchdog_timer(Adapter); 4142 } 4143 4144 /* 4145 * The function e1000g_link_timer() is called when the timer for link setup 4146 * is expired, which indicates the completion of the link setup. The link 4147 * state will not be updated until the link setup is completed. And the 4148 * link state will not be sent to the upper layer through mac_link_update() 4149 * in this function. It will be updated in the local timer routine or the 4150 * interrupt service routine after the interface is started (plumbed). 4151 */ 4152 static void 4153 e1000g_link_timer(void *arg) 4154 { 4155 struct e1000g *Adapter = (struct e1000g *)arg; 4156 4157 mutex_enter(&Adapter->link_lock); 4158 Adapter->link_complete = B_TRUE; 4159 Adapter->link_tid = 0; 4160 mutex_exit(&Adapter->link_lock); 4161 } 4162 4163 /* 4164 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4165 * 4166 * This function read the forced speed and duplex for 10/100 Mbps speeds 4167 * and also for 1000 Mbps speeds from the e1000g.conf file 4168 */ 4169 static void 4170 e1000g_force_speed_duplex(struct e1000g *Adapter) 4171 { 4172 int forced; 4173 struct e1000_mac_info *mac = &Adapter->shared.mac; 4174 struct e1000_phy_info *phy = &Adapter->shared.phy; 4175 4176 /* 4177 * get value out of config file 4178 */ 4179 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4180 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 4181 4182 switch (forced) { 4183 case GDIAG_10_HALF: 4184 /* 4185 * Disable Auto Negotiation 4186 */ 4187 mac->autoneg = B_FALSE; 4188 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4189 break; 4190 case GDIAG_10_FULL: 4191 /* 4192 * Disable Auto Negotiation 4193 */ 4194 mac->autoneg = B_FALSE; 4195 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4196 break; 4197 case GDIAG_100_HALF: 4198 /* 4199 * Disable Auto Negotiation 4200 */ 4201 mac->autoneg = B_FALSE; 4202 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4203 break; 4204 case GDIAG_100_FULL: 4205 /* 4206 * Disable Auto Negotiation 4207 */ 4208 mac->autoneg = B_FALSE; 4209 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4210 break; 4211 case GDIAG_1000_FULL: 4212 /* 4213 * The gigabit spec requires autonegotiation. Therefore, 4214 * when the user wants to force the speed to 1000Mbps, we 4215 * enable AutoNeg, but only allow the harware to advertise 4216 * 1000Mbps. This is different from 10/100 operation, where 4217 * we are allowed to link without any negotiation. 4218 */ 4219 mac->autoneg = B_TRUE; 4220 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4221 break; 4222 default: /* obey the setting of AutoNegAdvertised */ 4223 mac->autoneg = B_TRUE; 4224 phy->autoneg_advertised = 4225 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 4226 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4227 AUTONEG_ADVERTISE_SPEED_DEFAULT); 4228 break; 4229 } /* switch */ 4230 } 4231 4232 /* 4233 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4234 * 4235 * This function reads MaxFrameSize from e1000g.conf 4236 */ 4237 static void 4238 e1000g_get_max_frame_size(struct e1000g *Adapter) 4239 { 4240 int max_frame; 4241 4242 /* 4243 * get value out of config file 4244 */ 4245 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 4246 4247 switch (max_frame) { 4248 case 0: 4249 Adapter->default_mtu = ETHERMTU; 4250 break; 4251 /* 4252 * To avoid excessive memory allocation for rx buffers, 4253 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4254 */ 4255 case 1: 4256 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4257 sizeof (struct ether_vlan_header) - ETHERFCSL - 4258 E1000G_IPALIGNPRESERVEROOM; 4259 break; 4260 case 2: 4261 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4262 sizeof (struct ether_vlan_header) - ETHERFCSL - 4263 E1000G_IPALIGNPRESERVEROOM; 4264 break; 4265 case 3: 4266 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4267 sizeof (struct ether_vlan_header) - ETHERFCSL - 4268 E1000G_IPALIGNPRESERVEROOM; 4269 break; 4270 default: 4271 Adapter->default_mtu = ETHERMTU; 4272 break; 4273 } /* switch */ 4274 4275 /* 4276 * If the user configed MTU is larger than the deivce's maximum MTU, 4277 * the MTU is set to the deivce's maximum value. 4278 */ 4279 if (Adapter->default_mtu > Adapter->max_mtu) 4280 Adapter->default_mtu = Adapter->max_mtu; 4281 4282 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4283 } 4284 4285 /* 4286 * e1000g_pch_limits - Apply limits of the PCH silicon type 4287 * 4288 * At any frame size larger than the ethernet default, 4289 * prevent linking at 10/100 speeds. 4290 */ 4291 static void 4292 e1000g_pch_limits(struct e1000g *Adapter) 4293 { 4294 struct e1000_hw *hw = &Adapter->shared; 4295 4296 /* only applies to PCH silicon type */ 4297 if (hw->mac.type != e1000_pchlan) 4298 return; 4299 4300 /* only applies to frames larger than ethernet default */ 4301 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4302 hw->mac.autoneg = B_TRUE; 4303 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4304 4305 Adapter->param_adv_autoneg = 1; 4306 Adapter->param_adv_1000fdx = 1; 4307 4308 Adapter->param_adv_100fdx = 0; 4309 Adapter->param_adv_100hdx = 0; 4310 Adapter->param_adv_10fdx = 0; 4311 Adapter->param_adv_10hdx = 0; 4312 4313 e1000g_param_sync(Adapter); 4314 } 4315 } 4316 4317 /* 4318 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4319 */ 4320 static uint32_t 4321 e1000g_mtu2maxframe(uint32_t mtu) 4322 { 4323 uint32_t maxframe; 4324 4325 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4326 4327 return (maxframe); 4328 } 4329 4330 static void 4331 arm_watchdog_timer(struct e1000g *Adapter) 4332 { 4333 Adapter->watchdog_tid = 4334 timeout(e1000g_local_timer, 4335 (void *)Adapter, 1 * drv_usectohz(1000000)); 4336 } 4337 #pragma inline(arm_watchdog_timer) 4338 4339 static void 4340 enable_watchdog_timer(struct e1000g *Adapter) 4341 { 4342 mutex_enter(&Adapter->watchdog_lock); 4343 4344 if (!Adapter->watchdog_timer_enabled) { 4345 Adapter->watchdog_timer_enabled = B_TRUE; 4346 Adapter->watchdog_timer_started = B_TRUE; 4347 arm_watchdog_timer(Adapter); 4348 } 4349 4350 mutex_exit(&Adapter->watchdog_lock); 4351 } 4352 4353 static void 4354 disable_watchdog_timer(struct e1000g *Adapter) 4355 { 4356 timeout_id_t tid; 4357 4358 mutex_enter(&Adapter->watchdog_lock); 4359 4360 Adapter->watchdog_timer_enabled = B_FALSE; 4361 Adapter->watchdog_timer_started = B_FALSE; 4362 tid = Adapter->watchdog_tid; 4363 Adapter->watchdog_tid = 0; 4364 4365 mutex_exit(&Adapter->watchdog_lock); 4366 4367 if (tid != 0) 4368 (void) untimeout(tid); 4369 } 4370 4371 static void 4372 start_watchdog_timer(struct e1000g *Adapter) 4373 { 4374 mutex_enter(&Adapter->watchdog_lock); 4375 4376 if (Adapter->watchdog_timer_enabled) { 4377 if (!Adapter->watchdog_timer_started) { 4378 Adapter->watchdog_timer_started = B_TRUE; 4379 arm_watchdog_timer(Adapter); 4380 } 4381 } 4382 4383 mutex_exit(&Adapter->watchdog_lock); 4384 } 4385 4386 static void 4387 restart_watchdog_timer(struct e1000g *Adapter) 4388 { 4389 mutex_enter(&Adapter->watchdog_lock); 4390 4391 if (Adapter->watchdog_timer_started) 4392 arm_watchdog_timer(Adapter); 4393 4394 mutex_exit(&Adapter->watchdog_lock); 4395 } 4396 4397 static void 4398 stop_watchdog_timer(struct e1000g *Adapter) 4399 { 4400 timeout_id_t tid; 4401 4402 mutex_enter(&Adapter->watchdog_lock); 4403 4404 Adapter->watchdog_timer_started = B_FALSE; 4405 tid = Adapter->watchdog_tid; 4406 Adapter->watchdog_tid = 0; 4407 4408 mutex_exit(&Adapter->watchdog_lock); 4409 4410 if (tid != 0) 4411 (void) untimeout(tid); 4412 } 4413 4414 static void 4415 stop_link_timer(struct e1000g *Adapter) 4416 { 4417 timeout_id_t tid; 4418 4419 /* Disable the link timer */ 4420 mutex_enter(&Adapter->link_lock); 4421 4422 tid = Adapter->link_tid; 4423 Adapter->link_tid = 0; 4424 4425 mutex_exit(&Adapter->link_lock); 4426 4427 if (tid != 0) 4428 (void) untimeout(tid); 4429 } 4430 4431 static void 4432 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4433 { 4434 timeout_id_t tid; 4435 4436 /* Disable the tx timer for 82547 chipset */ 4437 mutex_enter(&tx_ring->tx_lock); 4438 4439 tx_ring->timer_enable_82547 = B_FALSE; 4440 tid = tx_ring->timer_id_82547; 4441 tx_ring->timer_id_82547 = 0; 4442 4443 mutex_exit(&tx_ring->tx_lock); 4444 4445 if (tid != 0) 4446 (void) untimeout(tid); 4447 } 4448 4449 void 4450 e1000g_clear_interrupt(struct e1000g *Adapter) 4451 { 4452 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4453 0xffffffff & ~E1000_IMS_RXSEQ); 4454 } 4455 4456 void 4457 e1000g_mask_interrupt(struct e1000g *Adapter) 4458 { 4459 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4460 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4461 4462 if (Adapter->tx_intr_enable) 4463 e1000g_mask_tx_interrupt(Adapter); 4464 } 4465 4466 /* 4467 * This routine is called by e1000g_quiesce(), therefore must not block. 4468 */ 4469 void 4470 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4471 { 4472 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4473 } 4474 4475 void 4476 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4477 { 4478 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4479 } 4480 4481 void 4482 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4483 { 4484 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4485 } 4486 4487 static void 4488 e1000g_smartspeed(struct e1000g *Adapter) 4489 { 4490 struct e1000_hw *hw = &Adapter->shared; 4491 uint16_t phy_status; 4492 uint16_t phy_ctrl; 4493 4494 /* 4495 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4496 * advertising 1000Full, we don't even use the workaround 4497 */ 4498 if ((hw->phy.type != e1000_phy_igp) || 4499 !hw->mac.autoneg || 4500 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4501 return; 4502 4503 /* 4504 * True if this is the first call of this function or after every 4505 * 30 seconds of not having link 4506 */ 4507 if (Adapter->smartspeed == 0) { 4508 /* 4509 * If Master/Slave config fault is asserted twice, we 4510 * assume back-to-back 4511 */ 4512 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4513 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4514 return; 4515 4516 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4517 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4518 return; 4519 /* 4520 * We're assuming back-2-back because our status register 4521 * insists! there's a fault in the master/slave 4522 * relationship that was "negotiated" 4523 */ 4524 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4525 /* 4526 * Is the phy configured for manual configuration of 4527 * master/slave? 4528 */ 4529 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4530 /* 4531 * Yes. Then disable manual configuration (enable 4532 * auto configuration) of master/slave 4533 */ 4534 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4535 (void) e1000_write_phy_reg(hw, 4536 PHY_1000T_CTRL, phy_ctrl); 4537 /* 4538 * Effectively starting the clock 4539 */ 4540 Adapter->smartspeed++; 4541 /* 4542 * Restart autonegotiation 4543 */ 4544 if (!e1000_phy_setup_autoneg(hw) && 4545 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4546 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4547 MII_CR_RESTART_AUTO_NEG); 4548 (void) e1000_write_phy_reg(hw, 4549 PHY_CONTROL, phy_ctrl); 4550 } 4551 } 4552 return; 4553 /* 4554 * Has 6 seconds transpired still without link? Remember, 4555 * you should reset the smartspeed counter once you obtain 4556 * link 4557 */ 4558 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4559 /* 4560 * Yes. Remember, we did at the start determine that 4561 * there's a master/slave configuration fault, so we're 4562 * still assuming there's someone on the other end, but we 4563 * just haven't yet been able to talk to it. We then 4564 * re-enable auto configuration of master/slave to see if 4565 * we're running 2/3 pair cables. 4566 */ 4567 /* 4568 * If still no link, perhaps using 2/3 pair cable 4569 */ 4570 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4571 phy_ctrl |= CR_1000T_MS_ENABLE; 4572 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4573 /* 4574 * Restart autoneg with phy enabled for manual 4575 * configuration of master/slave 4576 */ 4577 if (!e1000_phy_setup_autoneg(hw) && 4578 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4579 phy_ctrl |= 4580 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4581 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4582 } 4583 /* 4584 * Hopefully, there are no more faults and we've obtained 4585 * link as a result. 4586 */ 4587 } 4588 /* 4589 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4590 * seconds) 4591 */ 4592 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4593 Adapter->smartspeed = 0; 4594 } 4595 4596 static boolean_t 4597 is_valid_mac_addr(uint8_t *mac_addr) 4598 { 4599 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4600 const uint8_t addr_test2[6] = 4601 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4602 4603 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4604 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4605 return (B_FALSE); 4606 4607 return (B_TRUE); 4608 } 4609 4610 /* 4611 * e1000g_stall_check - check for tx stall 4612 * 4613 * This function checks if the adapter is stalled (in transmit). 4614 * 4615 * It is called each time the watchdog timeout is invoked. 4616 * If the transmit descriptor reclaim continuously fails, 4617 * the watchdog value will increment by 1. If the watchdog 4618 * value exceeds the threshold, the adapter is assumed to 4619 * have stalled and need to be reset. 4620 */ 4621 static boolean_t 4622 e1000g_stall_check(struct e1000g *Adapter) 4623 { 4624 e1000g_tx_ring_t *tx_ring; 4625 4626 tx_ring = Adapter->tx_ring; 4627 4628 if (Adapter->link_state != LINK_STATE_UP) 4629 return (B_FALSE); 4630 4631 (void) e1000g_recycle(tx_ring); 4632 4633 if (Adapter->stall_flag) { 4634 Adapter->stall_flag = B_FALSE; 4635 Adapter->reset_flag = B_TRUE; 4636 return (B_TRUE); 4637 } 4638 4639 return (B_FALSE); 4640 } 4641 4642 #ifdef E1000G_DEBUG 4643 static enum ioc_reply 4644 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4645 { 4646 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4647 e1000g_peekpoke_t *ppd; 4648 uint64_t mem_va; 4649 uint64_t maxoff; 4650 boolean_t peek; 4651 4652 switch (iocp->ioc_cmd) { 4653 4654 case E1000G_IOC_REG_PEEK: 4655 peek = B_TRUE; 4656 break; 4657 4658 case E1000G_IOC_REG_POKE: 4659 peek = B_FALSE; 4660 break; 4661 4662 deault: 4663 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4664 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4665 iocp->ioc_cmd); 4666 return (IOC_INVAL); 4667 } 4668 4669 /* 4670 * Validate format of ioctl 4671 */ 4672 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4673 return (IOC_INVAL); 4674 if (mp->b_cont == NULL) 4675 return (IOC_INVAL); 4676 4677 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4678 4679 /* 4680 * Validate request parameters 4681 */ 4682 switch (ppd->pp_acc_space) { 4683 4684 default: 4685 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4686 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4687 ppd->pp_acc_space); 4688 return (IOC_INVAL); 4689 4690 case E1000G_PP_SPACE_REG: 4691 /* 4692 * Memory-mapped I/O space 4693 */ 4694 ASSERT(ppd->pp_acc_size == 4); 4695 if (ppd->pp_acc_size != 4) 4696 return (IOC_INVAL); 4697 4698 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4699 return (IOC_INVAL); 4700 4701 mem_va = 0; 4702 maxoff = 0x10000; 4703 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4704 break; 4705 4706 case E1000G_PP_SPACE_E1000G: 4707 /* 4708 * E1000g data structure! 4709 */ 4710 mem_va = (uintptr_t)e1000gp; 4711 maxoff = sizeof (struct e1000g); 4712 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4713 break; 4714 4715 } 4716 4717 if (ppd->pp_acc_offset >= maxoff) 4718 return (IOC_INVAL); 4719 4720 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4721 return (IOC_INVAL); 4722 4723 /* 4724 * All OK - go! 4725 */ 4726 ppd->pp_acc_offset += mem_va; 4727 (*ppfn)(e1000gp, ppd); 4728 return (peek ? IOC_REPLY : IOC_ACK); 4729 } 4730 4731 static void 4732 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4733 { 4734 ddi_acc_handle_t handle; 4735 uint32_t *regaddr; 4736 4737 handle = e1000gp->osdep.reg_handle; 4738 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4739 (uintptr_t)ppd->pp_acc_offset); 4740 4741 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4742 } 4743 4744 static void 4745 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4746 { 4747 ddi_acc_handle_t handle; 4748 uint32_t *regaddr; 4749 uint32_t value; 4750 4751 handle = e1000gp->osdep.reg_handle; 4752 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4753 (uintptr_t)ppd->pp_acc_offset); 4754 value = (uint32_t)ppd->pp_acc_data; 4755 4756 ddi_put32(handle, regaddr, value); 4757 } 4758 4759 static void 4760 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4761 { 4762 uint64_t value; 4763 void *vaddr; 4764 4765 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4766 4767 switch (ppd->pp_acc_size) { 4768 case 1: 4769 value = *(uint8_t *)vaddr; 4770 break; 4771 4772 case 2: 4773 value = *(uint16_t *)vaddr; 4774 break; 4775 4776 case 4: 4777 value = *(uint32_t *)vaddr; 4778 break; 4779 4780 case 8: 4781 value = *(uint64_t *)vaddr; 4782 break; 4783 } 4784 4785 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4786 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4787 (void *)e1000gp, (void *)ppd, value, vaddr); 4788 4789 ppd->pp_acc_data = value; 4790 } 4791 4792 static void 4793 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4794 { 4795 uint64_t value; 4796 void *vaddr; 4797 4798 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4799 value = ppd->pp_acc_data; 4800 4801 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4802 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4803 (void *)e1000gp, (void *)ppd, value, vaddr); 4804 4805 switch (ppd->pp_acc_size) { 4806 case 1: 4807 *(uint8_t *)vaddr = (uint8_t)value; 4808 break; 4809 4810 case 2: 4811 *(uint16_t *)vaddr = (uint16_t)value; 4812 break; 4813 4814 case 4: 4815 *(uint32_t *)vaddr = (uint32_t)value; 4816 break; 4817 4818 case 8: 4819 *(uint64_t *)vaddr = (uint64_t)value; 4820 break; 4821 } 4822 } 4823 #endif 4824 4825 /* 4826 * Loopback Support 4827 */ 4828 static lb_property_t lb_normal = 4829 { normal, "normal", E1000G_LB_NONE }; 4830 static lb_property_t lb_external1000 = 4831 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4832 static lb_property_t lb_external100 = 4833 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4834 static lb_property_t lb_external10 = 4835 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4836 static lb_property_t lb_phy = 4837 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4838 4839 static enum ioc_reply 4840 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4841 { 4842 lb_info_sz_t *lbsp; 4843 lb_property_t *lbpp; 4844 struct e1000_hw *hw; 4845 uint32_t *lbmp; 4846 uint32_t size; 4847 uint32_t value; 4848 4849 hw = &Adapter->shared; 4850 4851 if (mp->b_cont == NULL) 4852 return (IOC_INVAL); 4853 4854 if (!e1000g_check_loopback_support(hw)) { 4855 e1000g_log(NULL, CE_WARN, 4856 "Loopback is not supported on e1000g%d", Adapter->instance); 4857 return (IOC_INVAL); 4858 } 4859 4860 switch (iocp->ioc_cmd) { 4861 default: 4862 return (IOC_INVAL); 4863 4864 case LB_GET_INFO_SIZE: 4865 size = sizeof (lb_info_sz_t); 4866 if (iocp->ioc_count != size) 4867 return (IOC_INVAL); 4868 4869 rw_enter(&Adapter->chip_lock, RW_WRITER); 4870 e1000g_get_phy_state(Adapter); 4871 4872 /* 4873 * Workaround for hardware faults. In order to get a stable 4874 * state of phy, we will wait for a specific interval and 4875 * try again. The time delay is an experiential value based 4876 * on our testing. 4877 */ 4878 msec_delay(100); 4879 e1000g_get_phy_state(Adapter); 4880 rw_exit(&Adapter->chip_lock); 4881 4882 value = sizeof (lb_normal); 4883 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4884 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4885 (hw->phy.media_type == e1000_media_type_fiber) || 4886 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4887 value += sizeof (lb_phy); 4888 switch (hw->mac.type) { 4889 case e1000_82571: 4890 case e1000_82572: 4891 case e1000_80003es2lan: 4892 value += sizeof (lb_external1000); 4893 break; 4894 } 4895 } 4896 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4897 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4898 value += sizeof (lb_external100); 4899 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4900 value += sizeof (lb_external10); 4901 4902 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4903 *lbsp = value; 4904 break; 4905 4906 case LB_GET_INFO: 4907 value = sizeof (lb_normal); 4908 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4909 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4910 (hw->phy.media_type == e1000_media_type_fiber) || 4911 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4912 value += sizeof (lb_phy); 4913 switch (hw->mac.type) { 4914 case e1000_82571: 4915 case e1000_82572: 4916 case e1000_80003es2lan: 4917 value += sizeof (lb_external1000); 4918 break; 4919 } 4920 } 4921 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4922 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4923 value += sizeof (lb_external100); 4924 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4925 value += sizeof (lb_external10); 4926 4927 size = value; 4928 if (iocp->ioc_count != size) 4929 return (IOC_INVAL); 4930 4931 value = 0; 4932 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4933 lbpp[value++] = lb_normal; 4934 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4935 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4936 (hw->phy.media_type == e1000_media_type_fiber) || 4937 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4938 lbpp[value++] = lb_phy; 4939 switch (hw->mac.type) { 4940 case e1000_82571: 4941 case e1000_82572: 4942 case e1000_80003es2lan: 4943 lbpp[value++] = lb_external1000; 4944 break; 4945 } 4946 } 4947 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4948 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4949 lbpp[value++] = lb_external100; 4950 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4951 lbpp[value++] = lb_external10; 4952 break; 4953 4954 case LB_GET_MODE: 4955 size = sizeof (uint32_t); 4956 if (iocp->ioc_count != size) 4957 return (IOC_INVAL); 4958 4959 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4960 *lbmp = Adapter->loopback_mode; 4961 break; 4962 4963 case LB_SET_MODE: 4964 size = 0; 4965 if (iocp->ioc_count != sizeof (uint32_t)) 4966 return (IOC_INVAL); 4967 4968 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4969 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4970 return (IOC_INVAL); 4971 break; 4972 } 4973 4974 iocp->ioc_count = size; 4975 iocp->ioc_error = 0; 4976 4977 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4978 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4979 return (IOC_INVAL); 4980 } 4981 4982 return (IOC_REPLY); 4983 } 4984 4985 static boolean_t 4986 e1000g_check_loopback_support(struct e1000_hw *hw) 4987 { 4988 switch (hw->mac.type) { 4989 case e1000_82540: 4990 case e1000_82545: 4991 case e1000_82545_rev_3: 4992 case e1000_82546: 4993 case e1000_82546_rev_3: 4994 case e1000_82541: 4995 case e1000_82541_rev_2: 4996 case e1000_82547: 4997 case e1000_82547_rev_2: 4998 case e1000_82571: 4999 case e1000_82572: 5000 case e1000_82573: 5001 case e1000_82574: 5002 case e1000_80003es2lan: 5003 case e1000_ich9lan: 5004 case e1000_ich10lan: 5005 return (B_TRUE); 5006 } 5007 return (B_FALSE); 5008 } 5009 5010 static boolean_t 5011 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5012 { 5013 struct e1000_hw *hw; 5014 int i, times; 5015 boolean_t link_up; 5016 5017 if (mode == Adapter->loopback_mode) 5018 return (B_TRUE); 5019 5020 hw = &Adapter->shared; 5021 times = 0; 5022 5023 Adapter->loopback_mode = mode; 5024 5025 if (mode == E1000G_LB_NONE) { 5026 /* Reset the chip */ 5027 hw->phy.autoneg_wait_to_complete = B_TRUE; 5028 (void) e1000g_reset_adapter(Adapter); 5029 hw->phy.autoneg_wait_to_complete = B_FALSE; 5030 return (B_TRUE); 5031 } 5032 5033 again: 5034 5035 rw_enter(&Adapter->chip_lock, RW_WRITER); 5036 5037 switch (mode) { 5038 default: 5039 rw_exit(&Adapter->chip_lock); 5040 return (B_FALSE); 5041 5042 case E1000G_LB_EXTERNAL_1000: 5043 e1000g_set_external_loopback_1000(Adapter); 5044 break; 5045 5046 case E1000G_LB_EXTERNAL_100: 5047 e1000g_set_external_loopback_100(Adapter); 5048 break; 5049 5050 case E1000G_LB_EXTERNAL_10: 5051 e1000g_set_external_loopback_10(Adapter); 5052 break; 5053 5054 case E1000G_LB_INTERNAL_PHY: 5055 e1000g_set_internal_loopback(Adapter); 5056 break; 5057 } 5058 5059 times++; 5060 5061 rw_exit(&Adapter->chip_lock); 5062 5063 /* Wait for link up */ 5064 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5065 msec_delay(100); 5066 5067 rw_enter(&Adapter->chip_lock, RW_WRITER); 5068 5069 link_up = e1000g_link_up(Adapter); 5070 5071 rw_exit(&Adapter->chip_lock); 5072 5073 if (!link_up) { 5074 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5075 "Failed to get the link up"); 5076 if (times < 2) { 5077 /* Reset the link */ 5078 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5079 "Reset the link ..."); 5080 (void) e1000g_reset_adapter(Adapter); 5081 goto again; 5082 } 5083 } 5084 5085 return (B_TRUE); 5086 } 5087 5088 /* 5089 * The following loopback settings are from Intel's technical 5090 * document - "How To Loopback". All the register settings and 5091 * time delay values are directly inherited from the document 5092 * without more explanations available. 5093 */ 5094 static void 5095 e1000g_set_internal_loopback(struct e1000g *Adapter) 5096 { 5097 struct e1000_hw *hw; 5098 uint32_t ctrl; 5099 uint32_t status; 5100 uint16_t phy_ctrl; 5101 uint16_t phy_reg; 5102 uint32_t txcw; 5103 5104 hw = &Adapter->shared; 5105 5106 /* Disable Smart Power Down */ 5107 phy_spd_state(hw, B_FALSE); 5108 5109 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5110 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5111 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5112 5113 switch (hw->mac.type) { 5114 case e1000_82540: 5115 case e1000_82545: 5116 case e1000_82545_rev_3: 5117 case e1000_82546: 5118 case e1000_82546_rev_3: 5119 case e1000_82573: 5120 /* Auto-MDI/MDIX off */ 5121 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5122 /* Reset PHY to update Auto-MDI/MDIX */ 5123 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5124 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5125 /* Reset PHY to auto-neg off and force 1000 */ 5126 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5127 phy_ctrl | MII_CR_RESET); 5128 /* 5129 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5130 * See comments above e1000g_set_internal_loopback() for the 5131 * background. 5132 */ 5133 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5134 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5135 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5136 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5137 break; 5138 case e1000_80003es2lan: 5139 /* Force Link Up */ 5140 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5141 0x1CC); 5142 /* Sets PCS loopback at 1Gbs */ 5143 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5144 0x1046); 5145 break; 5146 } 5147 5148 /* 5149 * The following registers should be set for e1000_phy_bm phy type. 5150 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5151 * For others, we do not need to set these registers. 5152 */ 5153 if (hw->phy.type == e1000_phy_bm) { 5154 /* Set Default MAC Interface speed to 1GB */ 5155 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5156 phy_reg &= ~0x0007; 5157 phy_reg |= 0x006; 5158 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5159 /* Assert SW reset for above settings to take effect */ 5160 (void) e1000_phy_commit(hw); 5161 msec_delay(1); 5162 /* Force Full Duplex */ 5163 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5164 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5165 phy_reg | 0x000C); 5166 /* Set Link Up (in force link) */ 5167 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5168 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5169 phy_reg | 0x0040); 5170 /* Force Link */ 5171 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5172 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5173 phy_reg | 0x0040); 5174 /* Set Early Link Enable */ 5175 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5176 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5177 phy_reg | 0x0400); 5178 } 5179 5180 /* Set loopback */ 5181 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5182 5183 msec_delay(250); 5184 5185 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5186 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5187 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5188 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5189 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5190 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5191 E1000_CTRL_FD); /* Force Duplex to FULL */ 5192 5193 switch (hw->mac.type) { 5194 case e1000_82540: 5195 case e1000_82545: 5196 case e1000_82545_rev_3: 5197 case e1000_82546: 5198 case e1000_82546_rev_3: 5199 /* 5200 * For some serdes we'll need to commit the writes now 5201 * so that the status is updated on link 5202 */ 5203 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5204 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5205 msec_delay(100); 5206 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5207 } 5208 5209 if (hw->phy.media_type == e1000_media_type_copper) { 5210 /* Invert Loss of Signal */ 5211 ctrl |= E1000_CTRL_ILOS; 5212 } else { 5213 /* Set ILOS on fiber nic if half duplex is detected */ 5214 status = E1000_READ_REG(hw, E1000_STATUS); 5215 if ((status & E1000_STATUS_FD) == 0) 5216 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5217 } 5218 break; 5219 5220 case e1000_82571: 5221 case e1000_82572: 5222 /* 5223 * The fiber/SerDes versions of this adapter do not contain an 5224 * accessible PHY. Therefore, loopback beyond MAC must be done 5225 * using SerDes analog loopback. 5226 */ 5227 if (hw->phy.media_type != e1000_media_type_copper) { 5228 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5229 txcw = E1000_READ_REG(hw, E1000_TXCW); 5230 txcw &= ~((uint32_t)1 << 31); 5231 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5232 5233 /* 5234 * Write 0x410 to Serdes Control register 5235 * to enable Serdes analog loopback 5236 */ 5237 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5238 msec_delay(10); 5239 } 5240 5241 status = E1000_READ_REG(hw, E1000_STATUS); 5242 /* Set ILOS on fiber nic if half duplex is detected */ 5243 if ((hw->phy.media_type == e1000_media_type_fiber) && 5244 ((status & E1000_STATUS_FD) == 0 || 5245 (status & E1000_STATUS_LU) == 0)) 5246 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5247 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5248 ctrl |= E1000_CTRL_SLU; 5249 break; 5250 5251 case e1000_82573: 5252 ctrl |= E1000_CTRL_ILOS; 5253 break; 5254 case e1000_ich9lan: 5255 case e1000_ich10lan: 5256 ctrl |= E1000_CTRL_SLU; 5257 break; 5258 } 5259 if (hw->phy.type == e1000_phy_bm) 5260 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5261 5262 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5263 } 5264 5265 static void 5266 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5267 { 5268 struct e1000_hw *hw; 5269 uint32_t rctl; 5270 uint32_t ctrl_ext; 5271 uint32_t ctrl; 5272 uint32_t status; 5273 uint32_t txcw; 5274 uint16_t phydata; 5275 5276 hw = &Adapter->shared; 5277 5278 /* Disable Smart Power Down */ 5279 phy_spd_state(hw, B_FALSE); 5280 5281 switch (hw->mac.type) { 5282 case e1000_82571: 5283 case e1000_82572: 5284 switch (hw->phy.media_type) { 5285 case e1000_media_type_copper: 5286 /* Force link up (Must be done before the PHY writes) */ 5287 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5288 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5289 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5290 5291 rctl = E1000_READ_REG(hw, E1000_RCTL); 5292 rctl |= (E1000_RCTL_EN | 5293 E1000_RCTL_SBP | 5294 E1000_RCTL_UPE | 5295 E1000_RCTL_MPE | 5296 E1000_RCTL_LPE | 5297 E1000_RCTL_BAM); /* 0x803E */ 5298 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5299 5300 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5301 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5302 E1000_CTRL_EXT_SDP6_DATA | 5303 E1000_CTRL_EXT_SDP3_DATA | 5304 E1000_CTRL_EXT_SDP4_DIR | 5305 E1000_CTRL_EXT_SDP6_DIR | 5306 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5307 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5308 5309 /* 5310 * This sequence tunes the PHY's SDP and no customer 5311 * settable values. For background, see comments above 5312 * e1000g_set_internal_loopback(). 5313 */ 5314 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5315 msec_delay(10); 5316 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5317 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5318 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5319 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5320 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5321 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5322 5323 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5324 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5325 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5326 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5327 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5328 5329 msec_delay(50); 5330 break; 5331 case e1000_media_type_fiber: 5332 case e1000_media_type_internal_serdes: 5333 status = E1000_READ_REG(hw, E1000_STATUS); 5334 if (((status & E1000_STATUS_LU) == 0) || 5335 (hw->phy.media_type == 5336 e1000_media_type_internal_serdes)) { 5337 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5338 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5339 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5340 } 5341 5342 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5343 txcw = E1000_READ_REG(hw, E1000_TXCW); 5344 txcw &= ~((uint32_t)1 << 31); 5345 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5346 5347 /* 5348 * Write 0x410 to Serdes Control register 5349 * to enable Serdes analog loopback 5350 */ 5351 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5352 msec_delay(10); 5353 break; 5354 default: 5355 break; 5356 } 5357 break; 5358 case e1000_82574: 5359 case e1000_80003es2lan: 5360 case e1000_ich9lan: 5361 case e1000_ich10lan: 5362 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5363 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5364 phydata | (1 << 5)); 5365 Adapter->param_adv_autoneg = 1; 5366 Adapter->param_adv_1000fdx = 1; 5367 (void) e1000g_reset_link(Adapter); 5368 break; 5369 } 5370 } 5371 5372 static void 5373 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5374 { 5375 struct e1000_hw *hw; 5376 uint32_t ctrl; 5377 uint16_t phy_ctrl; 5378 5379 hw = &Adapter->shared; 5380 5381 /* Disable Smart Power Down */ 5382 phy_spd_state(hw, B_FALSE); 5383 5384 phy_ctrl = (MII_CR_FULL_DUPLEX | 5385 MII_CR_SPEED_100); 5386 5387 /* Force 100/FD, reset PHY */ 5388 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5389 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5390 msec_delay(10); 5391 5392 /* Force 100/FD */ 5393 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5394 phy_ctrl); /* 0x2100 */ 5395 msec_delay(10); 5396 5397 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5398 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5399 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5400 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5401 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5402 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5403 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5404 E1000_CTRL_FD); /* Force Duplex to FULL */ 5405 5406 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5407 } 5408 5409 static void 5410 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5411 { 5412 struct e1000_hw *hw; 5413 uint32_t ctrl; 5414 uint16_t phy_ctrl; 5415 5416 hw = &Adapter->shared; 5417 5418 /* Disable Smart Power Down */ 5419 phy_spd_state(hw, B_FALSE); 5420 5421 phy_ctrl = (MII_CR_FULL_DUPLEX | 5422 MII_CR_SPEED_10); 5423 5424 /* Force 10/FD, reset PHY */ 5425 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5426 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5427 msec_delay(10); 5428 5429 /* Force 10/FD */ 5430 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5431 phy_ctrl); /* 0x0100 */ 5432 msec_delay(10); 5433 5434 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5435 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5436 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5437 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5438 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5439 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5440 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5441 E1000_CTRL_FD); /* Force Duplex to FULL */ 5442 5443 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5444 } 5445 5446 #ifdef __sparc 5447 static boolean_t 5448 e1000g_find_mac_address(struct e1000g *Adapter) 5449 { 5450 struct e1000_hw *hw = &Adapter->shared; 5451 uchar_t *bytes; 5452 struct ether_addr sysaddr; 5453 uint_t nelts; 5454 int err; 5455 boolean_t found = B_FALSE; 5456 5457 /* 5458 * The "vendor's factory-set address" may already have 5459 * been extracted from the chip, but if the property 5460 * "local-mac-address" is set we use that instead. 5461 * 5462 * We check whether it looks like an array of 6 5463 * bytes (which it should, if OBP set it). If we can't 5464 * make sense of it this way, we'll ignore it. 5465 */ 5466 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5467 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5468 if (err == DDI_PROP_SUCCESS) { 5469 if (nelts == ETHERADDRL) { 5470 while (nelts--) 5471 hw->mac.addr[nelts] = bytes[nelts]; 5472 found = B_TRUE; 5473 } 5474 ddi_prop_free(bytes); 5475 } 5476 5477 /* 5478 * Look up the OBP property "local-mac-address?". If the user has set 5479 * 'local-mac-address? = false', use "the system address" instead. 5480 */ 5481 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5482 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5483 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5484 if (localetheraddr(NULL, &sysaddr) != 0) { 5485 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5486 found = B_TRUE; 5487 } 5488 } 5489 ddi_prop_free(bytes); 5490 } 5491 5492 /* 5493 * Finally(!), if there's a valid "mac-address" property (created 5494 * if we netbooted from this interface), we must use this instead 5495 * of any of the above to ensure that the NFS/install server doesn't 5496 * get confused by the address changing as Solaris takes over! 5497 */ 5498 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5499 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5500 if (err == DDI_PROP_SUCCESS) { 5501 if (nelts == ETHERADDRL) { 5502 while (nelts--) 5503 hw->mac.addr[nelts] = bytes[nelts]; 5504 found = B_TRUE; 5505 } 5506 ddi_prop_free(bytes); 5507 } 5508 5509 if (found) { 5510 bcopy(hw->mac.addr, hw->mac.perm_addr, 5511 ETHERADDRL); 5512 } 5513 5514 return (found); 5515 } 5516 #endif 5517 5518 static int 5519 e1000g_add_intrs(struct e1000g *Adapter) 5520 { 5521 dev_info_t *devinfo; 5522 int intr_types; 5523 int rc; 5524 5525 devinfo = Adapter->dip; 5526 5527 /* Get supported interrupt types */ 5528 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5529 5530 if (rc != DDI_SUCCESS) { 5531 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5532 "Get supported interrupt types failed: %d\n", rc); 5533 return (DDI_FAILURE); 5534 } 5535 5536 /* 5537 * Based on Intel Technical Advisory document (TA-160), there are some 5538 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5539 * that it supports MSI, but in fact has problems. 5540 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5541 * PCI/PCI-X NICs. 5542 */ 5543 if (Adapter->shared.mac.type < e1000_82571) 5544 Adapter->msi_enable = B_FALSE; 5545 5546 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5547 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5548 5549 if (rc != DDI_SUCCESS) { 5550 /* EMPTY */ 5551 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5552 "Add MSI failed, trying Legacy interrupts\n"); 5553 } else { 5554 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5555 } 5556 } 5557 5558 if ((Adapter->intr_type == 0) && 5559 (intr_types & DDI_INTR_TYPE_FIXED)) { 5560 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5561 5562 if (rc != DDI_SUCCESS) { 5563 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5564 "Add Legacy interrupts failed\n"); 5565 return (DDI_FAILURE); 5566 } 5567 5568 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5569 } 5570 5571 if (Adapter->intr_type == 0) { 5572 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5573 "No interrupts registered\n"); 5574 return (DDI_FAILURE); 5575 } 5576 5577 return (DDI_SUCCESS); 5578 } 5579 5580 /* 5581 * e1000g_intr_add() handles MSI/Legacy interrupts 5582 */ 5583 static int 5584 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5585 { 5586 dev_info_t *devinfo; 5587 int count, avail, actual; 5588 int x, y, rc, inum = 0; 5589 int flag; 5590 ddi_intr_handler_t *intr_handler; 5591 5592 devinfo = Adapter->dip; 5593 5594 /* get number of interrupts */ 5595 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5596 if ((rc != DDI_SUCCESS) || (count == 0)) { 5597 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5598 "Get interrupt number failed. Return: %d, count: %d\n", 5599 rc, count); 5600 return (DDI_FAILURE); 5601 } 5602 5603 /* get number of available interrupts */ 5604 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5605 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5606 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5607 "Get interrupt available number failed. " 5608 "Return: %d, available: %d\n", rc, avail); 5609 return (DDI_FAILURE); 5610 } 5611 5612 if (avail < count) { 5613 /* EMPTY */ 5614 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5615 "Interrupts count: %d, available: %d\n", 5616 count, avail); 5617 } 5618 5619 /* Allocate an array of interrupt handles */ 5620 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5621 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5622 5623 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5624 flag = DDI_INTR_ALLOC_NORMAL; 5625 5626 /* call ddi_intr_alloc() */ 5627 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5628 count, &actual, flag); 5629 5630 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5631 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5632 "Allocate interrupts failed: %d\n", rc); 5633 5634 kmem_free(Adapter->htable, Adapter->intr_size); 5635 return (DDI_FAILURE); 5636 } 5637 5638 if (actual < count) { 5639 /* EMPTY */ 5640 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5641 "Interrupts requested: %d, received: %d\n", 5642 count, actual); 5643 } 5644 5645 Adapter->intr_cnt = actual; 5646 5647 /* Get priority for first msi, assume remaining are all the same */ 5648 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5649 5650 if (rc != DDI_SUCCESS) { 5651 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5652 "Get interrupt priority failed: %d\n", rc); 5653 5654 /* Free already allocated intr */ 5655 for (y = 0; y < actual; y++) 5656 (void) ddi_intr_free(Adapter->htable[y]); 5657 5658 kmem_free(Adapter->htable, Adapter->intr_size); 5659 return (DDI_FAILURE); 5660 } 5661 5662 /* 5663 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5664 * use the interrupt service routine e1000g_intr_pciexpress() 5665 * to avoid interrupt stealing when sharing interrupt with other 5666 * devices. 5667 */ 5668 if (Adapter->shared.mac.type < e1000_82571) 5669 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5670 else 5671 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5672 5673 /* Call ddi_intr_add_handler() */ 5674 for (x = 0; x < actual; x++) { 5675 rc = ddi_intr_add_handler(Adapter->htable[x], 5676 intr_handler, (caddr_t)Adapter, NULL); 5677 5678 if (rc != DDI_SUCCESS) { 5679 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5680 "Add interrupt handler failed: %d\n", rc); 5681 5682 /* Remove already added handler */ 5683 for (y = 0; y < x; y++) 5684 (void) ddi_intr_remove_handler( 5685 Adapter->htable[y]); 5686 5687 /* Free already allocated intr */ 5688 for (y = 0; y < actual; y++) 5689 (void) ddi_intr_free(Adapter->htable[y]); 5690 5691 kmem_free(Adapter->htable, Adapter->intr_size); 5692 return (DDI_FAILURE); 5693 } 5694 } 5695 5696 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5697 5698 if (rc != DDI_SUCCESS) { 5699 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5700 "Get interrupt cap failed: %d\n", rc); 5701 5702 /* Free already allocated intr */ 5703 for (y = 0; y < actual; y++) { 5704 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5705 (void) ddi_intr_free(Adapter->htable[y]); 5706 } 5707 5708 kmem_free(Adapter->htable, Adapter->intr_size); 5709 return (DDI_FAILURE); 5710 } 5711 5712 return (DDI_SUCCESS); 5713 } 5714 5715 static int 5716 e1000g_rem_intrs(struct e1000g *Adapter) 5717 { 5718 int x; 5719 int rc; 5720 5721 for (x = 0; x < Adapter->intr_cnt; x++) { 5722 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5723 if (rc != DDI_SUCCESS) { 5724 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5725 "Remove intr handler failed: %d\n", rc); 5726 return (DDI_FAILURE); 5727 } 5728 5729 rc = ddi_intr_free(Adapter->htable[x]); 5730 if (rc != DDI_SUCCESS) { 5731 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5732 "Free intr failed: %d\n", rc); 5733 return (DDI_FAILURE); 5734 } 5735 } 5736 5737 kmem_free(Adapter->htable, Adapter->intr_size); 5738 5739 return (DDI_SUCCESS); 5740 } 5741 5742 static int 5743 e1000g_enable_intrs(struct e1000g *Adapter) 5744 { 5745 int x; 5746 int rc; 5747 5748 /* Enable interrupts */ 5749 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5750 /* Call ddi_intr_block_enable() for MSI */ 5751 rc = ddi_intr_block_enable(Adapter->htable, 5752 Adapter->intr_cnt); 5753 if (rc != DDI_SUCCESS) { 5754 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5755 "Enable block intr failed: %d\n", rc); 5756 return (DDI_FAILURE); 5757 } 5758 } else { 5759 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5760 for (x = 0; x < Adapter->intr_cnt; x++) { 5761 rc = ddi_intr_enable(Adapter->htable[x]); 5762 if (rc != DDI_SUCCESS) { 5763 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5764 "Enable intr failed: %d\n", rc); 5765 return (DDI_FAILURE); 5766 } 5767 } 5768 } 5769 5770 return (DDI_SUCCESS); 5771 } 5772 5773 static int 5774 e1000g_disable_intrs(struct e1000g *Adapter) 5775 { 5776 int x; 5777 int rc; 5778 5779 /* Disable all interrupts */ 5780 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5781 rc = ddi_intr_block_disable(Adapter->htable, 5782 Adapter->intr_cnt); 5783 if (rc != DDI_SUCCESS) { 5784 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5785 "Disable block intr failed: %d\n", rc); 5786 return (DDI_FAILURE); 5787 } 5788 } else { 5789 for (x = 0; x < Adapter->intr_cnt; x++) { 5790 rc = ddi_intr_disable(Adapter->htable[x]); 5791 if (rc != DDI_SUCCESS) { 5792 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5793 "Disable intr failed: %d\n", rc); 5794 return (DDI_FAILURE); 5795 } 5796 } 5797 } 5798 5799 return (DDI_SUCCESS); 5800 } 5801 5802 /* 5803 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5804 */ 5805 static void 5806 e1000g_get_phy_state(struct e1000g *Adapter) 5807 { 5808 struct e1000_hw *hw = &Adapter->shared; 5809 5810 if (hw->phy.media_type == e1000_media_type_copper) { 5811 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5812 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5813 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 5814 &Adapter->phy_an_adv); 5815 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 5816 &Adapter->phy_an_exp); 5817 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 5818 &Adapter->phy_ext_status); 5819 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 5820 &Adapter->phy_1000t_ctrl); 5821 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5822 &Adapter->phy_1000t_status); 5823 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 5824 &Adapter->phy_lp_able); 5825 5826 Adapter->param_autoneg_cap = 5827 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5828 Adapter->param_pause_cap = 5829 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5830 Adapter->param_asym_pause_cap = 5831 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5832 Adapter->param_1000fdx_cap = 5833 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5834 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5835 Adapter->param_1000hdx_cap = 5836 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5837 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5838 Adapter->param_100t4_cap = 5839 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5840 Adapter->param_100fdx_cap = 5841 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5842 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5843 Adapter->param_100hdx_cap = 5844 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5845 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5846 Adapter->param_10fdx_cap = 5847 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5848 Adapter->param_10hdx_cap = 5849 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5850 5851 Adapter->param_adv_autoneg = hw->mac.autoneg; 5852 Adapter->param_adv_pause = 5853 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5854 Adapter->param_adv_asym_pause = 5855 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5856 Adapter->param_adv_1000hdx = 5857 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5858 Adapter->param_adv_100t4 = 5859 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5860 if (Adapter->param_adv_autoneg == 1) { 5861 Adapter->param_adv_1000fdx = 5862 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 5863 ? 1 : 0; 5864 Adapter->param_adv_100fdx = 5865 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 5866 ? 1 : 0; 5867 Adapter->param_adv_100hdx = 5868 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 5869 ? 1 : 0; 5870 Adapter->param_adv_10fdx = 5871 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5872 Adapter->param_adv_10hdx = 5873 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5874 } 5875 5876 Adapter->param_lp_autoneg = 5877 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5878 Adapter->param_lp_pause = 5879 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5880 Adapter->param_lp_asym_pause = 5881 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5882 Adapter->param_lp_1000fdx = 5883 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5884 Adapter->param_lp_1000hdx = 5885 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5886 Adapter->param_lp_100t4 = 5887 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5888 Adapter->param_lp_100fdx = 5889 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5890 Adapter->param_lp_100hdx = 5891 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5892 Adapter->param_lp_10fdx = 5893 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5894 Adapter->param_lp_10hdx = 5895 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5896 } else { 5897 /* 5898 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 5899 * it can only work with 1Gig Full Duplex Link Partner. 5900 */ 5901 Adapter->param_autoneg_cap = 0; 5902 Adapter->param_pause_cap = 1; 5903 Adapter->param_asym_pause_cap = 1; 5904 Adapter->param_1000fdx_cap = 1; 5905 Adapter->param_1000hdx_cap = 0; 5906 Adapter->param_100t4_cap = 0; 5907 Adapter->param_100fdx_cap = 0; 5908 Adapter->param_100hdx_cap = 0; 5909 Adapter->param_10fdx_cap = 0; 5910 Adapter->param_10hdx_cap = 0; 5911 5912 Adapter->param_adv_autoneg = 0; 5913 Adapter->param_adv_pause = 1; 5914 Adapter->param_adv_asym_pause = 1; 5915 Adapter->param_adv_1000fdx = 1; 5916 Adapter->param_adv_1000hdx = 0; 5917 Adapter->param_adv_100t4 = 0; 5918 Adapter->param_adv_100fdx = 0; 5919 Adapter->param_adv_100hdx = 0; 5920 Adapter->param_adv_10fdx = 0; 5921 Adapter->param_adv_10hdx = 0; 5922 5923 Adapter->param_lp_autoneg = 0; 5924 Adapter->param_lp_pause = 0; 5925 Adapter->param_lp_asym_pause = 0; 5926 Adapter->param_lp_1000fdx = 0; 5927 Adapter->param_lp_1000hdx = 0; 5928 Adapter->param_lp_100t4 = 0; 5929 Adapter->param_lp_100fdx = 0; 5930 Adapter->param_lp_100hdx = 0; 5931 Adapter->param_lp_10fdx = 0; 5932 Adapter->param_lp_10hdx = 0; 5933 } 5934 } 5935 5936 /* 5937 * FMA support 5938 */ 5939 5940 int 5941 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5942 { 5943 ddi_fm_error_t de; 5944 5945 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5946 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5947 return (de.fme_status); 5948 } 5949 5950 int 5951 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5952 { 5953 ddi_fm_error_t de; 5954 5955 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5956 return (de.fme_status); 5957 } 5958 5959 /* 5960 * The IO fault service error handling callback function 5961 */ 5962 /* ARGSUSED2 */ 5963 static int 5964 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5965 { 5966 /* 5967 * as the driver can always deal with an error in any dma or 5968 * access handle, we can just return the fme_status value. 5969 */ 5970 pci_ereport_post(dip, err, NULL); 5971 return (err->fme_status); 5972 } 5973 5974 static void 5975 e1000g_fm_init(struct e1000g *Adapter) 5976 { 5977 ddi_iblock_cookie_t iblk; 5978 int fma_dma_flag; 5979 5980 /* Only register with IO Fault Services if we have some capability */ 5981 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5982 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5983 } else { 5984 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5985 } 5986 5987 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5988 fma_dma_flag = 1; 5989 } else { 5990 fma_dma_flag = 0; 5991 } 5992 5993 (void) e1000g_set_fma_flags(fma_dma_flag); 5994 5995 if (Adapter->fm_capabilities) { 5996 5997 /* Register capabilities with IO Fault Services */ 5998 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5999 6000 /* 6001 * Initialize pci ereport capabilities if ereport capable 6002 */ 6003 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6004 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6005 pci_ereport_setup(Adapter->dip); 6006 6007 /* 6008 * Register error callback if error callback capable 6009 */ 6010 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6011 ddi_fm_handler_register(Adapter->dip, 6012 e1000g_fm_error_cb, (void*) Adapter); 6013 } 6014 } 6015 6016 static void 6017 e1000g_fm_fini(struct e1000g *Adapter) 6018 { 6019 /* Only unregister FMA capabilities if we registered some */ 6020 if (Adapter->fm_capabilities) { 6021 6022 /* 6023 * Release any resources allocated by pci_ereport_setup() 6024 */ 6025 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6026 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6027 pci_ereport_teardown(Adapter->dip); 6028 6029 /* 6030 * Un-register error callback if error callback capable 6031 */ 6032 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6033 ddi_fm_handler_unregister(Adapter->dip); 6034 6035 /* Unregister from IO Fault Services */ 6036 mutex_enter(&e1000g_rx_detach_lock); 6037 ddi_fm_fini(Adapter->dip); 6038 if (Adapter->priv_dip != NULL) { 6039 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6040 } 6041 mutex_exit(&e1000g_rx_detach_lock); 6042 } 6043 } 6044 6045 void 6046 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6047 { 6048 uint64_t ena; 6049 char buf[FM_MAX_CLASS]; 6050 6051 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6052 ena = fm_ena_generate(0, FM_ENA_FMT1); 6053 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6054 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6055 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6056 } 6057 } 6058 6059 /* 6060 * quiesce(9E) entry point. 6061 * 6062 * This function is called when the system is single-threaded at high 6063 * PIL with preemption disabled. Therefore, this function must not be 6064 * blocked. 6065 * 6066 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6067 * DDI_FAILURE indicates an error condition and should almost never happen. 6068 */ 6069 static int 6070 e1000g_quiesce(dev_info_t *devinfo) 6071 { 6072 struct e1000g *Adapter; 6073 6074 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6075 6076 if (Adapter == NULL) 6077 return (DDI_FAILURE); 6078 6079 e1000g_clear_all_interrupts(Adapter); 6080 6081 (void) e1000_reset_hw(&Adapter->shared); 6082 6083 /* Setup our HW Tx Head & Tail descriptor pointers */ 6084 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6085 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6086 6087 /* Setup our HW Rx Head & Tail descriptor pointers */ 6088 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6089 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6090 6091 return (DDI_SUCCESS); 6092 } 6093 6094 static int 6095 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 6096 uint_t pr_valsize, void *pr_val) 6097 { 6098 link_flowctrl_t fl; 6099 struct e1000_hw *hw = &Adapter->shared; 6100 int err = 0; 6101 6102 ASSERT(pr_valsize > 0); 6103 switch (pr_num) { 6104 case MAC_PROP_AUTONEG: 6105 if (hw->phy.media_type != e1000_media_type_copper) 6106 *(uint8_t *)pr_val = 0; 6107 else 6108 *(uint8_t *)pr_val = 6109 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) 6110 ? 1 : 0); 6111 break; 6112 case MAC_PROP_FLOWCTRL: 6113 if (pr_valsize < sizeof (link_flowctrl_t)) 6114 return (EINVAL); 6115 fl = LINK_FLOWCTRL_BI; 6116 bcopy(&fl, pr_val, sizeof (fl)); 6117 break; 6118 case MAC_PROP_ADV_1000FDX_CAP: 6119 case MAC_PROP_EN_1000FDX_CAP: 6120 if (hw->phy.media_type != e1000_media_type_copper) 6121 *(uint8_t *)pr_val = 1; 6122 else 6123 *(uint8_t *)pr_val = 6124 ((Adapter->phy_ext_status & 6125 IEEE_ESR_1000T_FD_CAPS) || 6126 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) 6127 ? 1 : 0; 6128 break; 6129 case MAC_PROP_ADV_1000HDX_CAP: 6130 case MAC_PROP_EN_1000HDX_CAP: 6131 *(uint8_t *)pr_val = 0; 6132 break; 6133 case MAC_PROP_ADV_100FDX_CAP: 6134 case MAC_PROP_EN_100FDX_CAP: 6135 if (hw->phy.media_type != e1000_media_type_copper) 6136 *(uint8_t *)pr_val = 0; 6137 else 6138 *(uint8_t *)pr_val = 6139 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6140 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 6141 ? 1 : 0; 6142 break; 6143 case MAC_PROP_ADV_100HDX_CAP: 6144 case MAC_PROP_EN_100HDX_CAP: 6145 if (hw->phy.media_type != e1000_media_type_copper) 6146 *(uint8_t *)pr_val = 0; 6147 else 6148 *(uint8_t *)pr_val = 6149 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6150 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 6151 ? 1 : 0; 6152 break; 6153 case MAC_PROP_ADV_10FDX_CAP: 6154 case MAC_PROP_EN_10FDX_CAP: 6155 if (hw->phy.media_type != e1000_media_type_copper) 6156 *(uint8_t *)pr_val = 0; 6157 else 6158 *(uint8_t *)pr_val = 6159 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6160 break; 6161 case MAC_PROP_ADV_10HDX_CAP: 6162 case MAC_PROP_EN_10HDX_CAP: 6163 if (hw->phy.media_type != e1000_media_type_copper) 6164 *(uint8_t *)pr_val = 0; 6165 else 6166 *(uint8_t *)pr_val = 6167 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6168 break; 6169 default: 6170 err = ENOTSUP; 6171 break; 6172 } 6173 return (err); 6174 } 6175 6176 /* 6177 * synchronize the adv* and en* parameters. 6178 * 6179 * See comments in <sys/dld.h> for details of the *_en_* 6180 * parameters. The usage of ndd for setting adv parameters will 6181 * synchronize all the en parameters with the e1000g parameters, 6182 * implicitly disabling any settings made via dladm. 6183 */ 6184 static void 6185 e1000g_param_sync(struct e1000g *Adapter) 6186 { 6187 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6188 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6189 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6190 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6191 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6192 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6193 } 6194 6195 /* 6196 * e1000g_get_driver_control - tell manageability firmware that the driver 6197 * has control. 6198 */ 6199 static void 6200 e1000g_get_driver_control(struct e1000_hw *hw) 6201 { 6202 uint32_t ctrl_ext; 6203 uint32_t swsm; 6204 6205 /* tell manageability firmware the driver has taken over */ 6206 switch (hw->mac.type) { 6207 case e1000_82573: 6208 swsm = E1000_READ_REG(hw, E1000_SWSM); 6209 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6210 break; 6211 case e1000_82571: 6212 case e1000_82572: 6213 case e1000_82574: 6214 case e1000_80003es2lan: 6215 case e1000_ich8lan: 6216 case e1000_ich9lan: 6217 case e1000_ich10lan: 6218 case e1000_pchlan: 6219 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6220 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6221 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6222 break; 6223 default: 6224 /* no manageability firmware: do nothing */ 6225 break; 6226 } 6227 } 6228 6229 /* 6230 * e1000g_release_driver_control - tell manageability firmware that the driver 6231 * has released control. 6232 */ 6233 static void 6234 e1000g_release_driver_control(struct e1000_hw *hw) 6235 { 6236 uint32_t ctrl_ext; 6237 uint32_t swsm; 6238 6239 /* tell manageability firmware the driver has released control */ 6240 switch (hw->mac.type) { 6241 case e1000_82573: 6242 swsm = E1000_READ_REG(hw, E1000_SWSM); 6243 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6244 break; 6245 case e1000_82571: 6246 case e1000_82572: 6247 case e1000_82574: 6248 case e1000_80003es2lan: 6249 case e1000_ich8lan: 6250 case e1000_ich9lan: 6251 case e1000_ich10lan: 6252 case e1000_pchlan: 6253 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6254 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6255 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6256 break; 6257 default: 6258 /* no manageability firmware: do nothing */ 6259 break; 6260 } 6261 } 6262 6263 /* 6264 * Restore e1000g promiscuous mode. 6265 */ 6266 static void 6267 e1000g_restore_promisc(struct e1000g *Adapter) 6268 { 6269 if (Adapter->e1000g_promisc) { 6270 uint32_t rctl; 6271 6272 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6273 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6274 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6275 } 6276 } 6277