xref: /titanic_52/usr/src/uts/common/io/bge/bge_chip2.c (revision 263f549e5da8b32c4922f586afb365b8ae388a6c)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2010-2013, by Broadcom, Inc.
24  * All Rights Reserved.
25  */
26 
27 /*
28  * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
29  * All rights reserved.
30  * Copyright 2016 Nexenta Systems, Inc.  All rights reserved.
31  */
32 
33 #include "bge_impl.h"
34 
35 #define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
36 #define	APE_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->ape_regs+(offset)))
37 
38 /*
39  * Future features ... ?
40  */
41 #define	BGE_CFG_IO8	1	/* 8/16-bit cfg space BIS/BIC	*/
42 #define	BGE_IND_IO32	1	/* indirect access code		*/
43 #define	BGE_SEE_IO32	1	/* SEEPROM access code		*/
44 #define	BGE_FLASH_IO32	1	/* FLASH access code		*/
45 
46 /*
47  * BGE MSI tunable:
48  *
49  * By default MSI is enabled on all supported platforms but it is disabled
50  * for some Broadcom chips due to known MSI hardware issues. Currently MSI
51  * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
52  */
53 boolean_t bge_enable_msi = B_TRUE;
54 
55 /*
56  * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
57  */
58 boolean_t bge_relaxed_ordering = B_TRUE;
59 
60 /*
61  * Patchable globals:
62  *
63  *	bge_autorecover
64  *		Enables/disables automatic recovery after fault detection
65  *
66  *	bge_mlcr_default
67  *		Value to program into the MLCR; controls the chip's GPIO pins
68  *
69  *	bge_dma_{rd,wr}prio
70  *		Relative priorities of DMA reads & DMA writes respectively.
71  *		These may each be patched to any value 0-3.  Equal values
72  *		will give "fair" (round-robin) arbitration for PCI access.
73  *		Unequal values will give one or the other function priority.
74  *
75  *	bge_dma_rwctrl
76  *		Value to put in the Read/Write DMA control register.  See
77  *	        the Broadcom PRM for things you can fiddle with in this
78  *		register ...
79  *
80  *	bge_{tx,rx}_{count,ticks}_{norm,intr}
81  *		Send/receive interrupt coalescing parameters.  Counts are
82  *		#s of descriptors, ticks are in microseconds.  *norm* values
83  *		apply between status updates/interrupts; the *intr* values
84  *		refer to the 'during-interrupt' versions - see the PRM.
85  *
86  *		NOTE: these values have been determined by measurement. They
87  *		differ significantly from the values recommended in the PRM.
88  */
89 static uint32_t bge_autorecover = 1;
90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
91 
92 static uint32_t bge_dma_rdprio = 1;
93 static uint32_t bge_dma_wrprio = 0;
94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
98 
99 uint32_t bge_rx_ticks_norm = 128;
100 uint32_t bge_tx_ticks_norm = 512;
101 uint32_t bge_rx_count_norm = 8;
102 uint32_t bge_tx_count_norm = 128;
103 
104 static uint32_t bge_rx_ticks_intr = 128;
105 static uint32_t bge_tx_ticks_intr = 0;		/* 8 for FJ2+ !?!?	*/
106 static uint32_t bge_rx_count_intr = 2;
107 static uint32_t bge_tx_count_intr = 0;
108 
109 /*
110  * Memory pool configuration parameters.
111  *
112  * These are generally specific to each member of the chip family, since
113  * each one may have a different memory size/configuration.
114  *
115  * Setting the mbuf pool length for a specific type of chip to 0 inhibits
116  * the driver from programming the various registers; instead they are left
117  * at their hardware defaults.  This is the preferred option for later chips
118  * (5705+), whereas the older chips *required* these registers to be set,
119  * since the h/w default was 0 ;-(
120  */
121 static uint32_t bge_mbuf_pool_base	= MBUF_POOL_BASE_DEFAULT;
122 static uint32_t bge_mbuf_pool_base_5704	= MBUF_POOL_BASE_5704;
123 static uint32_t bge_mbuf_pool_base_5705	= MBUF_POOL_BASE_5705;
124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
125 static uint32_t bge_mbuf_pool_len	= MBUF_POOL_LENGTH_DEFAULT;
126 static uint32_t bge_mbuf_pool_len_5704	= MBUF_POOL_LENGTH_5704;
127 static uint32_t bge_mbuf_pool_len_5705	= 0;	/* use h/w default	*/
128 static uint32_t bge_mbuf_pool_len_5721	= 0;
129 
130 /*
131  * Various high and low water marks, thresholds, etc ...
132  *
133  * Note: these are taken from revision 7 of the PRM, and some are different
134  * from both the values in earlier PRMs *and* those determined experimentally
135  * and used in earlier versions of this driver ...
136  */
137 static uint32_t bge_mbuf_hi_water	= MBUF_HIWAT_DEFAULT;
138 static uint32_t bge_mbuf_lo_water_rmac	= MAC_RX_MBUF_LOWAT_DEFAULT;
139 static uint32_t bge_mbuf_lo_water_rdma	= RDMA_MBUF_LOWAT_DEFAULT;
140 
141 static uint32_t bge_dmad_lo_water	= DMAD_POOL_LOWAT_DEFAULT;
142 static uint32_t bge_dmad_hi_water	= DMAD_POOL_HIWAT_DEFAULT;
143 static uint32_t bge_lowat_recv_frames	= LOWAT_MAX_RECV_FRAMES_DEFAULT;
144 
145 static uint32_t bge_replenish_std	= STD_RCV_BD_REPLENISH_DEFAULT;
146 static uint32_t bge_replenish_mini	= MINI_RCV_BD_REPLENISH_DEFAULT;
147 static uint32_t bge_replenish_jumbo	= JUMBO_RCV_BD_REPLENISH_DEFAULT;
148 
149 static uint32_t	bge_watchdog_count	= 1 << 16;
150 static uint16_t bge_dma_miss_limit	= 20;
151 
152 static uint32_t bge_stop_start_on_sync	= 0;
153 
154 /*
155  * bge_intr_max_loop controls the maximum loop number within bge_intr.
156  * When loading NIC with heavy network traffic, it is useful.
157  * Increasing this value could have positive effect to throughput,
158  * but it might also increase ticks of a bge ISR stick on CPU, which might
159  * lead to bad UI interactive experience. So tune this with caution.
160  */
161 static int bge_intr_max_loop = 1;
162 
163 /*
164  * ========== Low-level chip & ring buffer manipulation ==========
165  */
166 
167 #define	BGE_DBG		BGE_DBG_REGS	/* debug flag for this code	*/
168 
169 
170 /*
171  * Config space read-modify-write routines
172  */
173 
174 #if	BGE_CFG_IO8
175 
176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
177 #pragma	inline(bge_cfg_clr16)
178 
179 static void
180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
181 {
182 	uint16_t regval;
183 
184 	BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
185 	    (void *)bgep, regno, bits));
186 
187 	regval = pci_config_get16(bgep->cfg_handle, regno);
188 
189 	BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
190 	    (void *)bgep, regno, bits, regval, regval & ~bits));
191 
192 	regval &= ~bits;
193 	pci_config_put16(bgep->cfg_handle, regno, regval);
194 }
195 
196 #endif	/* BGE_CFG_IO8 */
197 
198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
199 #pragma	inline(bge_cfg_clr32)
200 
201 static void
202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
203 {
204 	uint32_t regval;
205 
206 	BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
207 	    (void *)bgep, regno, bits));
208 
209 	regval = pci_config_get32(bgep->cfg_handle, regno);
210 
211 	BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
212 	    (void *)bgep, regno, bits, regval, regval & ~bits));
213 
214 	regval &= ~bits;
215 	pci_config_put32(bgep->cfg_handle, regno, regval);
216 }
217 
218 #if	BGE_IND_IO32
219 
220 /*
221  * Indirect access to registers & RISC scratchpads, using config space
222  * accesses only.
223  *
224  * This isn't currently used, but someday we might want to use it for
225  * restoring the Subsystem Device/Vendor registers (which aren't directly
226  * writable in Config Space), or for downloading firmware into the RISCs
227  *
228  * In any case there are endian issues to be resolved before this code is
229  * enabled; the bizarre way that bytes get twisted by this chip AND by
230  * the PCI bridge in SPARC systems mean that we shouldn't enable it until
231  * it's been thoroughly tested for all access sizes on all supported
232  * architectures (SPARC *and* x86!).
233  */
234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
235 #pragma	inline(bge_ind_get32)
236 
237 uint32_t
238 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
239 {
240 	uint32_t val;
241 
242 	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
243 
244 #ifdef __sparc
245 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
246 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
247 		regno = LE_32(regno);
248 	}
249 #endif
250 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
251 	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
252 
253 	BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
254 	    (void *)bgep, regno, val));
255 
256 	val = LE_32(val);
257 
258 	return (val);
259 }
260 
261 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
262 #pragma	inline(bge_ind_put32)
263 
264 void
265 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
266 {
267 	BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
268 	    (void *)bgep, regno, val));
269 
270 	val = LE_32(val);
271 #ifdef __sparc
272 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
273 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
274 		regno = LE_32(regno);
275 	}
276 #endif
277 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
278 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
279 }
280 
281 #endif	/* BGE_IND_IO32 */
282 
283 #if	BGE_DEBUGGING
284 
285 static void bge_pci_check(bge_t *bgep);
286 #pragma	no_inline(bge_pci_check)
287 
288 static void
289 bge_pci_check(bge_t *bgep)
290 {
291 	uint16_t pcistatus;
292 
293 	pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
294 	if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
295 		BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
296 		    (void *)bgep, pcistatus));
297 }
298 
299 #endif	/* BGE_DEBUGGING */
300 
301 /*
302  * Perform first-stage chip (re-)initialisation, using only config-space
303  * accesses:
304  *
305  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
306  *   returning the data in the structure pointed to by <idp>.
307  * + Configure the target-mode endianness (swap) options.
308  * + Disable interrupts and enable Memory Space accesses.
309  * + Enable or disable Bus Mastering according to the <enable_dma> flag.
310  *
311  * This sequence is adapted from Broadcom document 570X-PG102-R,
312  * page 102, steps 1-3, 6-8 and 11-13.  The omitted parts of the sequence
313  * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
314  *
315  * This function MUST be called before any non-config-space accesses
316  * are made; on this first call <enable_dma> is B_FALSE, and it
317  * effectively performs steps 3-1(!) of the initialisation sequence
318  * (the rest are not required but should be harmless).
319  *
320  * It MUST also be called after a chip reset, as this disables
321  * Memory Space cycles!  In this case, <enable_dma> is B_TRUE, and
322  * it is effectively performing steps 6-8.
323  */
324 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
325 #pragma	no_inline(bge_chip_cfg_init)
326 
327 void
328 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
329 {
330 	ddi_acc_handle_t handle;
331 	uint16_t command;
332 	uint32_t mhcr;
333 	uint32_t prodid;
334 	uint32_t pci_state;
335 	uint16_t value16;
336 	int i;
337 
338 	BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
339 	    (void *)bgep, (void *)cidp, enable_dma));
340 
341 	/*
342 	 * Step 3: save PCI cache line size and subsystem vendor ID
343 	 *
344 	 * Read all the config-space registers that characterise the
345 	 * chip, specifically vendor/device/revision/subsystem vendor
346 	 * and subsystem device id.  We expect (but don't check) that
347 	 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
348 	 *
349 	 * Also save all bus-transaction related registers (cache-line
350 	 * size, bus-grant/latency parameters, etc).  Some of these are
351 	 * cleared by reset, so we'll have to restore them later.  This
352 	 * comes from the Broadcom document 570X-PG102-R ...
353 	 *
354 	 * Note: Broadcom document 570X-PG102-R seems to be in error
355 	 * here w.r.t. the offsets of the Subsystem Vendor ID and
356 	 * Subsystem (Device) ID registers, which are the opposite way
357 	 * round according to the PCI standard.  For good measure, we
358 	 * save/restore both anyway.
359 	 */
360 	handle = bgep->cfg_handle;
361 
362 	/*
363 	 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP
364 	 * has been set in PCI_CONF_COMM already, we need to write the
365 	 * byte-swapped value to it. So we just write zero first for simplicity.
366 	 */
367 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
368 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
369 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
370 		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
371 	}
372 
373 	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
374 	cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK);
375 	cidp->asic_rev_prod_id = 0;
376 	if ((cidp->asic_rev & 0xf0000000) == CHIP_ASIC_REV_USE_PROD_ID_REG) {
377 		prodid = CHIP_ASIC_REV_PROD_ID_REG;
378 		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
379 		    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
380 			prodid = CHIP_ASIC_REV_PROD_ID_GEN2_REG;
381 		}
382 		cidp->asic_rev_prod_id = pci_config_get32(handle, prodid);
383 	}
384 
385 	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
386 	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
387 
388 	cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
389 	cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
390 	cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
391 	cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
392 	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
393 	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
394 
395 	/* 5717 C0 is treated just like 5720 A0 */
396 	if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) ==
397 	    DEVICE_ID_5717_C0) {
398 		cidp->device = DEVICE_ID_5720;
399 	}
400 
401 	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
402 	    cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
403 	    cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
404 	    cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
405 	    cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
406 	BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
407 	    cidp->vendor, cidp->device, cidp->revision));
408 	BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
409 	    cidp->subven, cidp->subdev, cidp->asic_rev));
410 	BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
411 	    cidp->clsize, cidp->latency, cidp->command));
412 
413 	/*
414 	 * Step 2 (also step 6): disable and clear interrupts.
415 	 * Steps 11-13: configure PIO endianness options, and enable
416 	 * indirect register access.  We'll also select any other
417 	 * options controlled by the MHCR (e.g. tagged status, mask
418 	 * interrupt mode) at this stage ...
419 	 *
420 	 * Note: internally, the chip is 64-bit and BIG-endian, but
421 	 * since it talks to the host over a (LITTLE-endian) PCI bus,
422 	 * it normally swaps bytes around at the PCI interface.
423 	 * However, the PCI host bridge on SPARC systems normally
424 	 * swaps the byte lanes around too, since SPARCs are also
425 	 * BIG-endian.  So it turns out that on SPARC, the right
426 	 * option is to tell the chip to swap (and the host bridge
427 	 * will swap back again), whereas on x86 we ask the chip
428 	 * NOT to swap, so the natural little-endianness of the
429 	 * PCI bus is assumed.  Then the only thing that doesn't
430 	 * automatically work right is access to an 8-byte register
431 	 * by a little-endian host; but we don't want to set the
432 	 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
433 	 * accesses don't go where expected ;-(  So we live with
434 	 * that, and perform word-swaps in software in the few cases
435 	 * where a chip register is defined as an 8-byte value --
436 	 * see the code below for details ...
437 	 *
438 	 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
439 	 * very clear in the register description in the PRM, but
440 	 * Broadcom document 570X-PG104-R page 248 explains a little
441 	 * more (under "Broadcom Mask Mode").  The bit changes the way
442 	 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
443 	 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
444 	 * way as the 5700 did, which isn't very convenient.  Setting
445 	 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
446 	 * bit do just what its name says -- MASK the PCI #INTA output
447 	 * (i.e. deassert the signal at the pin) leaving all internal
448 	 * state unchanged.  This is much more convenient for our
449 	 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
450 	 *
451 	 * Note: the inconvenient semantics of the interrupt mailbox
452 	 * (nonzero disables and acknowledges/clears the interrupt,
453 	 * zero enables AND CLEARS it) would make race conditions
454 	 * likely in the interrupt handler:
455 	 *
456 	 * (1)	acknowledge & disable interrupts
457 	 * (2)	while (more to do)
458 	 * 		process packets
459 	 * (3)	enable interrupts -- also clears pending
460 	 *
461 	 * If the chip received more packets and internally generated
462 	 * an interrupt between the check at (2) and the mbox write
463 	 * at (3), this interrupt would be lost :-(
464 	 *
465 	 * The best way to avoid this is to use TAGGED STATUS mode,
466 	 * where the chip includes a unique tag in each status block
467 	 * update, and the host, when re-enabling interrupts, passes
468 	 * the last tag it saw back to the chip; then the chip can
469 	 * see whether the host is truly up to date, and regenerate
470 	 * its interrupt if not.
471 	 */
472 	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
473 	       MHCR_ENABLE_PCI_STATE_RW |
474 	       MHCR_ENABLE_TAGGED_STATUS_MODE |
475 	       MHCR_MASK_INTERRUPT_MODE |
476 	       MHCR_CLEAR_INTERRUPT_INTA;
477 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
478 		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
479 
480 #ifdef	_BIG_ENDIAN
481 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
482 #endif	/* _BIG_ENDIAN */
483 	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
484 
485 #ifdef BGE_IPMI_ASF
486 	bgep->asf_wordswapped = B_FALSE;
487 #endif
488 
489 	pci_state = (PCISTATE_EXT_ROM_ENABLE | PCISTATE_EXT_ROM_RETRY);
490 	/* allow reads and writes to the APE register and memory space */
491 	if (bgep->ape_enabled) {
492 		pci_state |= PCISTATE_ALLOW_APE_CTLSPC_WR |
493 		    PCISTATE_ALLOW_APE_SHMEM_WR | PCISTATE_ALLOW_APE_PSPACE_WR;
494 	}
495 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PCISTATE, pci_state);
496 
497 	/*
498 	 * Step 1 (also step 7): Enable PCI Memory Space accesses
499 	 *			 Disable Memory Write/Invalidate
500 	 *			 Enable or disable Bus Mastering
501 	 *
502 	 * Note that all other bits are taken from the original value saved
503 	 * the first time through here, rather than from the current register
504 	 * value, 'cos that will have been cleared by a soft RESET since.
505 	 * In this way we preserve the OBP/nexus-parent's preferred settings
506 	 * of the parity-error and system-error enable bits across multiple
507 	 * chip RESETs.
508 	 */
509 	command = bgep->chipid.command | PCI_COMM_MAE;
510 	command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
511 	if (enable_dma)
512 		command |= PCI_COMM_ME;
513 	/*
514 	 * on BCM5714 revision A0, false parity error gets generated
515 	 * due to a logic bug. Provide a workaround by disabling parity
516 	 * error.
517 	 */
518 	if (((cidp->device == DEVICE_ID_5714C) ||
519 	    (cidp->device == DEVICE_ID_5714S)) &&
520 	    (cidp->revision == REVISION_ID_5714_A0)) {
521 		command &= ~PCI_COMM_PARITY_DETECT;
522 	}
523 	pci_config_put16(handle, PCI_CONF_COMM, command);
524 
525 	/*
526 	 * On some PCI-E device, there were instances when
527 	 * the device was still link training.
528 	 */
529 	if (bgep->chipid.pci_type == BGE_PCI_E) {
530 		i = 0;
531 		value16 = pci_config_get16(handle, PCI_CONF_COMM);
532 		while ((value16 != command) && (i < 100)) {
533 			drv_usecwait(200);
534 			value16 = pci_config_get16(handle, PCI_CONF_COMM);
535 			++i;
536 		}
537 	}
538 
539 	/*
540 	 * Clear any remaining error status bits
541 	 */
542 	pci_config_put16(handle, PCI_CONF_STAT, ~0);
543 
544 	/*
545 	 * Do following if and only if the device is NOT BCM5714C OR
546 	 * BCM5715C
547 	 */
548 	if (!((cidp->device == DEVICE_ID_5714C) ||
549 	    (cidp->device == DEVICE_ID_5715C))) {
550 		/*
551 		 * Make sure these indirect-access registers are sane
552 		 * rather than random after power-up or reset
553 		 */
554 		pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
555 		pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
556 	}
557 	/*
558 	 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
559 	 */
560 	bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
561 
562 	if (cidp->pci_type == BGE_PCI_E) {
563 		if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
564 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
565 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
566 		} else if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
567 		           DEVICE_5725_SERIES_CHIPSETS(bgep)) {
568 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717,
569 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
570 		} else {
571 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
572 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
573 		}
574 	}
575 }
576 
577 #ifdef __amd64
578 /*
579  * Distinguish CPU types
580  *
581  * These use to  distinguish AMD64 or Intel EM64T of CPU running mode.
582  * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
583  * for PCI-Express based network interface card. This is the work-around
584  * for those nics.
585  */
586 static boolean_t bge_get_em64t_type(void);
587 #pragma	inline(bge_get_em64t_type)
588 
589 static boolean_t
590 bge_get_em64t_type(void)
591 {
592 
593 	return (x86_vendor == X86_VENDOR_Intel);
594 }
595 #endif
596 
597 /*
598  * Operating register get/set access routines
599  */
600 
601 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
602 #pragma	inline(bge_reg_get32)
603 
604 uint32_t
605 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
606 {
607 	BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
608 	    (void *)bgep, regno));
609 
610 	return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
611 }
612 
613 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
614 #pragma	inline(bge_reg_put32)
615 
616 void
617 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
618 {
619 	BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
620 	    (void *)bgep, regno, data));
621 
622 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
623 	BGE_PCICHK(bgep);
624 }
625 
626 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
627 #pragma	inline(bge_reg_set32)
628 
629 void
630 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
631 {
632 	uint32_t regval;
633 
634 	BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
635 	    (void *)bgep, regno, bits));
636 
637 	regval = bge_reg_get32(bgep, regno);
638 	regval |= bits;
639 	bge_reg_put32(bgep, regno, regval);
640 }
641 
642 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
643 #pragma	inline(bge_reg_clr32)
644 
645 void
646 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
647 {
648 	uint32_t regval;
649 
650 	BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
651 	    (void *)bgep, regno, bits));
652 
653 	regval = bge_reg_get32(bgep, regno);
654 	regval &= ~bits;
655 	bge_reg_put32(bgep, regno, regval);
656 }
657 
658 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
659 #pragma	inline(bge_reg_get64)
660 
661 static uint64_t
662 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
663 {
664 	uint64_t regval;
665 
666 #ifdef	__amd64
667 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
668 	    bge_get_em64t_type() ||
669 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
670 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
671 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
672 		regval <<= 32;
673 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
674 	} else {
675 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
676 	}
677 #elif defined(__sparc)
678 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
679 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
680 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
681 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
682 		regval <<= 32;
683 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
684 	} else {
685 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
686 	}
687 #else
688 	regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
689 #endif
690 
691 #ifdef	_LITTLE_ENDIAN
692 	regval = (regval >> 32) | (regval << 32);
693 #endif	/* _LITTLE_ENDIAN */
694 
695 	BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
696 	    (void *)bgep, regno, regval));
697 
698 	return (regval);
699 }
700 
701 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
702 #pragma	inline(bge_reg_put64)
703 
704 static void
705 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
706 {
707 	BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
708 	    (void *)bgep, regno, data));
709 
710 #ifdef	_LITTLE_ENDIAN
711 	data = ((data >> 32) | (data << 32));
712 #endif	/* _LITTLE_ENDIAN */
713 
714 #ifdef	__amd64
715 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
716 	    bge_get_em64t_type() ||
717 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
718 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
719 		ddi_put32(bgep->io_handle,
720 		    PIO_ADDR(bgep, regno), (uint32_t)data);
721 		BGE_PCICHK(bgep);
722 		ddi_put32(bgep->io_handle,
723 		    PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
724 
725 	} else {
726 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
727 	}
728 #elif defined(__sparc)
729 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
730 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
731 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
732 		ddi_put32(bgep->io_handle,
733 		    PIO_ADDR(bgep, regno + 4), (uint32_t)data);
734 		BGE_PCICHK(bgep);
735 		ddi_put32(bgep->io_handle,
736 		    PIO_ADDR(bgep, regno), (uint32_t)(data >> 32));
737 	} else {
738 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
739 	}
740 #else
741 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
742 #endif
743 
744 	BGE_PCICHK(bgep);
745 }
746 
747 /*
748  * The DDI doesn't provide get/put functions for 128 bit data
749  * so we put RCBs out as two 64-bit chunks instead.
750  */
751 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
752 #pragma	inline(bge_reg_putrcb)
753 
754 static void
755 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
756 {
757 	uint64_t *p;
758 
759 	BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
760 	    (void *)bgep, addr, rcbp->host_ring_addr,
761 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
762 
763 	ASSERT((addr % sizeof (*rcbp)) == 0);
764 
765 	p = (void *)rcbp;
766 	bge_reg_put64(bgep, addr, *p++);
767 	bge_reg_put64(bgep, addr+8, *p);
768 }
769 
770 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
771 #pragma	inline(bge_mbx_put)
772 
773 void
774 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
775 {
776 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
777 		regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
778 
779 	BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
780 	    (void *)bgep, regno, data));
781 
782 	/*
783 	 * Mailbox registers are nominally 64 bits on the 5701, but
784 	 * the MSW isn't used.  On the 5703, they're only 32 bits
785 	 * anyway.  So here we just write the lower(!) 32 bits -
786 	 * remembering that the chip is big-endian, even though the
787 	 * PCI bus is little-endian ...
788 	 */
789 #ifdef	_BIG_ENDIAN
790 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
791 #else
792 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
793 #endif	/* _BIG_ENDIAN */
794 	BGE_PCICHK(bgep);
795 }
796 
797 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
798 #pragma inline(bge_mbx_get)
799 
800 uint32_t
801 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
802 {
803 	uint32_t val32;
804 
805 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
806 		regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
807 
808 	BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
809 	    (void *)bgep, regno));
810 
811 #ifdef	_BIG_ENDIAN
812 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
813 #else
814 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
815 #endif	/* _BIG_ENDIAN */
816 	BGE_PCICHK(bgep);
817 
818 	BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x",
819 	    (void *)bgep, regno, val32));
820 
821 	return (val32);
822 }
823 
824 
825 #if	BGE_DEBUGGING
826 
827 void bge_led_mark(bge_t *bgep);
828 #pragma	no_inline(bge_led_mark)
829 
830 void
831 bge_led_mark(bge_t *bgep)
832 {
833 	uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
834 	    LED_CONTROL_1000MBPS_LED |
835 	    LED_CONTROL_100MBPS_LED |
836 	    LED_CONTROL_10MBPS_LED;
837 
838 	/*
839 	 * Blink all three LINK LEDs on simultaneously, then all off,
840 	 * then restore to automatic hardware control.  This is used
841 	 * in laboratory testing to trigger a logic analyser or scope.
842 	 */
843 	bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
844 	led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
845 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
846 	led_ctrl = LED_CONTROL_OVERRIDE_LINK;
847 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
848 }
849 
850 #endif	/* BGE_DEBUGGING */
851 
852 /*
853  * NIC on-chip memory access routines
854  *
855  * Only 32K of NIC memory is visible at a time, controlled by the
856  * Memory Window Base Address Register (in PCI config space).  Once
857  * this is set, the 32K region of NIC-local memory that it refers
858  * to can be directly addressed in the upper 32K of the 64K of PCI
859  * memory space used for the device.
860  */
861 
862 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
863 #pragma	inline(bge_nic_setwin)
864 
865 static void
866 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
867 {
868 	chip_id_t *cidp;
869 
870 	BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
871 	    (void *)bgep, base));
872 
873 	ASSERT((base & MWBAR_GRANULE_MASK) == 0);
874 
875 	/*
876 	 * Don't do repeated zero data writes,
877 	 * if the device is BCM5714C/15C.
878 	 */
879 	cidp = &bgep->chipid;
880 	if ((cidp->device == DEVICE_ID_5714C) ||
881 	    (cidp->device == DEVICE_ID_5715C)) {
882 		if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
883 			return;
884 		/* Adjust lastWriteZeroData */
885 		bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
886 		    B_TRUE : B_FALSE);
887 	}
888 #ifdef __sparc
889 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
890 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
891 		base = LE_32(base);
892 	}
893 #endif
894 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
895 }
896 
897 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
898 #pragma	inline(bge_nic_get32)
899 
900 static uint32_t
901 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
902 {
903 	uint32_t data;
904 
905 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
906 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
907 		/* workaround for word swap error */
908 		if (addr & 4)
909 			addr = addr - 4;
910 		else
911 			addr = addr + 4;
912 	}
913 #endif
914 
915 #ifdef __sparc
916 	data = bge_nic_read32(bgep, addr);
917 #else
918 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
919 	addr &= MWBAR_GRANULE_MASK;
920 	addr += NIC_MEM_WINDOW_OFFSET;
921 
922 	data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
923 #endif
924 
925 	BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
926 	    (void *)bgep, addr, data));
927 
928 	return (data);
929 }
930 
931 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
932 #pragma inline(bge_nic_put32)
933 
934 void
935 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
936 {
937 	BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
938 	    (void *)bgep, addr, data));
939 
940 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
941 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
942 		/* workaround for word swap error */
943 		if (addr & 4)
944 			addr = addr - 4;
945 		else
946 			addr = addr + 4;
947 	}
948 #endif
949 
950 #ifdef __sparc
951 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
952 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
953 		addr = LE_32(addr);
954 	}
955 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
956 	data = LE_32(data);
957 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
958 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
959 #else
960 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
961 	addr &= MWBAR_GRANULE_MASK;
962 	addr += NIC_MEM_WINDOW_OFFSET;
963 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
964 	BGE_PCICHK(bgep);
965 #endif
966 }
967 
968 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
969 #pragma	inline(bge_nic_get64)
970 
971 static uint64_t
972 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
973 {
974 	uint64_t data;
975 
976 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
977 	addr &= MWBAR_GRANULE_MASK;
978 	addr += NIC_MEM_WINDOW_OFFSET;
979 
980 #ifdef	__amd64
981 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
982 	    bge_get_em64t_type() ||
983 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
984 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
985 		data = ddi_get32(bgep->io_handle,
986 		    PIO_ADDR(bgep, addr + 4));
987 		data <<= 32;
988 		data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
989 	} else {
990 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
991 	}
992 #elif defined(__sparc)
993 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
994 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
995 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
996 		data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
997 		data <<= 32;
998 		data |= ddi_get32(bgep->io_handle,
999 		    PIO_ADDR(bgep, addr + 4));
1000 	} else {
1001 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
1002 	}
1003 #else
1004 	data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
1005 #endif
1006 
1007 	BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
1008 	    (void *)bgep, addr, data));
1009 
1010 	return (data);
1011 }
1012 
1013 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
1014 #pragma	inline(bge_nic_put64)
1015 
1016 static void
1017 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
1018 {
1019 	BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
1020 	    (void *)bgep, addr, data));
1021 
1022 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1023 	addr &= MWBAR_GRANULE_MASK;
1024 	addr += NIC_MEM_WINDOW_OFFSET;
1025 
1026 #ifdef	__amd64
1027 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1028 	    bge_get_em64t_type() ||
1029 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1030 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
1031 		ddi_put32(bgep->io_handle,
1032 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
1033 		BGE_PCICHK(bgep);
1034 		ddi_put32(bgep->io_handle,
1035 		    PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
1036 	} else {
1037 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1038 	}
1039 #elif defined(__sparc)
1040 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1041 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1042 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
1043 		ddi_put32(bgep->io_handle,
1044 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
1045 		BGE_PCICHK(bgep);
1046 		ddi_put32(bgep->io_handle,
1047 		    PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
1048 	} else {
1049 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1050 	}
1051 #else
1052 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1053 #endif
1054 
1055 	BGE_PCICHK(bgep);
1056 }
1057 
1058 /*
1059  * The DDI doesn't provide get/put functions for 128 bit data
1060  * so we put RCBs out as two 64-bit chunks instead.
1061  */
1062 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
1063 #pragma	inline(bge_nic_putrcb)
1064 
1065 static void
1066 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
1067 {
1068 	uint64_t *p;
1069 
1070 	BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
1071 	    (void *)bgep, addr, rcbp->host_ring_addr,
1072 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
1073 
1074 	ASSERT((addr % sizeof (*rcbp)) == 0);
1075 
1076 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1077 	addr &= MWBAR_GRANULE_MASK;
1078 	addr += NIC_MEM_WINDOW_OFFSET;
1079 
1080 	p = (void *)rcbp;
1081 #ifdef	__amd64
1082 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1083 	    bge_get_em64t_type() ||
1084 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1085 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
1086 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1087 		    (uint32_t)(*p));
1088 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1089 		    (uint32_t)(*p++ >> 32));
1090 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1091 		    (uint32_t)(*p));
1092 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1093 		    (uint32_t)(*p >> 32));
1094 
1095 	} else {
1096 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1097 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
1098 	}
1099 #elif defined(__sparc)
1100 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1101 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1102 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
1103 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1104 		    (uint32_t)(*p));
1105 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1106 		    (uint32_t)(*p++ >> 32));
1107 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1108 		    (uint32_t)(*p));
1109 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1110 		    (uint32_t)(*p >> 32));
1111 	} else {
1112 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1113 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1114 	}
1115 #else
1116 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1117 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1118 #endif
1119 
1120 	BGE_PCICHK(bgep);
1121 }
1122 
1123 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
1124 #pragma	inline(bge_nic_zero)
1125 
1126 static void
1127 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
1128 {
1129 	BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
1130 	    (void *)bgep, addr, nbytes));
1131 
1132 	ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
1133 	    ((addr+nbytes) & ~MWBAR_GRANULE_MASK));
1134 
1135 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1136 	addr &= MWBAR_GRANULE_MASK;
1137 	addr += NIC_MEM_WINDOW_OFFSET;
1138 
1139 	(void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
1140 	    nbytes, 1, DDI_DATA_SZ08_ACC);
1141 	BGE_PCICHK(bgep);
1142 }
1143 
1144 /*
1145  * MII (PHY) register get/set access routines
1146  *
1147  * These use the chip's MII auto-access method, controlled by the
1148  * MII Communication register at 0x044c, so the CPU doesn't have
1149  * to fiddle with the individual bits.
1150  */
1151 
1152 #undef	BGE_DBG
1153 #define	BGE_DBG		BGE_DBG_MII	/* debug flag for this code	*/
1154 
1155 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1156 				uint16_t data, uint32_t cmd);
1157 #pragma	no_inline(bge_mii_access)
1158 
1159 static uint16_t
1160 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1161 {
1162 	uint32_t timeout;
1163 	uint32_t regval1;
1164 	uint32_t regval2;
1165 
1166 	BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1167 	    (void *)bgep, regno, data, cmd));
1168 
1169 	ASSERT(mutex_owned(bgep->genlock));
1170 
1171 	/*
1172 	 * Assemble the command ...
1173 	 */
1174 	cmd |= data << MI_COMMS_DATA_SHIFT;
1175 	cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1176 	cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1177 	cmd |= MI_COMMS_START;
1178 
1179 	/*
1180 	 * Wait for any command already in progress ...
1181 	 *
1182 	 * Note: this *shouldn't* ever find that there is a command
1183 	 * in progress, because we already hold the <genlock> mutex.
1184 	 * Nonetheless, we have sometimes seen the MI_COMMS_START
1185 	 * bit set here -- it seems that the chip can initiate MII
1186 	 * accesses internally, even with polling OFF.
1187 	 */
1188 	regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1189 	for (timeout = 100; ; ) {
1190 		if ((regval2 & MI_COMMS_START) == 0) {
1191 			bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1192 			break;
1193 		}
1194 		if (--timeout == 0)
1195 			break;
1196 		drv_usecwait(10);
1197 		regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1198 	}
1199 
1200 	if (timeout == 0)
1201 		return ((uint16_t)~0u);
1202 
1203 	if (timeout != 100)
1204 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1205 		    "MI_COMMS_START set for %d us; 0x%x->0x%x",
1206 		    cmd, 10*(100-timeout), regval1, regval2));
1207 
1208 	regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1209 	for (timeout = 1000; ; ) {
1210 		if ((regval1 & MI_COMMS_START) == 0)
1211 			break;
1212 		if (--timeout == 0)
1213 			break;
1214 		drv_usecwait(10);
1215 		regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1216 	}
1217 
1218 	/*
1219 	 * Drop out early if the READ FAILED bit is set -- this chip
1220 	 * could be a 5703/4S, with a SerDes instead of a PHY!
1221 	 */
1222 	if (regval2 & MI_COMMS_READ_FAILED)
1223 		return ((uint16_t)~0u);
1224 
1225 	if (timeout == 0)
1226 		return ((uint16_t)~0u);
1227 
1228 	/*
1229 	 * The PRM says to wait 5us after seeing the START bit clear
1230 	 * and then re-read the register to get the final value of the
1231 	 * data field, in order to avoid a race condition where the
1232 	 * START bit is clear but the data field isn't yet valid.
1233 	 *
1234 	 * Note: we don't actually seem to be encounter this race;
1235 	 * except when the START bit is seen set again (see below),
1236 	 * the data field doesn't change during this 5us interval.
1237 	 */
1238 	drv_usecwait(5);
1239 	regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1240 
1241 	/*
1242 	 * Unfortunately, when following the PRMs instructions above,
1243 	 * we have occasionally seen the START bit set again(!) in the
1244 	 * value read after the 5us delay. This seems to be due to the
1245 	 * chip autonomously starting another MII access internally.
1246 	 * In such cases, the command/data/etc fields relate to the
1247 	 * internal command, rather than the one that we thought had
1248 	 * just finished.  So in this case, we fall back to returning
1249 	 * the data from the original read that showed START clear.
1250 	 */
1251 	if (regval2 & MI_COMMS_START) {
1252 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1253 		    "MI_COMMS_START set after transaction; 0x%x->0x%x",
1254 		    cmd, regval1, regval2));
1255 		regval2 = regval1;
1256 	}
1257 
1258 	if (regval2 & MI_COMMS_START)
1259 		return ((uint16_t)~0u);
1260 
1261 	if (regval2 & MI_COMMS_READ_FAILED)
1262 		return ((uint16_t)~0u);
1263 
1264 	return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1265 }
1266 
1267 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1268 #pragma	no_inline(bge_mii_get16)
1269 
1270 uint16_t
1271 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1272 {
1273 	BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1274 	    (void *)bgep, regno));
1275 
1276 	ASSERT(mutex_owned(bgep->genlock));
1277 
1278 	if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1279 	    (regno == MII_MSCONTROL)))
1280 		return (0);
1281 
1282 	return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1283 }
1284 
1285 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1286 #pragma	no_inline(bge_mii_put16)
1287 
1288 void
1289 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1290 {
1291 	BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1292 	    (void *)bgep, regno, data));
1293 
1294 	ASSERT(mutex_owned(bgep->genlock));
1295 
1296 	if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1297 	    (regno == MII_MSCONTROL)))
1298 		return;
1299 
1300 	(void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1301 }
1302 
1303 uint16_t
1304 bge_phydsp_read(bge_t *bgep, bge_regno_t regno)
1305 {
1306 	BGE_TRACE(("bge_phydsp_read($%p, 0x%lx)",
1307 	          (void *)bgep, regno));
1308 
1309 	ASSERT(mutex_owned(bgep->genlock));
1310 
1311 	bge_mii_put16(bgep, MII_DSP_ADDRESS, regno);
1312 	return bge_mii_get16(bgep, MII_DSP_RW_PORT);
1313 }
1314 
1315 #pragma	no_inline(bge_phydsp_write)
1316 
1317 void
1318 bge_phydsp_write(bge_t *bgep, bge_regno_t regno, uint16_t data)
1319 {
1320 	BGE_TRACE(("bge_phydsp_write($%p, 0x%lx, 0x%x)",
1321 	          (void *)bgep, regno, data));
1322 
1323 	ASSERT(mutex_owned(bgep->genlock));
1324 
1325 	bge_mii_put16(bgep, MII_DSP_ADDRESS, regno);
1326 	bge_mii_put16(bgep, MII_DSP_RW_PORT, data);
1327 }
1328 
1329 #undef	BGE_DBG
1330 #define	BGE_DBG		BGE_DBG_SEEPROM	/* debug flag for this code	*/
1331 
1332 #if	BGE_SEE_IO32 || BGE_FLASH_IO32
1333 
1334 /*
1335  * Basic SEEPROM get/set access routine
1336  *
1337  * This uses the chip's SEEPROM auto-access method, controlled by the
1338  * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1339  * doesn't have to fiddle with the individual bits.
1340  *
1341  * The caller should hold <genlock> and *also* have already acquired
1342  * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1343  *
1344  * Return value:
1345  *	0 on success,
1346  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1347  *	EPROTO on other h/w or s/w errors.
1348  *
1349  * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1350  * from a (successful) SEEPROM_ACCESS_READ.
1351  */
1352 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1353 				uint32_t *dp);
1354 #pragma	no_inline(bge_seeprom_access)
1355 
1356 static int
1357 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1358 {
1359 	uint32_t tries;
1360 	uint32_t regval;
1361 
1362 	ASSERT(mutex_owned(bgep->genlock));
1363 
1364 	/*
1365 	 * On the newer chips that support both SEEPROM & Flash, we need
1366 	 * to specifically enable SEEPROM access (Flash is the default).
1367 	 * On older chips, we don't; SEEPROM is the only NVtype supported,
1368 	 * and the NVM control registers don't exist ...
1369 	 */
1370 	switch (bgep->chipid.nvtype) {
1371 	case BGE_NVTYPE_NONE:
1372 	case BGE_NVTYPE_UNKNOWN:
1373 		_NOTE(NOTREACHED)
1374 	case BGE_NVTYPE_SEEPROM:
1375 		break;
1376 
1377 	case BGE_NVTYPE_LEGACY_SEEPROM:
1378 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1379 	case BGE_NVTYPE_BUFFERED_FLASH:
1380 	default:
1381 		bge_reg_set32(bgep, NVM_CONFIG1_REG,
1382 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1383 		break;
1384 	}
1385 
1386 	/*
1387 	 * Check there's no command in progress.
1388 	 *
1389 	 * Note: this *shouldn't* ever find that there is a command
1390 	 * in progress, because we already hold the <genlock> mutex.
1391 	 * Also, to ensure we don't have a conflict with the chip's
1392 	 * internal firmware or a process accessing the same (shared)
1393 	 * SEEPROM through the other port of a 5704, we've already
1394 	 * been through the "software arbitration" protocol.
1395 	 * So this is just a final consistency check: we shouldn't
1396 	 * see EITHER the START bit (command started but not complete)
1397 	 * OR the COMPLETE bit (command completed but not cleared).
1398 	 */
1399 	regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1400 	if (regval & SEEPROM_ACCESS_START)
1401 		return (EPROTO);
1402 	if (regval & SEEPROM_ACCESS_COMPLETE)
1403 		return (EPROTO);
1404 
1405 	/*
1406 	 * Assemble the command ...
1407 	 */
1408 	cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1409 	addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1410 	addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1411 	cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1412 	cmd |= SEEPROM_ACCESS_START;
1413 	cmd |= SEEPROM_ACCESS_COMPLETE;
1414 	cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1415 
1416 	bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1417 	bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1418 
1419 	/*
1420 	 * By observation, a successful access takes ~20us on a 5703/4,
1421 	 * but apparently much longer (up to 1000us) on the obsolescent
1422 	 * BCM5700/BCM5701.  We want to be sure we don't get any false
1423 	 * timeouts here; but OTOH, we don't want a bogus access to lock
1424 	 * out interrupts for longer than necessary. So we'll allow up
1425 	 * to 1000us ...
1426 	 */
1427 	for (tries = 0; tries < 1000; ++tries) {
1428 		regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1429 		if (regval & SEEPROM_ACCESS_COMPLETE)
1430 			break;
1431 		drv_usecwait(1);
1432 	}
1433 
1434 	if (regval & SEEPROM_ACCESS_COMPLETE) {
1435 		/*
1436 		 * All OK; read the SEEPROM data register, then write back
1437 		 * the value read from the address register in order to
1438 		 * clear the <complete> bit and leave the SEEPROM access
1439 		 * state machine idle, ready for the next access ...
1440 		 */
1441 		BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1442 		*dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1443 		bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1444 		return (0);
1445 	}
1446 
1447 	/*
1448 	 * Hmm ... what happened here?
1449 	 *
1450 	 * Most likely, the user addressed a non-existent SEEPROM. Or
1451 	 * maybe the SEEPROM was busy internally (e.g. processing a write)
1452 	 * and didn't respond to being addressed. Either way, it's left
1453 	 * the SEEPROM access state machine wedged. So we'll reset it
1454 	 * before we leave, so it's ready for next time ...
1455 	 */
1456 	BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1457 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1458 	return (ENODATA);
1459 }
1460 
1461 /*
1462  * Basic Flash get/set access routine
1463  *
1464  * These use the chip's Flash auto-access method, controlled by the
1465  * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1466  * fiddle with the individual bits.
1467  *
1468  * The caller should hold <genlock> and *also* have already acquired
1469  * the right to access the Flash, via bge_nvmem_acquire() above.
1470  *
1471  * Return value:
1472  *	0 on success,
1473  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1474  *	ENODEV if the NVmem device is missing or otherwise unusable
1475  *
1476  * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1477  * from a (successful) NVM_FLASH_CMD_RD.
1478  */
1479 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1480 				uint32_t *dp);
1481 #pragma	no_inline(bge_flash_access)
1482 
1483 static int
1484 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1485 {
1486 	uint32_t tries;
1487 	uint32_t regval;
1488 
1489 	ASSERT(mutex_owned(bgep->genlock));
1490 
1491 	/*
1492 	 * On the newer chips that support both SEEPROM & Flash, we need
1493 	 * to specifically disable SEEPROM access while accessing Flash.
1494 	 * The older chips don't support Flash, and the NVM registers don't
1495 	 * exist, so we shouldn't be here at all!
1496 	 */
1497 	switch (bgep->chipid.nvtype) {
1498 	case BGE_NVTYPE_NONE:
1499 	case BGE_NVTYPE_UNKNOWN:
1500 		_NOTE(NOTREACHED)
1501 	case BGE_NVTYPE_SEEPROM:
1502 		return (ENODEV);
1503 
1504 	case BGE_NVTYPE_LEGACY_SEEPROM:
1505 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1506 	case BGE_NVTYPE_BUFFERED_FLASH:
1507 	default:
1508 		bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1509 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1510 		break;
1511 	}
1512 
1513 	/*
1514 	 * Assemble the command ...
1515 	 */
1516 	addr &= NVM_FLASH_ADDR_MASK;
1517 	cmd |= NVM_FLASH_CMD_DOIT;
1518 	cmd |= NVM_FLASH_CMD_FIRST;
1519 	cmd |= NVM_FLASH_CMD_LAST;
1520 	cmd |= NVM_FLASH_CMD_DONE;
1521 
1522 	bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1523 	bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1524 	bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1525 
1526 	/*
1527 	 * Allow up to 1000ms ...
1528 	 */
1529 	for (tries = 0; tries < 1000; ++tries) {
1530 		regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1531 		if (regval & NVM_FLASH_CMD_DONE)
1532 			break;
1533 		drv_usecwait(1);
1534 	}
1535 
1536 	if (regval & NVM_FLASH_CMD_DONE) {
1537 		/*
1538 		 * All OK; read the data from the Flash read register
1539 		 */
1540 		BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1541 		*dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1542 		return (0);
1543 	}
1544 
1545 	/*
1546 	 * Hmm ... what happened here?
1547 	 *
1548 	 * Most likely, the user addressed a non-existent Flash. Or
1549 	 * maybe the Flash was busy internally (e.g. processing a write)
1550 	 * and didn't respond to being addressed. Either way, there's
1551 	 * nothing we can here ...
1552 	 */
1553 	BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1554 	return (ENODATA);
1555 }
1556 
1557 /*
1558  * The next two functions regulate access to the NVram (if fitted).
1559  *
1560  * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1561  * (SPI) interface, but they can be accessed through either port. These
1562  * are managed by different instance of this driver and have no software
1563  * state in common.
1564  *
1565  * In addition (and even on a single core chip) the chip's internal
1566  * firmware can access the SEEPROM/Flash, most notably after a RESET
1567  * when it may download code to run internally.
1568  *
1569  * So we need to arbitrate between these various software agents.  For
1570  * this purpose, the chip provides the Software Arbitration Register,
1571  * which implements hardware(!) arbitration.
1572  *
1573  * This functionality didn't exist on older (5700/5701) chips, so there's
1574  * nothing we can do by way of arbitration on those; also, if there's no
1575  * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1576  * nothing to do.
1577  *
1578  * The internal firmware appears to use Request 0, which is the highest
1579  * priority.  So we'd like to use Request 2, leaving one higher and one
1580  * lower for any future developments ... but apparently this doesn't
1581  * always work.  So for now, the code uses Request 1 ;-(
1582  */
1583 
1584 #define	NVM_READ_REQ	NVM_READ_REQ1
1585 #define	NVM_RESET_REQ	NVM_RESET_REQ1
1586 #define	NVM_SET_REQ	NVM_SET_REQ1
1587 
1588 static void bge_nvmem_relinquish(bge_t *bgep);
1589 #pragma	no_inline(bge_nvmem_relinquish)
1590 
1591 static void
1592 bge_nvmem_relinquish(bge_t *bgep)
1593 {
1594 	ASSERT(mutex_owned(bgep->genlock));
1595 
1596 	switch (bgep->chipid.nvtype) {
1597 	case BGE_NVTYPE_NONE:
1598 	case BGE_NVTYPE_UNKNOWN:
1599 		_NOTE(NOTREACHED)
1600 		return;
1601 
1602 	case BGE_NVTYPE_SEEPROM:
1603 		/*
1604 		 * No arbitration performed, no release needed
1605 		 */
1606 		return;
1607 
1608 	case BGE_NVTYPE_LEGACY_SEEPROM:
1609 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1610 	case BGE_NVTYPE_BUFFERED_FLASH:
1611 	default:
1612 		break;
1613 	}
1614 
1615 	/*
1616 	 * Our own request should be present (whether or not granted) ...
1617 	 */
1618 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1619 
1620 	/*
1621 	 * ... this will make it go away.
1622 	 */
1623 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1624 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1625 }
1626 
1627 /*
1628  * Arbitrate for access to the NVmem, if necessary
1629  *
1630  * Return value:
1631  *	0 on success
1632  *	EAGAIN if the device is in use (retryable)
1633  *	ENODEV if the NVmem device is missing or otherwise unusable
1634  */
1635 static int bge_nvmem_acquire(bge_t *bgep);
1636 #pragma	no_inline(bge_nvmem_acquire)
1637 
1638 static int
1639 bge_nvmem_acquire(bge_t *bgep)
1640 {
1641 	uint32_t regval;
1642 	uint32_t tries;
1643 
1644 	ASSERT(mutex_owned(bgep->genlock));
1645 
1646 	switch (bgep->chipid.nvtype) {
1647 	case BGE_NVTYPE_NONE:
1648 	case BGE_NVTYPE_UNKNOWN:
1649 		/*
1650 		 * Access denied: no (recognisable) device fitted
1651 		 */
1652 		return (ENODEV);
1653 
1654 	case BGE_NVTYPE_SEEPROM:
1655 		/*
1656 		 * Access granted: no arbitration needed (or possible)
1657 		 */
1658 		return (0);
1659 
1660 	case BGE_NVTYPE_LEGACY_SEEPROM:
1661 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1662 	case BGE_NVTYPE_BUFFERED_FLASH:
1663 	default:
1664 		/*
1665 		 * Access conditional: conduct arbitration protocol
1666 		 */
1667 		break;
1668 	}
1669 
1670 	/*
1671 	 * We're holding the per-port mutex <genlock>, so no-one other
1672 	 * thread can be attempting to access the NVmem through *this*
1673 	 * port. But it could be in use by the *other* port (of a 5704),
1674 	 * or by the chip's internal firmware, so we have to go through
1675 	 * the full (hardware) arbitration protocol ...
1676 	 *
1677 	 * Note that *because* we're holding <genlock>, the interrupt handler
1678 	 * won't be able to progress.  So we're only willing to spin for a
1679 	 * fairly short time.  Specifically:
1680 	 *
1681 	 *	We *must* wait long enough for the hardware to resolve all
1682 	 *	requests and determine the winner.  Fortunately, this is
1683 	 *	"almost instantaneous", even as observed by GHz CPUs.
1684 	 *
1685 	 *	A successful access by another Solaris thread (via either
1686 	 *	port) typically takes ~20us.  So waiting a bit longer than
1687 	 *	that will give a good chance of success, if the other user
1688 	 *	*is* another thread on the other port.
1689 	 *
1690 	 *	However, the internal firmware can hold on to the NVmem
1691 	 *	for *much* longer: at least 10 milliseconds just after a
1692 	 *	RESET, and maybe even longer if the NVmem actually contains
1693 	 *	code to download and run on the internal CPUs.
1694 	 *
1695 	 * So, we'll allow 50us; if that's not enough then it's up to the
1696 	 * caller to retry later (hence the choice of return code EAGAIN).
1697 	 */
1698 	regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1699 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1700 
1701 	for (tries = 0; tries < 50; ++tries) {
1702 		regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1703 		if (regval & NVM_WON_REQ1)
1704 			break;
1705 		drv_usecwait(1);
1706 	}
1707 
1708 	if (regval & NVM_WON_REQ1) {
1709 		BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1710 		return (0);
1711 	}
1712 
1713 	/*
1714 	 * Somebody else must be accessing the NVmem, so abandon our
1715 	 * attempt take control of it.  The caller can try again later ...
1716 	 */
1717 	BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1718 	bge_nvmem_relinquish(bgep);
1719 	return (EAGAIN);
1720 }
1721 
1722 /*
1723  * This code assumes that the GPIO1 bit has been wired up to the NVmem
1724  * write protect line in such a way that the NVmem is protected when
1725  * GPIO1 is an input, or is an output but driven high.  Thus, to make the
1726  * NVmem writable we have to change GPIO1 to an output AND drive it low.
1727  *
1728  * Note: there's only one set of GPIO pins on a 5704, even though they
1729  * can be accessed through either port.  So the chip has to resolve what
1730  * happens if the two ports program a single pin differently ... the rule
1731  * it uses is that if the ports disagree about the *direction* of a pin,
1732  * "output" wins over "input", but if they disagree about its *value* as
1733  * an output, then the pin is TRISTATED instead!  In such a case, no-one
1734  * wins, and the external signal does whatever the external circuitry
1735  * defines as the default -- which we've assumed is the PROTECTED state.
1736  * So, we always change GPIO1 back to being an *input* whenever we're not
1737  * specifically using it to unprotect the NVmem. This allows either port
1738  * to update the NVmem, although obviously only one at a time!
1739  *
1740  * The caller should hold <genlock> and *also* have already acquired the
1741  * right to access the NVmem, via bge_nvmem_acquire() above.
1742  */
1743 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1744 #pragma	inline(bge_nvmem_protect)
1745 
1746 static void
1747 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1748 {
1749 	uint32_t regval;
1750 
1751 	ASSERT(mutex_owned(bgep->genlock));
1752 
1753 	regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1754 	if (protect) {
1755 		regval |= MLCR_MISC_PINS_OUTPUT_1;
1756 		regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1757 	} else {
1758 		regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1759 		regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1760 	}
1761 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1762 }
1763 
1764 /*
1765  * Now put it all together ...
1766  *
1767  * Try to acquire control of the NVmem; if successful, then:
1768  *	unprotect it (if we want to write to it)
1769  *	perform the requested access
1770  *	reprotect it (after a write)
1771  *	relinquish control
1772  *
1773  * Return value:
1774  *	0 on success,
1775  *	EAGAIN if the device is in use (retryable)
1776  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1777  *	ENODEV if the NVmem device is missing or otherwise unusable
1778  *	EPROTO on other h/w or s/w errors.
1779  */
1780 static int
1781 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1782 {
1783 	int err;
1784 
1785 	if ((err = bge_nvmem_acquire(bgep)) == 0) {
1786 		switch (cmd) {
1787 		case BGE_SEE_READ:
1788 			err = bge_seeprom_access(bgep,
1789 			    SEEPROM_ACCESS_READ, addr, dp);
1790 			break;
1791 
1792 		case BGE_SEE_WRITE:
1793 			bge_nvmem_protect(bgep, B_FALSE);
1794 			err = bge_seeprom_access(bgep,
1795 			    SEEPROM_ACCESS_WRITE, addr, dp);
1796 			bge_nvmem_protect(bgep, B_TRUE);
1797 			break;
1798 
1799 		case BGE_FLASH_READ:
1800 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1801 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1802 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1803 			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1804 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1805 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1806 				    NVM_ACCESS_ENABLE);
1807 			}
1808 			err = bge_flash_access(bgep,
1809 			    NVM_FLASH_CMD_RD, addr, dp);
1810 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1811 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1812 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1813 			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1814 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1815 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1816 				    NVM_ACCESS_ENABLE);
1817 			}
1818 			break;
1819 
1820 		case BGE_FLASH_WRITE:
1821 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1822 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1823 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1824 			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1825 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1826 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1827 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1828 			}
1829 			bge_nvmem_protect(bgep, B_FALSE);
1830 			err = bge_flash_access(bgep,
1831 			    NVM_FLASH_CMD_WR, addr, dp);
1832 			bge_nvmem_protect(bgep, B_TRUE);
1833 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1834 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1835 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1836 			    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1837 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1838 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1839 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1840 			}
1841 
1842 			break;
1843 
1844 		default:
1845 			_NOTE(NOTREACHED)
1846 			break;
1847 		}
1848 		bge_nvmem_relinquish(bgep);
1849 	}
1850 
1851 	BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1852 	return (err);
1853 }
1854 
1855 static uint32_t
1856 bge_nvmem_access_cmd(bge_t *bgep, boolean_t read)
1857 {
1858 	switch (bgep->chipid.nvtype) {
1859 	case BGE_NVTYPE_NONE:
1860 	case BGE_NVTYPE_UNKNOWN:
1861 	default:
1862 		return 0;
1863 
1864 	case BGE_NVTYPE_SEEPROM:
1865 	case BGE_NVTYPE_LEGACY_SEEPROM:
1866 		return (read ? BGE_SEE_READ : BGE_SEE_WRITE);
1867 
1868 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1869 	case BGE_NVTYPE_BUFFERED_FLASH:
1870 		return (read ? BGE_FLASH_READ : BGE_FLASH_WRITE);
1871 	}
1872 }
1873 
1874 
1875 int
1876 bge_nvmem_read32(bge_t *bgep, bge_regno_t addr, uint32_t *dp)
1877 {
1878 	return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_TRUE),
1879 	    addr, dp));
1880 }
1881 
1882 
1883 int
1884 bge_nvmem_write32(bge_t *bgep, bge_regno_t addr, uint32_t *dp)
1885 {
1886 	return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_FALSE),
1887 	    addr, dp));
1888 }
1889 
1890 
1891 /*
1892  * Attempt to get a MAC address from the SEEPROM or Flash, if any
1893  */
1894 static uint64_t bge_get_nvmac(bge_t *bgep);
1895 #pragma no_inline(bge_get_nvmac)
1896 
1897 static uint64_t
1898 bge_get_nvmac(bge_t *bgep)
1899 {
1900 	uint32_t mac_high;
1901 	uint32_t mac_low;
1902 	uint32_t addr;
1903 	uint32_t cmd;
1904 	uint64_t mac;
1905 
1906 	BGE_TRACE(("bge_get_nvmac($%p)",
1907 	    (void *)bgep));
1908 
1909 	switch (bgep->chipid.nvtype) {
1910 	case BGE_NVTYPE_NONE:
1911 	case BGE_NVTYPE_UNKNOWN:
1912 	default:
1913 		return (0ULL);
1914 
1915 	case BGE_NVTYPE_SEEPROM:
1916 	case BGE_NVTYPE_LEGACY_SEEPROM:
1917 		cmd = BGE_SEE_READ;
1918 		break;
1919 
1920 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1921 	case BGE_NVTYPE_BUFFERED_FLASH:
1922 		cmd = BGE_FLASH_READ;
1923 		break;
1924 	}
1925 
1926 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
1927 		addr = NVMEM_DATA_MAC_ADDRESS_5906;
1928 	else
1929 		addr = NVMEM_DATA_MAC_ADDRESS;
1930 
1931 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1932 		return (0ULL);
1933 	addr += 4;
1934 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1935 		return (0ULL);
1936 
1937 	/*
1938 	 * The Broadcom chip is natively BIG-endian, so that's how the
1939 	 * MAC address is represented in NVmem.  We may need to swap it
1940 	 * around on a little-endian host ...
1941 	 */
1942 #ifdef	_BIG_ENDIAN
1943 	mac = mac_high;
1944 	mac = mac << 32;
1945 	mac |= mac_low;
1946 #else
1947 	mac = BGE_BSWAP_32(mac_high);
1948 	mac = mac << 32;
1949 	mac |= BGE_BSWAP_32(mac_low);
1950 #endif	/* _BIG_ENDIAN */
1951 
1952 	return (mac);
1953 }
1954 
1955 #else	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1956 
1957 /*
1958  * Dummy version for when we're not supporting NVmem access
1959  */
1960 static uint64_t bge_get_nvmac(bge_t *bgep);
1961 #pragma inline(bge_get_nvmac)
1962 
1963 static uint64_t
1964 bge_get_nvmac(bge_t *bgep)
1965 {
1966 	_NOTE(ARGUNUSED(bgep))
1967 	return (0ULL);
1968 }
1969 
1970 #endif	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1971 
1972 /*
1973  * Determine the type of NVmem that is (or may be) attached to this chip,
1974  */
1975 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1976 #pragma no_inline(bge_nvmem_id)
1977 
1978 static enum bge_nvmem_type
1979 bge_nvmem_id(bge_t *bgep)
1980 {
1981 	enum bge_nvmem_type nvtype;
1982 	uint32_t config1;
1983 
1984 	BGE_TRACE(("bge_nvmem_id($%p)",
1985 	    (void *)bgep));
1986 
1987 	switch (bgep->chipid.device) {
1988 	default:
1989 		/*
1990 		 * We shouldn't get here; it means we don't recognise
1991 		 * the chip, which means we don't know how to determine
1992 		 * what sort of NVmem (if any) it has.  So we'll say
1993 		 * NONE, to disable the NVmem access code ...
1994 		 */
1995 		nvtype = BGE_NVTYPE_NONE;
1996 		break;
1997 
1998 	case DEVICE_ID_5700:
1999 	case DEVICE_ID_5700x:
2000 	case DEVICE_ID_5701:
2001 		/*
2002 		 * These devices support *only* SEEPROMs
2003 		 */
2004 		nvtype = BGE_NVTYPE_SEEPROM;
2005 		break;
2006 
2007 	case DEVICE_ID_5702:
2008 	case DEVICE_ID_5702fe:
2009 	case DEVICE_ID_5703C:
2010 	case DEVICE_ID_5703S:
2011 	case DEVICE_ID_5704C:
2012 	case DEVICE_ID_5704S:
2013 	case DEVICE_ID_5704:
2014 	case DEVICE_ID_5705M:
2015 	case DEVICE_ID_5705C:
2016 	case DEVICE_ID_5705_2:
2017 	case DEVICE_ID_5717:
2018 	case DEVICE_ID_5718:
2019 	case DEVICE_ID_5719:
2020 	case DEVICE_ID_5720:
2021 	case DEVICE_ID_5724:
2022 	case DEVICE_ID_5725:
2023 	case DEVICE_ID_5727:
2024 	case DEVICE_ID_57780:
2025 	case DEVICE_ID_5780:
2026 	case DEVICE_ID_5782:
2027 	case DEVICE_ID_5785:
2028 	case DEVICE_ID_5787:
2029 	case DEVICE_ID_5787M:
2030 	case DEVICE_ID_5788:
2031 	case DEVICE_ID_5789:
2032 	case DEVICE_ID_5751:
2033 	case DEVICE_ID_5751M:
2034 	case DEVICE_ID_5752:
2035 	case DEVICE_ID_5752M:
2036 	case DEVICE_ID_5754:
2037 	case DEVICE_ID_5755:
2038 	case DEVICE_ID_5755M:
2039 	case DEVICE_ID_5756M:
2040 	case DEVICE_ID_5721:
2041 	case DEVICE_ID_5722:
2042 	case DEVICE_ID_5723:
2043 	case DEVICE_ID_5761:
2044 	case DEVICE_ID_5761E:
2045 	case DEVICE_ID_5764:
2046 	case DEVICE_ID_5714C:
2047 	case DEVICE_ID_5714S:
2048 	case DEVICE_ID_5715C:
2049 	case DEVICE_ID_5715S:
2050 		config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
2051 		if (config1 & NVM_CFG1_FLASH_MODE)
2052 			if (config1 & NVM_CFG1_BUFFERED_MODE)
2053 				nvtype = BGE_NVTYPE_BUFFERED_FLASH;
2054 			else
2055 				nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
2056 		else
2057 			nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
2058 		break;
2059 	case DEVICE_ID_5906:
2060 	case DEVICE_ID_5906M:
2061 		nvtype = BGE_NVTYPE_BUFFERED_FLASH;
2062 		break;
2063 	}
2064 
2065 	return (nvtype);
2066 }
2067 
2068 #undef	BGE_DBG
2069 #define	BGE_DBG		BGE_DBG_APE	/* debug flag for this code	*/
2070 
2071 uint32_t bge_ape_get32(bge_t *bgep, bge_regno_t regno);
2072 #pragma	inline(bge_ape_get32)
2073 
2074 uint32_t
2075 bge_ape_get32(bge_t *bgep, bge_regno_t regno)
2076 {
2077 	BGE_TRACE(("bge_ape_get32($%p, 0x%lx)",
2078 	    (void *)bgep, regno));
2079 
2080 	return (ddi_get32(bgep->ape_handle, APE_ADDR(bgep, regno)));
2081 }
2082 
2083 void bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
2084 #pragma	inline(bge_ape_put32)
2085 
2086 void
2087 bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
2088 {
2089 	BGE_TRACE(("bge_ape_put32($%p, 0x%lx, 0x%x)",
2090 	    (void *)bgep, regno, data));
2091 
2092 	ddi_put32(bgep->ape_handle, APE_ADDR(bgep, regno), data);
2093 	BGE_PCICHK(bgep);
2094 }
2095 
2096 void
2097 bge_ape_lock_init(bge_t *bgep)
2098 {
2099 	int i;
2100 	uint32_t regbase;
2101 	uint32_t bit;
2102 
2103 	BGE_TRACE(("bge_ape_lock_init($%p)", (void *)bgep));
2104 
2105 	if (bgep->chipid.device == DEVICE_ID_5761)
2106 		regbase = BGE_APE_LOCK_GRANT;
2107 	else
2108 		regbase = BGE_APE_PER_LOCK_GRANT;
2109 
2110 	/* Make sure the driver hasn't any stale locks. */
2111 	for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
2112 		switch (i) {
2113 		case BGE_APE_LOCK_PHY0:
2114 		case BGE_APE_LOCK_PHY1:
2115 		case BGE_APE_LOCK_PHY2:
2116 		case BGE_APE_LOCK_PHY3:
2117 			bit = APE_LOCK_GRANT_DRIVER;
2118 			break;
2119 		default:
2120 			if (!bgep->pci_func)
2121 				bit = APE_LOCK_GRANT_DRIVER;
2122 			else
2123 				bit = 1 << bgep->pci_func;
2124 		}
2125 		bge_ape_put32(bgep, regbase + 4 * i, bit);
2126 	}
2127 }
2128 
2129 static int
2130 bge_ape_lock(bge_t *bgep, int locknum)
2131 {
2132 	int i, off;
2133 	int ret = 0;
2134 	uint32_t status;
2135 	uint32_t req;
2136 	uint32_t gnt;
2137 	uint32_t bit;
2138 
2139 	BGE_TRACE(("bge_ape_lock($%p, 0x%x)", (void *)bgep, locknum));
2140 
2141 	if (!bgep->ape_enabled)
2142 		return (0);
2143 
2144 	switch (locknum) {
2145 	case BGE_APE_LOCK_GPIO:
2146 		if (bgep->chipid.device == DEVICE_ID_5761)
2147 			return (0);
2148 	case BGE_APE_LOCK_GRC:
2149 	case BGE_APE_LOCK_MEM:
2150 		if (!bgep->pci_func)
2151 			bit = APE_LOCK_REQ_DRIVER;
2152 		else
2153 			bit = 1 << bgep->pci_func;
2154 		break;
2155 	case BGE_APE_LOCK_PHY0:
2156 	case BGE_APE_LOCK_PHY1:
2157 	case BGE_APE_LOCK_PHY2:
2158 	case BGE_APE_LOCK_PHY3:
2159 		bit = APE_LOCK_REQ_DRIVER;
2160 		break;
2161 	default:
2162 		return (-1);
2163 	}
2164 
2165 	if (bgep->chipid.device == DEVICE_ID_5761) {
2166 		req = BGE_APE_LOCK_REQ;
2167 		gnt = BGE_APE_LOCK_GRANT;
2168 	} else {
2169 		req = BGE_APE_PER_LOCK_REQ;
2170 		gnt = BGE_APE_PER_LOCK_GRANT;
2171 	}
2172 
2173 	off = 4 * locknum;
2174 
2175 	bge_ape_put32(bgep, req + off, bit);
2176 
2177 	/* Wait for up to 1 millisecond to acquire lock. */
2178 	for (i = 0; i < 100; i++) {
2179 		status = bge_ape_get32(bgep, gnt + off);
2180 		if (status == bit)
2181 			break;
2182 		drv_usecwait(10);
2183 	}
2184 
2185 	if (status != bit) {
2186 		/* Revoke the lock request. */
2187 		bge_ape_put32(bgep, gnt + off, bit);
2188 		ret = -1;
2189 	}
2190 
2191 	return (ret);
2192 }
2193 
2194 static void
2195 bge_ape_unlock(bge_t *bgep, int locknum)
2196 {
2197 	uint32_t gnt;
2198 	uint32_t bit;
2199 
2200 	BGE_TRACE(("bge_ape_unlock($%p, 0x%x)", (void *)bgep, locknum));
2201 
2202 	if (!bgep->ape_enabled)
2203 		return;
2204 
2205 	switch (locknum) {
2206 	case BGE_APE_LOCK_GPIO:
2207 		if (bgep->chipid.device == DEVICE_ID_5761)
2208 			return;
2209 	case BGE_APE_LOCK_GRC:
2210 	case BGE_APE_LOCK_MEM:
2211 		if (!bgep->pci_func)
2212 			bit = APE_LOCK_GRANT_DRIVER;
2213 		else
2214 			bit = 1 << bgep->pci_func;
2215 		break;
2216 	case BGE_APE_LOCK_PHY0:
2217 	case BGE_APE_LOCK_PHY1:
2218 	case BGE_APE_LOCK_PHY2:
2219 	case BGE_APE_LOCK_PHY3:
2220 		bit = APE_LOCK_GRANT_DRIVER;
2221 		break;
2222 	default:
2223 		return;
2224 	}
2225 
2226 	if (bgep->chipid.device == DEVICE_ID_5761)
2227 		gnt = BGE_APE_LOCK_GRANT;
2228 	else
2229 		gnt = BGE_APE_PER_LOCK_GRANT;
2230 
2231 	bge_ape_put32(bgep, gnt + 4 * locknum, bit);
2232 }
2233 
2234 /* wait for pending event to finish, if successful returns with MEM locked */
2235 static int
2236 bge_ape_event_lock(bge_t *bgep, uint32_t timeout_us)
2237 {
2238 	uint32_t apedata;
2239 
2240 	BGE_TRACE(("bge_ape_event_lock($%p, %d)", (void *)bgep, timeout_us));
2241 
2242 	ASSERT(timeout_us > 0);
2243 
2244 	while (timeout_us) {
2245 		if (bge_ape_lock(bgep, BGE_APE_LOCK_MEM))
2246 			return (-1);
2247 
2248 		apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS);
2249 		if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
2250 			break;
2251 
2252 		bge_ape_unlock(bgep, BGE_APE_LOCK_MEM);
2253 
2254 		drv_usecwait(10);
2255 		timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
2256 	}
2257 
2258 	return (timeout_us ? 0 : -1);
2259 }
2260 
2261 /* wait for pending event to finish, returns non-zero if not finished */
2262 static int
2263 bge_ape_wait_for_event(bge_t *bgep, uint32_t timeout_us)
2264 {
2265 	uint32_t i;
2266 	uint32_t apedata;
2267 
2268 	BGE_TRACE(("bge_ape_wait_for_event($%p, %d)", (void *)bgep, timeout_us));
2269 
2270 	ASSERT(timeout_us > 0);
2271 
2272 	for (i = 0; i < timeout_us / 10; i++) {
2273 		apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS);
2274 
2275 		if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
2276 			break;
2277 
2278 		drv_usecwait(10);
2279 	}
2280 
2281 	return (i == timeout_us / 10);
2282 }
2283 
2284 int
2285 bge_ape_scratchpad_read(bge_t *bgep, uint32_t *data, uint32_t base_off,
2286     uint32_t lenToRead)
2287 {
2288 	int err;
2289 	uint32_t i;
2290 	uint32_t bufoff;
2291 	uint32_t msgoff;
2292 	uint32_t maxlen;
2293 	uint32_t apedata;
2294 
2295 	BGE_TRACE(("bge_ape_scratchpad_read($%p, %p, 0x%0x, %d)",
2296 	    (void *)bgep, (void*)data, base_off, lenToRead));
2297 
2298 	if (!bgep->ape_has_ncsi)
2299 		return (0);
2300 
2301 	apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG);
2302 	if (apedata != APE_SEG_SIG_MAGIC)
2303 		return (-1);
2304 
2305 	apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS);
2306 	if (!(apedata & APE_FW_STATUS_READY))
2307 		return (-1);
2308 
2309 	bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) +
2310 	          BGE_APE_SHMEM_BASE);
2311 	msgoff = bufoff + 2 * sizeof(uint32_t);
2312 	maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN);
2313 
2314 	while (lenToRead) {
2315 		uint32_t transferLen;
2316 
2317 		/* Cap xfer sizes to scratchpad limits. */
2318 		transferLen = (lenToRead > maxlen) ? maxlen : lenToRead;
2319 		lenToRead -= transferLen;
2320 
2321 		apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS);
2322 		if (!(apedata & APE_FW_STATUS_READY))
2323 			return (-1);
2324 
2325 		/* Wait for up to 1 millisecond for APE to service previous event. */
2326 		err = bge_ape_event_lock(bgep, 1000);
2327 		if (err)
2328 			return (err);
2329 
2330 		apedata = (APE_EVENT_STATUS_DRIVER_EVNT |
2331 		           APE_EVENT_STATUS_SCRTCHPD_READ |
2332 		           APE_EVENT_STATUS_EVENT_PENDING);
2333 		bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata);
2334 
2335 		bge_ape_put32(bgep, bufoff, base_off);
2336 		bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen);
2337 
2338 		bge_ape_unlock(bgep, BGE_APE_LOCK_MEM);
2339 		bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1);
2340 
2341 		base_off += transferLen;
2342 
2343 		if (bge_ape_wait_for_event(bgep, 30000))
2344 			return (-1);
2345 
2346 		for (i = 0; transferLen; i += 4, transferLen -= 4) {
2347 			uint32_t val = bge_ape_get32(bgep, msgoff + i);
2348 			memcpy(data, &val, sizeof(uint32_t));
2349 			data++;
2350 		}
2351 	}
2352 
2353 	return (0);
2354 }
2355 
2356 int
2357 bge_ape_scratchpad_write(bge_t *bgep, uint32_t dstoff, uint32_t *data,
2358     uint32_t lenToWrite)
2359 {
2360 	int err;
2361 	uint32_t i;
2362 	uint32_t bufoff;
2363 	uint32_t msgoff;
2364 	uint32_t maxlen;
2365 	uint32_t apedata;
2366 
2367 	BGE_TRACE(("bge_ape_scratchpad_write($%p, %d, %p, %d)",
2368 	    (void *)bgep, dstoff, data, lenToWrite));
2369 
2370 	if (!bgep->ape_has_ncsi)
2371 		return (0);
2372 
2373 	apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG);
2374 	if (apedata != APE_SEG_SIG_MAGIC)
2375 		return (-1);
2376 
2377 	apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS);
2378 	if (!(apedata & APE_FW_STATUS_READY))
2379 		return (-1);
2380 
2381 	bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) +
2382 	          BGE_APE_SHMEM_BASE);
2383 	msgoff = bufoff + 2 * sizeof(uint32_t);
2384 	maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN);
2385 
2386 	while (lenToWrite) {
2387 		uint32_t transferLen;
2388 
2389 		/* Cap xfer sizes to scratchpad limits. */
2390 		transferLen = (lenToWrite > maxlen) ? maxlen : lenToWrite;
2391 		lenToWrite -= transferLen;
2392 
2393 		/* Wait for up to 1 millisecond for
2394 		 * APE to service previous event.
2395 		 */
2396 		err = bge_ape_event_lock(bgep, 1000);
2397 		if (err)
2398 			return (err);
2399 
2400 		bge_ape_put32(bgep, bufoff, dstoff);
2401 		bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen);
2402 		apedata = msgoff;
2403 
2404 		dstoff += transferLen;
2405 
2406 		for (i = 0; transferLen; i += 4, transferLen -= 4) {
2407 			bge_ape_put32(bgep, apedata, *data++);
2408 			apedata += sizeof(uint32_t);
2409 		}
2410 
2411 		apedata = (APE_EVENT_STATUS_DRIVER_EVNT |
2412 		           APE_EVENT_STATUS_SCRTCHPD_WRITE |
2413 		           APE_EVENT_STATUS_EVENT_PENDING);
2414 		bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata);
2415 
2416 		bge_ape_unlock(bgep, BGE_APE_LOCK_MEM);
2417 		bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1);
2418 	}
2419 
2420 	return (0);
2421 }
2422 
2423 static int
2424 bge_ape_send_event(bge_t *bgep, uint32_t event)
2425 {
2426 	int err;
2427 	uint32_t apedata;
2428 
2429 	BGE_TRACE(("bge_ape_send_event($%p, %d)", (void *)bgep, event));
2430 
2431 	apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG);
2432 	if (apedata != APE_SEG_SIG_MAGIC)
2433 		return (-1);
2434 
2435 	apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS);
2436 	if (!(apedata & APE_FW_STATUS_READY))
2437 		return (-1);
2438 
2439 	/* Wait for up to 1 millisecond for APE to service previous event. */
2440 	err = bge_ape_event_lock(bgep, 1000);
2441 	if (err)
2442 		return (err);
2443 
2444 	bge_ape_put32(bgep, BGE_APE_EVENT_STATUS,
2445 	              event | APE_EVENT_STATUS_EVENT_PENDING);
2446 
2447 	bge_ape_unlock(bgep, BGE_APE_LOCK_MEM);
2448 	bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1);
2449 
2450 	return 0;
2451 }
2452 
2453 static void
2454 bge_ape_driver_state_change(bge_t *bgep, int mode)
2455 {
2456 	uint32_t event;
2457 	uint32_t apedata;
2458 
2459 	BGE_TRACE(("bge_ape_driver_state_change($%p, %d)",
2460 	    (void *)bgep, mode));
2461 
2462 	if (!bgep->ape_enabled)
2463 		return;
2464 
2465 	switch (mode) {
2466 	case BGE_INIT_RESET:
2467 		bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG,
2468 		              APE_HOST_SEG_SIG_MAGIC);
2469 		bge_ape_put32(bgep, BGE_APE_HOST_SEG_LEN,
2470 		              APE_HOST_SEG_LEN_MAGIC);
2471 		apedata = bge_ape_get32(bgep, BGE_APE_HOST_INIT_COUNT);
2472 		bge_ape_put32(bgep, BGE_APE_HOST_INIT_COUNT, ++apedata);
2473 		bge_ape_put32(bgep, BGE_APE_HOST_DRIVER_ID,
2474 		              APE_HOST_DRIVER_ID_MAGIC(1, 0));
2475 		bge_ape_put32(bgep, BGE_APE_HOST_BEHAVIOR,
2476 		              APE_HOST_BEHAV_NO_PHYLOCK);
2477 		bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE,
2478 		              BGE_APE_HOST_DRVR_STATE_START);
2479 
2480 		event = APE_EVENT_STATUS_STATE_START;
2481 		break;
2482 	case BGE_SHUTDOWN_RESET:
2483 		/* With the interface we are currently using,
2484 		 * APE does not track driver state.  Wiping
2485 		 * out the HOST SEGMENT SIGNATURE forces
2486 		 * the APE to assume OS absent status.
2487 		 */
2488 		bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG, 0x0);
2489 
2490 #if 0
2491 		if (WOL supported) {
2492 			bge_ape_put32(bgep, BGE_APE_HOST_WOL_SPEED,
2493 			              BGE_APE_HOST_WOL_SPEED_AUTO);
2494 			apedata = BGE_APE_HOST_DRVR_STATE_WOL;
2495 		} else
2496 #endif
2497 			apedata = BGE_APE_HOST_DRVR_STATE_UNLOAD;
2498 
2499 		bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE, apedata);
2500 
2501 		event = APE_EVENT_STATUS_STATE_UNLOAD;
2502 		break;
2503 	case BGE_SUSPEND_RESET:
2504 		event = APE_EVENT_STATUS_STATE_SUSPEND;
2505 		break;
2506 	default:
2507 		return;
2508 	}
2509 
2510 	event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
2511 
2512 	bge_ape_send_event(bgep, event);
2513 }
2514 
2515 #undef	BGE_DBG
2516 #define	BGE_DBG		BGE_DBG_CHIP	/* debug flag for this code	*/
2517 
2518 static void
2519 bge_init_recv_rule(bge_t *bgep)
2520 {
2521 	bge_recv_rule_t *rulep = bgep->recv_rules;
2522 	uint32_t i;
2523 
2524 	/*
2525 	 * Initialize receive rule registers.
2526 	 * Note that rules may persist across each bge_m_start/stop() call.
2527 	 */
2528 	for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
2529 		bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
2530 		bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
2531 	}
2532 }
2533 
2534 /*
2535  * Using the values captured by bge_chip_cfg_init(), and additional probes
2536  * as required, characterise the chip fully: determine the label by which
2537  * to refer to this chip, the correct settings for various registers, and
2538  * of course whether the device and/or subsystem are supported!
2539  */
2540 int bge_chip_id_init(bge_t *bgep);
2541 #pragma	no_inline(bge_chip_id_init)
2542 
2543 int
2544 bge_chip_id_init(bge_t *bgep)
2545 {
2546 	char buf[MAXPATHLEN];		/* any risk of stack overflow?	*/
2547 	boolean_t dev_ok;
2548 	chip_id_t *cidp;
2549 	uint32_t subid;
2550 	char *devname;
2551 	char *sysname;
2552 	int *ids;
2553 	int err;
2554 	uint_t i;
2555 
2556 	dev_ok = B_FALSE;
2557 	cidp = &bgep->chipid;
2558 
2559 	/*
2560 	 * Check the PCI device ID to determine the generic chip type and
2561 	 * select parameters that depend on this.
2562 	 *
2563 	 * Note: because the SPARC platforms in general don't fit the
2564 	 * SEEPROM 'behind' the chip, the PCI revision ID register reads
2565 	 * as zero - which is why we use <asic_rev> rather than <revision>
2566 	 * below ...
2567 	 *
2568 	 * Note: in general we can't distinguish between the Copper/SerDes
2569 	 * versions by ID alone, as some Copper devices (e.g. some but not
2570 	 * all 5703Cs) have the same ID as the SerDes equivalents.  So we
2571 	 * treat them the same here, and the MII code works out the media
2572 	 * type later on ...
2573 	 */
2574 	cidp->mbuf_base = bge_mbuf_pool_base;
2575 	cidp->mbuf_length = bge_mbuf_pool_len;
2576 	cidp->recv_slots = BGE_RECV_SLOTS_USED;
2577 	cidp->bge_dma_rwctrl = bge_dma_rwctrl;
2578 	cidp->pci_type = BGE_PCI_X;
2579 	cidp->statistic_type = BGE_STAT_BLK;
2580 	cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
2581 	cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
2582 	cidp->mbuf_hi_water = bge_mbuf_hi_water;
2583 	cidp->rx_ticks_norm = bge_rx_ticks_norm;
2584 	cidp->rx_count_norm = bge_rx_count_norm;
2585 	cidp->tx_ticks_norm = bge_tx_ticks_norm;
2586 	cidp->tx_count_norm = bge_tx_count_norm;
2587 	cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT;
2588 
2589 	if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
2590 		cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
2591 	if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
2592 		cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
2593 
2594 	cidp->msi_enabled = B_FALSE;
2595 
2596 	switch (cidp->device) {
2597 	case DEVICE_ID_5717:
2598 	case DEVICE_ID_5718:
2599 	case DEVICE_ID_5719:
2600 	case DEVICE_ID_5720:
2601 	case DEVICE_ID_5724:
2602 	case DEVICE_ID_5725:
2603 	case DEVICE_ID_5727:
2604 		if (cidp->device == DEVICE_ID_5717) {
2605 			cidp->chip_label = 5717;
2606 		} else if (cidp->device == DEVICE_ID_5718) {
2607 			cidp->chip_label = 5718;
2608 		} else if (cidp->device == DEVICE_ID_5719) {
2609 			cidp->chip_label = 5719;
2610 		} else if (cidp->device == DEVICE_ID_5720) {
2611 			if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) ==
2612 			    DEVICE_ID_5717_C0) {
2613 				cidp->chip_label = 5717;
2614 			} else {
2615 				cidp->chip_label = 5720;
2616 			}
2617 		} else if (cidp->device == DEVICE_ID_5724) {
2618 			cidp->chip_label = 5724;
2619 		} else if (cidp->device == DEVICE_ID_5725) {
2620 			cidp->chip_label = 5725;
2621 		} else /* (cidp->device == DEVICE_ID_5727) */ {
2622 			cidp->chip_label = 5727;
2623 		}
2624 		cidp->msi_enabled = bge_enable_msi;
2625 #ifdef __sparc
2626 		cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT);
2627 #endif
2628 		cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717);
2629 		cidp->pci_type = BGE_PCI_E;
2630 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2631 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717;
2632 		cidp->mbuf_hi_water = MBUF_HIWAT_5717;
2633 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2634 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2635 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2636 		cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
2637 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2638 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2639 		cidp->statistic_type = BGE_STAT_REG;
2640 		dev_ok = B_TRUE;
2641 		break;
2642 
2643 	case DEVICE_ID_5700:
2644 	case DEVICE_ID_5700x:
2645 		cidp->chip_label = 5700;
2646 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2647 		break;
2648 
2649 	case DEVICE_ID_5701:
2650 		cidp->chip_label = 5701;
2651 		dev_ok = B_TRUE;
2652 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2653 		break;
2654 
2655 	case DEVICE_ID_5702:
2656 	case DEVICE_ID_5702fe:
2657 		cidp->chip_label = 5702;
2658 		dev_ok = B_TRUE;
2659 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2660 		cidp->pci_type = BGE_PCI;
2661 		break;
2662 
2663 	case DEVICE_ID_5703C:
2664 	case DEVICE_ID_5703S:
2665 	case DEVICE_ID_5703:
2666 		/*
2667 		 * Revision A0 of the 5703/5793 had various errata
2668 		 * that we can't or don't work around, so it's not
2669 		 * supported, but all later versions are
2670 		 */
2671 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
2672 		if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
2673 			dev_ok = B_TRUE;
2674 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2675 		break;
2676 
2677 	case DEVICE_ID_5704C:
2678 	case DEVICE_ID_5704S:
2679 	case DEVICE_ID_5704:
2680 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
2681 		cidp->mbuf_base = bge_mbuf_pool_base_5704;
2682 		cidp->mbuf_length = bge_mbuf_pool_len_5704;
2683 		dev_ok = B_TRUE;
2684 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2685 		break;
2686 
2687 	case DEVICE_ID_5705C:
2688 	case DEVICE_ID_5705M:
2689 	case DEVICE_ID_5705MA3:
2690 	case DEVICE_ID_5705F:
2691 	case DEVICE_ID_5705_2:
2692 	case DEVICE_ID_5754:
2693 		if (cidp->device == DEVICE_ID_5754) {
2694 			cidp->chip_label = 5754;
2695 			cidp->pci_type = BGE_PCI_E;
2696 		} else {
2697 			cidp->chip_label = 5705;
2698 			cidp->pci_type = BGE_PCI;
2699 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2700 		}
2701 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2702 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2703 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2704 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2705 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2706 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2707 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2708 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2709 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2710 		cidp->statistic_type = BGE_STAT_REG;
2711 		dev_ok = B_TRUE;
2712 		break;
2713 
2714 	case DEVICE_ID_5906:
2715 	case DEVICE_ID_5906M:
2716 		cidp->chip_label = 5906;
2717 		cidp->pci_type = BGE_PCI_E;
2718 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906;
2719 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906;
2720 		cidp->mbuf_hi_water = MBUF_HIWAT_5906;
2721 		cidp->mbuf_base = bge_mbuf_pool_base;
2722 		cidp->mbuf_length = bge_mbuf_pool_len;
2723 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2724 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2725 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2726 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2727 		cidp->statistic_type = BGE_STAT_REG;
2728 		dev_ok = B_TRUE;
2729 		break;
2730 
2731 	case DEVICE_ID_5753:
2732 		cidp->chip_label = 5753;
2733 		cidp->pci_type = BGE_PCI_E;
2734 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2735 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2736 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2737 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2738 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2739 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2740 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2741 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2742 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2743 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2744 		cidp->statistic_type = BGE_STAT_REG;
2745 		dev_ok = B_TRUE;
2746 		break;
2747 
2748 	case DEVICE_ID_5755:
2749 	case DEVICE_ID_5755M:
2750 		cidp->chip_label = 5755;
2751 		cidp->pci_type = BGE_PCI_E;
2752 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2753 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2754 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2755 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2756 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2757 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2758 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2759 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2760 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2761 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2762 		if (cidp->device == DEVICE_ID_5755M)
2763 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2764 		cidp->statistic_type = BGE_STAT_REG;
2765 		dev_ok = B_TRUE;
2766 		break;
2767 
2768 	case DEVICE_ID_5756M:
2769 		/*
2770 		 * This is nearly identical to the 5755M.
2771 		 * (Actually reports the 5755 chip ID.)
2772 		 */
2773 		cidp->chip_label = 5756;
2774 		cidp->pci_type = BGE_PCI_E;
2775 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2776 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2777 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2778 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2779 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2780 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2781 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2782 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2783 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2784 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2785 		cidp->statistic_type = BGE_STAT_REG;
2786 		dev_ok = B_TRUE;
2787 		break;
2788 
2789 	case DEVICE_ID_5787:
2790 	case DEVICE_ID_5787M:
2791 		cidp->chip_label = 5787;
2792 		cidp->pci_type = BGE_PCI_E;
2793 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2794 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2795 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2796 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2797 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2798 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2799 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2800 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2801 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2802 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2803 		cidp->statistic_type = BGE_STAT_REG;
2804 		dev_ok = B_TRUE;
2805 		break;
2806 
2807 	case DEVICE_ID_5723:
2808 	case DEVICE_ID_5761:
2809 	case DEVICE_ID_5761E:
2810 	case DEVICE_ID_57780:
2811 		cidp->msi_enabled = bge_enable_msi;
2812 		/*
2813 		 * We don't use MSI for BCM5764 and BCM5785, as the
2814 		 * status block may fail to update when the network
2815 		 * traffic is heavy.
2816 		 */
2817 		/* FALLTHRU */
2818 	case DEVICE_ID_5785:
2819 	case DEVICE_ID_5764:
2820 		if (cidp->device == DEVICE_ID_5723)
2821 			cidp->chip_label = 5723;
2822 		else if (cidp->device == DEVICE_ID_5764)
2823 			cidp->chip_label = 5764;
2824 		else if (cidp->device == DEVICE_ID_5785)
2825 			cidp->chip_label = 5785;
2826 		else if (cidp->device == DEVICE_ID_57780)
2827 			cidp->chip_label = 57780;
2828 		else
2829 			cidp->chip_label = 5761;
2830 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2831 		cidp->pci_type = BGE_PCI_E;
2832 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2833 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2834 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2835 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2836 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2837 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2838 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2839 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2840 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2841 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2842 		cidp->statistic_type = BGE_STAT_REG;
2843 		dev_ok = B_TRUE;
2844 		break;
2845 
2846 	/* PCI-X device, identical to 5714 */
2847 	case DEVICE_ID_5780:
2848 		cidp->chip_label = 5780;
2849 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2850 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2851 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2852 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2853 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2854 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2855 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2856 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2857 		cidp->statistic_type = BGE_STAT_REG;
2858 		dev_ok = B_TRUE;
2859 		break;
2860 
2861 	case DEVICE_ID_5782:
2862 		/*
2863 		 * Apart from the label, we treat this as a 5705(?)
2864 		 */
2865 		cidp->chip_label = 5782;
2866 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2867 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2868 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2869 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2870 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2871 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2872 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2873 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2874 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2875 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2876 		cidp->statistic_type = BGE_STAT_REG;
2877 		dev_ok = B_TRUE;
2878 		break;
2879 
2880 	case DEVICE_ID_5788:
2881 		/*
2882 		 * Apart from the label, we treat this as a 5705(?)
2883 		 */
2884 		cidp->chip_label = 5788;
2885 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2886 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2887 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2888 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2889 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2890 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2891 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2892 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2893 		cidp->statistic_type = BGE_STAT_REG;
2894 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2895 		dev_ok = B_TRUE;
2896 		break;
2897 
2898 	case DEVICE_ID_5714C:
2899 		if (cidp->revision >= REVISION_ID_5714_A2)
2900 			cidp->msi_enabled = bge_enable_msi;
2901 		/* FALLTHRU */
2902 	case DEVICE_ID_5714S:
2903 		cidp->chip_label = 5714;
2904 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2905 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2906 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2907 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2908 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2909 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2910 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2911 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2912 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2913 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2914 		cidp->pci_type = BGE_PCI_E;
2915 		cidp->statistic_type = BGE_STAT_REG;
2916 		dev_ok = B_TRUE;
2917 		break;
2918 
2919 	case DEVICE_ID_5715C:
2920 	case DEVICE_ID_5715S:
2921 		cidp->chip_label = 5715;
2922 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2923 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2924 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2925 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2926 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2927 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2928 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2929 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2930 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2931 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2932 		cidp->pci_type = BGE_PCI_E;
2933 		cidp->statistic_type = BGE_STAT_REG;
2934 		if (cidp->revision >= REVISION_ID_5715_A2)
2935 			cidp->msi_enabled = bge_enable_msi;
2936 		dev_ok = B_TRUE;
2937 		break;
2938 
2939 	case DEVICE_ID_5721:
2940 		cidp->chip_label = 5721;
2941 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2942 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2943 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2944 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2945 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2946 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2947 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2948 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2949 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2950 		cidp->pci_type = BGE_PCI_E;
2951 		cidp->statistic_type = BGE_STAT_REG;
2952 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2953 		dev_ok = B_TRUE;
2954 		break;
2955 
2956 	case DEVICE_ID_5722:
2957 		cidp->chip_label = 5722;
2958 		cidp->pci_type = BGE_PCI_E;
2959 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2960 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2961 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2962 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2963 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2964 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2965 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2966 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2967 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2968 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2969 		cidp->statistic_type = BGE_STAT_REG;
2970 		dev_ok = B_TRUE;
2971 		break;
2972 
2973 	case DEVICE_ID_5751:
2974 	case DEVICE_ID_5751M:
2975 		cidp->chip_label = 5751;
2976 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2977 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2978 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2979 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2980 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2981 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2982 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2983 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2984 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2985 		cidp->pci_type = BGE_PCI_E;
2986 		cidp->statistic_type = BGE_STAT_REG;
2987 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2988 		dev_ok = B_TRUE;
2989 		break;
2990 
2991 	case DEVICE_ID_5752:
2992 	case DEVICE_ID_5752M:
2993 		cidp->chip_label = 5752;
2994 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2995 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2996 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2997 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2998 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2999 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
3000 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
3001 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
3002 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
3003 		cidp->pci_type = BGE_PCI_E;
3004 		cidp->statistic_type = BGE_STAT_REG;
3005 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
3006 		dev_ok = B_TRUE;
3007 		break;
3008 
3009 	case DEVICE_ID_5789:
3010 		cidp->chip_label = 5789;
3011 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
3012 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
3013 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
3014 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
3015 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
3016 		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
3017 		cidp->pci_type = BGE_PCI_E;
3018 		cidp->statistic_type = BGE_STAT_REG;
3019 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
3020 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
3021 		cidp->msi_enabled = B_TRUE;
3022 		dev_ok = B_TRUE;
3023 		break;
3024 
3025 	}
3026 
3027 	/*
3028 	 * Setup the default jumbo parameter.
3029 	 */
3030 	cidp->ethmax_size = ETHERMAX;
3031 	cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
3032 	cidp->std_buf_size = BGE_STD_BUFF_SIZE;
3033 
3034 	/*
3035 	 * If jumbo is enabled and this kind of chipset supports jumbo feature,
3036 	 * setup below jumbo specific parameters.
3037 	 *
3038 	 * For BCM5714/5715, there is only one standard receive ring. So the
3039 	 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
3040 	 * feature is enabled.
3041 	 *
3042 	 * For the BCM5718 family we hijack the standard receive ring for
3043 	 * the jumboframe traffic, keeps it simple.
3044 	 */
3045 	if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
3046 	    (cidp->default_mtu > BGE_DEFAULT_MTU)) {
3047 		if (DEVICE_5714_SERIES_CHIPSETS(bgep) ||
3048 		    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
3049 		    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
3050 			cidp->mbuf_lo_water_rdma =
3051 			    RDMA_MBUF_LOWAT_5714_JUMBO;
3052 			cidp->mbuf_lo_water_rmac =
3053 			    MAC_RX_MBUF_LOWAT_5714_JUMBO;
3054 			cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
3055 			cidp->jumbo_slots = 0;
3056 			cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
3057 		} else {
3058 			cidp->mbuf_lo_water_rdma =
3059 			    RDMA_MBUF_LOWAT_JUMBO;
3060 			cidp->mbuf_lo_water_rmac =
3061 			    MAC_RX_MBUF_LOWAT_JUMBO;
3062 			cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
3063 			cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
3064 		}
3065 		cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
3066 		cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
3067 		cidp->ethmax_size = cidp->default_mtu +
3068 		    sizeof (struct ether_header);
3069 	}
3070 
3071 	/*
3072 	 * Identify the NV memory type: SEEPROM or Flash?
3073 	 */
3074 	cidp->nvtype = bge_nvmem_id(bgep);
3075 
3076 	/*
3077 	 * Now check what we've discovered: is this truly a supported
3078 	 * chip on (the motherboard of) a supported platform?
3079 	 *
3080 	 * Possible problems here:
3081 	 * 1)	it's a completely unheard-of chip
3082 	 * 2)	it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
3083 	 * 3)	it's a chip we would support if it were on the motherboard
3084 	 *	of a Sun platform, but this one isn't ;-(
3085 	 */
3086 	if (cidp->chip_label == 0)
3087 		bge_problem(bgep,
3088 		    "Device 'pci%04x,%04x' not recognized (%d?)",
3089 		    cidp->vendor, cidp->device, cidp->device);
3090 	else if (!dev_ok)
3091 		bge_problem(bgep,
3092 		    "Device 'pci%04x,%04x' (%d) revision %d not supported",
3093 		    cidp->vendor, cidp->device, cidp->chip_label,
3094 		    cidp->revision);
3095 	else
3096 		cidp->flags |= CHIP_FLAG_SUPPORTED;
3097 
3098 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
3099 		return (EIO);
3100 
3101 	return (0);
3102 }
3103 
3104 void
3105 bge_chip_msi_trig(bge_t *bgep)
3106 {
3107 	uint32_t	regval;
3108 
3109 	regval = bgep->param_msi_cnt<<4;
3110 	bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
3111 	BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
3112 }
3113 
3114 /*
3115  * Various registers that control the chip's internal engines (state
3116  * machines) have a <reset> and <enable> bits (fortunately, in the
3117  * same place in each such register :-).
3118  *
3119  * To reset the state machine, the <reset> bit must be written with 1;
3120  * it will then read back as 1 while the reset is in progress, but
3121  * self-clear to 0 when the reset completes.
3122  *
3123  * To enable a state machine, one must set the <enable> bit, which
3124  * will continue to read back as 0 until the state machine is running.
3125  *
3126  * To disable a state machine, the <enable> bit must be cleared, but
3127  * it will continue to read back as 1 until the state machine actually
3128  * stops.
3129  *
3130  * This routine implements polling for completion of a reset, enable
3131  * or disable operation, returning B_TRUE on success (bit reached the
3132  * required state) or B_FALSE on timeout (200*100us == 20ms).
3133  */
3134 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
3135 					uint32_t mask, uint32_t val);
3136 #pragma	no_inline(bge_chip_poll_engine)
3137 
3138 static boolean_t
3139 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
3140 	uint32_t mask, uint32_t val)
3141 {
3142 	uint32_t regval;
3143 	uint32_t n;
3144 
3145 	BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
3146 	    (void *)bgep, regno, mask, val));
3147 
3148 	for (n = 200; n; --n) {
3149 		regval = bge_reg_get32(bgep, regno);
3150 		if ((regval & mask) == val)
3151 			return (B_TRUE);
3152 		drv_usecwait(100);
3153 	}
3154 
3155 	bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno);
3156 	bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
3157 	return (B_FALSE);
3158 }
3159 
3160 /*
3161  * Various registers that control the chip's internal engines (state
3162  * machines) have a <reset> bit (fortunately, in the same place in
3163  * each such register :-).  To reset the state machine, this bit must
3164  * be written with 1; it will then read back as 1 while the reset is
3165  * in progress, but self-clear to 0 when the reset completes.
3166  *
3167  * This code sets the bit, then polls for it to read back as zero.
3168  * The return value is B_TRUE on success (reset bit cleared itself),
3169  * or B_FALSE if the state machine didn't recover :(
3170  *
3171  * NOTE: the Core reset is similar to other resets, except that we
3172  * can't poll for completion, since the Core reset disables memory
3173  * access!  So we just have to assume that it will all complete in
3174  * 100us.  See Broadcom document 570X-PG102-R, p102, steps 4-5.
3175  */
3176 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
3177 #pragma	no_inline(bge_chip_reset_engine)
3178 
3179 static boolean_t
3180 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
3181 {
3182 	uint32_t regval;
3183 	uint16_t val16;
3184 	uint32_t val32;
3185 	uint32_t mhcr;
3186 
3187 	regval = bge_reg_get32(bgep, regno);
3188 
3189 	BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
3190 	    (void *)bgep, regno));
3191 	BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
3192 	    regno, regval));
3193 
3194 	regval |= STATE_MACHINE_RESET_BIT;
3195 
3196 	switch (regno) {
3197 	case MISC_CONFIG_REG:
3198 		/*
3199 		 * BCM5714/5721/5751 pcie chip special case. In order to avoid
3200 		 * resetting PCIE block and bringing PCIE link down, bit 29
3201 		 * in the register needs to be set first, and then set it again
3202 		 * while the reset bit is written.
3203 		 * See:P500 of 57xx-PG102-RDS.pdf.
3204 		 */
3205 		if (DEVICE_5705_SERIES_CHIPSETS(bgep) ||
3206 		    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
3207 		    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
3208 		    DEVICE_5721_SERIES_CHIPSETS(bgep) ||
3209 		    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
3210 		    DEVICE_5714_SERIES_CHIPSETS(bgep) ||
3211 		    DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3212 			regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
3213 			if (bgep->chipid.pci_type == BGE_PCI_E) {
3214 				if (bgep->chipid.asic_rev ==
3215 				    MHCR_CHIP_REV_5751_A0 ||
3216 				    bgep->chipid.asic_rev ==
3217 				    MHCR_CHIP_REV_5721_A0 ||
3218 				    bgep->chipid.asic_rev ==
3219 				    MHCR_CHIP_REV_5755_A0) {
3220 					val32 = bge_reg_get32(bgep,
3221 					    PHY_TEST_CTRL_REG);
3222 					if (val32 == (PHY_PCIE_SCRAM_MODE |
3223 					    PHY_PCIE_LTASS_MODE))
3224 						bge_reg_put32(bgep,
3225 						    PHY_TEST_CTRL_REG,
3226 						    PHY_PCIE_SCRAM_MODE);
3227 					val32 = pci_config_get32
3228 					    (bgep->cfg_handle,
3229 					    PCI_CONF_BGE_CLKCTL);
3230 					val32 |= CLKCTL_PCIE_A0_FIX;
3231 					pci_config_put32(bgep->cfg_handle,
3232 					    PCI_CONF_BGE_CLKCTL, val32);
3233 				}
3234 				bge_reg_set32(bgep, regno,
3235 				    MISC_CONFIG_GRC_RESET_DISABLE);
3236 				regval |= MISC_CONFIG_GRC_RESET_DISABLE;
3237 			}
3238 		}
3239 
3240 		/*
3241 		 * Special case - causes Core reset
3242 		 *
3243 		 * On SPARC v9 we want to ensure that we don't start
3244 		 * timing until the I/O access has actually reached
3245 		 * the chip, otherwise we might make the next access
3246 		 * too early.  And we can't just force the write out
3247 		 * by following it with a read (even to config space)
3248 		 * because that would cause the fault we're trying
3249 		 * to avoid.  Hence the need for membar_sync() here.
3250 		 */
3251 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
3252 #ifdef	__sparcv9
3253 		membar_sync();
3254 #endif	/* __sparcv9 */
3255 		/*
3256 		 * On some platforms,system need about 300us for
3257 		 * link setup.
3258 		 */
3259 		drv_usecwait(300);
3260 		if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3261 			bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET);
3262 			bge_reg_clr32(
3263 			    bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF);
3264 		}
3265 
3266 		if (bgep->chipid.pci_type == BGE_PCI_E) {
3267 			/* PCI-E device need more reset time */
3268 			drv_usecwait(120000);
3269 
3270 			/*
3271 			 * (re)Disable interrupts as the bit can be reset after a
3272 			 * core clock reset.
3273 			 */
3274 			mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);
3275 			pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3276 			    mhcr | MHCR_MASK_PCI_INT_OUTPUT);
3277 
3278 			/* Set PCIE max payload size and clear error status. */
3279 			if ((bgep->chipid.chip_label == 5721) ||
3280 			    (bgep->chipid.chip_label == 5751) ||
3281 			    (bgep->chipid.chip_label == 5752) ||
3282 			    (bgep->chipid.chip_label == 5789) ||
3283 			    (bgep->chipid.chip_label == 5906)) {
3284 				pci_config_put16(bgep->cfg_handle,
3285 				    PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
3286 				pci_config_put16(bgep->cfg_handle,
3287 				    PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
3288 			}
3289 
3290 			if ((bgep->chipid.chip_label == 5723) ||
3291 			    (bgep->chipid.chip_label == 5761)) {
3292 				pci_config_put16(bgep->cfg_handle,
3293 				    PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX);
3294 				pci_config_put16(bgep->cfg_handle,
3295 				    PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS);
3296 			}
3297 
3298 			if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
3299 			    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
3300 				val16 = pci_config_get16(bgep->cfg_handle,
3301 				                         PCI_CONF_DEV_CTRL_5717);
3302 				val16 &= ~READ_REQ_SIZE_MASK;
3303 				val16 |= READ_REQ_SIZE_2K;
3304 				pci_config_put16(bgep->cfg_handle,
3305 				    PCI_CONF_DEV_CTRL_5717, val16);
3306 			}
3307 		}
3308 
3309 		BGE_PCICHK(bgep);
3310 		return (B_TRUE);
3311 
3312 	default:
3313 		bge_reg_put32(bgep, regno, regval);
3314 		return (bge_chip_poll_engine(bgep, regno,
3315 		    STATE_MACHINE_RESET_BIT, 0));
3316 	}
3317 }
3318 
3319 /*
3320  * Various registers that control the chip's internal engines (state
3321  * machines) have an <enable> bit (fortunately, in the same place in
3322  * each such register :-).  To stop the state machine, this bit must
3323  * be written with 0, then polled to see when the state machine has
3324  * actually stopped.
3325  *
3326  * The return value is B_TRUE on success (enable bit cleared), or
3327  * B_FALSE if the state machine didn't stop :(
3328  */
3329 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
3330 						uint32_t morebits);
3331 #pragma	no_inline(bge_chip_disable_engine)
3332 
3333 static boolean_t
3334 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
3335 {
3336 	uint32_t regval;
3337 
3338 	BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
3339 	    (void *)bgep, regno, morebits));
3340 
3341 	switch (regno) {
3342 	case FTQ_RESET_REG:
3343 		/*
3344 		 * For Schumacher's bugfix CR6490108
3345 		 */
3346 #ifdef BGE_IPMI_ASF
3347 #ifdef BGE_NETCONSOLE
3348 		if (bgep->asf_enabled)
3349 			return (B_TRUE);
3350 #endif
3351 #endif
3352 		/*
3353 		 * Not quite like the others; it doesn't
3354 		 * have an <enable> bit, but instead we
3355 		 * have to set and then clear all the bits
3356 		 */
3357 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
3358 		drv_usecwait(100);
3359 		bge_reg_put32(bgep, regno, 0);
3360 		return (B_TRUE);
3361 
3362 	default:
3363 		if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3364 			break;
3365 		}
3366 
3367 		if ((regno == RCV_LIST_SELECTOR_MODE_REG) ||
3368 		    (regno == DMA_COMPLETION_MODE_REG) ||
3369 		    (regno == MBUF_CLUSTER_FREE_MODE_REG) ||
3370 		    (regno == BUFFER_MANAGER_MODE_REG) ||
3371 		    (regno == MEMORY_ARBITER_MODE_REG)) {
3372 			return B_TRUE;
3373 		}
3374 
3375 		break;
3376 	}
3377 
3378 	regval = bge_reg_get32(bgep, regno);
3379 	regval &= ~STATE_MACHINE_ENABLE_BIT;
3380 	regval &= ~morebits;
3381 	bge_reg_put32(bgep, regno, regval);
3382 
3383 	return bge_chip_poll_engine(bgep, regno, STATE_MACHINE_ENABLE_BIT, 0);
3384 }
3385 
3386 /*
3387  * Various registers that control the chip's internal engines (state
3388  * machines) have an <enable> bit (fortunately, in the same place in
3389  * each such register :-).  To start the state machine, this bit must
3390  * be written with 1, then polled to see when the state machine has
3391  * actually started.
3392  *
3393  * The return value is B_TRUE on success (enable bit set), or
3394  * B_FALSE if the state machine didn't start :(
3395  */
3396 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
3397 					uint32_t morebits);
3398 #pragma	no_inline(bge_chip_enable_engine)
3399 
3400 static boolean_t
3401 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
3402 {
3403 	uint32_t regval;
3404 
3405 	BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
3406 	    (void *)bgep, regno, morebits));
3407 
3408 	switch (regno) {
3409 	case FTQ_RESET_REG:
3410 #ifdef BGE_IPMI_ASF
3411 #ifdef BGE_NETCONSOLE
3412 		if (bgep->asf_enabled)
3413 			return (B_TRUE);
3414 #endif
3415 #endif
3416 		/*
3417 		 * Not quite like the others; it doesn't
3418 		 * have an <enable> bit, but instead we
3419 		 * have to set and then clear all the bits
3420 		 */
3421 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
3422 		drv_usecwait(100);
3423 		bge_reg_put32(bgep, regno, 0);
3424 		return (B_TRUE);
3425 
3426 	default:
3427 		regval = bge_reg_get32(bgep, regno);
3428 		regval |= STATE_MACHINE_ENABLE_BIT;
3429 		regval |= morebits;
3430 		bge_reg_put32(bgep, regno, regval);
3431 		return (bge_chip_poll_engine(bgep, regno,
3432 		    STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
3433 	}
3434 }
3435 
3436 /*
3437  * Reprogram the Ethernet, Transmit, and Receive MAC
3438  * modes to match the param_* variables
3439  */
3440 void bge_sync_mac_modes(bge_t *bgep);
3441 #pragma	no_inline(bge_sync_mac_modes)
3442 
3443 void
3444 bge_sync_mac_modes(bge_t *bgep)
3445 {
3446 	uint32_t macmode;
3447 	uint32_t regval;
3448 
3449 	ASSERT(mutex_owned(bgep->genlock));
3450 
3451 	/*
3452 	 * Reprogram the Ethernet MAC mode ...
3453 	 */
3454 	macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
3455 	macmode &= ~ETHERNET_MODE_LINK_POLARITY;
3456 	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
3457 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
3458 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
3459 		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
3460 		    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
3461 		    DEVICE_5714_SERIES_CHIPSETS(bgep))
3462 			macmode |= ETHERNET_MODE_PORTMODE_GMII;
3463 		else
3464 			macmode |= ETHERNET_MODE_PORTMODE_TBI;
3465 	} else if (bgep->param_link_speed == 10 ||
3466 	    bgep->param_link_speed == 100)
3467 		macmode |= ETHERNET_MODE_PORTMODE_MII;
3468 	else
3469 		macmode |= ETHERNET_MODE_PORTMODE_GMII;
3470 	if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
3471 		macmode |= ETHERNET_MODE_HALF_DUPLEX;
3472 	else
3473 		macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
3474 	if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
3475 		macmode |= ETHERNET_MODE_MAC_LOOPBACK;
3476 	else
3477 		macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
3478 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
3479 	BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
3480 	    (void *)bgep, regval, macmode));
3481 
3482 	/*
3483 	 * ... the Transmit MAC mode ...
3484 	 */
3485 	macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
3486 	if (bgep->param_link_tx_pause)
3487 		macmode |= TRANSMIT_MODE_FLOW_CONTROL;
3488 	else
3489 		macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
3490 	bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
3491 	BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
3492 	    (void *)bgep, regval, macmode));
3493 
3494 	/*
3495 	 * ... and the Receive MAC mode
3496 	 */
3497 	macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
3498 	if (bgep->param_link_rx_pause)
3499 		macmode |= RECEIVE_MODE_FLOW_CONTROL;
3500 	else
3501 		macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
3502 	bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
3503 	BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
3504 	    (void *)bgep, regval, macmode));
3505 
3506 	/*
3507 	 * For BCM5785, we need to configure the link status in the MI Status
3508 	 * register with a write command when auto-polling is disabled.
3509 	 */
3510 	if (bgep->chipid.device == DEVICE_ID_5785)
3511 		if (bgep->param_link_speed == 10)
3512 			bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
3513 			    | MI_STATUS_10MBPS);
3514 		else
3515 			bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
3516 }
3517 
3518 /*
3519  * bge_chip_sync() -- program the chip with the unicast MAC address,
3520  * the multicast hash table, the required level of promiscuity, and
3521  * the current loopback mode ...
3522  */
3523 #ifdef BGE_IPMI_ASF
3524 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
3525 #else
3526 int bge_chip_sync(bge_t *bgep);
3527 #endif
3528 #pragma	no_inline(bge_chip_sync)
3529 
3530 int
3531 #ifdef BGE_IPMI_ASF
3532 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
3533 #else
3534 bge_chip_sync(bge_t *bgep)
3535 #endif
3536 {
3537 	void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
3538 	boolean_t promisc;
3539 	uint64_t macaddr;
3540 	uint32_t fill = 0;
3541 	int i, j;
3542 	int retval = DDI_SUCCESS;
3543 
3544 	BGE_TRACE(("bge_chip_sync($%p)",
3545 	    (void *)bgep));
3546 
3547 	ASSERT(mutex_owned(bgep->genlock));
3548 
3549 	promisc = B_FALSE;
3550 	fill = ~(uint32_t)0;
3551 
3552 	if (bgep->promisc)
3553 		promisc = B_TRUE;
3554 	else
3555 		fill = (uint32_t)0;
3556 
3557 	/*
3558 	 * If the TX/RX MAC engines are already running, we should stop
3559 	 * them (and reset the RX engine) before changing the parameters.
3560 	 * If they're not running, this will have no effect ...
3561 	 *
3562 	 * NOTE: this is currently disabled by default because stopping
3563 	 * and restarting the Tx engine may cause an outgoing packet in
3564 	 * transit to be truncated.  Also, stopping and restarting the
3565 	 * Rx engine seems to not work correctly on the 5705.  Testing
3566 	 * has not (yet!) revealed any problems with NOT stopping and
3567 	 * restarting these engines (and Broadcom say their drivers don't
3568 	 * do this), but if it is found to cause problems, this variable
3569 	 * can be patched to re-enable the old behaviour ...
3570 	 */
3571 	if (bge_stop_start_on_sync) {
3572 #ifdef BGE_IPMI_ASF
3573 		if (!bgep->asf_enabled) {
3574 			if (!bge_chip_disable_engine(bgep,
3575 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3576 				retval = DDI_FAILURE;
3577 		} else {
3578 			if (!bge_chip_disable_engine(bgep,
3579 			    RECEIVE_MAC_MODE_REG, 0))
3580 				retval = DDI_FAILURE;
3581 		}
3582 #else
3583 		if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
3584 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3585 			retval = DDI_FAILURE;
3586 #endif
3587 		if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3588 			retval = DDI_FAILURE;
3589 		if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
3590 			retval = DDI_FAILURE;
3591 	}
3592 
3593 	/*
3594 	 * Reprogram the hashed multicast address table ...
3595 	 */
3596 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3597 		bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
3598 
3599 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3600 		bge_reg_put32(bgep, MAC_HASH_REG(i),
3601 			bgep->mcast_hash[i] | fill);
3602 
3603 #ifdef BGE_IPMI_ASF
3604 	if (!bgep->asf_enabled || !asf_keeplive) {
3605 #endif
3606 		/*
3607 		 * Transform the MAC address(es) from host to chip format, then
3608 		 * reprogram the transmit random backoff seed and the unicast
3609 		 * MAC address(es) ...
3610 		 */
3611 		for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
3612 			for (i = 0, macaddr = 0ull;
3613 			    i < ETHERADDRL; ++i) {
3614 				macaddr <<= 8;
3615 				macaddr |= bgep->curr_addr[j].addr[i];
3616 			}
3617 			fill += (macaddr >> 16) + (macaddr & 0xffffffff);
3618 			bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
3619 
3620 			BGE_DEBUG(("bge_chip_sync($%p) "
3621 			    "setting MAC address %012llx",
3622 			    (void *)bgep, macaddr));
3623 		}
3624 #ifdef BGE_IPMI_ASF
3625 	}
3626 #endif
3627 	/*
3628 	 * Set random seed of backoff interval
3629 	 *   - Writing zero means no backoff interval
3630 	 */
3631 	fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff;
3632 	if (fill == 0)
3633 		fill = 1;
3634 	bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
3635 
3636 	/*
3637 	 * Set or clear the PROMISCUOUS mode bit
3638 	 */
3639 	opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
3640 	(*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
3641 
3642 	/*
3643 	 * Sync the rest of the MAC modes too ...
3644 	 */
3645 	bge_sync_mac_modes(bgep);
3646 
3647 	/*
3648 	 * Restart RX/TX MAC engines if required ...
3649 	 */
3650 	if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
3651 		if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3652 			retval = DDI_FAILURE;
3653 #ifdef BGE_IPMI_ASF
3654 		if (!bgep->asf_enabled) {
3655 			if (!bge_chip_enable_engine(bgep,
3656 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3657 				retval = DDI_FAILURE;
3658 		} else {
3659 			if (!bge_chip_enable_engine(bgep,
3660 			    RECEIVE_MAC_MODE_REG, 0))
3661 				retval = DDI_FAILURE;
3662 		}
3663 #else
3664 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3665 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3666 			retval = DDI_FAILURE;
3667 #endif
3668 	}
3669 	return (retval);
3670 }
3671 
3672 #ifndef __sparc
3673 static bge_regno_t quiesce_regs[] = {
3674 	READ_DMA_MODE_REG,
3675 	DMA_COMPLETION_MODE_REG,
3676 	WRITE_DMA_MODE_REG,
3677 	BGE_REGNO_NONE
3678 };
3679 
3680 void bge_chip_stop_nonblocking(bge_t *bgep);
3681 #pragma no_inline(bge_chip_stop_nonblocking)
3682 
3683 /*
3684  * This function is called by bge_quiesce(). We
3685  * turn off all the DMA engines here.
3686  */
3687 void
3688 bge_chip_stop_nonblocking(bge_t *bgep)
3689 {
3690 	bge_regno_t *rbp;
3691 
3692 	/*
3693 	 * Flag that no more activity may be initiated
3694 	 */
3695 	bgep->progress &= ~PROGRESS_READY;
3696 
3697 	rbp = quiesce_regs;
3698 	while (*rbp != BGE_REGNO_NONE) {
3699 		(void) bge_chip_disable_engine(bgep, *rbp, 0);
3700 		++rbp;
3701 	}
3702 
3703 	bgep->bge_chip_state = BGE_CHIP_STOPPED;
3704 }
3705 
3706 #endif
3707 
3708 /*
3709  * bge_chip_stop() -- stop all chip processing
3710  *
3711  * If the <fault> parameter is B_TRUE, we're stopping the chip because
3712  * we've detected a problem internally; otherwise, this is a normal
3713  * (clean) stop (at user request i.e. the last STREAM has been closed).
3714  */
3715 void bge_chip_stop(bge_t *bgep, boolean_t fault);
3716 #pragma	no_inline(bge_chip_stop)
3717 
3718 void
3719 bge_chip_stop(bge_t *bgep, boolean_t fault)
3720 {
3721 	bge_regno_t regno;
3722 	bge_regno_t *rbp;
3723 	boolean_t ok = B_TRUE;
3724 
3725 	BGE_TRACE(("bge_chip_stop($%p)",
3726 	    (void *)bgep));
3727 
3728 	ASSERT(mutex_owned(bgep->genlock));
3729 
3730 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3731 	    (pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR) |
3732 	     MHCR_MASK_PCI_INT_OUTPUT));
3733 
3734 	ok &= bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 0);
3735 	ok &= bge_chip_disable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 0);
3736 	ok &= bge_chip_disable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0);
3737 	ok &= bge_chip_disable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 0);
3738 	ok &= bge_chip_disable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 0);
3739 	ok &= bge_chip_disable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 0);
3740 	ok &= bge_chip_disable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 0);
3741 
3742 	ok &= bge_chip_disable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 0);
3743 	ok &= bge_chip_disable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 0);
3744 	ok &= bge_chip_disable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0);
3745 	ok &= bge_chip_disable_engine(bgep, READ_DMA_MODE_REG, 0);
3746 	ok &= bge_chip_disable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0);
3747 	ok &= bge_chip_disable_engine(bgep, DMA_COMPLETION_MODE_REG, 0);
3748 	ok &= bge_chip_disable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 0);
3749 	ok &= bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0);
3750 
3751 	bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_ENABLE_TDE);
3752 	drv_usecwait(40);
3753 
3754 	ok &= bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, 0);
3755 	ok &= bge_chip_disable_engine(bgep, WRITE_DMA_MODE_REG, 0);
3756 	ok &= bge_chip_disable_engine(bgep, MBUF_CLUSTER_FREE_MODE_REG, 0);
3757 	ok &= bge_chip_disable_engine(bgep, FTQ_RESET_REG, 0);
3758 	ok &= bge_chip_disable_engine(bgep, BUFFER_MANAGER_MODE_REG, 0);
3759 	ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0);
3760 	ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0);
3761 
3762 	if (!ok && !fault)
3763 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
3764 
3765 	/*
3766 	 * Finally, disable (all) MAC events & clear the MAC status
3767 	 */
3768 	bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3769 	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3770 
3771 	/*
3772 	 * if we're stopping the chip because of a detected fault then do
3773 	 * appropriate actions
3774 	 */
3775 	if (fault) {
3776 		if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
3777 			bgep->bge_chip_state = BGE_CHIP_FAULT;
3778 			if (!bgep->manual_reset)
3779 				ddi_fm_service_impact(bgep->devinfo,
3780 				    DDI_SERVICE_LOST);
3781 			if (bgep->bge_dma_error) {
3782 				/*
3783 				 * need to free buffers in case the fault was
3784 				 * due to a memory error in a buffer - got to
3785 				 * do a fair bit of tidying first
3786 				 */
3787 				if (bgep->progress & PROGRESS_KSTATS) {
3788 					bge_fini_kstats(bgep);
3789 					bgep->progress &= ~PROGRESS_KSTATS;
3790 				}
3791 				if (bgep->progress & PROGRESS_INTR) {
3792 					bge_intr_disable(bgep);
3793 					rw_enter(bgep->errlock, RW_WRITER);
3794 					bge_fini_rings(bgep);
3795 					rw_exit(bgep->errlock);
3796 					bgep->progress &= ~PROGRESS_INTR;
3797 				}
3798 				if (bgep->progress & PROGRESS_BUFS) {
3799 					bge_free_bufs(bgep);
3800 					bgep->progress &= ~PROGRESS_BUFS;
3801 				}
3802 				bgep->bge_dma_error = B_FALSE;
3803 			}
3804 		}
3805 	} else
3806 		bgep->bge_chip_state = BGE_CHIP_STOPPED;
3807 }
3808 
3809 /*
3810  * Poll for completion of chip's ROM firmware; also, at least on the
3811  * first time through, find and return the hardware MAC address, if any.
3812  */
3813 static uint64_t bge_poll_firmware(bge_t *bgep);
3814 #pragma	no_inline(bge_poll_firmware)
3815 
3816 static uint64_t
3817 bge_poll_firmware(bge_t *bgep)
3818 {
3819 	uint64_t magic;
3820 	uint64_t mac;
3821 	uint32_t gen, val;
3822 	uint32_t i;
3823 
3824 	/*
3825 	 * Step 19: poll for firmware completion (GENCOMM port set
3826 	 * to the ones complement of T3_MAGIC_NUMBER).
3827 	 *
3828 	 * While we're at it, we also read the MAC address register;
3829 	 * at some stage the firmware will load this with the
3830 	 * factory-set value.
3831 	 *
3832 	 * When both the magic number and the MAC address are set,
3833 	 * we're done; but we impose a time limit of one second
3834 	 * (1000*1000us) in case the firmware fails in some fashion
3835 	 * or the SEEPROM that provides that MAC address isn't fitted.
3836 	 *
3837 	 * After the first time through (chip state != INITIAL), we
3838 	 * don't need the MAC address to be set (we've already got it
3839 	 * or not, from the first time), so we don't wait for it, but
3840 	 * we still have to wait for the T3_MAGIC_NUMBER.
3841 	 *
3842 	 * Note: the magic number is only a 32-bit quantity, but the NIC
3843 	 * memory is 64-bit (and big-endian) internally.  Addressing the
3844 	 * GENCOMM word as "the upper half of a 64-bit quantity" makes
3845 	 * it work correctly on both big- and little-endian hosts.
3846 	 */
3847 	if (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906) {
3848 		for (i = 0; i < 1000; ++i) {
3849 			drv_usecwait(1000);
3850 			val = bge_reg_get32(bgep, VCPU_STATUS_REG);
3851 			if (val & VCPU_INIT_DONE)
3852 				break;
3853 		}
3854 		BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops",
3855 		    (void *)bgep, i));
3856 		mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3857 	} else {
3858 		for (i = 0; i < 1000; ++i) {
3859 			drv_usecwait(1000);
3860 			gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
3861 			if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep))
3862 				drv_usecwait(100000);
3863 			mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3864 #ifdef BGE_IPMI_ASF
3865 			if (!bgep->asf_enabled) {
3866 #endif
3867 				if (gen != ~T3_MAGIC_NUMBER)
3868 					continue;
3869 #ifdef BGE_IPMI_ASF
3870 			}
3871 #endif
3872 			if (mac != 0ULL)
3873 				break;
3874 			if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
3875 				break;
3876 		}
3877 	}
3878 
3879 	magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
3880 	BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
3881 	    (void *)bgep, gen, i));
3882 	BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
3883 	    mac, magic));
3884 
3885 	return (mac);
3886 }
3887 
3888 /*
3889  * Maximum times of trying to get the NVRAM access lock
3890  * by calling bge_nvmem_acquire()
3891  */
3892 #define	MAX_TRY_NVMEM_ACQUIRE	10000
3893 
3894 #ifdef BGE_IPMI_ASF
3895 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3896 #else
3897 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3898 #endif
3899 #pragma	no_inline(bge_chip_reset)
3900 
3901 int
3902 #ifdef BGE_IPMI_ASF
3903 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3904 #else
3905 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3906 #endif
3907 {
3908 	chip_id_t chipid;
3909 	uint64_t mac;
3910 	uint64_t magic;
3911 	uint32_t tmp;
3912 	uint32_t mhcr_base;
3913 	uint32_t mhcr;
3914 	uint32_t sx0;
3915 	uint32_t i, tries;
3916 #ifdef BGE_IPMI_ASF
3917 	uint32_t mailbox;
3918 #endif
3919 	int retval = DDI_SUCCESS;
3920 
3921 	BGE_TRACE(("bge_chip_reset($%p, %d)",
3922 		(void *)bgep, enable_dma));
3923 
3924 	ASSERT(mutex_owned(bgep->genlock));
3925 
3926 	BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3927 		(void *)bgep, enable_dma, bgep->bge_chip_state));
3928 
3929 	/*
3930 	 * Do we need to stop the chip cleanly before resetting?
3931 	 */
3932 	switch (bgep->bge_chip_state) {
3933 	default:
3934 		_NOTE(NOTREACHED)
3935 		return (DDI_FAILURE);
3936 
3937 	case BGE_CHIP_INITIAL:
3938 	case BGE_CHIP_STOPPED:
3939 	case BGE_CHIP_RESET:
3940 		break;
3941 
3942 	case BGE_CHIP_RUNNING:
3943 	case BGE_CHIP_ERROR:
3944 	case BGE_CHIP_FAULT:
3945 		bge_chip_stop(bgep, B_FALSE);
3946 		break;
3947 	}
3948 
3949 	mhcr_base = MHCR_ENABLE_INDIRECT_ACCESS |
3950 	            MHCR_ENABLE_PCI_STATE_RW |
3951 	            MHCR_ENABLE_TAGGED_STATUS_MODE |
3952 	            MHCR_MASK_INTERRUPT_MODE |
3953 	            MHCR_MASK_PCI_INT_OUTPUT |
3954 	            MHCR_CLEAR_INTERRUPT_INTA;
3955 
3956 #ifdef BGE_IPMI_ASF
3957 	if (bgep->asf_enabled) {
3958 		mhcr = mhcr_base;
3959 #ifdef _BIG_ENDIAN
3960 		mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP |
3961 		         MHCR_ENABLE_ENDIAN_BYTE_SWAP);
3962 #endif
3963 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3964 
3965 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3966 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3967 			MEMORY_ARBITER_ENABLE);
3968 
3969 		if (asf_mode == ASF_MODE_INIT) {
3970 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3971 		} else if (asf_mode == ASF_MODE_SHUTDOWN) {
3972 			bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3973 		}
3974 	}
3975 #endif
3976 
3977 	/*
3978 	 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3979 	 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3980 	 *
3981 	 * Before reset Core clock,it is
3982 	 * also required to initialize the Memory Arbiter as specified in step9
3983 	 * and Misc Host Control Register as specified in step-13
3984 	 * Step 4-5: reset Core clock & wait for completion
3985 	 * Steps 6-8: are done by bge_chip_cfg_init()
3986 	 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3987 	 */
3988 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3989 		retval = DDI_FAILURE;
3990 
3991 	mhcr = mhcr_base;
3992 #ifdef _BIG_ENDIAN
3993 	mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP |
3994 	         MHCR_ENABLE_ENDIAN_BYTE_SWAP);
3995 #endif
3996 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3997 
3998 #ifdef BGE_IPMI_ASF
3999 	if (bgep->asf_enabled)
4000 		bgep->asf_wordswapped = B_FALSE;
4001 #endif
4002 	/*
4003 	 * NVRAM Corruption Workaround
4004 	 */
4005 	for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
4006 		if (bge_nvmem_acquire(bgep) != EAGAIN)
4007 			break;
4008 	if (tries >= MAX_TRY_NVMEM_ACQUIRE)
4009 		BGE_DEBUG(("%s: fail to acquire nvram lock",
4010 			bgep->ifname));
4011 
4012 	bge_ape_lock(bgep, BGE_APE_LOCK_GRC);
4013 
4014 #ifdef BGE_IPMI_ASF
4015 	if (!bgep->asf_enabled) {
4016 #endif
4017 		magic = (uint64_t)T3_MAGIC_NUMBER << 32;
4018 		bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
4019 #ifdef BGE_IPMI_ASF
4020 	}
4021 #endif
4022 
4023 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4024 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
4025 		bge_reg_set32(bgep, FAST_BOOT_PC, 0);
4026 		if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
4027 			retval = DDI_FAILURE;
4028 	}
4029 
4030 	mhcr = mhcr_base;
4031 #ifdef _BIG_ENDIAN
4032 	mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP |
4033 	         MHCR_ENABLE_ENDIAN_BYTE_SWAP);
4034 #endif
4035 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
4036 
4037 	if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
4038 		retval = DDI_FAILURE;
4039 
4040 	bge_chip_cfg_init(bgep, &chipid, enable_dma);
4041 
4042 	/*
4043 	 * Step 8a: This may belong elsewhere, but BCM5721 needs
4044 	 * a bit set to avoid a fifo overflow/underflow bug.
4045 	 */
4046 	if ((bgep->chipid.chip_label == 5721) ||
4047 		(bgep->chipid.chip_label == 5751) ||
4048 		(bgep->chipid.chip_label == 5752) ||
4049 		(bgep->chipid.chip_label == 5755) ||
4050 		(bgep->chipid.chip_label == 5756) ||
4051 		(bgep->chipid.chip_label == 5789) ||
4052 		(bgep->chipid.chip_label == 5906))
4053 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
4054 
4055 	/*
4056 	 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
4057 	 * not be changed.
4058 	 */
4059 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
4060 		retval = DDI_FAILURE;
4061 
4062 	/*
4063 	 * Steps 10-11: configure PIO endianness options and
4064 	 * enable indirect register access -- already done
4065 	 * Steps 12-13: enable writing to the PCI state & clock
4066 	 * control registers -- not required; we aren't going to
4067 	 * use those features.
4068 	 * Steps 14-15: Configure DMA endianness options.  See
4069 	 * the comments on the setting of the MHCR above.
4070 	 */
4071 	tmp = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
4072 #ifdef _BIG_ENDIAN
4073 	tmp |= (MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME);
4074 #endif
4075 #ifdef BGE_IPMI_ASF
4076 	if (bgep->asf_enabled)
4077 		tmp |= MODE_HOST_STACK_UP;
4078 #endif
4079 	bge_reg_put32(bgep, MODE_CONTROL_REG, tmp);
4080 
4081 #ifdef BGE_IPMI_ASF
4082 	if (bgep->asf_enabled) {
4083 #ifdef __sparc
4084 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
4085 			MEMORY_ARBITER_ENABLE |
4086 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
4087 #endif
4088 
4089 #ifdef  BGE_NETCONSOLE
4090 		if (!bgep->asf_newhandshake) {
4091 			if ((asf_mode == ASF_MODE_INIT) ||
4092 			(asf_mode == ASF_MODE_POST_INIT)) {
4093 				bge_asf_post_reset_old_mode(bgep,
4094 					BGE_INIT_RESET);
4095 			} else {
4096 				bge_asf_post_reset_old_mode(bgep,
4097 					BGE_SHUTDOWN_RESET);
4098 			}
4099 		}
4100 #endif
4101 
4102 		/* Wait for NVRAM init */
4103 		i = 0;
4104 		drv_usecwait(5000);
4105 		mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
4106 
4107 		while ((mailbox != (uint32_t)
4108 			~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
4109 			(i < 10000)) {
4110 			drv_usecwait(100);
4111 			mailbox = bge_nic_get32(bgep,
4112 				BGE_FIRMWARE_MAILBOX);
4113 			i++;
4114 		}
4115 
4116 #ifndef BGE_NETCONSOLE
4117 		if (!bgep->asf_newhandshake) {
4118 			if ((asf_mode == ASF_MODE_INIT) ||
4119 				(asf_mode == ASF_MODE_POST_INIT)) {
4120 
4121 				bge_asf_post_reset_old_mode(bgep,
4122 					BGE_INIT_RESET);
4123 			} else {
4124 				bge_asf_post_reset_old_mode(bgep,
4125 					BGE_SHUTDOWN_RESET);
4126 			}
4127 		}
4128 #endif
4129 	}
4130 #endif
4131 
4132 	bge_ape_unlock(bgep, BGE_APE_LOCK_GRC);
4133 
4134 	/*
4135 	 * Steps 16-17: poll for firmware completion
4136 	 */
4137 	mac = bge_poll_firmware(bgep);
4138 
4139 	if (bgep->chipid.device == DEVICE_ID_5720) {
4140 		tmp = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG);
4141 		bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG,
4142 		              (tmp & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN));
4143 	}
4144 
4145 	/*
4146 	 * Step 18: enable external memory -- doesn't apply.
4147 	 *
4148 	 * However we take the opportunity to set the MLCR anyway, as
4149 	 * this register also controls the SEEPROM auto-access method
4150 	 * which we may want to use later ...
4151 	 *
4152 	 * The proper value here depends on the way the chip is wired
4153 	 * into the circuit board, as this register *also* controls which
4154 	 * of the "Miscellaneous I/O" pins are driven as outputs and the
4155 	 * values driven onto those pins!
4156 	 *
4157 	 * See also step 74 in the PRM ...
4158 	 */
4159 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
4160 	    bgep->chipid.bge_mlcr_default);
4161 
4162 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
4163 	    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
4164 		tmp = bge_reg_get32(bgep, SERDES_RX_CONTROL);
4165 		tmp |= SERDES_RX_CONTROL_SIG_DETECT;
4166 		bge_reg_put32(bgep, SERDES_RX_CONTROL, tmp);
4167 	}
4168 
4169 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
4170 
4171 	/*
4172 	 * Step 20: clear the Ethernet MAC mode register
4173 	 */
4174 	if (bgep->ape_enabled)
4175 		bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG,
4176 		    ETHERNET_MODE_APE_TX_EN | ETHERNET_MODE_APE_RX_EN);
4177 	else
4178 		bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
4179 
4180 	/*
4181 	 * Step 21: restore cache-line-size, latency timer, and
4182 	 * subsystem ID registers to their original values (not
4183 	 * those read into the local structure <chipid>, 'cos
4184 	 * that was after they were cleared by the RESET).
4185 	 *
4186 	 * Note: the Subsystem Vendor/Device ID registers are not
4187 	 * directly writable in config space, so we use the shadow
4188 	 * copy in "Page Zero" of register space to restore them
4189 	 * both in one go ...
4190 	 */
4191 	pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
4192 		bgep->chipid.clsize);
4193 	pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
4194 		bgep->chipid.latency);
4195 	bge_reg_put32(bgep, PCI_CONF_SUBVENID,
4196 		(bgep->chipid.subdev << 16) | bgep->chipid.subven);
4197 
4198 	/*
4199 	 * The SEND INDEX registers should be reset to zero by the
4200 	 * global chip reset; if they're not, there'll be trouble
4201 	 * later on.
4202 	 */
4203 	sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
4204 	if (sx0 != 0) {
4205 		BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
4206 		bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
4207 		retval = DDI_FAILURE;
4208 	}
4209 
4210 	/* Enable MSI code */
4211 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4212 		bge_reg_set32(bgep, MSI_MODE_REG,
4213 		    MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION);
4214 
4215 	/*
4216 	 * On the first time through, save the factory-set MAC address
4217 	 * (if any).  If bge_poll_firmware() above didn't return one
4218 	 * (from a chip register) consider looking in the attached NV
4219 	 * memory device, if any.  Once we have it, we save it in both
4220 	 * register-image (64-bit) and byte-array forms.  All-zero and
4221 	 * all-one addresses are not valid, and we refuse to stash those.
4222 	 */
4223 	if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
4224 		if (mac == 0ULL)
4225 			mac = bge_get_nvmac(bgep);
4226 		if (mac != 0ULL && mac != ~0ULL) {
4227 			bgep->chipid.hw_mac_addr = mac;
4228 			for (i = ETHERADDRL; i-- != 0; ) {
4229 				bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
4230 				mac >>= 8;
4231 			}
4232 			bgep->chipid.vendor_addr.set = B_TRUE;
4233 		}
4234 	}
4235 
4236 #ifdef BGE_IPMI_ASF
4237 	if (bgep->asf_enabled && bgep->asf_newhandshake) {
4238 		if (asf_mode != ASF_MODE_NONE) {
4239 			if ((asf_mode == ASF_MODE_INIT) ||
4240 				(asf_mode == ASF_MODE_POST_INIT)) {
4241 
4242 				bge_asf_post_reset_new_mode(bgep,
4243 					BGE_INIT_RESET);
4244 			} else {
4245 				bge_asf_post_reset_new_mode(bgep,
4246 					BGE_SHUTDOWN_RESET);
4247 			}
4248 		}
4249 	}
4250 #endif
4251 
4252 	/*
4253 	 * Record the new state
4254 	 */
4255 	bgep->chip_resets += 1;
4256 	bgep->bge_chip_state = BGE_CHIP_RESET;
4257 	return (retval);
4258 }
4259 
4260 /*
4261  * bge_chip_start() -- start the chip transmitting and/or receiving,
4262  * including enabling interrupts
4263  */
4264 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
4265 #pragma	no_inline(bge_chip_start)
4266 
4267 void
4268 bge_chip_coalesce_update(bge_t *bgep)
4269 {
4270 	bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
4271 	    bgep->chipid.tx_count_norm);
4272 	bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
4273 	    bgep->chipid.tx_ticks_norm);
4274 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
4275 	    bgep->chipid.rx_count_norm);
4276 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
4277 	    bgep->chipid.rx_ticks_norm);
4278 }
4279 
4280 int
4281 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
4282 {
4283 	uint32_t coalmode;
4284 	uint32_t ledctl;
4285 	uint32_t mtu;
4286 	uint32_t maxring;
4287 	uint32_t stats_mask;
4288 	uint32_t dma_wrprio;
4289 	uint64_t ring;
4290 	uint32_t reg;
4291 	uint32_t regval;
4292 	uint32_t mhcr;
4293 	int retval = DDI_SUCCESS;
4294 	int i;
4295 
4296 	BGE_TRACE(("bge_chip_start($%p)",
4297 	    (void *)bgep));
4298 
4299 	ASSERT(mutex_owned(bgep->genlock));
4300 	ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
4301 
4302 	/* Initialize EEE, enable MAC control of LPI */
4303 	bge_eee_init(bgep);
4304 
4305 	if (bgep->ape_enabled) {
4306 		/*
4307 		 * Allow reads and writes to the
4308 		 * APE register and memory space.
4309 		 */
4310 		regval = pci_config_get32(bgep->cfg_handle,
4311 		    PCI_CONF_BGE_PCISTATE);
4312 		regval |= PCISTATE_ALLOW_APE_CTLSPC_WR |
4313 		    PCISTATE_ALLOW_APE_SHMEM_WR | PCISTATE_ALLOW_APE_PSPACE_WR;
4314 		pci_config_put32(bgep->cfg_handle,
4315 		    PCI_CONF_BGE_PCISTATE, regval);
4316 	}
4317 
4318 	/*
4319 	 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
4320 	 * The document specifies 95 separate steps to fully
4321 	 * initialise the chip!!!!
4322 	 *
4323 	 * The reset code above has already got us as far as step
4324 	 * 21, so we continue with ...
4325 	 *
4326 	 * Step 22: clear the MAC statistics block
4327 	 * (0x0300-0x0aff in NIC-local memory)
4328 	 */
4329 	if (bgep->chipid.statistic_type == BGE_STAT_BLK)
4330 		bge_nic_zero(bgep, NIC_MEM_STATISTICS,
4331 		    NIC_MEM_STATISTICS_SIZE);
4332 
4333 	/*
4334 	 * Step 23: clear the status block (in host memory)
4335 	 */
4336 	DMA_ZERO(bgep->status_block);
4337 
4338 	/*
4339 	 * Step 24: set DMA read/write control register
4340 	 */
4341 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
4342 	    bgep->chipid.bge_dma_rwctrl);
4343 
4344 	/*
4345 	 * Step 25: Configure DMA endianness -- already done (16/17)
4346 	 * Step 26: Configure Host-Based Send Rings
4347 	 * Step 27: Indicate Host Stack Up
4348 	 */
4349 	bge_reg_set32(bgep, MODE_CONTROL_REG,
4350 	    MODE_HOST_SEND_BDS |
4351 	    MODE_HOST_STACK_UP);
4352 
4353 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4354 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
4355 		reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)
4356 		          ? RDMA_RSRV_CTRL_REG2 : RDMA_RSRV_CTRL_REG;
4357 		regval = bge_reg_get32(bgep, reg);
4358 		if ((bgep->chipid.device == DEVICE_ID_5719) ||
4359 		    (bgep->chipid.device == DEVICE_ID_5720) ||
4360 		    (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) {
4361 			regval &= ~(RDMA_RSRV_CTRL_TXMRGN_MASK |
4362 			            RDMA_RSRV_CTRL_FIFO_LWM_MASK |
4363 			            RDMA_RSRV_CTRL_FIFO_HWM_MASK);
4364 			regval |= (RDMA_RSRV_CTRL_TXMRGN_320B |
4365 			           RDMA_RSRV_CTRL_FIFO_LWM_1_5K |
4366 			           RDMA_RSRV_CTRL_FIFO_HWM_1_5K);
4367 		}
4368 		/* Enable the DMA FIFO Overrun fix. */
4369 		bge_reg_put32(bgep, reg,
4370 		    (regval | RDMA_RSRV_CTRL_FIFO_OFLW_FIX));
4371 
4372 		if ((CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5719) ||
4373 		    (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5720) ||
4374 		    (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) {
4375 			reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)
4376 			          ? RDMA_CORR_CTRL_REG2 : RDMA_CORR_CTRL_REG;
4377 			regval = bge_reg_get32(bgep, reg);
4378 			bge_reg_put32(bgep, reg, (regval |
4379 			                          RDMA_CORR_CTRL_BLEN_BD_4K |
4380 			                          RDMA_CORR_CTRL_BLEN_LSO_4K));
4381 		}
4382 	}
4383 
4384 	/*
4385 	 * Step 28: Configure checksum options:
4386 	 *	Solaris supports the hardware default checksum options.
4387 	 *
4388 	 *	Workaround for Incorrect pseudo-header checksum calculation.
4389 	 */
4390 	if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
4391 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4392 		    MODE_SEND_NO_PSEUDO_HDR_CSUM);
4393 
4394 	/*
4395 	 * Step 29: configure Timer Prescaler.  The value is always the
4396 	 * same: the Core Clock frequency in MHz (66), minus 1, shifted
4397 	 * into bits 7-1.  Don't set bit 0, 'cos that's the RESET bit
4398 	 * for the whole chip!
4399 	 */
4400 	regval = bge_reg_get32(bgep, MISC_CONFIG_REG);
4401 	regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT;
4402 	bge_reg_put32(bgep, MISC_CONFIG_REG, regval);
4403 
4404 	if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
4405 		drv_usecwait(40);
4406 		/* put PHY into ready state */
4407 		bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
4408 		(void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
4409 		drv_usecwait(40);
4410 	}
4411 
4412 	/*
4413 	 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
4414 	 *
4415 	 * If the mbuf_length is specified as 0, we just leave these at
4416 	 * their hardware defaults, rather than explicitly setting them.
4417 	 * As the Broadcom HRM,driver better not change the parameters
4418 	 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
4419 	 */
4420 	if ((bgep->chipid.mbuf_length != 0) &&
4421 	    (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
4422 			bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
4423 			    bgep->chipid.mbuf_base);
4424 			bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
4425 			    bgep->chipid.mbuf_length);
4426 			bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
4427 			    DMAD_POOL_BASE_DEFAULT);
4428 			bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
4429 			    DMAD_POOL_LENGTH_DEFAULT);
4430 	}
4431 
4432 	/*
4433 	 * Step 32: configure MAC memory pool watermarks
4434 	 */
4435 	bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
4436 	    bgep->chipid.mbuf_lo_water_rdma);
4437 	bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
4438 	    bgep->chipid.mbuf_lo_water_rmac);
4439 	bge_reg_put32(bgep, MBUF_HIWAT_REG,
4440 	    bgep->chipid.mbuf_hi_water);
4441 
4442 	/*
4443 	 * Step 33: configure DMA resource watermarks
4444 	 */
4445 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4446 		bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
4447 		    bge_dmad_lo_water);
4448 		bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
4449 		    bge_dmad_hi_water);
4450 	}
4451 	bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
4452 
4453 	/*
4454 	 * Steps 34-36: enable buffer manager & internal h/w queues
4455 	 */
4456 	regval = STATE_MACHINE_ATTN_ENABLE_BIT;
4457 	if (bgep->chipid.device == DEVICE_ID_5719)
4458 		regval |= BUFFER_MANAGER_MODE_NO_TX_UNDERRUN;
4459 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4460 	    DEVICE_5725_SERIES_CHIPSETS(bgep))
4461 		regval |= BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE;
4462 	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval))
4463 		retval = DDI_FAILURE;
4464 
4465 	if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
4466 		retval = DDI_FAILURE;
4467 
4468 	/*
4469 	 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
4470 	 */
4471 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4472 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
4473 		buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING];
4474 		bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG,
4475 		    brp->desc.cookie.dmac_laddress);
4476 		bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
4477 		    (brp->desc.nslots) << 16 | brp->buf[0].size << 2);
4478 		bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
4479 		    NIC_MEM_SHADOW_BUFF_STD_5717);
4480 	} else
4481 		bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
4482 		    &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
4483 
4484 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4485 		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
4486 		    &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
4487 		bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
4488 		    &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
4489 	}
4490 
4491 	/*
4492 	 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
4493 	 */
4494 	bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
4495 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4496 		bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
4497 		    bge_replenish_jumbo);
4498 		bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
4499 		    bge_replenish_mini);
4500 	}
4501 
4502 	/*
4503 	 * Steps 41-43: clear Send Ring Producer Indices and initialise
4504 	 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
4505 	 */
4506 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4507 		maxring = BGE_SEND_RINGS_MAX;
4508 	else
4509 		maxring = BGE_SEND_RINGS_MAX_5705;
4510 	for (ring = 0; ring < maxring; ++ring) {
4511 		bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
4512 		bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
4513 		bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
4514 		    &bgep->send[ring].hw_rcb);
4515 	}
4516 
4517 	/*
4518 	 * Steps 44-45: initialise Receive Return Rings
4519 	 * (0x0200-0x02ff in NIC-local memory)
4520 	 */
4521 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4522 		maxring = BGE_RECV_RINGS_MAX;
4523 	else
4524 		maxring = BGE_RECV_RINGS_MAX_5705;
4525 	for (ring = 0; ring < maxring; ++ring)
4526 		bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
4527 		    &bgep->recv[ring].hw_rcb);
4528 
4529 	/*
4530 	 * Step 46: initialise Receive Buffer (Producer) Ring indexes
4531 	 */
4532 	bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
4533 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4534 		bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
4535 		bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
4536 	}
4537 	/*
4538 	 * Step 47: configure the MAC unicast address
4539 	 * Step 48: configure the random backoff seed
4540 	 * Step 96: set up multicast filters
4541 	 */
4542 #ifdef BGE_IPMI_ASF
4543 	if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
4544 #else
4545 	if (bge_chip_sync(bgep) == DDI_FAILURE)
4546 #endif
4547 		retval = DDI_FAILURE;
4548 
4549 	/*
4550 	 * Step 49: configure the MTU
4551 	 */
4552 	mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
4553 	bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
4554 
4555 	/*
4556 	 * Step 50: configure the IPG et al
4557 	 */
4558 	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
4559 
4560 	/*
4561 	 * Step 51: configure the default Rx Return Ring
4562 	 */
4563 	bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
4564 
4565 	/*
4566 	 * Steps 52-54: configure Receive List Placement,
4567 	 * and enable Receive List Placement Statistics
4568 	 */
4569 	bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
4570 	    RCV_LP_CONFIG(bgep->chipid.rx_rings));
4571 	switch (MHCR_CHIP_ASIC_REV(bgep)) {
4572 	case MHCR_CHIP_ASIC_REV_5700:
4573 	case MHCR_CHIP_ASIC_REV_5701:
4574 	case MHCR_CHIP_ASIC_REV_5703:
4575 	case MHCR_CHIP_ASIC_REV_5704:
4576 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
4577 		break;
4578 	case MHCR_CHIP_ASIC_REV_5705:
4579 		break;
4580 	default:
4581 		stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
4582 		stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ;
4583 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
4584 		break;
4585 	}
4586 	bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
4587 
4588 	if (bgep->chipid.rx_rings > 1)
4589 		bge_init_recv_rule(bgep);
4590 
4591 	/*
4592 	 * Steps 55-56: enable Send Data Initiator Statistics
4593 	 */
4594 	bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
4595 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4596 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
4597 		    SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
4598 	} else {
4599 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
4600 		    SEND_INIT_STATS_ENABLE);
4601 	}
4602 	/*
4603 	 * Steps 57-58: stop (?) the Host Coalescing Engine
4604 	 */
4605 	if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
4606 		retval = DDI_FAILURE;
4607 
4608 	/*
4609 	 * Steps 59-62: initialise Host Coalescing parameters
4610 	 */
4611 	bge_chip_coalesce_update(bgep);
4612 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4613 		bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
4614 		    bge_tx_count_intr);
4615 		bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
4616 		    bge_tx_ticks_intr);
4617 		bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
4618 		    bge_rx_count_intr);
4619 		bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
4620 		    bge_rx_ticks_intr);
4621 	}
4622 
4623 	/*
4624 	 * Steps 63-64: initialise status block & statistics
4625 	 * host memory addresses
4626 	 * The statistic block does not exist in some chipsets
4627 	 * Step 65: initialise Statistics Coalescing Tick Counter
4628 	 */
4629 	bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
4630 	    bgep->status_block.cookie.dmac_laddress);
4631 
4632 	/*
4633 	 * Steps 66-67: initialise status block & statistics
4634 	 * NIC-local memory addresses
4635 	 */
4636 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4637 		bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
4638 		    bgep->statistics.cookie.dmac_laddress);
4639 		bge_reg_put32(bgep, STATISTICS_TICKS_REG,
4640 		    STATISTICS_TICKS_DEFAULT);
4641 		bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
4642 		    NIC_MEM_STATUS_BLOCK);
4643 		bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
4644 		    NIC_MEM_STATISTICS);
4645 	}
4646 
4647 	/*
4648 	 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
4649 	 * Completion Engine, the Receive List Placement Engine, and the
4650 	 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
4651 	 * and BCM5715.
4652 	 */
4653 
4654 	if (bgep->chipid.device == DEVICE_ID_5719) {
4655 		for (i = 0; i < BGE_NUM_RDMA_CHANNELS; i++) {
4656 			if (bge_reg_get32(bgep, (BGE_RDMA_LENGTH + (i << 2))) >
4657 			    bgep->chipid.default_mtu)
4658 				break;
4659 		}
4660 		if (i < BGE_NUM_RDMA_CHANNELS) {
4661 			regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG);
4662 			regval |= RDMA_CORR_CTRL_TX_LENGTH_WA;
4663 			bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval);
4664 			bgep->rdma_length_bug_on_5719 = B_TRUE;
4665 		}
4666 	}
4667 
4668 	if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
4669 	    bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
4670 		coalmode = COALESCE_64_BYTE_STATUS;
4671 	else
4672 		coalmode = 0;
4673 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4674 	    DEVICE_5725_SERIES_CHIPSETS(bgep))
4675 		coalmode = COALESCE_CLR_TICKS_RX;
4676 	if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
4677 		retval = DDI_FAILURE;
4678 	if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
4679 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4680 		retval = DDI_FAILURE;
4681 	if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
4682 		retval = DDI_FAILURE;
4683 
4684 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4685 		if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
4686 		    STATE_MACHINE_ATTN_ENABLE_BIT))
4687 			retval = DDI_FAILURE;
4688 
4689 	/*
4690 	 * Step 72: Enable MAC DMA engines
4691 	 * Step 73: Clear & enable MAC statistics
4692 	 */
4693 	if (bgep->ape_enabled) {
4694 		/* XXX put32 instead of set32 ? */
4695 		bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG,
4696 		    ETHERNET_MODE_APE_TX_EN | ETHERNET_MODE_APE_RX_EN);
4697 	}
4698 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4699 	    ETHERNET_MODE_ENABLE_FHDE |
4700 	    ETHERNET_MODE_ENABLE_RDE |
4701 	    ETHERNET_MODE_ENABLE_TDE);
4702 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4703 	    ETHERNET_MODE_ENABLE_TX_STATS |
4704 	    ETHERNET_MODE_ENABLE_RX_STATS |
4705 	    ETHERNET_MODE_CLEAR_TX_STATS |
4706 	    ETHERNET_MODE_CLEAR_RX_STATS);
4707 
4708 	drv_usecwait(140);
4709 
4710 	if (bgep->ape_enabled) {
4711 		/* Write our heartbeat update interval to APE. */
4712 		bge_ape_put32(bgep, BGE_APE_HOST_HEARTBEAT_INT_MS,
4713 		    APE_HOST_HEARTBEAT_INT_DISABLE);
4714 	}
4715 
4716 	/*
4717 	 * Step 74: configure the MLCR (Miscellaneous Local Control
4718 	 * Register); not required, as we set up the MLCR in step 10
4719 	 * (part of the reset code) above.
4720 	 *
4721 	 * Step 75: clear Interrupt Mailbox 0
4722 	 */
4723 	bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
4724 
4725 	/*
4726 	 * Steps 76-87: Gentlemen, start your engines ...
4727 	 *
4728 	 * Enable the DMA Completion Engine, the Write DMA Engine,
4729 	 * the Read DMA Engine, Receive Data Completion Engine,
4730 	 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
4731 	 * the Send BD Completion Engine, the Receive BD Initiator Engine,
4732 	 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
4733 	 * the Send BD Initiator Engine, and the Send BD Selector Engine.
4734 	 *
4735 	 * Beware exhaust fumes?
4736 	 */
4737 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4738 		if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
4739 			retval = DDI_FAILURE;
4740 	dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
4741 	    ALL_DMA_ATTN_BITS;
4742 	/* the 5723 check here covers all newer chip families (OK) */
4743 	if ((MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5755) ||
4744 	    (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5723) ||
4745 	    (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906)) {
4746 		dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
4747 	}
4748 	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
4749 	    dma_wrprio))
4750 		retval = DDI_FAILURE;
4751 
4752 	drv_usecwait(40);
4753 
4754 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
4755 	    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4756 	    DEVICE_5725_SERIES_CHIPSETS(bgep))
4757 		bge_dma_rdprio = 0;
4758 	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
4759 	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
4760 		retval = DDI_FAILURE;
4761 
4762 	drv_usecwait(40);
4763 
4764 	if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
4765 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4766 		retval = DDI_FAILURE;
4767 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4768 		if (!bge_chip_enable_engine(bgep,
4769 		    MBUF_CLUSTER_FREE_MODE_REG, 0))
4770 			retval = DDI_FAILURE;
4771 	if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
4772 		retval = DDI_FAILURE;
4773 	if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
4774 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4775 		retval = DDI_FAILURE;
4776 	if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
4777 	    RCV_BD_DISABLED_RING_ATTN))
4778 		retval = DDI_FAILURE;
4779 	if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
4780 	    RCV_DATA_BD_ILL_RING_ATTN))
4781 		retval = DDI_FAILURE;
4782 	if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
4783 		retval = DDI_FAILURE;
4784 	if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
4785 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4786 		retval = DDI_FAILURE;
4787 	if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
4788 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4789 		retval = DDI_FAILURE;
4790 
4791 	drv_usecwait(40);
4792 
4793 	/*
4794 	 * Step 88: download firmware -- doesn't apply
4795 	 * Steps 89-90: enable Transmit & Receive MAC Engines
4796 	 */
4797 	regval = 0;
4798 	if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
4799 		regval |= TRANSMIT_MODE_MBUF_LOCKUP_FIX;
4800 	}
4801 	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval))
4802 		retval = DDI_FAILURE;
4803 
4804 	drv_usecwait(100);
4805 
4806 #ifdef BGE_IPMI_ASF
4807 	if (!bgep->asf_enabled) {
4808 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4809 		    RECEIVE_MODE_KEEP_VLAN_TAG))
4810 			retval = DDI_FAILURE;
4811 	} else {
4812 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
4813 			retval = DDI_FAILURE;
4814 	}
4815 #else
4816 	if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4817 	    RECEIVE_MODE_KEEP_VLAN_TAG))
4818 		retval = DDI_FAILURE;
4819 #endif
4820 
4821 	drv_usecwait(100);
4822 
4823 	/*
4824 	 * Step 91: disable auto-polling of PHY status
4825 	 */
4826 	bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4827 
4828 	/*
4829 	 * Step 92: configure D0 power state (not required)
4830 	 * Step 93: initialise LED control register ()
4831 	 */
4832 	ledctl = LED_CONTROL_DEFAULT;
4833 	switch (bgep->chipid.device) {
4834 	case DEVICE_ID_5700:
4835 	case DEVICE_ID_5700x:
4836 	case DEVICE_ID_5701:
4837 		/*
4838 		 * Switch to 5700 (MAC) mode on these older chips
4839 		 */
4840 		ledctl &= ~LED_CONTROL_LED_MODE_MASK;
4841 		ledctl |= LED_CONTROL_LED_MODE_5700;
4842 		break;
4843 
4844 	default:
4845 		break;
4846 	}
4847 	bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4848 
4849 	/*
4850 	 * Step 94: activate link
4851 	 */
4852 	bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
4853 
4854 	/*
4855 	 * Step 95: set up physical layer (PHY/SerDes)
4856 	 * restart autoneg (if required)
4857 	 */
4858 	if (reset_phys)
4859 	{
4860 		if (bge_phys_update(bgep) == DDI_FAILURE)
4861 			retval = DDI_FAILURE;
4862 		/* forcing a mac link update here */
4863 		bge_phys_check(bgep);
4864 		bgep->link_state = (bgep->param_link_up) ? LINK_STATE_UP :
4865 		                                           LINK_STATE_DOWN;
4866 		bge_sync_mac_modes(bgep);
4867 		mac_link_update(bgep->mh, bgep->link_state);
4868 	}
4869 
4870 	/*
4871 	 * Extra step (DSG): hand over all the Receive Buffers to the chip
4872 	 */
4873 	for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
4874 		bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
4875 		    bgep->buff[ring].rf_next);
4876 
4877 	/*
4878 	 * MSI bits:The least significant MSI 16-bit word.
4879 	 * ISR will be triggered different.
4880 	 */
4881 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4882 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
4883 
4884 	/*
4885 	 * Extra step (DSG): select which interrupts are enabled
4886 	 *
4887 	 * Program the Ethernet MAC engine to signal attention on
4888 	 * Link Change events, then enable interrupts on MAC, DMA,
4889 	 * and FLOW attention signals.
4890 	 */
4891 	bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
4892 	    ETHERNET_EVENT_LINK_INT |
4893 	    ETHERNET_STATUS_PCS_ERROR_INT);
4894 #ifdef BGE_IPMI_ASF
4895 	if (bgep->asf_enabled) {
4896 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4897 		    MODE_INT_ON_FLOW_ATTN |
4898 		    MODE_INT_ON_DMA_ATTN |
4899 		    MODE_HOST_STACK_UP|
4900 		    MODE_INT_ON_MAC_ATTN);
4901 	} else {
4902 #endif
4903 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4904 		    MODE_INT_ON_FLOW_ATTN |
4905 		    MODE_INT_ON_DMA_ATTN |
4906 		    MODE_INT_ON_MAC_ATTN);
4907 #ifdef BGE_IPMI_ASF
4908 	}
4909 #endif
4910 
4911 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4912 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
4913 		bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717,
4914 		    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
4915 #if 0
4916 		mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);
4917 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
4918 		                 (mhcr | MHCR_TLP_MINOR_ERR_TOLERANCE));
4919 #endif
4920 	}
4921 
4922 	/*
4923 	 * Step 97: enable PCI interrupts!!!
4924 	 */
4925 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
4926 		bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
4927 		    bgep->chipid.mask_pci_int);
4928 
4929 	/*
4930 	 * All done!
4931 	 */
4932 	bgep->bge_chip_state = BGE_CHIP_RUNNING;
4933 	return (retval);
4934 }
4935 
4936 
4937 /*
4938  * ========== Hardware interrupt handler ==========
4939  */
4940 
4941 #undef	BGE_DBG
4942 #define	BGE_DBG		BGE_DBG_INT	/* debug flag for this code	*/
4943 
4944 /*
4945  * Sync the status block, then atomically clear the specified bits in
4946  * the <flags-and-tag> field of the status block.
4947  * the <flags> word of the status block, returning the value of the
4948  * <tag> and the <flags> before the bits were cleared.
4949  */
4950 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
4951 #pragma	inline(bge_status_sync)
4952 
4953 static int
4954 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
4955 {
4956 	bge_status_t *bsp;
4957 	int retval;
4958 
4959 	BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
4960 	    (void *)bgep, bits));
4961 
4962 	ASSERT(bgep->bge_guard == BGE_GUARD);
4963 
4964 	DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
4965 	retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
4966 	if (retval != DDI_FM_OK)
4967 		return (retval);
4968 
4969 	bsp = DMA_VPTR(bgep->status_block);
4970 	*flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
4971 
4972 	BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
4973 	    (void *)bgep, bits, *flags));
4974 
4975 	return (retval);
4976 }
4977 
4978 void bge_wake_factotum(bge_t *bgep);
4979 #pragma	inline(bge_wake_factotum)
4980 
4981 void
4982 bge_wake_factotum(bge_t *bgep)
4983 {
4984 	mutex_enter(bgep->softintrlock);
4985 	if (bgep->factotum_flag == 0) {
4986 		bgep->factotum_flag = 1;
4987 		ddi_trigger_softintr(bgep->factotum_id);
4988 	}
4989 	mutex_exit(bgep->softintrlock);
4990 }
4991 
4992 static void
4993 bge_intr_error_handler(bge_t *bgep)
4994 {
4995 	uint32_t flow;
4996 	uint32_t rdma;
4997 	uint32_t wdma;
4998 	uint32_t tmac;
4999 	uint32_t rmac;
5000 	uint32_t rxrs;
5001 	uint32_t emac;
5002 	uint32_t msis;
5003 	uint32_t txrs = 0;
5004 
5005 	ASSERT(mutex_owned(bgep->genlock));
5006 
5007 	/*
5008 	 * Read all the registers that show the possible
5009 	 * reasons for the ERROR bit to be asserted
5010 	 */
5011 	flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
5012 	rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
5013 	wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
5014 	tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
5015 	rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
5016 	rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
5017 	emac = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG);
5018 	msis = bge_reg_get32(bgep, MSI_STATUS_REG);
5019 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
5020 		txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
5021 
5022 	BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x emac 0x%x msis 0x%x",
5023 	    (void *)bgep, flow, rdma, wdma, emac, msis));
5024 	BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
5025 	    (void *)bgep, tmac, rmac, rxrs, txrs));
5026 
5027 	/*
5028 	 * For now, just clear all the errors ...
5029 	 */
5030 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
5031 		bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
5032 	bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
5033 	bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
5034 	bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
5035 	bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
5036 	bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
5037 }
5038 
5039 /*
5040  *	bge_intr() -- handle chip interrupts
5041  */
5042 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
5043 #pragma	no_inline(bge_intr)
5044 
5045 uint_t
5046 bge_intr(caddr_t arg1, caddr_t arg2)
5047 {
5048 	bge_t *bgep = (void *)arg1;		/* private device info	*/
5049 	bge_status_t *bsp;
5050 	uint64_t flags;
5051 	uint32_t regval;
5052 	uint_t result;
5053 	int retval, loop_cnt = 0;
5054 
5055 	BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
5056 
5057 	/*
5058 	 * GLD v2 checks that s/w setup is complete before passing
5059 	 * interrupts to this routine, thus eliminating the old
5060 	 * (and well-known) race condition around ddi_add_intr()
5061 	 */
5062 	ASSERT(bgep->progress & PROGRESS_HWINT);
5063 
5064 	result = DDI_INTR_UNCLAIMED;
5065 	mutex_enter(bgep->genlock);
5066 
5067 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
5068 		/*
5069 		 * Check whether chip's says it's asserting #INTA;
5070 		 * if not, don't process or claim the interrupt.
5071 		 *
5072 		 * Note that the PCI signal is active low, so the
5073 		 * bit is *zero* when the interrupt is asserted.
5074 		 */
5075 		regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
5076 		if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) ||
5077 		      DEVICE_5725_SERIES_CHIPSETS(bgep)) &&
5078 		    (regval & MLCR_INTA_STATE)) {
5079 			if (bge_check_acc_handle(bgep, bgep->io_handle)
5080 			    != DDI_FM_OK)
5081 				goto chip_stop;
5082 			mutex_exit(bgep->genlock);
5083 			return (result);
5084 		}
5085 
5086 		/*
5087 		 * Block further PCI interrupts ...
5088 		 */
5089 		bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
5090 		    bgep->chipid.mask_pci_int);
5091 
5092 	} else {
5093 		/*
5094 		 * Check MSI status
5095 		 */
5096 		regval = bge_reg_get32(bgep, MSI_STATUS_REG);
5097 		if (regval & MSI_ERROR_ATTENTION) {
5098 			BGE_REPORT((bgep, "msi error attention,"
5099 			    " status=0x%x", regval));
5100 			bge_reg_put32(bgep, MSI_STATUS_REG, regval);
5101 		}
5102 	}
5103 
5104 	result = DDI_INTR_CLAIMED;
5105 
5106 	BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
5107 
5108 	/*
5109 	 * Sync the status block and grab the flags-n-tag from it.
5110 	 * We count the number of interrupts where there doesn't
5111 	 * seem to have been a DMA update of the status block; if
5112 	 * it *has* been updated, the counter will be cleared in
5113 	 * the while() loop below ...
5114 	 */
5115 	bgep->missed_dmas += 1;
5116 	bsp = DMA_VPTR(bgep->status_block);
5117 	for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
5118 		if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
5119 			/*
5120 			 * bge_chip_stop() may have freed dma area etc
5121 			 * while we were in this interrupt handler -
5122 			 * better not call bge_status_sync()
5123 			 */
5124 			(void) bge_check_acc_handle(bgep,
5125 			    bgep->io_handle);
5126 			mutex_exit(bgep->genlock);
5127 			return (DDI_INTR_CLAIMED);
5128 		}
5129 
5130 		retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED |
5131 		    STATUS_FLAG_LINK_CHANGED | STATUS_FLAG_ERROR, &flags);
5132 		if (retval != DDI_FM_OK) {
5133 			bgep->bge_dma_error = B_TRUE;
5134 			goto chip_stop;
5135 		}
5136 
5137 		if (!(flags & STATUS_FLAG_UPDATED))
5138 			break;
5139 
5140 		/*
5141 		 * Tell the chip that we're processing the interrupt
5142 		 */
5143 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
5144 		    INTERRUPT_MBOX_DISABLE(flags));
5145 		if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5146 		    DDI_FM_OK)
5147 			goto chip_stop;
5148 
5149 		if (flags & STATUS_FLAG_LINK_CHANGED) {
5150 			BGE_DEBUG(("bge_intr($%p) ($%p) link event", arg1, arg2));
5151 			if (bge_phys_check(bgep)) {
5152 				bgep->link_state = bgep->param_link_up ?
5153 				    LINK_STATE_UP : LINK_STATE_DOWN;
5154 				bge_sync_mac_modes(bgep);
5155 				mac_link_update(bgep->mh, bgep->link_state);
5156 			}
5157 
5158 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5159 			    DDI_FM_OK)
5160 				goto chip_stop;
5161 		}
5162 
5163 		if (flags & STATUS_FLAG_ERROR) {
5164 			bge_intr_error_handler(bgep);
5165 
5166 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5167 			    DDI_FM_OK)
5168 				goto chip_stop;
5169 		}
5170 
5171 		/*
5172 		 * Drop the mutex while we:
5173 		 * 	Receive any newly-arrived packets
5174 		 *	Recycle any newly-finished send buffers
5175 		 */
5176 		bgep->bge_intr_running = B_TRUE;
5177 		mutex_exit(bgep->genlock);
5178 		bge_receive(bgep, bsp);
5179 		(void) bge_recycle(bgep, bsp);
5180 		mutex_enter(bgep->genlock);
5181 		bgep->bge_intr_running = B_FALSE;
5182 
5183 		/*
5184 		 * Tell the chip we've finished processing, and
5185 		 * give it the tag that we got from the status
5186 		 * block earlier, so that it knows just how far
5187 		 * we've gone.  If it's got more for us to do,
5188 		 * it will now update the status block and try
5189 		 * to assert an interrupt (but we've got the
5190 		 * #INTA blocked at present).  If we see the
5191 		 * update, we'll loop around to do some more.
5192 		 * Eventually we'll get out of here ...
5193 		 */
5194 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
5195 		    INTERRUPT_MBOX_ENABLE(flags));
5196 		if (bgep->chipid.pci_type == BGE_PCI_E)
5197 			(void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
5198 		bgep->missed_dmas = 0;
5199 	}
5200 
5201 	if (bgep->missed_dmas) {
5202 		/*
5203 		 * Probably due to the internal status tag not
5204 		 * being reset.  Force a status block update now;
5205 		 * this should ensure that we get an update and
5206 		 * a new interrupt.  After that, we should be in
5207 		 * sync again ...
5208 		 */
5209 		BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
5210 		    "not updated?", flags));
5211 		bgep->missed_updates++;
5212 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
5213 		    COALESCE_NOW);
5214 
5215 		if (bgep->missed_dmas >= bge_dma_miss_limit) {
5216 			/*
5217 			 * If this happens multiple times in a row,
5218 			 * it means DMA is just not working.  Maybe
5219 			 * the chip's failed, or maybe there's a
5220 			 * problem on the PCI bus or in the host-PCI
5221 			 * bridge (Tomatillo).
5222 			 *
5223 			 * At all events, we want to stop further
5224 			 * interrupts and let the recovery code take
5225 			 * over to see whether anything can be done
5226 			 * about it ...
5227 			 */
5228 			bge_fm_ereport(bgep,
5229 			    DDI_FM_DEVICE_BADINT_LIMIT);
5230 			goto chip_stop;
5231 		}
5232 	}
5233 
5234 	/*
5235 	 * Reenable assertion of #INTA, unless there's a DMA fault
5236 	 */
5237 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
5238 		bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
5239 		    bgep->chipid.mask_pci_int);
5240 		if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
5241 		    DDI_FM_OK)
5242 			goto chip_stop;
5243 	}
5244 
5245 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5246 		goto chip_stop;
5247 
5248 	mutex_exit(bgep->genlock);
5249 	return (result);
5250 
5251 chip_stop:
5252 
5253 #ifdef BGE_IPMI_ASF
5254 	if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
5255 		/*
5256 		 * We must stop ASF heart beat before
5257 		 * bge_chip_stop(), otherwise some
5258 		 * computers (ex. IBM HS20 blade
5259 		 * server) may crash.
5260 		 */
5261 		bge_asf_update_status(bgep);
5262 		bge_asf_stop_timer(bgep);
5263 		bgep->asf_status = ASF_STAT_STOP;
5264 
5265 		bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
5266 		(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
5267 	}
5268 #endif
5269 	bge_chip_stop(bgep, B_TRUE);
5270 	(void) bge_check_acc_handle(bgep, bgep->io_handle);
5271 	mutex_exit(bgep->genlock);
5272 	return (result);
5273 }
5274 
5275 /*
5276  * ========== Factotum, implemented as a softint handler ==========
5277  */
5278 
5279 #undef	BGE_DBG
5280 #define	BGE_DBG		BGE_DBG_FACT	/* debug flag for this code	*/
5281 
5282 /*
5283  * Factotum routine to check for Tx stall, using the 'watchdog' counter
5284  */
5285 static boolean_t bge_factotum_stall_check(bge_t *bgep);
5286 #pragma	no_inline(bge_factotum_stall_check)
5287 
5288 static boolean_t
5289 bge_factotum_stall_check(bge_t *bgep)
5290 {
5291 	uint32_t dogval;
5292 	bge_status_t *bsp;
5293 	uint64_t now = gethrtime();
5294 
5295 	if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD)
5296 		return (B_FALSE);
5297 
5298 	bgep->timestamp = now;
5299 
5300 	ASSERT(mutex_owned(bgep->genlock));
5301 
5302 	/*
5303 	 * Specific check for Tx stall ...
5304 	 *
5305 	 * The 'watchdog' counter is incremented whenever a packet
5306 	 * is queued, reset to 1 when some (but not all) buffers
5307 	 * are reclaimed, reset to 0 (disabled) when all buffers
5308 	 * are reclaimed, and shifted left here.  If it exceeds the
5309 	 * threshold value, the chip is assumed to have stalled and
5310 	 * is put into the ERROR state.  The factotum will then reset
5311 	 * it on the next pass.
5312 	 *
5313 	 * All of which should ensure that we don't get into a state
5314 	 * where packets are left pending indefinitely!
5315 	 */
5316 	dogval = bge_atomic_shl32(&bgep->watchdog, 1);
5317 	bsp = DMA_VPTR(bgep->status_block);
5318 	if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp))
5319 		return (B_FALSE);
5320 
5321 #if !defined(BGE_NETCONSOLE)
5322 	BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
5323 #endif
5324 	bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
5325 	return (B_TRUE);
5326 }
5327 
5328 /*
5329  * The factotum is woken up when there's something to do that we'd rather
5330  * not do from inside a hardware interrupt handler or high-level cyclic.
5331  * Its main task is to reset & restart the chip after an error.
5332  */
5333 uint_t bge_chip_factotum(caddr_t arg);
5334 #pragma	no_inline(bge_chip_factotum)
5335 
5336 uint_t
5337 bge_chip_factotum(caddr_t arg)
5338 {
5339 	bge_t *bgep;
5340 	uint_t result;
5341 	boolean_t error;
5342 	int dma_state;
5343 
5344 	bgep = (void *)arg;
5345 
5346 	BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
5347 
5348 	mutex_enter(bgep->softintrlock);
5349 	if (bgep->factotum_flag == 0) {
5350 		mutex_exit(bgep->softintrlock);
5351 		return (DDI_INTR_UNCLAIMED);
5352 	}
5353 	bgep->factotum_flag = 0;
5354 	mutex_exit(bgep->softintrlock);
5355 
5356 	result = DDI_INTR_CLAIMED;
5357 	error = B_FALSE;
5358 
5359 	mutex_enter(bgep->genlock);
5360 	switch (bgep->bge_chip_state) {
5361 	default:
5362 		break;
5363 
5364 	case BGE_CHIP_RUNNING:
5365 
5366 		if (bgep->chipid.device == DEVICE_ID_5700) {
5367 			if (bge_phys_check(bgep)) {
5368 				bgep->link_state = (bgep->param_link_up) ?
5369 				    LINK_STATE_UP : LINK_STATE_DOWN;
5370 				bge_sync_mac_modes(bgep);
5371 				mac_link_update(bgep->mh, bgep->link_state);
5372 			}
5373 		}
5374 
5375 		error = bge_factotum_stall_check(bgep);
5376 		if (dma_state != DDI_FM_OK) {
5377 			bgep->bge_dma_error = B_TRUE;
5378 			error = B_TRUE;
5379 		}
5380 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5381 			error = B_TRUE;
5382 		if (error)
5383 			bgep->bge_chip_state = BGE_CHIP_ERROR;
5384 		break;
5385 
5386 	case BGE_CHIP_ERROR:
5387 		error = B_TRUE;
5388 		break;
5389 
5390 	case BGE_CHIP_FAULT:
5391 		/*
5392 		 * Fault detected, time to reset ...
5393 		 */
5394 		if (bge_autorecover) {
5395 			if (!(bgep->progress & PROGRESS_BUFS)) {
5396 				/*
5397 				 * if we can't allocate the ring buffers,
5398 				 * try later
5399 				 */
5400 				if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
5401 					mutex_exit(bgep->genlock);
5402 					return (result);
5403 				}
5404 				bgep->progress |= PROGRESS_BUFS;
5405 			}
5406 			if (!(bgep->progress & PROGRESS_INTR)) {
5407 				bge_init_rings(bgep);
5408 				bge_intr_enable(bgep);
5409 				bgep->progress |= PROGRESS_INTR;
5410 			}
5411 			if (!(bgep->progress & PROGRESS_KSTATS)) {
5412 				bge_init_kstats(bgep,
5413 				    ddi_get_instance(bgep->devinfo));
5414 				bgep->progress |= PROGRESS_KSTATS;
5415 			}
5416 
5417 			BGE_REPORT((bgep, "automatic recovery activated"));
5418 
5419 			if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
5420 				bgep->bge_chip_state = BGE_CHIP_ERROR;
5421 				error = B_TRUE;
5422 			}
5423 			if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
5424 			    DDI_FM_OK) {
5425 				bgep->bge_chip_state = BGE_CHIP_ERROR;
5426 				error = B_TRUE;
5427 			}
5428 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5429 			    DDI_FM_OK) {
5430 				bgep->bge_chip_state = BGE_CHIP_ERROR;
5431 				error = B_TRUE;
5432 			}
5433 			if (error == B_FALSE) {
5434 #ifdef BGE_IPMI_ASF
5435 				if (bgep->asf_enabled &&
5436 				    bgep->asf_status != ASF_STAT_RUN) {
5437 					bgep->asf_timeout_id = timeout(
5438 					    bge_asf_heartbeat, (void *)bgep,
5439 					    drv_usectohz(
5440 					    BGE_ASF_HEARTBEAT_INTERVAL));
5441 					bgep->asf_status = ASF_STAT_RUN;
5442 				}
5443 #endif
5444 				if (!bgep->manual_reset) {
5445 					ddi_fm_service_impact(bgep->devinfo,
5446 					    DDI_SERVICE_RESTORED);
5447 				}
5448 			}
5449 		}
5450 		break;
5451 	}
5452 
5453 	/*
5454 	 * If an error is detected, stop the chip now, marking it as
5455 	 * faulty, so that it will be reset next time through ...
5456 	 *
5457 	 * Note that if intr_running is set, then bge_intr() has dropped
5458 	 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
5459 	 * this point so have to wait until the next time the factotum runs.
5460 	 */
5461 	if (error && !bgep->bge_intr_running) {
5462 #ifdef BGE_IPMI_ASF
5463 		if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
5464 			/*
5465 			 * We must stop ASF heart beat before bge_chip_stop(),
5466 			 * otherwise some computers (ex. IBM HS20 blade server)
5467 			 * may crash.
5468 			 */
5469 			bge_asf_update_status(bgep);
5470 			bge_asf_stop_timer(bgep);
5471 			bgep->asf_status = ASF_STAT_STOP;
5472 
5473 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
5474 			(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
5475 		}
5476 #endif
5477 		bge_chip_stop(bgep, B_TRUE);
5478 		(void) bge_check_acc_handle(bgep, bgep->io_handle);
5479 	}
5480 	mutex_exit(bgep->genlock);
5481 
5482 	return (result);
5483 }
5484 
5485 /*
5486  * High-level cyclic handler
5487  *
5488  * This routine schedules a (low-level) softint callback to the
5489  * factotum, and prods the chip to update the status block (which
5490  * will cause a hardware interrupt when complete).
5491  */
5492 void bge_chip_cyclic(void *arg);
5493 #pragma	no_inline(bge_chip_cyclic)
5494 
5495 void
5496 bge_chip_cyclic(void *arg)
5497 {
5498 	bge_t *bgep;
5499 	uint32_t regval;
5500 
5501 	bgep = arg;
5502 
5503 	switch (bgep->bge_chip_state) {
5504 	default:
5505 		return;
5506 
5507 	case BGE_CHIP_RUNNING:
5508 
5509 		/* XXX I really don't like this forced interrupt... */
5510 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
5511 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5512 			ddi_fm_service_impact(bgep->devinfo,
5513 			    DDI_SERVICE_UNAFFECTED);
5514 
5515 		break;
5516 
5517 	case BGE_CHIP_FAULT:
5518 	case BGE_CHIP_ERROR:
5519 
5520 		break;
5521 	}
5522 
5523 	mutex_enter(bgep->genlock);
5524 
5525 	if (bgep->eee_lpi_wait && !--bgep->eee_lpi_wait) {
5526 		BGE_DEBUG(("eee cyclic, lpi enabled"));
5527 		bge_eee_enable(bgep);
5528 	}
5529 
5530 	if (bgep->rdma_length_bug_on_5719) {
5531 		if ((bge_reg_get32(bgep, STAT_IFHCOUT_UPKGS_REG) +
5532 		     bge_reg_get32(bgep, STAT_IFHCOUT_MPKGS_REG) +
5533 		     bge_reg_get32(bgep, STAT_IFHCOUT_BPKGS_REG)) >
5534 		    BGE_NUM_RDMA_CHANNELS) {
5535 			regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG);
5536 			regval &= ~RDMA_CORR_CTRL_TX_LENGTH_WA;
5537 			bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval);
5538 			bgep->rdma_length_bug_on_5719 = B_FALSE;
5539 		}
5540 	}
5541 
5542 	mutex_exit(bgep->genlock);
5543 
5544 	bge_wake_factotum(bgep);
5545 
5546 }
5547 
5548 
5549 /*
5550  * ========== Ioctl subfunctions ==========
5551  */
5552 
5553 #undef	BGE_DBG
5554 #define	BGE_DBG		BGE_DBG_PPIO	/* debug flag for this code	*/
5555 
5556 #if	BGE_DEBUGGING || BGE_DO_PPIO
5557 
5558 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
5559 #pragma	no_inline(bge_chip_peek_cfg)
5560 
5561 static void
5562 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
5563 {
5564 	uint64_t regval;
5565 	uint64_t regno;
5566 
5567 	BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
5568 	    (void *)bgep, (void *)ppd));
5569 
5570 	regno = ppd->pp_acc_offset;
5571 
5572 	switch (ppd->pp_acc_size) {
5573 	case 1:
5574 		regval = pci_config_get8(bgep->cfg_handle, regno);
5575 		break;
5576 
5577 	case 2:
5578 		regval = pci_config_get16(bgep->cfg_handle, regno);
5579 		break;
5580 
5581 	case 4:
5582 		regval = pci_config_get32(bgep->cfg_handle, regno);
5583 		break;
5584 
5585 	case 8:
5586 		regval = pci_config_get64(bgep->cfg_handle, regno);
5587 		break;
5588 	}
5589 
5590 	ppd->pp_acc_data = regval;
5591 }
5592 
5593 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
5594 #pragma	no_inline(bge_chip_poke_cfg)
5595 
5596 static void
5597 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
5598 {
5599 	uint64_t regval;
5600 	uint64_t regno;
5601 
5602 	BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
5603 	    (void *)bgep, (void *)ppd));
5604 
5605 	regno = ppd->pp_acc_offset;
5606 	regval = ppd->pp_acc_data;
5607 
5608 	switch (ppd->pp_acc_size) {
5609 	case 1:
5610 		pci_config_put8(bgep->cfg_handle, regno, regval);
5611 		break;
5612 
5613 	case 2:
5614 		pci_config_put16(bgep->cfg_handle, regno, regval);
5615 		break;
5616 
5617 	case 4:
5618 		pci_config_put32(bgep->cfg_handle, regno, regval);
5619 		break;
5620 
5621 	case 8:
5622 		pci_config_put64(bgep->cfg_handle, regno, regval);
5623 		break;
5624 	}
5625 }
5626 
5627 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5628 #pragma	no_inline(bge_chip_peek_reg)
5629 
5630 static void
5631 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5632 {
5633 	uint64_t regval;
5634 	void *regaddr;
5635 
5636 	BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
5637 	    (void *)bgep, (void *)ppd));
5638 
5639 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5640 
5641 	switch (ppd->pp_acc_size) {
5642 	case 1:
5643 		regval = ddi_get8(bgep->io_handle, regaddr);
5644 		break;
5645 
5646 	case 2:
5647 		regval = ddi_get16(bgep->io_handle, regaddr);
5648 		break;
5649 
5650 	case 4:
5651 		regval = ddi_get32(bgep->io_handle, regaddr);
5652 		break;
5653 
5654 	case 8:
5655 		regval = ddi_get64(bgep->io_handle, regaddr);
5656 		break;
5657 	}
5658 
5659 	ppd->pp_acc_data = regval;
5660 }
5661 
5662 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5663 #pragma	no_inline(bge_chip_peek_reg)
5664 
5665 static void
5666 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5667 {
5668 	uint64_t regval;
5669 	void *regaddr;
5670 
5671 	BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
5672 	    (void *)bgep, (void *)ppd));
5673 
5674 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5675 	regval = ppd->pp_acc_data;
5676 
5677 	switch (ppd->pp_acc_size) {
5678 	case 1:
5679 		ddi_put8(bgep->io_handle, regaddr, regval);
5680 		break;
5681 
5682 	case 2:
5683 		ddi_put16(bgep->io_handle, regaddr, regval);
5684 		break;
5685 
5686 	case 4:
5687 		ddi_put32(bgep->io_handle, regaddr, regval);
5688 		break;
5689 
5690 	case 8:
5691 		ddi_put64(bgep->io_handle, regaddr, regval);
5692 		break;
5693 	}
5694 	BGE_PCICHK(bgep);
5695 }
5696 
5697 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5698 #pragma	no_inline(bge_chip_peek_nic)
5699 
5700 static void
5701 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5702 {
5703 	uint64_t regoff;
5704 	uint64_t regval;
5705 	void *regaddr;
5706 
5707 	BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
5708 	    (void *)bgep, (void *)ppd));
5709 
5710 	regoff = ppd->pp_acc_offset;
5711 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5712 	regoff &= MWBAR_GRANULE_MASK;
5713 	regoff += NIC_MEM_WINDOW_OFFSET;
5714 	regaddr = PIO_ADDR(bgep, regoff);
5715 
5716 	switch (ppd->pp_acc_size) {
5717 	case 1:
5718 		regval = ddi_get8(bgep->io_handle, regaddr);
5719 		break;
5720 
5721 	case 2:
5722 		regval = ddi_get16(bgep->io_handle, regaddr);
5723 		break;
5724 
5725 	case 4:
5726 		regval = ddi_get32(bgep->io_handle, regaddr);
5727 		break;
5728 
5729 	case 8:
5730 		regval = ddi_get64(bgep->io_handle, regaddr);
5731 		break;
5732 	}
5733 
5734 	ppd->pp_acc_data = regval;
5735 }
5736 
5737 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5738 #pragma	no_inline(bge_chip_poke_nic)
5739 
5740 static void
5741 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5742 {
5743 	uint64_t regoff;
5744 	uint64_t regval;
5745 	void *regaddr;
5746 
5747 	BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
5748 	    (void *)bgep, (void *)ppd));
5749 
5750 	regoff = ppd->pp_acc_offset;
5751 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5752 	regoff &= MWBAR_GRANULE_MASK;
5753 	regoff += NIC_MEM_WINDOW_OFFSET;
5754 	regaddr = PIO_ADDR(bgep, regoff);
5755 	regval = ppd->pp_acc_data;
5756 
5757 	switch (ppd->pp_acc_size) {
5758 	case 1:
5759 		ddi_put8(bgep->io_handle, regaddr, regval);
5760 		break;
5761 
5762 	case 2:
5763 		ddi_put16(bgep->io_handle, regaddr, regval);
5764 		break;
5765 
5766 	case 4:
5767 		ddi_put32(bgep->io_handle, regaddr, regval);
5768 		break;
5769 
5770 	case 8:
5771 		ddi_put64(bgep->io_handle, regaddr, regval);
5772 		break;
5773 	}
5774 	BGE_PCICHK(bgep);
5775 }
5776 
5777 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5778 #pragma	no_inline(bge_chip_peek_mii)
5779 
5780 static void
5781 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5782 {
5783 	BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
5784 	    (void *)bgep, (void *)ppd));
5785 
5786 	ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
5787 }
5788 
5789 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5790 #pragma	no_inline(bge_chip_poke_mii)
5791 
5792 static void
5793 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5794 {
5795 	BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
5796 	    (void *)bgep, (void *)ppd));
5797 
5798 	bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
5799 }
5800 
5801 #if	BGE_SEE_IO32
5802 
5803 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5804 #pragma	no_inline(bge_chip_peek_seeprom)
5805 
5806 static void
5807 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5808 {
5809 	uint32_t data;
5810 	int err;
5811 
5812 	BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
5813 	    (void *)bgep, (void *)ppd));
5814 
5815 	err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
5816 	ppd->pp_acc_data = err ? ~0ull : data;
5817 }
5818 
5819 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5820 #pragma	no_inline(bge_chip_poke_seeprom)
5821 
5822 static void
5823 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5824 {
5825 	uint32_t data;
5826 
5827 	BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
5828 	    (void *)bgep, (void *)ppd));
5829 
5830 	data = ppd->pp_acc_data;
5831 	(void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
5832 }
5833 #endif	/* BGE_SEE_IO32 */
5834 
5835 #if	BGE_FLASH_IO32
5836 
5837 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5838 #pragma	no_inline(bge_chip_peek_flash)
5839 
5840 static void
5841 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5842 {
5843 	uint32_t data;
5844 	int err;
5845 
5846 	BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
5847 	    (void *)bgep, (void *)ppd));
5848 
5849 	err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
5850 	ppd->pp_acc_data = err ? ~0ull : data;
5851 }
5852 
5853 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5854 #pragma	no_inline(bge_chip_poke_flash)
5855 
5856 static void
5857 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5858 {
5859 	uint32_t data;
5860 
5861 	BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
5862 	    (void *)bgep, (void *)ppd));
5863 
5864 	data = ppd->pp_acc_data;
5865 	(void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
5866 	    ppd->pp_acc_offset, &data);
5867 }
5868 #endif	/* BGE_FLASH_IO32 */
5869 
5870 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5871 #pragma	no_inline(bge_chip_peek_mem)
5872 
5873 static void
5874 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5875 {
5876 	uint64_t regval;
5877 	void *vaddr;
5878 
5879 	BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
5880 	    (void *)bgep, (void *)ppd));
5881 
5882 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5883 
5884 	switch (ppd->pp_acc_size) {
5885 	case 1:
5886 		regval = *(uint8_t *)vaddr;
5887 		break;
5888 
5889 	case 2:
5890 		regval = *(uint16_t *)vaddr;
5891 		break;
5892 
5893 	case 4:
5894 		regval = *(uint32_t *)vaddr;
5895 		break;
5896 
5897 	case 8:
5898 		regval = *(uint64_t *)vaddr;
5899 		break;
5900 	}
5901 
5902 	BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
5903 	    (void *)bgep, (void *)ppd, regval, vaddr));
5904 
5905 	ppd->pp_acc_data = regval;
5906 }
5907 
5908 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5909 #pragma	no_inline(bge_chip_poke_mem)
5910 
5911 static void
5912 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5913 {
5914 	uint64_t regval;
5915 	void *vaddr;
5916 
5917 	BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
5918 	    (void *)bgep, (void *)ppd));
5919 
5920 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5921 	regval = ppd->pp_acc_data;
5922 
5923 	BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
5924 	    (void *)bgep, (void *)ppd, regval, vaddr));
5925 
5926 	switch (ppd->pp_acc_size) {
5927 	case 1:
5928 		*(uint8_t *)vaddr = (uint8_t)regval;
5929 		break;
5930 
5931 	case 2:
5932 		*(uint16_t *)vaddr = (uint16_t)regval;
5933 		break;
5934 
5935 	case 4:
5936 		*(uint32_t *)vaddr = (uint32_t)regval;
5937 		break;
5938 
5939 	case 8:
5940 		*(uint64_t *)vaddr = (uint64_t)regval;
5941 		break;
5942 	}
5943 }
5944 
5945 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5946 					struct iocblk *iocp);
5947 #pragma	no_inline(bge_pp_ioctl)
5948 
5949 static enum ioc_reply
5950 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5951 {
5952 	void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
5953 	bge_peekpoke_t *ppd;
5954 	dma_area_t *areap;
5955 	uint64_t sizemask;
5956 	uint64_t mem_va;
5957 	uint64_t maxoff;
5958 	boolean_t peek;
5959 
5960 	switch (cmd) {
5961 	default:
5962 		/* NOTREACHED */
5963 		bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
5964 		return (IOC_INVAL);
5965 
5966 	case BGE_PEEK:
5967 		peek = B_TRUE;
5968 		break;
5969 
5970 	case BGE_POKE:
5971 		peek = B_FALSE;
5972 		break;
5973 	}
5974 
5975 	/*
5976 	 * Validate format of ioctl
5977 	 */
5978 	if (iocp->ioc_count != sizeof (bge_peekpoke_t))
5979 		return (IOC_INVAL);
5980 	if (mp->b_cont == NULL)
5981 		return (IOC_INVAL);
5982 	ppd = (void *)mp->b_cont->b_rptr;
5983 
5984 	/*
5985 	 * Validate request parameters
5986 	 */
5987 	switch (ppd->pp_acc_space) {
5988 	default:
5989 		return (IOC_INVAL);
5990 
5991 	case BGE_PP_SPACE_CFG:
5992 		/*
5993 		 * Config space
5994 		 */
5995 		sizemask = 8|4|2|1;
5996 		mem_va = 0;
5997 		maxoff = PCI_CONF_HDR_SIZE;
5998 		ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
5999 		break;
6000 
6001 	case BGE_PP_SPACE_REG:
6002 		/*
6003 		 * Memory-mapped I/O space
6004 		 */
6005 		sizemask = 8|4|2|1;
6006 		mem_va = 0;
6007 		maxoff = RIAAR_REGISTER_MAX;
6008 		ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
6009 		break;
6010 
6011 	case BGE_PP_SPACE_NIC:
6012 		/*
6013 		 * NIC on-chip memory
6014 		 */
6015 		sizemask = 8|4|2|1;
6016 		mem_va = 0;
6017 		maxoff = MWBAR_ONCHIP_MAX;
6018 		ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
6019 		break;
6020 
6021 	case BGE_PP_SPACE_MII:
6022 		/*
6023 		 * PHY's MII registers
6024 		 * NB: all PHY registers are two bytes, but the
6025 		 * addresses increment in ones (word addressing).
6026 		 * So we scale the address here, then undo the
6027 		 * transformation inside the peek/poke functions.
6028 		 */
6029 		ppd->pp_acc_offset *= 2;
6030 		sizemask = 2;
6031 		mem_va = 0;
6032 		maxoff = (MII_MAXREG+1)*2;
6033 		ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
6034 		break;
6035 
6036 #if	BGE_SEE_IO32
6037 	case BGE_PP_SPACE_SEEPROM:
6038 		/*
6039 		 * Attached SEEPROM(s), if any.
6040 		 * NB: we use the high-order bits of the 'address' as
6041 		 * a device select to accommodate multiple SEEPROMS,
6042 		 * If each one is the maximum size (64kbytes), this
6043 		 * makes them appear contiguous.  Otherwise, there may
6044 		 * be holes in the mapping.  ENxS doesn't have any
6045 		 * SEEPROMs anyway ...
6046 		 */
6047 		sizemask = 4;
6048 		mem_va = 0;
6049 		maxoff = SEEPROM_DEV_AND_ADDR_MASK;
6050 		ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
6051 		break;
6052 #endif	/* BGE_SEE_IO32 */
6053 
6054 #if	BGE_FLASH_IO32
6055 	case BGE_PP_SPACE_FLASH:
6056 		/*
6057 		 * Attached Flash device (if any); a maximum of one device
6058 		 * is currently supported.  But it can be up to 1MB (unlike
6059 		 * the 64k limit on SEEPROMs) so why would you need more ;-)
6060 		 */
6061 		sizemask = 4;
6062 		mem_va = 0;
6063 		maxoff = NVM_FLASH_ADDR_MASK;
6064 		ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
6065 		break;
6066 #endif	/* BGE_FLASH_IO32 */
6067 
6068 	case BGE_PP_SPACE_BGE:
6069 		/*
6070 		 * BGE data structure!
6071 		 */
6072 		sizemask = 8|4|2|1;
6073 		mem_va = (uintptr_t)bgep;
6074 		maxoff = sizeof (*bgep);
6075 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
6076 		break;
6077 
6078 	case BGE_PP_SPACE_STATUS:
6079 	case BGE_PP_SPACE_STATISTICS:
6080 	case BGE_PP_SPACE_TXDESC:
6081 	case BGE_PP_SPACE_TXBUFF:
6082 	case BGE_PP_SPACE_RXDESC:
6083 	case BGE_PP_SPACE_RXBUFF:
6084 		/*
6085 		 * Various DMA_AREAs
6086 		 */
6087 		switch (ppd->pp_acc_space) {
6088 		case BGE_PP_SPACE_TXDESC:
6089 			areap = &bgep->tx_desc;
6090 			break;
6091 		case BGE_PP_SPACE_TXBUFF:
6092 			areap = &bgep->tx_buff[0];
6093 			break;
6094 		case BGE_PP_SPACE_RXDESC:
6095 			areap = &bgep->rx_desc[0];
6096 			break;
6097 		case BGE_PP_SPACE_RXBUFF:
6098 			areap = &bgep->rx_buff[0];
6099 			break;
6100 		case BGE_PP_SPACE_STATUS:
6101 			areap = &bgep->status_block;
6102 			break;
6103 		case BGE_PP_SPACE_STATISTICS:
6104 			if (bgep->chipid.statistic_type == BGE_STAT_BLK)
6105 				areap = &bgep->statistics;
6106 			break;
6107 		}
6108 
6109 		sizemask = 8|4|2|1;
6110 		mem_va = (uintptr_t)areap->mem_va;
6111 		maxoff = areap->alength;
6112 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
6113 		break;
6114 	}
6115 
6116 	switch (ppd->pp_acc_size) {
6117 	default:
6118 		return (IOC_INVAL);
6119 
6120 	case 8:
6121 	case 4:
6122 	case 2:
6123 	case 1:
6124 		if ((ppd->pp_acc_size & sizemask) == 0)
6125 			return (IOC_INVAL);
6126 		break;
6127 	}
6128 
6129 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
6130 		return (IOC_INVAL);
6131 
6132 	if (ppd->pp_acc_offset >= maxoff)
6133 		return (IOC_INVAL);
6134 
6135 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
6136 		return (IOC_INVAL);
6137 
6138 	/*
6139 	 * All OK - go do it!
6140 	 */
6141 	ppd->pp_acc_offset += mem_va;
6142 	(*ppfn)(bgep, ppd);
6143 	return (peek ? IOC_REPLY : IOC_ACK);
6144 }
6145 
6146 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
6147 					struct iocblk *iocp);
6148 #pragma	no_inline(bge_diag_ioctl)
6149 
6150 static enum ioc_reply
6151 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
6152 {
6153 	ASSERT(mutex_owned(bgep->genlock));
6154 
6155 	switch (cmd) {
6156 	default:
6157 		/* NOTREACHED */
6158 		bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
6159 		return (IOC_INVAL);
6160 
6161 	case BGE_DIAG:
6162 		/*
6163 		 * Currently a no-op
6164 		 */
6165 		return (IOC_ACK);
6166 
6167 	case BGE_PEEK:
6168 	case BGE_POKE:
6169 		return (bge_pp_ioctl(bgep, cmd, mp, iocp));
6170 
6171 	case BGE_PHY_RESET:
6172 		return (IOC_RESTART_ACK);
6173 
6174 	case BGE_SOFT_RESET:
6175 	case BGE_HARD_RESET:
6176 		/*
6177 		 * Reset and reinitialise the 570x hardware
6178 		 */
6179 		bgep->bge_chip_state = BGE_CHIP_FAULT;
6180 		ddi_trigger_softintr(bgep->factotum_id);
6181 		(void) bge_restart(bgep, cmd == BGE_HARD_RESET);
6182 		return (IOC_ACK);
6183 	}
6184 
6185 	/* NOTREACHED */
6186 }
6187 
6188 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
6189 
6190 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
6191 				    struct iocblk *iocp);
6192 #pragma	no_inline(bge_mii_ioctl)
6193 
6194 static enum ioc_reply
6195 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
6196 {
6197 	struct bge_mii_rw *miirwp;
6198 
6199 	/*
6200 	 * Validate format of ioctl
6201 	 */
6202 	if (iocp->ioc_count != sizeof (struct bge_mii_rw))
6203 		return (IOC_INVAL);
6204 	if (mp->b_cont == NULL)
6205 		return (IOC_INVAL);
6206 	miirwp = (void *)mp->b_cont->b_rptr;
6207 
6208 	/*
6209 	 * Validate request parameters ...
6210 	 */
6211 	if (miirwp->mii_reg > MII_MAXREG)
6212 		return (IOC_INVAL);
6213 
6214 	switch (cmd) {
6215 	default:
6216 		/* NOTREACHED */
6217 		bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
6218 		return (IOC_INVAL);
6219 
6220 	case BGE_MII_READ:
6221 		miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
6222 		return (IOC_REPLY);
6223 
6224 	case BGE_MII_WRITE:
6225 		bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
6226 		return (IOC_ACK);
6227 	}
6228 
6229 	/* NOTREACHED */
6230 }
6231 
6232 #if	BGE_SEE_IO32
6233 
6234 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
6235 				    struct iocblk *iocp);
6236 #pragma	no_inline(bge_see_ioctl)
6237 
6238 static enum ioc_reply
6239 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
6240 {
6241 	struct bge_see_rw *seerwp;
6242 
6243 	/*
6244 	 * Validate format of ioctl
6245 	 */
6246 	if (iocp->ioc_count != sizeof (struct bge_see_rw))
6247 		return (IOC_INVAL);
6248 	if (mp->b_cont == NULL)
6249 		return (IOC_INVAL);
6250 	seerwp = (void *)mp->b_cont->b_rptr;
6251 
6252 	/*
6253 	 * Validate request parameters ...
6254 	 */
6255 	if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
6256 		return (IOC_INVAL);
6257 
6258 	switch (cmd) {
6259 	default:
6260 		/* NOTREACHED */
6261 		bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
6262 		return (IOC_INVAL);
6263 
6264 	case BGE_SEE_READ:
6265 	case BGE_SEE_WRITE:
6266 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
6267 		    seerwp->see_addr, &seerwp->see_data);
6268 		return (IOC_REPLY);
6269 	}
6270 
6271 	/* NOTREACHED */
6272 }
6273 
6274 #endif	/* BGE_SEE_IO32 */
6275 
6276 #if	BGE_FLASH_IO32
6277 
6278 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
6279 				    struct iocblk *iocp);
6280 #pragma	no_inline(bge_flash_ioctl)
6281 
6282 static enum ioc_reply
6283 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
6284 {
6285 	struct bge_flash_rw *flashrwp;
6286 
6287 	/*
6288 	 * Validate format of ioctl
6289 	 */
6290 	if (iocp->ioc_count != sizeof (struct bge_flash_rw))
6291 		return (IOC_INVAL);
6292 	if (mp->b_cont == NULL)
6293 		return (IOC_INVAL);
6294 	flashrwp = (void *)mp->b_cont->b_rptr;
6295 
6296 	/*
6297 	 * Validate request parameters ...
6298 	 */
6299 	if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
6300 		return (IOC_INVAL);
6301 
6302 	switch (cmd) {
6303 	default:
6304 		/* NOTREACHED */
6305 		bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
6306 		return (IOC_INVAL);
6307 
6308 	case BGE_FLASH_READ:
6309 	case BGE_FLASH_WRITE:
6310 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
6311 		    flashrwp->flash_addr, &flashrwp->flash_data);
6312 		return (IOC_REPLY);
6313 	}
6314 
6315 	/* NOTREACHED */
6316 }
6317 
6318 #endif	/* BGE_FLASH_IO32 */
6319 
6320 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
6321 				struct iocblk *iocp);
6322 #pragma	no_inline(bge_chip_ioctl)
6323 
6324 enum ioc_reply
6325 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
6326 {
6327 	int cmd;
6328 
6329 	BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
6330 	    (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
6331 
6332 	ASSERT(mutex_owned(bgep->genlock));
6333 
6334 	cmd = iocp->ioc_cmd;
6335 	switch (cmd) {
6336 	default:
6337 		/* NOTREACHED */
6338 		bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
6339 		return (IOC_INVAL);
6340 
6341 	case BGE_DIAG:
6342 	case BGE_PEEK:
6343 	case BGE_POKE:
6344 	case BGE_PHY_RESET:
6345 	case BGE_SOFT_RESET:
6346 	case BGE_HARD_RESET:
6347 #if	BGE_DEBUGGING || BGE_DO_PPIO
6348 		return (bge_diag_ioctl(bgep, cmd, mp, iocp));
6349 #else
6350 		return (IOC_INVAL);
6351 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
6352 
6353 	case BGE_MII_READ:
6354 	case BGE_MII_WRITE:
6355 		return (bge_mii_ioctl(bgep, cmd, mp, iocp));
6356 
6357 #if	BGE_SEE_IO32
6358 	case BGE_SEE_READ:
6359 	case BGE_SEE_WRITE:
6360 		return (bge_see_ioctl(bgep, cmd, mp, iocp));
6361 #endif	/* BGE_SEE_IO32 */
6362 
6363 #if	BGE_FLASH_IO32
6364 	case BGE_FLASH_READ:
6365 	case BGE_FLASH_WRITE:
6366 		return (bge_flash_ioctl(bgep, cmd, mp, iocp));
6367 #endif	/* BGE_FLASH_IO32 */
6368 	}
6369 
6370 	/* NOTREACHED */
6371 }
6372 
6373 /* ARGSUSED */
6374 void
6375 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag)
6376 {
6377 	recv_ring_t *rrp = arg;
6378 	bge_t *bgep = rrp->bgep;
6379 
6380 	mutex_enter(bgep->genlock);
6381 	rrp->poll_flag = flag;
6382 #ifdef NOT_YET
6383 	/*
6384 	 * XXX-Sunay: Since most broadcom cards support only one
6385 	 * interrupt but multiple rx rings, we can't disable the
6386 	 * physical interrupt. This need to be done via capability
6387 	 * negotiation depending on the NIC.
6388 	 */
6389 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
6390 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
6391 #endif
6392 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
6393 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
6394 	mutex_exit(bgep->genlock);
6395 }
6396 
6397 #ifdef BGE_IPMI_ASF
6398 
6399 uint32_t
6400 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
6401 {
6402 	uint32_t data;
6403 
6404 #ifndef __sparc
6405 	if (!bgep->asf_wordswapped) {
6406 		/* a workaround word swap error */
6407 		if (addr & 4)
6408 			addr = addr - 4;
6409 		else
6410 			addr = addr + 4;
6411 	}
6412 #else
6413 	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
6414 	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
6415 		addr = LE_32(addr);
6416 	}
6417 #endif
6418 
6419 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
6420 	data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
6421 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
6422 
6423 	data = LE_32(data);
6424 
6425 	BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x",
6426 	    (void *)bgep, addr, data));
6427 
6428 	return (data);
6429 }
6430 
6431 void
6432 bge_asf_update_status(bge_t *bgep)
6433 {
6434 	uint32_t event;
6435 
6436 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
6437 	bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
6438 	bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX,   3);
6439 
6440 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6441 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
6442 }
6443 
6444 
6445 /*
6446  * The driver is supposed to notify ASF that the OS is still running
6447  * every three seconds, otherwise the management server may attempt
6448  * to reboot the machine.  If it hasn't actually failed, this is
6449  * not a desirable result.  However, this isn't running as a real-time
6450  * thread, and even if it were, it might not be able to generate the
6451  * heartbeat in a timely manner due to system load.  As it isn't a
6452  * significant strain on the machine, we will set the interval to half
6453  * of the required value.
6454  */
6455 void
6456 bge_asf_heartbeat(void *arg)
6457 {
6458 	bge_t *bgep = (bge_t *)arg;
6459 
6460 	mutex_enter(bgep->genlock);
6461 	bge_asf_update_status((bge_t *)bgep);
6462 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
6463 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
6464 	if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
6465 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
6466 	mutex_exit(bgep->genlock);
6467 	((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
6468 	    drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
6469 }
6470 
6471 
6472 void
6473 bge_asf_stop_timer(bge_t *bgep)
6474 {
6475 	timeout_id_t tmp_id = 0;
6476 
6477 	while ((bgep->asf_timeout_id != 0) &&
6478 	    (tmp_id != bgep->asf_timeout_id)) {
6479 		tmp_id = bgep->asf_timeout_id;
6480 		(void) untimeout(tmp_id);
6481 	}
6482 	bgep->asf_timeout_id = 0;
6483 }
6484 
6485 
6486 
6487 /*
6488  * This function should be placed at the earliest position of bge_attach().
6489  */
6490 void
6491 bge_asf_get_config(bge_t *bgep)
6492 {
6493 	uint32_t nicsig;
6494 	uint32_t niccfg;
6495 
6496 	bgep->asf_enabled = B_FALSE;
6497 
6498 	/* No ASF if APE present. */
6499 	if (bgep->ape_enabled)
6500 		return;
6501 
6502 	nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
6503 	if (nicsig == BGE_NIC_DATA_SIG) {
6504 		niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
6505 		if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
6506 			/*
6507 			 * Here, we don't consider BAXTER, because BGE haven't
6508 			 * supported BAXTER (that is 5752). Also, as I know,
6509 			 * BAXTER doesn't support ASF feature.
6510 			 */
6511 			bgep->asf_enabled = B_TRUE;
6512 		else
6513 			bgep->asf_enabled = B_FALSE;
6514 	} else
6515 		bgep->asf_enabled = B_FALSE;
6516 }
6517 
6518 
6519 void
6520 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
6521 {
6522 	uint32_t tries;
6523 	uint32_t event;
6524 
6525 	ASSERT(bgep->asf_enabled);
6526 
6527 	/* Issues "pause firmware" command and wait for ACK */
6528 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
6529 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6530 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
6531 
6532 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6533 	tries = 0;
6534 	while ((event & RRER_ASF_EVENT) && (tries < 100)) {
6535 		drv_usecwait(1);
6536 		tries ++;
6537 		event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6538 	}
6539 
6540 	bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
6541 	    BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
6542 
6543 	if (bgep->asf_newhandshake) {
6544 		switch (mode) {
6545 		case BGE_INIT_RESET:
6546 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6547 			    BGE_DRV_STATE_START);
6548 			break;
6549 		case BGE_SHUTDOWN_RESET:
6550 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6551 			    BGE_DRV_STATE_UNLOAD);
6552 			break;
6553 		case BGE_SUSPEND_RESET:
6554 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6555 			    BGE_DRV_STATE_SUSPEND);
6556 			break;
6557 		default:
6558 			break;
6559 		}
6560 	}
6561 
6562 	if (mode == BGE_INIT_RESET ||
6563 	    mode == BGE_SUSPEND_RESET)
6564 		bge_ape_driver_state_change(bgep, mode);
6565 }
6566 
6567 
6568 void
6569 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
6570 {
6571 	switch (mode) {
6572 	case BGE_INIT_RESET:
6573 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6574 		    BGE_DRV_STATE_START);
6575 		break;
6576 	case BGE_SHUTDOWN_RESET:
6577 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6578 		    BGE_DRV_STATE_UNLOAD);
6579 		break;
6580 	case BGE_SUSPEND_RESET:
6581 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6582 		    BGE_DRV_STATE_SUSPEND);
6583 		break;
6584 	default:
6585 		break;
6586 	}
6587 }
6588 
6589 
6590 void
6591 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
6592 {
6593 	switch (mode) {
6594 	case BGE_INIT_RESET:
6595 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6596 		    BGE_DRV_STATE_START_DONE);
6597 		break;
6598 	case BGE_SHUTDOWN_RESET:
6599 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6600 		    BGE_DRV_STATE_UNLOAD_DONE);
6601 		break;
6602 	default:
6603 		break;
6604 	}
6605 
6606 	if (mode == BGE_SHUTDOWN_RESET)
6607 		bge_ape_driver_state_change(bgep, mode);
6608 }
6609 
6610 #endif /* BGE_IPMI_ASF */
6611