1.\" Copyright (c) 2008, Sun Microsystems, Inc. All Rights Reserved. 2.\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. 3.\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. 4.\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] 5.\" Copyright (c) 2019, Joyent, Inc. 6.Dd January 8, 2019 7.Dt CPC 3CPC 8.Os 9.Sh NAME 10.Nm cpc 11.Nd hardware performance counters 12.Sh DESCRIPTION 13Modern microprocessors contain 14.Em hardware performance counters 15that allow 16the measurement of many different hardware events related to CPU behavior, 17including instruction and data cache misses as well as various internal states 18of the processor. 19The counters can be configured to count user events, system 20events, or both. 21Data from the performance counters can be used to analyze and 22tune the behavior of software on a particular type of processor. 23.Pp 24Most processors are able to generate an interrupt on counter overflow, allowing 25the counters to be used for various forms of profiling. 26.Pp 27This manual page describes a set of APIs that allow illumos applications to use 28these counters. 29Applications can measure their own behavior, the behavior of 30other applications, or the behavior of the whole system. 31.Ss Shared Counters or Private Counters 32There are two principal models for using these performance counters. 33Some users of these statistics want to observe system-wide behavior. 34Other users want to view the performance counters as part of the register set 35exported by each 36.Sy LWP . 37On a machine performing more than one activity, these two models are 38in conflict because the counters represent a critical hardware resource that 39cannot simultaneously be both shared and private. 40.Ss Configuration Interfaces 41The following configuration interfaces are provided: 42.Bl -tag -width Xr 43.It Xr cpc_open 3CPC 44Check the version the application was compiled with against the version of the 45.It Xr cpc_cciname 3CPC 46Return a printable string to describe the performance counters of the 47processor. 48.It Xr cpc_npic 3CPC 49Return the number of performance counters on the processor. 50.It cpc_cpuref 3CPC 51Return a reference to documentation that should be consulted to understand how 52to use and interpret data from the performance counters. 53.El 54.Ss Performance Counter Access 55Performance counters can be present in hardware but not acccessible because 56either some of the necessary system software components are not available or 57not installed, or the counters might be in use by other processes. 58The 59.Xr cpc_open 3CPC 60function determines the accessibility of the counters and 61must be invoked before any attempt to program the counters. 62.Ss "Finding Events" 63Each different type of processor has its own set of events available for 64measurement. 65The 66.Xr cpc_walk_events_all 3CPC 67and 68.Xr cpc_walk_events_pic 3CPC 69functions allow an application to determine the 70names of events supported by the underlying processor. 71A collection of generic, platform independent event names are defined by 72.Xr generic_events 3CPC . 73Each generic event maps to an underlying hardware event specific to the 74underlying processor and any optional attributes. 75The 76.Xr cpc_walk_generic_events_all 3CPC 77and 78.Xr cpc_walk_generic_events_pic 3CPC 79functions allow an application to determine the generic events supported 80on the underlying platform. 81.Ss Processor Specific Events 82Manual pages specific to events for recent Intel processors are 83available. 84The following manual pages cover the following Intel processor models 85which are listed in hexadecimal: 86.Bl -tag -width Xr 87.It Xr bdw_de_events 3CPC 88Intel Broadwell-DE events; covers model 56h. 89.It Xr bdw_events 3CPC 90Intel Broadwell client events; covers models 3dh and 47h. 91.It Xr bdx_events 3CPC 92Intel Broadwell server events; covers model 4fh. 93.It Xr bnl_events 3CPC 94Intel Atom Bonnell events; covers models 35h, 36h, 27h, 26h, and 1ch. 95.It Xr clx_events 3CPC 96Intel Cascade Lake server events; covers model 55h, steppings 5-fh. 97.It Xr glm_events 3CPC 98Intel Goldmont SoC events; covers models 5fh and 5ch. 99.It Xr glp_events 3CPC 100Intel Goldmont Plus SoC events; covers model 7ah. 101.It Xr hsw_events 3CPC 102Intel Haswell client events; covers models 46h, 45h, and 3ch. 103.It Xr hsx_events 3CPC 104Intel Haswell server events; covers model 3fh. 105.It Xr ivb_events 3CPC 106Intel Ivy Bridge client events; covers model 3ah. 107.It Xr ivt_events 3CPC 108Intel Ivy Bridge server events; covers model 3eh. 109.It Xr jkt_events 3CPC 110Intel Sandy Bridge server events; covers model 2dh. 111.It Xr nhm_ep_events 3CPC 112Intel Nehalem-EP events; covers models, 1ah, 1fh, and 1eh. 113.It Xr nhm_ex_events 3CPC 114Intel Sandy Bridge server events; covers model 23h. 115.It Xr skl_events 3CPC 116Intel Skylake client events; covers model 9eh, 8eh, 5e, and 4eh. 117.It Xr skx_events 3CPC 118Intel Skylake server events; covers model 55h, steppings 0-4h. 119.It Xr slm_events 3CPC 120Intel Atom Silvermont events; covers models 4ch, 4dh, and 37h. 121.It Xr snb_events 3CPC 122Intel Sandy Bridge Client events; covers model 2ah. 123.It Xr wsm_ep_dp_events 3CPC 124Intel Westmere-EP-DP events; covers model 2ch. 125.It Xr wsm_ep_sp_events 3CPC 126Intel Westmere-EP-SP events; covers model 25h. 127.It Xr wsm_ex_events 3CPC 128Intel Westmere-EX events; covers model 2fh. 129.El 130.Ss Using Attributes 131Some processors have advanced performance counter capabilities that are 132configured with attributes. 133The 134.Xr cpc_walk_attrs 3CPC 135function can be used to determine the names of attributes supported by 136the underlying processor. 137The documentation referenced by 138.Xr cpc_cpuref 3CPC 139should be consulted to understand the meaning of a processor's performance 140counter attributes. 141.Ss Performance Counter Context 142Each processor on the system possesses its own set of performance counter 143registers. 144For a single process, it is often desirable to maintain the illusion 145that the counters are an intrinsic part of that process (whichever processors 146it runs on), since this allows the events to be directly attributed to the 147process without having to make passive all other activity on the system. 148.Pp 149To achieve this behavior, the library associates 150.Em performance counter context 151with each 152.Sy LWP 153in the process. 154The context consists of a small amount of kernel memory to hold the counter 155values when the 156.Sy BLWP 157is not running, and some simple kernel functions to save and restore those counter 158values from and to the hardware registers when the 159.Sy LWP 160performs a normal context switch. 161A process can only observe and manipulate its own copy of the 162performance counter control and data registers. 163.Ss Performance Counters \&In Other Processes 164Though applications can be modified to instrument themselves as demonstrated 165above, it is frequently useful to be able to examine the behavior of an 166existing application without changing the source code. 167A separate library, 168.Sy libpctx , 169provides a simple set of interfaces that use the facilities of 170.Xr proc 4 171to control a target process, and together with functions in 172.Sy libcpc , 173allow 174.Sy truss No -like 175tools to be constructed to measure the performance counters in other 176applications. 177An example of one such application is 178.Xr cputrack 1 . 179.Pp 180The functions in 181.Sy libpctx 182are independent of those in 183.Sy libcpc . 184These functions manage a process using an event-loop paradigm \(em that is, the 185execution of certain system calls by the controlled process cause the library 186to stop the controlled process and execute callback functions in the context of 187the controlling process. 188These handlers can perform various operations on the target process using APIs 189in 190.Sy libpctx 191and 192.Sy libcpc 193that consume 194.Vt pctx_t 195handles. 196.Sh SEE ALSO 197.Xr cputrack 1 , 198.Xr cpustat 1M , 199.Xr cpc_bind_curlwp 3CPC , 200.Xr cpc_buf_create 3CPC , 201.Xr cpc_enable 3CPC , 202.Xr cpc_npic 3CPC , 203.Xr cpc_open 3CPC , 204.Xr cpc_set_create 3CPC , 205.Xr cpc_seterrhndlr 3CPC , 206.Xr generic_events 3CPC , 207.Xr pctx_capture 3CPC , 208.Xr pctx_set_events 3CPC , 209.Xr libcpc 3LIB , 210.Xr proc 4 211