1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29#if !defined(lint) 30#include "assym.h" 31#endif /* !lint */ 32#include <sys/asm_linkage.h> 33#include <sys/privregs.h> 34#include <sys/sun4asi.h> 35#include <sys/machasi.h> 36#include <sys/hypervisor_api.h> 37#include <sys/machtrap.h> 38#include <sys/machthread.h> 39#include <sys/pcb.h> 40#include <sys/pte.h> 41#include <sys/mmu.h> 42#include <sys/machpcb.h> 43#include <sys/async.h> 44#include <sys/intreg.h> 45#include <sys/scb.h> 46#include <sys/psr_compat.h> 47#include <sys/syscall.h> 48#include <sys/machparam.h> 49#include <sys/traptrace.h> 50#include <vm/hat_sfmmu.h> 51#include <sys/archsystm.h> 52#include <sys/utrap.h> 53#include <sys/clock.h> 54#include <sys/intr.h> 55#include <sys/fpu/fpu_simulator.h> 56#include <vm/seg_spt.h> 57 58/* 59 * WARNING: If you add a fast trap handler which can be invoked by a 60 * non-privileged user, you may have to use the FAST_TRAP_DONE macro 61 * instead of "done" instruction to return back to the user mode. See 62 * comments for the "fast_trap_done" entry point for more information. 63 * 64 * An alternate FAST_TRAP_DONE_CHK_INTR macro should be used for the 65 * cases where you always want to process any pending interrupts before 66 * returning back to the user mode. 67 */ 68#define FAST_TRAP_DONE \ 69 ba,a fast_trap_done 70 71#define FAST_TRAP_DONE_CHK_INTR \ 72 ba,a fast_trap_done_chk_intr 73 74/* 75 * SPARC V9 Trap Table 76 * 77 * Most of the trap handlers are made from common building 78 * blocks, and some are instantiated multiple times within 79 * the trap table. So, I build a bunch of macros, then 80 * populate the table using only the macros. 81 * 82 * Many macros branch to sys_trap. Its calling convention is: 83 * %g1 kernel trap handler 84 * %g2, %g3 args for above 85 * %g4 desire %pil 86 */ 87 88#ifdef TRAPTRACE 89 90/* 91 * Tracing macro. Adds two instructions if TRAPTRACE is defined. 92 */ 93#define TT_TRACE(label) \ 94 ba label ;\ 95 rd %pc, %g7 96#define TT_TRACE_INS 2 97 98#define TT_TRACE_L(label) \ 99 ba label ;\ 100 rd %pc, %l4 ;\ 101 clr %l4 102#define TT_TRACE_L_INS 3 103 104#else 105 106#define TT_TRACE(label) 107#define TT_TRACE_INS 0 108 109#define TT_TRACE_L(label) 110#define TT_TRACE_L_INS 0 111 112#endif 113 114/* 115 * This macro is used to update per cpu mmu stats in perf critical 116 * paths. It is only enabled in debug kernels or if SFMMU_STAT_GATHER 117 * is defined. 118 */ 119#if defined(DEBUG) || defined(SFMMU_STAT_GATHER) 120#define HAT_PERCPU_DBSTAT(stat) \ 121 mov stat, %g1 ;\ 122 ba stat_mmu ;\ 123 rd %pc, %g7 124#else 125#define HAT_PERCPU_DBSTAT(stat) 126#endif /* DEBUG || SFMMU_STAT_GATHER */ 127 128/* 129 * This first set are funneled to trap() with %tt as the type. 130 * Trap will then either panic or send the user a signal. 131 */ 132/* 133 * NOT is used for traps that just shouldn't happen. 134 * It comes in both single and quadruple flavors. 135 */ 136#if !defined(lint) 137 .global trap 138#endif /* !lint */ 139#define NOT \ 140 TT_TRACE(trace_gen) ;\ 141 set trap, %g1 ;\ 142 rdpr %tt, %g3 ;\ 143 ba,pt %xcc, sys_trap ;\ 144 sub %g0, 1, %g4 ;\ 145 .align 32 146#define NOT4 NOT; NOT; NOT; NOT 147 148#define NOTP \ 149 TT_TRACE(trace_gen) ;\ 150 ba,pt %xcc, ptl1_panic ;\ 151 mov PTL1_BAD_TRAP, %g1 ;\ 152 .align 32 153#define NOTP4 NOTP; NOTP; NOTP; NOTP 154 155/* 156 * RED is for traps that use the red mode handler. 157 * We should never see these either. 158 */ 159#define RED NOT 160/* 161 * BAD is used for trap vectors we don't have a kernel 162 * handler for. 163 * It also comes in single and quadruple versions. 164 */ 165#define BAD NOT 166#define BAD4 NOT4 167 168#define DONE \ 169 done; \ 170 .align 32 171 172/* 173 * TRAP vectors to the trap() function. 174 * It's main use is for user errors. 175 */ 176#if !defined(lint) 177 .global trap 178#endif /* !lint */ 179#define TRAP(arg) \ 180 TT_TRACE(trace_gen) ;\ 181 set trap, %g1 ;\ 182 mov arg, %g3 ;\ 183 ba,pt %xcc, sys_trap ;\ 184 sub %g0, 1, %g4 ;\ 185 .align 32 186 187/* 188 * SYSCALL is used for system calls on both ILP32 and LP64 kernels 189 * depending on the "which" parameter (should be either syscall_trap 190 * or syscall_trap32). 191 */ 192#define SYSCALL(which) \ 193 TT_TRACE(trace_gen) ;\ 194 set (which), %g1 ;\ 195 ba,pt %xcc, sys_trap ;\ 196 sub %g0, 1, %g4 ;\ 197 .align 32 198 199/* 200 * GOTO just jumps to a label. 201 * It's used for things that can be fixed without going thru sys_trap. 202 */ 203#define GOTO(label) \ 204 .global label ;\ 205 ba,a label ;\ 206 .empty ;\ 207 .align 32 208 209/* 210 * GOTO_TT just jumps to a label. 211 * correctable ECC error traps at level 0 and 1 will use this macro. 212 * It's used for things that can be fixed without going thru sys_trap. 213 */ 214#define GOTO_TT(label, ttlabel) \ 215 .global label ;\ 216 TT_TRACE(ttlabel) ;\ 217 ba,a label ;\ 218 .empty ;\ 219 .align 32 220 221/* 222 * Privileged traps 223 * Takes breakpoint if privileged, calls trap() if not. 224 */ 225#define PRIV(label) \ 226 rdpr %tstate, %g1 ;\ 227 btst TSTATE_PRIV, %g1 ;\ 228 bnz label ;\ 229 rdpr %tt, %g3 ;\ 230 set trap, %g1 ;\ 231 ba,pt %xcc, sys_trap ;\ 232 sub %g0, 1, %g4 ;\ 233 .align 32 234 235 236/* 237 * DTrace traps. 238 */ 239#define DTRACE_FASTTRAP \ 240 .global dtrace_fasttrap_probe ;\ 241 .global dtrace_fasttrap_probe_ptr ;\ 242 sethi %hi(dtrace_fasttrap_probe_ptr), %g4 ;\ 243 ldn [%g4 + %lo(dtrace_fasttrap_probe_ptr)], %g4 ;\ 244 set dtrace_fasttrap_probe, %g1 ;\ 245 brnz,pn %g4, user_trap ;\ 246 sub %g0, 1, %g4 ;\ 247 FAST_TRAP_DONE ;\ 248 .align 32 249 250#define DTRACE_PID \ 251 .global dtrace_pid_probe ;\ 252 set dtrace_pid_probe, %g1 ;\ 253 ba,pt %xcc, user_trap ;\ 254 sub %g0, 1, %g4 ;\ 255 .align 32 256 257#define DTRACE_RETURN \ 258 .global dtrace_return_probe ;\ 259 set dtrace_return_probe, %g1 ;\ 260 ba,pt %xcc, user_trap ;\ 261 sub %g0, 1, %g4 ;\ 262 .align 32 263 264/* 265 * REGISTER WINDOW MANAGEMENT MACROS 266 */ 267 268/* 269 * various convenient units of padding 270 */ 271#define SKIP(n) .skip 4*(n) 272 273/* 274 * CLEAN_WINDOW is the simple handler for cleaning a register window. 275 */ 276#define CLEAN_WINDOW \ 277 TT_TRACE_L(trace_win) ;\ 278 rdpr %cleanwin, %l0; inc %l0; wrpr %l0, %cleanwin ;\ 279 clr %l0; clr %l1; clr %l2; clr %l3 ;\ 280 clr %l4; clr %l5; clr %l6; clr %l7 ;\ 281 clr %o0; clr %o1; clr %o2; clr %o3 ;\ 282 clr %o4; clr %o5; clr %o6; clr %o7 ;\ 283 retry; .align 128 284 285#if !defined(lint) 286 287/* 288 * If we get an unresolved tlb miss while in a window handler, the fault 289 * handler will resume execution at the last instruction of the window 290 * hander, instead of delivering the fault to the kernel. Spill handlers 291 * use this to spill windows into the wbuf. 292 * 293 * The mixed handler works by checking %sp, and branching to the correct 294 * handler. This is done by branching back to label 1: for 32b frames, 295 * or label 2: for 64b frames; which implies the handler order is: 32b, 296 * 64b, mixed. The 1: and 2: labels are offset into the routines to 297 * allow the branchs' delay slots to contain useful instructions. 298 */ 299 300/* 301 * SPILL_32bit spills a 32-bit-wide kernel register window. It 302 * assumes that the kernel context and the nucleus context are the 303 * same. The stack pointer is required to be eight-byte aligned even 304 * though this code only needs it to be four-byte aligned. 305 */ 306#define SPILL_32bit(tail) \ 307 srl %sp, 0, %sp ;\ 3081: st %l0, [%sp + 0] ;\ 309 st %l1, [%sp + 4] ;\ 310 st %l2, [%sp + 8] ;\ 311 st %l3, [%sp + 12] ;\ 312 st %l4, [%sp + 16] ;\ 313 st %l5, [%sp + 20] ;\ 314 st %l6, [%sp + 24] ;\ 315 st %l7, [%sp + 28] ;\ 316 st %i0, [%sp + 32] ;\ 317 st %i1, [%sp + 36] ;\ 318 st %i2, [%sp + 40] ;\ 319 st %i3, [%sp + 44] ;\ 320 st %i4, [%sp + 48] ;\ 321 st %i5, [%sp + 52] ;\ 322 st %i6, [%sp + 56] ;\ 323 st %i7, [%sp + 60] ;\ 324 TT_TRACE_L(trace_win) ;\ 325 saved ;\ 326 retry ;\ 327 SKIP(31-19-TT_TRACE_L_INS) ;\ 328 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 329 .empty 330 331/* 332 * SPILL_32bit_asi spills a 32-bit-wide register window into a 32-bit 333 * wide address space via the designated asi. It is used to spill 334 * non-kernel windows. The stack pointer is required to be eight-byte 335 * aligned even though this code only needs it to be four-byte 336 * aligned. 337 */ 338#define SPILL_32bit_asi(asi_num, tail) \ 339 srl %sp, 0, %sp ;\ 3401: sta %l0, [%sp + %g0]asi_num ;\ 341 mov 4, %g1 ;\ 342 sta %l1, [%sp + %g1]asi_num ;\ 343 mov 8, %g2 ;\ 344 sta %l2, [%sp + %g2]asi_num ;\ 345 mov 12, %g3 ;\ 346 sta %l3, [%sp + %g3]asi_num ;\ 347 add %sp, 16, %g4 ;\ 348 sta %l4, [%g4 + %g0]asi_num ;\ 349 sta %l5, [%g4 + %g1]asi_num ;\ 350 sta %l6, [%g4 + %g2]asi_num ;\ 351 sta %l7, [%g4 + %g3]asi_num ;\ 352 add %g4, 16, %g4 ;\ 353 sta %i0, [%g4 + %g0]asi_num ;\ 354 sta %i1, [%g4 + %g1]asi_num ;\ 355 sta %i2, [%g4 + %g2]asi_num ;\ 356 sta %i3, [%g4 + %g3]asi_num ;\ 357 add %g4, 16, %g4 ;\ 358 sta %i4, [%g4 + %g0]asi_num ;\ 359 sta %i5, [%g4 + %g1]asi_num ;\ 360 sta %i6, [%g4 + %g2]asi_num ;\ 361 sta %i7, [%g4 + %g3]asi_num ;\ 362 TT_TRACE_L(trace_win) ;\ 363 saved ;\ 364 retry ;\ 365 SKIP(31-25-TT_TRACE_L_INS) ;\ 366 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 367 .empty 368 369#define SPILL_32bit_tt1(asi_num, tail) \ 370 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 371 .empty ;\ 372 .align 128 373 374 375/* 376 * FILL_32bit fills a 32-bit-wide kernel register window. It assumes 377 * that the kernel context and the nucleus context are the same. The 378 * stack pointer is required to be eight-byte aligned even though this 379 * code only needs it to be four-byte aligned. 380 */ 381#define FILL_32bit(tail) \ 382 srl %sp, 0, %sp ;\ 3831: TT_TRACE_L(trace_win) ;\ 384 ld [%sp + 0], %l0 ;\ 385 ld [%sp + 4], %l1 ;\ 386 ld [%sp + 8], %l2 ;\ 387 ld [%sp + 12], %l3 ;\ 388 ld [%sp + 16], %l4 ;\ 389 ld [%sp + 20], %l5 ;\ 390 ld [%sp + 24], %l6 ;\ 391 ld [%sp + 28], %l7 ;\ 392 ld [%sp + 32], %i0 ;\ 393 ld [%sp + 36], %i1 ;\ 394 ld [%sp + 40], %i2 ;\ 395 ld [%sp + 44], %i3 ;\ 396 ld [%sp + 48], %i4 ;\ 397 ld [%sp + 52], %i5 ;\ 398 ld [%sp + 56], %i6 ;\ 399 ld [%sp + 60], %i7 ;\ 400 restored ;\ 401 retry ;\ 402 SKIP(31-19-TT_TRACE_L_INS) ;\ 403 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 404 .empty 405 406/* 407 * FILL_32bit_asi fills a 32-bit-wide register window from a 32-bit 408 * wide address space via the designated asi. It is used to fill 409 * non-kernel windows. The stack pointer is required to be eight-byte 410 * aligned even though this code only needs it to be four-byte 411 * aligned. 412 */ 413#define FILL_32bit_asi(asi_num, tail) \ 414 srl %sp, 0, %sp ;\ 4151: TT_TRACE_L(trace_win) ;\ 416 mov 4, %g1 ;\ 417 lda [%sp + %g0]asi_num, %l0 ;\ 418 mov 8, %g2 ;\ 419 lda [%sp + %g1]asi_num, %l1 ;\ 420 mov 12, %g3 ;\ 421 lda [%sp + %g2]asi_num, %l2 ;\ 422 lda [%sp + %g3]asi_num, %l3 ;\ 423 add %sp, 16, %g4 ;\ 424 lda [%g4 + %g0]asi_num, %l4 ;\ 425 lda [%g4 + %g1]asi_num, %l5 ;\ 426 lda [%g4 + %g2]asi_num, %l6 ;\ 427 lda [%g4 + %g3]asi_num, %l7 ;\ 428 add %g4, 16, %g4 ;\ 429 lda [%g4 + %g0]asi_num, %i0 ;\ 430 lda [%g4 + %g1]asi_num, %i1 ;\ 431 lda [%g4 + %g2]asi_num, %i2 ;\ 432 lda [%g4 + %g3]asi_num, %i3 ;\ 433 add %g4, 16, %g4 ;\ 434 lda [%g4 + %g0]asi_num, %i4 ;\ 435 lda [%g4 + %g1]asi_num, %i5 ;\ 436 lda [%g4 + %g2]asi_num, %i6 ;\ 437 lda [%g4 + %g3]asi_num, %i7 ;\ 438 restored ;\ 439 retry ;\ 440 SKIP(31-25-TT_TRACE_L_INS) ;\ 441 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 442 .empty 443 444 445/* 446 * SPILL_64bit spills a 64-bit-wide kernel register window. It 447 * assumes that the kernel context and the nucleus context are the 448 * same. The stack pointer is required to be eight-byte aligned. 449 */ 450#define SPILL_64bit(tail) \ 4512: stx %l0, [%sp + V9BIAS64 + 0] ;\ 452 stx %l1, [%sp + V9BIAS64 + 8] ;\ 453 stx %l2, [%sp + V9BIAS64 + 16] ;\ 454 stx %l3, [%sp + V9BIAS64 + 24] ;\ 455 stx %l4, [%sp + V9BIAS64 + 32] ;\ 456 stx %l5, [%sp + V9BIAS64 + 40] ;\ 457 stx %l6, [%sp + V9BIAS64 + 48] ;\ 458 stx %l7, [%sp + V9BIAS64 + 56] ;\ 459 stx %i0, [%sp + V9BIAS64 + 64] ;\ 460 stx %i1, [%sp + V9BIAS64 + 72] ;\ 461 stx %i2, [%sp + V9BIAS64 + 80] ;\ 462 stx %i3, [%sp + V9BIAS64 + 88] ;\ 463 stx %i4, [%sp + V9BIAS64 + 96] ;\ 464 stx %i5, [%sp + V9BIAS64 + 104] ;\ 465 stx %i6, [%sp + V9BIAS64 + 112] ;\ 466 stx %i7, [%sp + V9BIAS64 + 120] ;\ 467 TT_TRACE_L(trace_win) ;\ 468 saved ;\ 469 retry ;\ 470 SKIP(31-18-TT_TRACE_L_INS) ;\ 471 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 472 .empty 473 474#define SPILL_64bit_ktt1(tail) \ 475 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 476 .empty ;\ 477 .align 128 478 479#define SPILL_mixed_ktt1(tail) \ 480 btst 1, %sp ;\ 481 bz,a,pt %xcc, fault_32bit_/**/tail ;\ 482 srl %sp, 0, %sp ;\ 483 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 484 .empty ;\ 485 .align 128 486 487/* 488 * SPILL_64bit_asi spills a 64-bit-wide register window into a 64-bit 489 * wide address space via the designated asi. It is used to spill 490 * non-kernel windows. The stack pointer is required to be eight-byte 491 * aligned. 492 */ 493#define SPILL_64bit_asi(asi_num, tail) \ 494 mov 0 + V9BIAS64, %g1 ;\ 4952: stxa %l0, [%sp + %g1]asi_num ;\ 496 mov 8 + V9BIAS64, %g2 ;\ 497 stxa %l1, [%sp + %g2]asi_num ;\ 498 mov 16 + V9BIAS64, %g3 ;\ 499 stxa %l2, [%sp + %g3]asi_num ;\ 500 mov 24 + V9BIAS64, %g4 ;\ 501 stxa %l3, [%sp + %g4]asi_num ;\ 502 add %sp, 32, %g5 ;\ 503 stxa %l4, [%g5 + %g1]asi_num ;\ 504 stxa %l5, [%g5 + %g2]asi_num ;\ 505 stxa %l6, [%g5 + %g3]asi_num ;\ 506 stxa %l7, [%g5 + %g4]asi_num ;\ 507 add %g5, 32, %g5 ;\ 508 stxa %i0, [%g5 + %g1]asi_num ;\ 509 stxa %i1, [%g5 + %g2]asi_num ;\ 510 stxa %i2, [%g5 + %g3]asi_num ;\ 511 stxa %i3, [%g5 + %g4]asi_num ;\ 512 add %g5, 32, %g5 ;\ 513 stxa %i4, [%g5 + %g1]asi_num ;\ 514 stxa %i5, [%g5 + %g2]asi_num ;\ 515 stxa %i6, [%g5 + %g3]asi_num ;\ 516 stxa %i7, [%g5 + %g4]asi_num ;\ 517 TT_TRACE_L(trace_win) ;\ 518 saved ;\ 519 retry ;\ 520 SKIP(31-25-TT_TRACE_L_INS) ;\ 521 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 522 .empty 523 524#define SPILL_64bit_tt1(asi_num, tail) \ 525 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 526 .empty ;\ 527 .align 128 528 529/* 530 * FILL_64bit fills a 64-bit-wide kernel register window. It assumes 531 * that the kernel context and the nucleus context are the same. The 532 * stack pointer is required to be eight-byte aligned. 533 */ 534#define FILL_64bit(tail) \ 5352: TT_TRACE_L(trace_win) ;\ 536 ldx [%sp + V9BIAS64 + 0], %l0 ;\ 537 ldx [%sp + V9BIAS64 + 8], %l1 ;\ 538 ldx [%sp + V9BIAS64 + 16], %l2 ;\ 539 ldx [%sp + V9BIAS64 + 24], %l3 ;\ 540 ldx [%sp + V9BIAS64 + 32], %l4 ;\ 541 ldx [%sp + V9BIAS64 + 40], %l5 ;\ 542 ldx [%sp + V9BIAS64 + 48], %l6 ;\ 543 ldx [%sp + V9BIAS64 + 56], %l7 ;\ 544 ldx [%sp + V9BIAS64 + 64], %i0 ;\ 545 ldx [%sp + V9BIAS64 + 72], %i1 ;\ 546 ldx [%sp + V9BIAS64 + 80], %i2 ;\ 547 ldx [%sp + V9BIAS64 + 88], %i3 ;\ 548 ldx [%sp + V9BIAS64 + 96], %i4 ;\ 549 ldx [%sp + V9BIAS64 + 104], %i5 ;\ 550 ldx [%sp + V9BIAS64 + 112], %i6 ;\ 551 ldx [%sp + V9BIAS64 + 120], %i7 ;\ 552 restored ;\ 553 retry ;\ 554 SKIP(31-18-TT_TRACE_L_INS) ;\ 555 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 556 .empty 557 558/* 559 * FILL_64bit_asi fills a 64-bit-wide register window from a 64-bit 560 * wide address space via the designated asi. It is used to fill 561 * non-kernel windows. The stack pointer is required to be eight-byte 562 * aligned. 563 */ 564#define FILL_64bit_asi(asi_num, tail) \ 565 mov V9BIAS64 + 0, %g1 ;\ 5662: TT_TRACE_L(trace_win) ;\ 567 ldxa [%sp + %g1]asi_num, %l0 ;\ 568 mov V9BIAS64 + 8, %g2 ;\ 569 ldxa [%sp + %g2]asi_num, %l1 ;\ 570 mov V9BIAS64 + 16, %g3 ;\ 571 ldxa [%sp + %g3]asi_num, %l2 ;\ 572 mov V9BIAS64 + 24, %g4 ;\ 573 ldxa [%sp + %g4]asi_num, %l3 ;\ 574 add %sp, 32, %g5 ;\ 575 ldxa [%g5 + %g1]asi_num, %l4 ;\ 576 ldxa [%g5 + %g2]asi_num, %l5 ;\ 577 ldxa [%g5 + %g3]asi_num, %l6 ;\ 578 ldxa [%g5 + %g4]asi_num, %l7 ;\ 579 add %g5, 32, %g5 ;\ 580 ldxa [%g5 + %g1]asi_num, %i0 ;\ 581 ldxa [%g5 + %g2]asi_num, %i1 ;\ 582 ldxa [%g5 + %g3]asi_num, %i2 ;\ 583 ldxa [%g5 + %g4]asi_num, %i3 ;\ 584 add %g5, 32, %g5 ;\ 585 ldxa [%g5 + %g1]asi_num, %i4 ;\ 586 ldxa [%g5 + %g2]asi_num, %i5 ;\ 587 ldxa [%g5 + %g3]asi_num, %i6 ;\ 588 ldxa [%g5 + %g4]asi_num, %i7 ;\ 589 restored ;\ 590 retry ;\ 591 SKIP(31-25-TT_TRACE_L_INS) ;\ 592 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 593 .empty 594 595 596#endif /* !lint */ 597 598/* 599 * SPILL_mixed spills either size window, depending on 600 * whether %sp is even or odd, to a 32-bit address space. 601 * This may only be used in conjunction with SPILL_32bit/ 602 * FILL_64bit. 603 * Clear upper 32 bits of %sp if it is odd. 604 * We won't need to clear them in 64 bit kernel. 605 */ 606#define SPILL_mixed \ 607 btst 1, %sp ;\ 608 bz,a,pt %xcc, 1b ;\ 609 srl %sp, 0, %sp ;\ 610 ba,pt %xcc, 2b ;\ 611 nop ;\ 612 .align 128 613 614/* 615 * FILL_mixed(ASI) fills either size window, depending on 616 * whether %sp is even or odd, from a 32-bit address space. 617 * This may only be used in conjunction with FILL_32bit/ 618 * FILL_64bit. New versions of FILL_mixed_{tt1,asi} would be 619 * needed for use with FILL_{32,64}bit_{tt1,asi}. Particular 620 * attention should be paid to the instructions that belong 621 * in the delay slots of the branches depending on the type 622 * of fill handler being branched to. 623 * Clear upper 32 bits of %sp if it is odd. 624 * We won't need to clear them in 64 bit kernel. 625 */ 626#define FILL_mixed \ 627 btst 1, %sp ;\ 628 bz,a,pt %xcc, 1b ;\ 629 srl %sp, 0, %sp ;\ 630 ba,pt %xcc, 2b ;\ 631 nop ;\ 632 .align 128 633 634 635/* 636 * SPILL_32clean/SPILL_64clean spill 32-bit and 64-bit register windows, 637 * respectively, into the address space via the designated asi. The 638 * unbiased stack pointer is required to be eight-byte aligned (even for 639 * the 32-bit case even though this code does not require such strict 640 * alignment). 641 * 642 * With SPARC v9 the spill trap takes precedence over the cleanwin trap 643 * so when cansave == 0, canrestore == 6, and cleanwin == 6 the next save 644 * will cause cwp + 2 to be spilled but will not clean cwp + 1. That 645 * window may contain kernel data so in user_rtt we set wstate to call 646 * these spill handlers on the first user spill trap. These handler then 647 * spill the appropriate window but also back up a window and clean the 648 * window that didn't get a cleanwin trap. 649 */ 650#define SPILL_32clean(asi_num, tail) \ 651 srl %sp, 0, %sp ;\ 652 sta %l0, [%sp + %g0]asi_num ;\ 653 mov 4, %g1 ;\ 654 sta %l1, [%sp + %g1]asi_num ;\ 655 mov 8, %g2 ;\ 656 sta %l2, [%sp + %g2]asi_num ;\ 657 mov 12, %g3 ;\ 658 sta %l3, [%sp + %g3]asi_num ;\ 659 add %sp, 16, %g4 ;\ 660 sta %l4, [%g4 + %g0]asi_num ;\ 661 sta %l5, [%g4 + %g1]asi_num ;\ 662 sta %l6, [%g4 + %g2]asi_num ;\ 663 sta %l7, [%g4 + %g3]asi_num ;\ 664 add %g4, 16, %g4 ;\ 665 sta %i0, [%g4 + %g0]asi_num ;\ 666 sta %i1, [%g4 + %g1]asi_num ;\ 667 sta %i2, [%g4 + %g2]asi_num ;\ 668 sta %i3, [%g4 + %g3]asi_num ;\ 669 add %g4, 16, %g4 ;\ 670 sta %i4, [%g4 + %g0]asi_num ;\ 671 sta %i5, [%g4 + %g1]asi_num ;\ 672 sta %i6, [%g4 + %g2]asi_num ;\ 673 sta %i7, [%g4 + %g3]asi_num ;\ 674 TT_TRACE_L(trace_win) ;\ 675 b .spill_clean ;\ 676 mov WSTATE_USER32, %g7 ;\ 677 SKIP(31-25-TT_TRACE_L_INS) ;\ 678 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 679 .empty 680 681#define SPILL_64clean(asi_num, tail) \ 682 mov 0 + V9BIAS64, %g1 ;\ 683 stxa %l0, [%sp + %g1]asi_num ;\ 684 mov 8 + V9BIAS64, %g2 ;\ 685 stxa %l1, [%sp + %g2]asi_num ;\ 686 mov 16 + V9BIAS64, %g3 ;\ 687 stxa %l2, [%sp + %g3]asi_num ;\ 688 mov 24 + V9BIAS64, %g4 ;\ 689 stxa %l3, [%sp + %g4]asi_num ;\ 690 add %sp, 32, %g5 ;\ 691 stxa %l4, [%g5 + %g1]asi_num ;\ 692 stxa %l5, [%g5 + %g2]asi_num ;\ 693 stxa %l6, [%g5 + %g3]asi_num ;\ 694 stxa %l7, [%g5 + %g4]asi_num ;\ 695 add %g5, 32, %g5 ;\ 696 stxa %i0, [%g5 + %g1]asi_num ;\ 697 stxa %i1, [%g5 + %g2]asi_num ;\ 698 stxa %i2, [%g5 + %g3]asi_num ;\ 699 stxa %i3, [%g5 + %g4]asi_num ;\ 700 add %g5, 32, %g5 ;\ 701 stxa %i4, [%g5 + %g1]asi_num ;\ 702 stxa %i5, [%g5 + %g2]asi_num ;\ 703 stxa %i6, [%g5 + %g3]asi_num ;\ 704 stxa %i7, [%g5 + %g4]asi_num ;\ 705 TT_TRACE_L(trace_win) ;\ 706 b .spill_clean ;\ 707 mov WSTATE_USER64, %g7 ;\ 708 SKIP(31-25-TT_TRACE_L_INS) ;\ 709 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 710 .empty 711 712 713/* 714 * Floating point disabled. 715 */ 716#define FP_DISABLED_TRAP \ 717 TT_TRACE(trace_gen) ;\ 718 ba,pt %xcc,.fp_disabled ;\ 719 nop ;\ 720 .align 32 721 722/* 723 * Floating point exceptions. 724 */ 725#define FP_IEEE_TRAP \ 726 TT_TRACE(trace_gen) ;\ 727 ba,pt %xcc,.fp_ieee_exception ;\ 728 nop ;\ 729 .align 32 730 731#define FP_TRAP \ 732 TT_TRACE(trace_gen) ;\ 733 ba,pt %xcc,.fp_exception ;\ 734 nop ;\ 735 .align 32 736 737#if !defined(lint) 738 739/* 740 * ECACHE_ECC error traps at level 0 and level 1 741 */ 742#define ECACHE_ECC(table_name) \ 743 .global table_name ;\ 744table_name: ;\ 745 membar #Sync ;\ 746 set trap, %g1 ;\ 747 rdpr %tt, %g3 ;\ 748 ba,pt %xcc, sys_trap ;\ 749 sub %g0, 1, %g4 ;\ 750 .align 32 751 752#endif /* !lint */ 753 754/* 755 * illegal instruction trap 756 */ 757#define ILLTRAP_INSTR \ 758 membar #Sync ;\ 759 TT_TRACE(trace_gen) ;\ 760 or %g0, P_UTRAP4, %g2 ;\ 761 or %g0, T_UNIMP_INSTR, %g3 ;\ 762 sethi %hi(.check_v9utrap), %g4 ;\ 763 jmp %g4 + %lo(.check_v9utrap) ;\ 764 nop ;\ 765 .align 32 766 767/* 768 * tag overflow trap 769 */ 770#define TAG_OVERFLOW \ 771 TT_TRACE(trace_gen) ;\ 772 or %g0, P_UTRAP10, %g2 ;\ 773 or %g0, T_TAG_OVERFLOW, %g3 ;\ 774 sethi %hi(.check_v9utrap), %g4 ;\ 775 jmp %g4 + %lo(.check_v9utrap) ;\ 776 nop ;\ 777 .align 32 778 779/* 780 * divide by zero trap 781 */ 782#define DIV_BY_ZERO \ 783 TT_TRACE(trace_gen) ;\ 784 or %g0, P_UTRAP11, %g2 ;\ 785 or %g0, T_IDIV0, %g3 ;\ 786 sethi %hi(.check_v9utrap), %g4 ;\ 787 jmp %g4 + %lo(.check_v9utrap) ;\ 788 nop ;\ 789 .align 32 790 791/* 792 * trap instruction for V9 user trap handlers 793 */ 794#define TRAP_INSTR \ 795 TT_TRACE(trace_gen) ;\ 796 or %g0, T_SOFTWARE_TRAP, %g3 ;\ 797 sethi %hi(.check_v9utrap), %g4 ;\ 798 jmp %g4 + %lo(.check_v9utrap) ;\ 799 nop ;\ 800 .align 32 801#define TRP4 TRAP_INSTR; TRAP_INSTR; TRAP_INSTR; TRAP_INSTR 802 803/* 804 * LEVEL_INTERRUPT is for level N interrupts. 805 * VECTOR_INTERRUPT is for the vector trap. 806 */ 807#define LEVEL_INTERRUPT(level) \ 808 .global tt_pil/**/level ;\ 809tt_pil/**/level: ;\ 810 ba,pt %xcc, pil_interrupt ;\ 811 mov level, %g4 ;\ 812 .align 32 813 814#define LEVEL14_INTERRUPT \ 815 ba pil14_interrupt ;\ 816 mov PIL_14, %g4 ;\ 817 .align 32 818 819#define CPU_MONDO \ 820 ba,a,pt %xcc, cpu_mondo ;\ 821 .align 32 822 823#define DEV_MONDO \ 824 ba,a,pt %xcc, dev_mondo ;\ 825 .align 32 826 827/* 828 * MMU Trap Handlers. 829 */ 830 831/* 832 * synthesize for trap(): SFSR in %g3 833 */ 834#define IMMU_EXCEPTION \ 835 MMU_FAULT_STATUS_AREA(%g3) ;\ 836 rdpr %tpc, %g2 ;\ 837 ldx [%g3 + MMFSA_I_TYPE], %g1 ;\ 838 ldx [%g3 + MMFSA_I_CTX], %g3 ;\ 839 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 840 or %g3, %g1, %g3 ;\ 841 ba,pt %xcc, .mmu_exception_end ;\ 842 mov T_INSTR_EXCEPTION, %g1 ;\ 843 .align 32 844 845/* 846 * synthesize for trap(): TAG_ACCESS in %g2, SFSR in %g3 847 */ 848#define DMMU_EXCEPTION \ 849 ba,a,pt %xcc, .dmmu_exception ;\ 850 .align 32 851 852/* 853 * synthesize for trap(): SFAR in %g2, SFSR in %g3 854 */ 855#define DMMU_EXC_AG_PRIV \ 856 MMU_FAULT_STATUS_AREA(%g3) ;\ 857 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 858 /* Fault type not available in MMU fault status area */ ;\ 859 mov MMFSA_F_PRVACT, %g1 ;\ 860 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 861 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 862 ba,pt %xcc, .mmu_priv_exception ;\ 863 or %g3, %g1, %g3 ;\ 864 .align 32 865 866/* 867 * synthesize for trap(): SFAR in %g2, SFSR in %g3 868 */ 869#define DMMU_EXC_AG_NOT_ALIGNED \ 870 MMU_FAULT_STATUS_AREA(%g3) ;\ 871 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 872 /* Fault type not available in MMU fault status area */ ;\ 873 mov MMFSA_F_UNALIGN, %g1 ;\ 874 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 875 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 876 ba,pt %xcc, .mmu_exception_not_aligned ;\ 877 or %g3, %g1, %g3 /* SFSR */ ;\ 878 .align 32 879/* 880 * SPARC V9 IMPL. DEP. #109(1) and (2) and #110(1) and (2) 881 */ 882 883/* 884 * synthesize for trap(): SFAR in %g2, SFSR in %g3 885 */ 886#define DMMU_EXC_LDDF_NOT_ALIGNED \ 887 ba,a,pt %xcc, .dmmu_exc_lddf_not_aligned ;\ 888 .align 32 889/* 890 * synthesize for trap(): SFAR in %g2, SFSR in %g3 891 */ 892#define DMMU_EXC_STDF_NOT_ALIGNED \ 893 ba,a,pt %xcc, .dmmu_exc_stdf_not_aligned ;\ 894 .align 32 895 896#if TAGACC_CTX_MASK != CTXREG_CTX_MASK 897#error "TAGACC_CTX_MASK != CTXREG_CTX_MASK" 898#endif 899 900#if defined(cscope) 901/* 902 * Define labels to direct cscope quickly to labels that 903 * are generated by macro expansion of DTLB_MISS(). 904 */ 905 .global tt0_dtlbmiss 906tt0_dtlbmiss: 907 .global tt1_dtlbmiss 908tt1_dtlbmiss: 909 nop 910#endif 911 912/* 913 * Data miss handler (must be exactly 32 instructions) 914 * 915 * This handler is invoked only if the hypervisor has been instructed 916 * not to do any TSB walk. 917 * 918 * Kernel and invalid context cases are handled by the sfmmu_kdtlb_miss 919 * handler. 920 * 921 * User TLB miss handling depends upon whether a user process has one or 922 * two TSBs. User TSB information (physical base and size code) is kept 923 * in two dedicated scratchpad registers. Absence of a user TSB (primarily 924 * second TSB) is indicated by a negative value (-1) in that register. 925 */ 926 927/* 928 * synthesize for miss handler: TAG_ACCESS in %g2 929 */ 930#define DTLB_MISS(table_name) ;\ 931 .global table_name/**/_dtlbmiss ;\ 932table_name/**/_dtlbmiss: ;\ 933 HAT_PERCPU_DBSTAT(TSBMISS_DTLBMISS) /* 3 instr ifdef DEBUG */ ;\ 934 MMU_FAULT_STATUS_AREA(%g7) ;\ 935 ldx [%g7 + MMFSA_D_ADDR], %g2 /* address */ ;\ 936 ldx [%g7 + MMFSA_D_CTX], %g3 /* g3 = ctx */ ;\ 937 or %g2, %g3, %g2 /* TAG_ACCESS */ ;\ 938 cmp %g3, INVALID_CONTEXT ;\ 939 ble,pn %xcc, sfmmu_kdtlb_miss ;\ 940 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 941 mov SCRATCHPAD_UTSBREG2, %g1 ;\ 942 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\ 943 brgez,pn %g1, sfmmu_udtlb_slowpath /* brnach if 2 TSBs */ ;\ 944 nop ;\ 945 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\ 946 ba,pt %xcc, sfmmu_udtlb_fastpath /* no 4M TSB, miss */ ;\ 947 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 948 .align 128 949 950 951#if defined(cscope) 952/* 953 * Define labels to direct cscope quickly to labels that 954 * are generated by macro expansion of ITLB_MISS(). 955 */ 956 .global tt0_itlbmiss 957tt0_itlbmiss: 958 .global tt1_itlbmiss 959tt1_itlbmiss: 960 nop 961#endif 962 963/* 964 * Instruction miss handler. 965 * 966 * This handler is invoked only if the hypervisor has been instructed 967 * not to do any TSB walk. 968 * 969 * ldda instructions will have their ASI patched 970 * by sfmmu_patch_ktsb at runtime. 971 * MUST be EXACTLY 32 instructions or we'll break. 972 */ 973 974/* 975 * synthesize for miss handler: TAG_ACCESS in %g2 976 */ 977#define ITLB_MISS(table_name) \ 978 .global table_name/**/_itlbmiss ;\ 979table_name/**/_itlbmiss: ;\ 980 HAT_PERCPU_DBSTAT(TSBMISS_ITLBMISS) /* 3 instr ifdef DEBUG */ ;\ 981 MMU_FAULT_STATUS_AREA(%g7) ;\ 982 ldx [%g7 + MMFSA_I_ADDR], %g2 /* g2 = address */ ;\ 983 ldx [%g7 + MMFSA_I_CTX], %g3 /* g3 = ctx */ ;\ 984 or %g2, %g3, %g2 /* TAG_ACCESS */ ;\ 985 cmp %g3, INVALID_CONTEXT ;\ 986 ble,pn %xcc, sfmmu_kitlb_miss ;\ 987 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 988 mov SCRATCHPAD_UTSBREG2, %g1 ;\ 989 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\ 990 brgez,pn %g1, sfmmu_uitlb_slowpath /* branch if 2 TSBS */ ;\ 991 nop ;\ 992 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\ 993 ba,pt %xcc, sfmmu_uitlb_fastpath /* no 4M TSB, miss */ ;\ 994 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 995 .align 128 996 997#define DTSB_MISS \ 998 GOTO_TT(sfmmu_slow_dmmu_miss,trace_dmmu) 999 1000#define ITSB_MISS \ 1001 GOTO_TT(sfmmu_slow_immu_miss,trace_immu) 1002 1003/* 1004 * This macro is the first level handler for fast protection faults. 1005 * It first demaps the tlb entry which generated the fault and then 1006 * attempts to set the modify bit on the hash. It needs to be 1007 * exactly 32 instructions. 1008 */ 1009/* 1010 * synthesize for miss handler: TAG_ACCESS in %g2 1011 */ 1012#define DTLB_PROT \ 1013 MMU_FAULT_STATUS_AREA(%g7) ;\ 1014 ldx [%g7 + MMFSA_D_ADDR], %g2 /* address */ ;\ 1015 ldx [%g7 + MMFSA_D_CTX], %g3 /* %g3 = ctx */ ;\ 1016 or %g2, %g3, %g2 /* TAG_ACCESS */ ;\ 1017 /* ;\ 1018 * g2 = tag access register ;\ 1019 * g3 = ctx number ;\ 1020 */ ;\ 1021 TT_TRACE(trace_dataprot) /* 2 instr ifdef TRAPTRACE */ ;\ 1022 /* clobbers g1 and g6 XXXQ? */ ;\ 1023 brnz,pt %g3, sfmmu_uprot_trap /* user trap */ ;\ 1024 nop ;\ 1025 ba,a,pt %xcc, sfmmu_kprot_trap /* kernel trap */ ;\ 1026 .align 128 1027 1028#define DMMU_EXCEPTION_TL1 ;\ 1029 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1030 .align 32 1031 1032#define MISALIGN_ADDR_TL1 ;\ 1033 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1034 .align 32 1035 1036/* 1037 * Trace a tsb hit 1038 * g1 = tsbe pointer (in/clobbered) 1039 * g2 = tag access register (in) 1040 * g3 - g4 = scratch (clobbered) 1041 * g5 = tsbe data (in) 1042 * g6 = scratch (clobbered) 1043 * g7 = pc we jumped here from (in) 1044 * ttextra = value to OR in to trap type (%tt) (in) 1045 */ 1046#ifdef TRAPTRACE 1047#define TRACE_TSBHIT(ttextra) \ 1048 membar #Sync ;\ 1049 sethi %hi(FLUSH_ADDR), %g6 ;\ 1050 flush %g6 ;\ 1051 TRACE_PTR(%g3, %g6) ;\ 1052 GET_TRACE_TICK(%g6) ;\ 1053 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi ;\ 1054 stna %g2, [%g3 + TRAP_ENT_SP]%asi /* tag access */ ;\ 1055 stna %g5, [%g3 + TRAP_ENT_F1]%asi /* tsb data */ ;\ 1056 rdpr %tnpc, %g6 ;\ 1057 stna %g6, [%g3 + TRAP_ENT_F2]%asi ;\ 1058 stna %g1, [%g3 + TRAP_ENT_F3]%asi /* tsb pointer */ ;\ 1059 stna %g0, [%g3 + TRAP_ENT_F4]%asi ;\ 1060 rdpr %tpc, %g6 ;\ 1061 stna %g6, [%g3 + TRAP_ENT_TPC]%asi ;\ 1062 TRACE_SAVE_TL_GL_REGS(%g3, %g6) ;\ 1063 rdpr %tt, %g6 ;\ 1064 or %g6, (ttextra), %g1 ;\ 1065 stha %g1, [%g3 + TRAP_ENT_TT]%asi ;\ 1066 MMU_FAULT_STATUS_AREA(%g4) ;\ 1067 mov MMFSA_D_ADDR, %g1 ;\ 1068 cmp %g6, FAST_IMMU_MISS_TT ;\ 1069 move %xcc, MMFSA_I_ADDR, %g1 ;\ 1070 cmp %g6, T_INSTR_MMU_MISS ;\ 1071 move %xcc, MMFSA_I_ADDR, %g1 ;\ 1072 ldx [%g4 + %g1], %g1 ;\ 1073 stxa %g1, [%g3 + TRAP_ENT_TSTATE]%asi /* fault addr */ ;\ 1074 mov MMFSA_D_CTX, %g1 ;\ 1075 cmp %g6, FAST_IMMU_MISS_TT ;\ 1076 move %xcc, MMFSA_I_CTX, %g1 ;\ 1077 cmp %g6, T_INSTR_MMU_MISS ;\ 1078 move %xcc, MMFSA_I_CTX, %g1 ;\ 1079 ldx [%g4 + %g1], %g1 ;\ 1080 stna %g1, [%g3 + TRAP_ENT_TR]%asi ;\ 1081 TRACE_NEXT(%g3, %g4, %g6) 1082#else 1083#define TRACE_TSBHIT(ttextra) 1084#endif 1085 1086 1087#if defined(lint) 1088 1089struct scb trap_table; 1090struct scb scb; /* trap_table/scb are the same object */ 1091 1092#else /* lint */ 1093 1094/* 1095 * ======================================================================= 1096 * SPARC V9 TRAP TABLE 1097 * 1098 * The trap table is divided into two halves: the first half is used when 1099 * taking traps when TL=0; the second half is used when taking traps from 1100 * TL>0. Note that handlers in the second half of the table might not be able 1101 * to make the same assumptions as handlers in the first half of the table. 1102 * 1103 * Worst case trap nesting so far: 1104 * 1105 * at TL=0 client issues software trap requesting service 1106 * at TL=1 nucleus wants a register window 1107 * at TL=2 register window clean/spill/fill takes a TLB miss 1108 * at TL=3 processing TLB miss 1109 * at TL=4 handle asynchronous error 1110 * 1111 * Note that a trap from TL=4 to TL=5 places Spitfire in "RED mode". 1112 * 1113 * ======================================================================= 1114 */ 1115 .section ".text" 1116 .align 4 1117 .global trap_table, scb, trap_table0, trap_table1, etrap_table 1118 .type trap_table, #function 1119 .type trap_table0, #function 1120 .type trap_table1, #function 1121 .type scb, #function 1122trap_table: 1123scb: 1124trap_table0: 1125 /* hardware traps */ 1126 NOT; /* 000 reserved */ 1127 RED; /* 001 power on reset */ 1128 RED; /* 002 watchdog reset */ 1129 RED; /* 003 externally initiated reset */ 1130 RED; /* 004 software initiated reset */ 1131 RED; /* 005 red mode exception */ 1132 NOT; NOT; /* 006 - 007 reserved */ 1133 IMMU_EXCEPTION; /* 008 instruction access exception */ 1134 ITSB_MISS; /* 009 instruction access MMU miss */ 1135 NOT; /* 00A reserved */ 1136 NOT; NOT4; /* 00B - 00F reserved */ 1137 ILLTRAP_INSTR; /* 010 illegal instruction */ 1138 TRAP(T_PRIV_INSTR); /* 011 privileged opcode */ 1139 TRAP(T_UNIMP_LDD); /* 012 unimplemented LDD */ 1140 TRAP(T_UNIMP_STD); /* 013 unimplemented STD */ 1141 NOT4; NOT4; NOT4; /* 014 - 01F reserved */ 1142 FP_DISABLED_TRAP; /* 020 fp disabled */ 1143 FP_IEEE_TRAP; /* 021 fp exception ieee 754 */ 1144 FP_TRAP; /* 022 fp exception other */ 1145 TAG_OVERFLOW; /* 023 tag overflow */ 1146 CLEAN_WINDOW; /* 024 - 027 clean window */ 1147 DIV_BY_ZERO; /* 028 division by zero */ 1148 NOT; /* 029 internal processor error */ 1149 NOT; NOT; NOT4; /* 02A - 02F reserved */ 1150 DMMU_EXCEPTION; /* 030 data access exception */ 1151 DTSB_MISS; /* 031 data access MMU miss */ 1152 NOT; /* 032 reserved */ 1153 NOT; /* 033 data access protection */ 1154 DMMU_EXC_AG_NOT_ALIGNED; /* 034 mem address not aligned */ 1155 DMMU_EXC_LDDF_NOT_ALIGNED; /* 035 LDDF mem address not aligned */ 1156 DMMU_EXC_STDF_NOT_ALIGNED; /* 036 STDF mem address not aligned */ 1157 DMMU_EXC_AG_PRIV; /* 037 privileged action */ 1158 NOT; /* 038 LDQF mem address not aligned */ 1159 NOT; /* 039 STQF mem address not aligned */ 1160 NOT; NOT; NOT4; /* 03A - 03F reserved */ 1161 NOT; /* 040 async data error */ 1162 LEVEL_INTERRUPT(1); /* 041 interrupt level 1 */ 1163 LEVEL_INTERRUPT(2); /* 042 interrupt level 2 */ 1164 LEVEL_INTERRUPT(3); /* 043 interrupt level 3 */ 1165 LEVEL_INTERRUPT(4); /* 044 interrupt level 4 */ 1166 LEVEL_INTERRUPT(5); /* 045 interrupt level 5 */ 1167 LEVEL_INTERRUPT(6); /* 046 interrupt level 6 */ 1168 LEVEL_INTERRUPT(7); /* 047 interrupt level 7 */ 1169 LEVEL_INTERRUPT(8); /* 048 interrupt level 8 */ 1170 LEVEL_INTERRUPT(9); /* 049 interrupt level 9 */ 1171 LEVEL_INTERRUPT(10); /* 04A interrupt level 10 */ 1172 LEVEL_INTERRUPT(11); /* 04B interrupt level 11 */ 1173 LEVEL_INTERRUPT(12); /* 04C interrupt level 12 */ 1174 LEVEL_INTERRUPT(13); /* 04D interrupt level 13 */ 1175 LEVEL14_INTERRUPT; /* 04E interrupt level 14 */ 1176 LEVEL_INTERRUPT(15); /* 04F interrupt level 15 */ 1177 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F reserved */ 1178 NOT; /* 060 interrupt vector */ 1179 GOTO(kmdb_trap); /* 061 PA watchpoint */ 1180 GOTO(kmdb_trap); /* 062 VA watchpoint */ 1181 NOT; /* 063 reserved */ 1182 ITLB_MISS(tt0); /* 064 instruction access MMU miss */ 1183 DTLB_MISS(tt0); /* 068 data access MMU miss */ 1184 DTLB_PROT; /* 06C data access protection */ 1185 NOT; /* 070 reserved */ 1186 NOT; /* 071 reserved */ 1187 NOT; /* 072 reserved */ 1188 NOT; /* 073 reserved */ 1189 NOT4; NOT4 /* 074 - 07B reserved */ 1190 CPU_MONDO; /* 07C cpu_mondo */ 1191 DEV_MONDO; /* 07D dev_mondo */ 1192 GOTO_TT(resumable_error, trace_gen); /* 07E resumable error */ 1193 GOTO_TT(nonresumable_error, trace_gen); /* 07F non-reasumable error */ 1194 NOT4; /* 080 spill 0 normal */ 1195 SPILL_32bit_asi(ASI_AIUP,sn0); /* 084 spill 1 normal */ 1196 SPILL_64bit_asi(ASI_AIUP,sn0); /* 088 spill 2 normal */ 1197 SPILL_32clean(ASI_AIUP,sn0); /* 08C spill 3 normal */ 1198 SPILL_64clean(ASI_AIUP,sn0); /* 090 spill 4 normal */ 1199 SPILL_32bit(not); /* 094 spill 5 normal */ 1200 SPILL_64bit(not); /* 098 spill 6 normal */ 1201 SPILL_mixed; /* 09C spill 7 normal */ 1202 NOT4; /* 0A0 spill 0 other */ 1203 SPILL_32bit_asi(ASI_AIUS,so0); /* 0A4 spill 1 other */ 1204 SPILL_64bit_asi(ASI_AIUS,so0); /* 0A8 spill 2 other */ 1205 SPILL_32bit_asi(ASI_AIUS,so0); /* 0AC spill 3 other */ 1206 SPILL_64bit_asi(ASI_AIUS,so0); /* 0B0 spill 4 other */ 1207 NOT4; /* 0B4 spill 5 other */ 1208 NOT4; /* 0B8 spill 6 other */ 1209 NOT4; /* 0BC spill 7 other */ 1210 NOT4; /* 0C0 fill 0 normal */ 1211 FILL_32bit_asi(ASI_AIUP,fn0); /* 0C4 fill 1 normal */ 1212 FILL_64bit_asi(ASI_AIUP,fn0); /* 0C8 fill 2 normal */ 1213 FILL_32bit_asi(ASI_AIUP,fn0); /* 0CC fill 3 normal */ 1214 FILL_64bit_asi(ASI_AIUP,fn0); /* 0D0 fill 4 normal */ 1215 FILL_32bit(not); /* 0D4 fill 5 normal */ 1216 FILL_64bit(not); /* 0D8 fill 6 normal */ 1217 FILL_mixed; /* 0DC fill 7 normal */ 1218 NOT4; /* 0E0 fill 0 other */ 1219 NOT4; /* 0E4 fill 1 other */ 1220 NOT4; /* 0E8 fill 2 other */ 1221 NOT4; /* 0EC fill 3 other */ 1222 NOT4; /* 0F0 fill 4 other */ 1223 NOT4; /* 0F4 fill 5 other */ 1224 NOT4; /* 0F8 fill 6 other */ 1225 NOT4; /* 0FC fill 7 other */ 1226 /* user traps */ 1227 GOTO(syscall_trap_4x); /* 100 old system call */ 1228 TRAP(T_BREAKPOINT); /* 101 user breakpoint */ 1229 TRAP(T_DIV0); /* 102 user divide by zero */ 1230 GOTO(.flushw); /* 103 flush windows */ 1231 GOTO(.clean_windows); /* 104 clean windows */ 1232 BAD; /* 105 range check ?? */ 1233 GOTO(.fix_alignment); /* 106 do unaligned references */ 1234 BAD; /* 107 unused */ 1235 SYSCALL(syscall_trap32); /* 108 ILP32 system call on LP64 */ 1236 GOTO(set_trap0_addr); /* 109 set trap0 address */ 1237 BAD; BAD; BAD4; /* 10A - 10F unused */ 1238 TRP4; TRP4; TRP4; TRP4; /* 110 - 11F V9 user trap handlers */ 1239 GOTO(.getcc); /* 120 get condition codes */ 1240 GOTO(.setcc); /* 121 set condition codes */ 1241 GOTO(.getpsr); /* 122 get psr */ 1242 GOTO(.setpsr); /* 123 set psr (some fields) */ 1243 GOTO(get_timestamp); /* 124 get timestamp */ 1244 GOTO(get_virtime); /* 125 get lwp virtual time */ 1245 PRIV(self_xcall); /* 126 self xcall */ 1246 GOTO(get_hrestime); /* 127 get hrestime */ 1247 BAD; /* 128 ST_SETV9STACK */ 1248 GOTO(.getlgrp); /* 129 get lgrpid */ 1249 BAD; BAD; BAD4; /* 12A - 12F unused */ 1250 BAD4; BAD4; /* 130 - 137 unused */ 1251 DTRACE_PID; /* 138 dtrace pid tracing provider */ 1252 DTRACE_FASTTRAP; /* 139 dtrace fasttrap provider */ 1253 DTRACE_RETURN; /* 13A dtrace pid return probe */ 1254 BAD; BAD4; /* 13B - 13F unused */ 1255 SYSCALL(syscall_trap) /* 140 LP64 system call */ 1256 BAD; /* 141 unused */ 1257#ifdef DEBUG_USER_TRAPTRACECTL 1258 GOTO(.traptrace_freeze); /* 142 freeze traptrace */ 1259 GOTO(.traptrace_unfreeze); /* 143 unfreeze traptrace */ 1260#else 1261 BAD; BAD; /* 142 - 143 unused */ 1262#endif 1263 BAD4; BAD4; BAD4; /* 144 - 14F unused */ 1264 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1265 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1266 BAD; /* 170 - unused */ 1267 BAD; /* 171 - unused */ 1268 BAD; BAD; /* 172 - 173 unused */ 1269 BAD4; BAD4; /* 174 - 17B unused */ 1270#ifdef PTL1_PANIC_DEBUG 1271 mov PTL1_BAD_DEBUG, %g1; GOTO(ptl1_panic); 1272 /* 17C test ptl1_panic */ 1273#else 1274 BAD; /* 17C unused */ 1275#endif /* PTL1_PANIC_DEBUG */ 1276 PRIV(kmdb_trap); /* 17D kmdb enter (L1-A) */ 1277 PRIV(kmdb_trap); /* 17E kmdb breakpoint */ 1278 PRIV(obp_bpt); /* 17F obp breakpoint */ 1279 /* reserved */ 1280 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1281 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1282 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1283 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1284 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1285 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1286 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1287 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1288 .size trap_table0, (.-trap_table0) 1289trap_table1: 1290 NOT4; NOT4; /* 000 - 007 unused */ 1291 NOT; /* 008 instruction access exception */ 1292 ITSB_MISS; /* 009 instruction access MMU miss */ 1293 NOT; /* 00A reserved */ 1294 NOT; NOT4; /* 00B - 00F unused */ 1295 NOT4; NOT4; NOT4; NOT4; /* 010 - 01F unused */ 1296 NOT4; /* 020 - 023 unused */ 1297 CLEAN_WINDOW; /* 024 - 027 clean window */ 1298 NOT4; NOT4; /* 028 - 02F unused */ 1299 DMMU_EXCEPTION_TL1; /* 030 data access exception */ 1300 DTSB_MISS; /* 031 data access MMU miss */ 1301 NOT; /* 032 reserved */ 1302 NOT; /* 033 unused */ 1303 MISALIGN_ADDR_TL1; /* 034 mem address not aligned */ 1304 NOT; NOT; NOT; NOT4; NOT4 /* 035 - 03F unused */ 1305 NOT4; NOT4; NOT4; NOT4; /* 040 - 04F unused */ 1306 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F unused */ 1307 NOT; /* 060 unused */ 1308 GOTO(kmdb_trap_tl1); /* 061 PA watchpoint */ 1309 GOTO(kmdb_trap_tl1); /* 062 VA watchpoint */ 1310 NOT; /* 063 reserved */ 1311 ITLB_MISS(tt1); /* 064 instruction access MMU miss */ 1312 DTLB_MISS(tt1); /* 068 data access MMU miss */ 1313 DTLB_PROT; /* 06C data access protection */ 1314 NOT; /* 070 reserved */ 1315 NOT; /* 071 reserved */ 1316 NOT; /* 072 reserved */ 1317 NOT; /* 073 reserved */ 1318 NOT4; NOT4; /* 074 - 07B reserved */ 1319 NOT; /* 07C reserved */ 1320 NOT; /* 07D reserved */ 1321 NOT; /* 07E resumable error */ 1322 GOTO_TT(nonresumable_error, trace_gen); /* 07F nonresumable error */ 1323 NOTP4; /* 080 spill 0 normal */ 1324 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 084 spill 1 normal */ 1325 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 088 spill 2 normal */ 1326 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 08C spill 3 normal */ 1327 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 090 spill 4 normal */ 1328 NOTP4; /* 094 spill 5 normal */ 1329 SPILL_64bit_ktt1(sk); /* 098 spill 6 normal */ 1330 SPILL_mixed_ktt1(sk); /* 09C spill 7 normal */ 1331 NOTP4; /* 0A0 spill 0 other */ 1332 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0A4 spill 1 other */ 1333 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0A8 spill 2 other */ 1334 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0AC spill 3 other */ 1335 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0B0 spill 4 other */ 1336 NOTP4; /* 0B4 spill 5 other */ 1337 NOTP4; /* 0B8 spill 6 other */ 1338 NOTP4; /* 0BC spill 7 other */ 1339 NOT4; /* 0C0 fill 0 normal */ 1340 NOT4; /* 0C4 fill 1 normal */ 1341 NOT4; /* 0C8 fill 2 normal */ 1342 NOT4; /* 0CC fill 3 normal */ 1343 NOT4; /* 0D0 fill 4 normal */ 1344 NOT4; /* 0D4 fill 5 normal */ 1345 NOT4; /* 0D8 fill 6 normal */ 1346 NOT4; /* 0DC fill 7 normal */ 1347 NOT4; NOT4; NOT4; NOT4; /* 0E0 - 0EF unused */ 1348 NOT4; NOT4; NOT4; NOT4; /* 0F0 - 0FF unused */ 1349/* 1350 * Code running at TL>0 does not use soft traps, so 1351 * we can truncate the table here. 1352 * However: 1353 * sun4v uses (hypervisor) ta instructions at TL > 0, so 1354 * provide a safety net for now. 1355 */ 1356 /* soft traps */ 1357 BAD4; BAD4; BAD4; BAD4; /* 100 - 10F unused */ 1358 BAD4; BAD4; BAD4; BAD4; /* 110 - 11F unused */ 1359 BAD4; BAD4; BAD4; BAD4; /* 120 - 12F unused */ 1360 BAD4; BAD4; BAD4; BAD4; /* 130 - 13F unused */ 1361 BAD4; BAD4; BAD4; BAD4; /* 140 - 14F unused */ 1362 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1363 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1364 BAD4; BAD4; BAD4; BAD4; /* 170 - 17F unused */ 1365 /* reserved */ 1366 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1367 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1368 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1369 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1370 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1371 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1372 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1373 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1374etrap_table: 1375 .size trap_table1, (.-trap_table1) 1376 .size trap_table, (.-trap_table) 1377 .size scb, (.-scb) 1378 1379/* 1380 * We get to exec_fault in the case of an instruction miss and tte 1381 * has no execute bit set. We go to tl0 to handle it. 1382 * 1383 * g1 = tsbe pointer (in/clobbered) 1384 * g2 = tag access register (in) 1385 * g3 - g4 = scratch (clobbered) 1386 * g5 = tsbe data (in) 1387 * g6 = scratch (clobbered) 1388 * g7 = pc we jumped here from (in) 1389 */ 1390/* 1391 * synthesize for trap(): TAG_ACCESS in %g2 1392 */ 1393 ALTENTRY(exec_fault) 1394 TRACE_TSBHIT(TT_MMU_EXEC) 1395 MMU_FAULT_STATUS_AREA(%g4) 1396 ldx [%g4 + MMFSA_I_ADDR], %g2 /* g2 = address */ 1397 ldx [%g4 + MMFSA_I_CTX], %g3 /* g3 = ctx */ 1398 srlx %g2, MMU_PAGESHIFT, %g2 ! align address to page boundry 1399 sllx %g2, MMU_PAGESHIFT, %g2 1400 or %g2, %g3, %g2 /* TAG_ACCESS */ 1401 mov T_INSTR_MMU_MISS, %g3 ! arg2 = traptype 1402 set trap, %g1 1403 ba,pt %xcc, sys_trap 1404 mov -1, %g4 1405 1406.mmu_exception_not_aligned: 1407 /* %g2 = sfar, %g3 = sfsr */ 1408 rdpr %tstate, %g1 1409 btst TSTATE_PRIV, %g1 1410 bnz,pn %icc, 2f 1411 nop 1412 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1413 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1414 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1415 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1416 brz,pt %g5, 2f 1417 nop 1418 ldn [%g5 + P_UTRAP15], %g5 ! unaligned utrap? 1419 brz,pn %g5, 2f 1420 nop 1421 btst 1, %sp 1422 bz,pt %xcc, 1f ! 32 bit user program 1423 nop 1424 ba,pt %xcc, .setup_v9utrap ! 64 bit user program 1425 nop 14261: 1427 ba,pt %xcc, .setup_utrap 1428 or %g2, %g0, %g7 14292: 1430 ba,pt %xcc, .mmu_exception_end 1431 mov T_ALIGNMENT, %g1 1432 1433.mmu_priv_exception: 1434 rdpr %tstate, %g1 1435 btst TSTATE_PRIV, %g1 1436 bnz,pn %icc, 1f 1437 nop 1438 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1439 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1440 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1441 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1442 brz,pt %g5, 1f 1443 nop 1444 ldn [%g5 + P_UTRAP16], %g5 1445 brnz,pt %g5, .setup_v9utrap 1446 nop 14471: 1448 mov T_PRIV_INSTR, %g1 1449 1450.mmu_exception_end: 1451 CPU_INDEX(%g4, %g5) 1452 set cpu_core, %g5 1453 sllx %g4, CPU_CORE_SHIFT, %g4 1454 add %g4, %g5, %g4 1455 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5 1456 andcc %g5, CPU_DTRACE_NOFAULT, %g0 1457 bz 1f 1458 or %g5, CPU_DTRACE_BADADDR, %g5 1459 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS] 1460 done 1461 14621: 1463 sllx %g3, 32, %g3 1464 or %g3, %g1, %g3 1465 set trap, %g1 1466 ba,pt %xcc, sys_trap 1467 sub %g0, 1, %g4 1468 1469.fp_disabled: 1470 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1471 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1472 rdpr %tstate, %g4 1473 btst TSTATE_PRIV, %g4 1474 bnz,a,pn %icc, ptl1_panic 1475 mov PTL1_BAD_FPTRAP, %g1 1476 1477 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1478 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1479 brz,a,pt %g5, 2f 1480 nop 1481 ldn [%g5 + P_UTRAP7], %g5 ! fp_disabled utrap? 1482 brz,a,pn %g5, 2f 1483 nop 1484 btst 1, %sp 1485 bz,a,pt %xcc, 1f ! 32 bit user program 1486 nop 1487 ba,a,pt %xcc, .setup_v9utrap ! 64 bit user program 1488 nop 14891: 1490 ba,pt %xcc, .setup_utrap 1491 or %g0, %g0, %g7 14922: 1493 set fp_disabled, %g1 1494 ba,pt %xcc, sys_trap 1495 sub %g0, 1, %g4 1496 1497.fp_ieee_exception: 1498 rdpr %tstate, %g1 1499 btst TSTATE_PRIV, %g1 1500 bnz,a,pn %icc, ptl1_panic 1501 mov PTL1_BAD_FPTRAP, %g1 1502 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1503 stx %fsr, [%g1 + CPU_TMP1] 1504 ldx [%g1 + CPU_TMP1], %g2 1505 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1506 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1507 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1508 brz,a,pt %g5, 1f 1509 nop 1510 ldn [%g5 + P_UTRAP8], %g5 1511 brnz,a,pt %g5, .setup_v9utrap 1512 nop 15131: 1514 set _fp_ieee_exception, %g1 1515 ba,pt %xcc, sys_trap 1516 sub %g0, 1, %g4 1517 1518/* 1519 * Register Inputs: 1520 * %g5 user trap handler 1521 * %g7 misaligned addr - for alignment traps only 1522 */ 1523.setup_utrap: 1524 set trap, %g1 ! setup in case we go 1525 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1526 sub %g0, 1, %g4 ! the save instruction below 1527 1528 /* 1529 * If the DTrace pid provider is single stepping a copied-out 1530 * instruction, t->t_dtrace_step will be set. In that case we need 1531 * to abort the single-stepping (since execution of the instruction 1532 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1533 */ 1534 save %sp, -SA(MINFRAME32), %sp ! window for trap handler 1535 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1536 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1537 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1538 rdpr %tnpc, %l2 ! arg1 == tnpc 1539 brz,pt %g2, 1f 1540 rdpr %tpc, %l1 ! arg0 == tpc 1541 1542 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1543 ldn [%g1 + T_DTRACE_NPC], %l2 ! arg1 = t->t_dtrace_npc (step) 1544 brz,pt %g2, 1f 1545 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1546 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 15471: 1548 mov %g7, %l3 ! arg2 == misaligned address 1549 1550 rdpr %tstate, %g1 ! cwp for trap handler 1551 rdpr %cwp, %g4 1552 bclr TSTATE_CWP_MASK, %g1 1553 wrpr %g1, %g4, %tstate 1554 wrpr %g0, %g5, %tnpc ! trap handler address 1555 FAST_TRAP_DONE 1556 /* NOTREACHED */ 1557 1558.check_v9utrap: 1559 rdpr %tstate, %g1 1560 btst TSTATE_PRIV, %g1 1561 bnz,a,pn %icc, 3f 1562 nop 1563 CPU_ADDR(%g4, %g1) ! load CPU struct addr 1564 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer 1565 ldn [%g5 + T_PROCP], %g5 ! load proc pointer 1566 ldn [%g5 + P_UTRAPS], %g5 ! are there utraps? 1567 1568 cmp %g3, T_SOFTWARE_TRAP 1569 bne,a,pt %icc, 1f 1570 nop 1571 1572 brz,pt %g5, 3f ! if p_utraps == NULL goto trap() 1573 rdpr %tt, %g3 ! delay - get actual hw trap type 1574 1575 sub %g3, 254, %g1 ! UT_TRAP_INSTRUCTION_16 = p_utraps[18] 1576 ba,pt %icc, 2f 1577 smul %g1, CPTRSIZE, %g2 15781: 1579 brz,a,pt %g5, 3f ! if p_utraps == NULL goto trap() 1580 nop 1581 1582 cmp %g3, T_UNIMP_INSTR 1583 bne,a,pt %icc, 2f 1584 nop 1585 1586 mov 1, %g1 1587 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR 1588 rdpr %tpc, %g1 ! ld trapping instruction using 1589 lduwa [%g1]ASI_AIUP, %g1 ! "AS IF USER" ASI which could fault 1590 st %g0, [%g4 + CPU_TL1_HDLR] ! clr CPU_TL1_HDLR 1591 1592 sethi %hi(0xc1c00000), %g4 ! setup mask for illtrap instruction 1593 andcc %g1, %g4, %g4 ! and instruction with mask 1594 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP 1595 nop ! fall thru to setup 15962: 1597 ldn [%g5 + %g2], %g5 1598 brnz,a,pt %g5, .setup_v9utrap 1599 nop 16003: 1601 set trap, %g1 1602 ba,pt %xcc, sys_trap 1603 sub %g0, 1, %g4 1604 /* NOTREACHED */ 1605 1606/* 1607 * Register Inputs: 1608 * %g5 user trap handler 1609 */ 1610.setup_v9utrap: 1611 set trap, %g1 ! setup in case we go 1612 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1613 sub %g0, 1, %g4 ! the save instruction below 1614 1615 /* 1616 * If the DTrace pid provider is single stepping a copied-out 1617 * instruction, t->t_dtrace_step will be set. In that case we need 1618 * to abort the single-stepping (since execution of the instruction 1619 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1620 */ 1621 save %sp, -SA(MINFRAME64), %sp ! window for trap handler 1622 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1623 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1624 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1625 rdpr %tnpc, %l7 ! arg1 == tnpc 1626 brz,pt %g2, 1f 1627 rdpr %tpc, %l6 ! arg0 == tpc 1628 1629 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1630 ldn [%g1 + T_DTRACE_NPC], %l7 ! arg1 == t->t_dtrace_npc (step) 1631 brz,pt %g2, 1f 1632 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1633 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 16341: 1635 rdpr %tstate, %g2 ! cwp for trap handler 1636 rdpr %cwp, %g4 1637 bclr TSTATE_CWP_MASK, %g2 1638 wrpr %g2, %g4, %tstate 1639 1640 ldn [%g1 + T_PROCP], %g4 ! load proc pointer 1641 ldn [%g4 + P_AS], %g4 ! load as pointer 1642 ldn [%g4 + A_USERLIMIT], %g4 ! load as userlimit 1643 cmp %l7, %g4 ! check for single-step set 1644 bne,pt %xcc, 4f 1645 nop 1646 ldn [%g1 + T_LWP], %g1 ! load klwp pointer 1647 ld [%g1 + PCB_STEP], %g4 ! load single-step flag 1648 cmp %g4, STEP_ACTIVE ! step flags set in pcb? 1649 bne,pt %icc, 4f 1650 nop 1651 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb 1652 mov %l7, %g4 ! on entry to precise user trap 1653 add %l6, 4, %l7 ! handler, %l6 == pc, %l7 == npc 1654 ! at time of trap 1655 wrpr %g0, %g4, %tnpc ! generate FLTBOUNDS, 1656 ! %g4 == userlimit 1657 FAST_TRAP_DONE 1658 /* NOTREACHED */ 16594: 1660 wrpr %g0, %g5, %tnpc ! trap handler address 1661 FAST_TRAP_DONE_CHK_INTR 1662 /* NOTREACHED */ 1663 1664.fp_exception: 1665 CPU_ADDR(%g1, %g4) 1666 stx %fsr, [%g1 + CPU_TMP1] 1667 ldx [%g1 + CPU_TMP1], %g2 1668 1669 /* 1670 * Cheetah takes unfinished_FPop trap for certain range of operands 1671 * to the "fitos" instruction. Instead of going through the slow 1672 * software emulation path, we try to simulate the "fitos" instruction 1673 * via "fitod" and "fdtos" provided the following conditions are met: 1674 * 1675 * fpu_exists is set (if DEBUG) 1676 * not in privileged mode 1677 * ftt is unfinished_FPop 1678 * NXM IEEE trap is not enabled 1679 * instruction at %tpc is "fitos" 1680 * 1681 * Usage: 1682 * %g1 per cpu address 1683 * %g2 %fsr 1684 * %g6 user instruction 1685 * 1686 * Note that we can take a memory access related trap while trying 1687 * to fetch the user instruction. Therefore, we set CPU_TL1_HDLR 1688 * flag to catch those traps and let the SFMMU code deal with page 1689 * fault and data access exception. 1690 */ 1691#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 1692 sethi %hi(fpu_exists), %g7 1693 ld [%g7 + %lo(fpu_exists)], %g7 1694 brz,pn %g7, .fp_exception_cont 1695 nop 1696#endif 1697 rdpr %tstate, %g7 ! branch if in privileged mode 1698 btst TSTATE_PRIV, %g7 1699 bnz,pn %xcc, .fp_exception_cont 1700 srl %g2, FSR_FTT_SHIFT, %g7 ! extract ftt from %fsr 1701 and %g7, (FSR_FTT>>FSR_FTT_SHIFT), %g7 1702 cmp %g7, FTT_UNFIN 1703 set FSR_TEM_NX, %g5 1704 bne,pn %xcc, .fp_exception_cont ! branch if NOT unfinished_FPop 1705 andcc %g2, %g5, %g0 1706 bne,pn %xcc, .fp_exception_cont ! branch if FSR_TEM_NX enabled 1707 rdpr %tpc, %g5 ! get faulting PC 1708 1709 or %g0, 1, %g7 1710 st %g7, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 1711 lda [%g5]ASI_USER, %g6 ! get user's instruction 1712 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 1713 1714 set FITOS_INSTR_MASK, %g7 1715 and %g6, %g7, %g7 1716 set FITOS_INSTR, %g5 1717 cmp %g7, %g5 1718 bne,pn %xcc, .fp_exception_cont ! branch if not FITOS_INSTR 1719 nop 1720 1721 /* 1722 * This is unfinished FPops trap for "fitos" instruction. We 1723 * need to simulate "fitos" via "fitod" and "fdtos" instruction 1724 * sequence. 1725 * 1726 * We need a temporary FP register to do the conversion. Since 1727 * both source and destination operands for the "fitos" instruction 1728 * have to be within %f0-%f31, we use an FP register from the upper 1729 * half to guarantee that it won't collide with the source or the 1730 * dest operand. However, we do have to save and restore its value. 1731 * 1732 * We use %d62 as a temporary FP register for the conversion and 1733 * branch to appropriate instruction within the conversion tables 1734 * based upon the rs2 and rd values. 1735 */ 1736 1737 std %d62, [%g1 + CPU_TMP1] ! save original value 1738 1739 srl %g6, FITOS_RS2_SHIFT, %g7 1740 and %g7, FITOS_REG_MASK, %g7 1741 set _fitos_fitod_table, %g4 1742 sllx %g7, 2, %g7 1743 jmp %g4 + %g7 1744 ba,pt %xcc, _fitos_fitod_done 1745 .empty 1746 1747_fitos_fitod_table: 1748 fitod %f0, %d62 1749 fitod %f1, %d62 1750 fitod %f2, %d62 1751 fitod %f3, %d62 1752 fitod %f4, %d62 1753 fitod %f5, %d62 1754 fitod %f6, %d62 1755 fitod %f7, %d62 1756 fitod %f8, %d62 1757 fitod %f9, %d62 1758 fitod %f10, %d62 1759 fitod %f11, %d62 1760 fitod %f12, %d62 1761 fitod %f13, %d62 1762 fitod %f14, %d62 1763 fitod %f15, %d62 1764 fitod %f16, %d62 1765 fitod %f17, %d62 1766 fitod %f18, %d62 1767 fitod %f19, %d62 1768 fitod %f20, %d62 1769 fitod %f21, %d62 1770 fitod %f22, %d62 1771 fitod %f23, %d62 1772 fitod %f24, %d62 1773 fitod %f25, %d62 1774 fitod %f26, %d62 1775 fitod %f27, %d62 1776 fitod %f28, %d62 1777 fitod %f29, %d62 1778 fitod %f30, %d62 1779 fitod %f31, %d62 1780_fitos_fitod_done: 1781 1782 /* 1783 * Now convert data back into single precision 1784 */ 1785 srl %g6, FITOS_RD_SHIFT, %g7 1786 and %g7, FITOS_REG_MASK, %g7 1787 set _fitos_fdtos_table, %g4 1788 sllx %g7, 2, %g7 1789 jmp %g4 + %g7 1790 ba,pt %xcc, _fitos_fdtos_done 1791 .empty 1792 1793_fitos_fdtos_table: 1794 fdtos %d62, %f0 1795 fdtos %d62, %f1 1796 fdtos %d62, %f2 1797 fdtos %d62, %f3 1798 fdtos %d62, %f4 1799 fdtos %d62, %f5 1800 fdtos %d62, %f6 1801 fdtos %d62, %f7 1802 fdtos %d62, %f8 1803 fdtos %d62, %f9 1804 fdtos %d62, %f10 1805 fdtos %d62, %f11 1806 fdtos %d62, %f12 1807 fdtos %d62, %f13 1808 fdtos %d62, %f14 1809 fdtos %d62, %f15 1810 fdtos %d62, %f16 1811 fdtos %d62, %f17 1812 fdtos %d62, %f18 1813 fdtos %d62, %f19 1814 fdtos %d62, %f20 1815 fdtos %d62, %f21 1816 fdtos %d62, %f22 1817 fdtos %d62, %f23 1818 fdtos %d62, %f24 1819 fdtos %d62, %f25 1820 fdtos %d62, %f26 1821 fdtos %d62, %f27 1822 fdtos %d62, %f28 1823 fdtos %d62, %f29 1824 fdtos %d62, %f30 1825 fdtos %d62, %f31 1826_fitos_fdtos_done: 1827 1828 ldd [%g1 + CPU_TMP1], %d62 ! restore %d62 1829 1830#if DEBUG 1831 /* 1832 * Update FPop_unfinished trap kstat 1833 */ 1834 set fpustat+FPUSTAT_UNFIN_KSTAT, %g7 1835 ldx [%g7], %g5 18361: 1837 add %g5, 1, %g6 1838 1839 casxa [%g7] ASI_N, %g5, %g6 1840 cmp %g5, %g6 1841 bne,a,pn %xcc, 1b 1842 or %g0, %g6, %g5 1843 1844 /* 1845 * Update fpu_sim_fitos kstat 1846 */ 1847 set fpuinfo+FPUINFO_FITOS_KSTAT, %g7 1848 ldx [%g7], %g5 18491: 1850 add %g5, 1, %g6 1851 1852 casxa [%g7] ASI_N, %g5, %g6 1853 cmp %g5, %g6 1854 bne,a,pn %xcc, 1b 1855 or %g0, %g6, %g5 1856#endif /* DEBUG */ 1857 1858 FAST_TRAP_DONE 1859 1860.fp_exception_cont: 1861 /* 1862 * Let _fp_exception deal with simulating FPop instruction. 1863 * Note that we need to pass %fsr in %g2 (already read above). 1864 */ 1865 1866 set _fp_exception, %g1 1867 ba,pt %xcc, sys_trap 1868 sub %g0, 1, %g4 1869 1870 1871/* 1872 * Register windows 1873 */ 1874 1875/* 1876 * FILL_32bit_flushw/FILL_64bit_flushw fills a 32/64-bit-wide register window 1877 * from a 32/64-bit * wide address space via the designated asi. 1878 * It is used to fill windows in user_flushw to avoid going above TL 2. 1879 */ 1880/* TODO: Use the faster FILL based on FILL_32bit_asi/FILL_64bit_asi */ 1881#define FILL_32bit_flushw(asi_num) \ 1882 mov asi_num, %asi ;\ 1883 rdpr %cwp, %g2 ;\ 1884 sub %g2, 1, %g2 ;\ 1885 wrpr %g2, %cwp ;\ 18861: srl %sp, 0, %sp ;\ 1887 lda [%sp + 0]%asi, %l0 ;\ 1888 lda [%sp + 4]%asi, %l1 ;\ 1889 lda [%sp + 8]%asi, %l2 ;\ 1890 lda [%sp + 12]%asi, %l3 ;\ 1891 lda [%sp + 16]%asi, %l4 ;\ 1892 lda [%sp + 20]%asi, %l5 ;\ 1893 lda [%sp + 24]%asi, %l6 ;\ 1894 lda [%sp + 28]%asi, %l7 ;\ 1895 lda [%sp + 32]%asi, %i0 ;\ 1896 lda [%sp + 36]%asi, %i1 ;\ 1897 lda [%sp + 40]%asi, %i2 ;\ 1898 lda [%sp + 44]%asi, %i3 ;\ 1899 lda [%sp + 48]%asi, %i4 ;\ 1900 lda [%sp + 52]%asi, %i5 ;\ 1901 lda [%sp + 56]%asi, %i6 ;\ 1902 lda [%sp + 60]%asi, %i7 ;\ 1903 restored ;\ 1904 add %g2, 1, %g2 ;\ 1905 wrpr %g2, %cwp 1906 1907#define FILL_64bit_flushw(asi_num) \ 1908 mov asi_num, %asi ;\ 1909 rdpr %cwp, %g2 ;\ 1910 sub %g2, 1, %g2 ;\ 1911 wrpr %g2, %cwp ;\ 1912 ldxa [%sp + V9BIAS64 + 0]%asi, %l0 ;\ 1913 ldxa [%sp + V9BIAS64 + 8]%asi, %l1 ;\ 1914 ldxa [%sp + V9BIAS64 + 16]%asi, %l2 ;\ 1915 ldxa [%sp + V9BIAS64 + 24]%asi, %l3 ;\ 1916 ldxa [%sp + V9BIAS64 + 32]%asi, %l4 ;\ 1917 ldxa [%sp + V9BIAS64 + 40]%asi, %l5 ;\ 1918 ldxa [%sp + V9BIAS64 + 48]%asi, %l6 ;\ 1919 ldxa [%sp + V9BIAS64 + 56]%asi, %l7 ;\ 1920 ldxa [%sp + V9BIAS64 + 64]%asi, %i0 ;\ 1921 ldxa [%sp + V9BIAS64 + 72]%asi, %i1 ;\ 1922 ldxa [%sp + V9BIAS64 + 80]%asi, %i2 ;\ 1923 ldxa [%sp + V9BIAS64 + 88]%asi, %i3 ;\ 1924 ldxa [%sp + V9BIAS64 + 96]%asi, %i4 ;\ 1925 ldxa [%sp + V9BIAS64 + 104]%asi, %i5 ;\ 1926 ldxa [%sp + V9BIAS64 + 112]%asi, %i6 ;\ 1927 ldxa [%sp + V9BIAS64 + 120]%asi, %i7 ;\ 1928 restored ;\ 1929 add %g2, 1, %g2 ;\ 1930 wrpr %g2, %cwp 1931 1932.flushw: 1933 rdpr %tnpc, %g1 1934 wrpr %g1, %tpc 1935 add %g1, 4, %g1 1936 wrpr %g1, %tnpc 1937 set trap, %g1 1938 mov T_FLUSH_PCB, %g3 1939 ba,pt %xcc, sys_trap 1940 sub %g0, 1, %g4 1941 1942.clean_windows: 1943 set trap, %g1 1944 mov T_FLUSH_PCB, %g3 1945 sub %g0, 1, %g4 1946 save 1947 flushw 1948 rdpr %canrestore, %g2 1949 brnz %g2, 1f 1950 nop 1951 rdpr %wstate, %g2 1952 btst 1, %g2 1953 beq 2f 1954 nop 1955 FILL_32bit_flushw(ASI_AIUP) 1956 ba,a 1f 1957 .empty 19582: 1959 FILL_64bit_flushw(ASI_AIUP) 19601: 1961 restore 1962 wrpr %g0, %g0, %cleanwin ! no clean windows 1963 1964 CPU_ADDR(%g4, %g5) 1965 ldn [%g4 + CPU_MPCB], %g4 1966 brz,a,pn %g4, 1f 1967 nop 1968 ld [%g4 + MPCB_WSTATE], %g5 1969 add %g5, WSTATE_CLEAN_OFFSET, %g5 1970 wrpr %g0, %g5, %wstate 19711: FAST_TRAP_DONE 1972 1973/* 1974 * .spill_clean: clean the previous window, restore the wstate, and 1975 * "done". 1976 * 1977 * Entry: %g7 contains new wstate 1978 */ 1979.spill_clean: 1980 sethi %hi(nwin_minus_one), %g5 1981 ld [%g5 + %lo(nwin_minus_one)], %g5 ! %g5 = nwin - 1 1982 rdpr %cwp, %g6 ! %g6 = %cwp 1983 deccc %g6 ! %g6-- 1984 movneg %xcc, %g5, %g6 ! if (%g6<0) %g6 = nwin-1 1985 wrpr %g6, %cwp 1986 TT_TRACE_L(trace_win) 1987 clr %l0 1988 clr %l1 1989 clr %l2 1990 clr %l3 1991 clr %l4 1992 clr %l5 1993 clr %l6 1994 clr %l7 1995 wrpr %g0, %g7, %wstate 1996 saved 1997 retry ! restores correct %cwp 1998 1999.fix_alignment: 2000 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2001 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 2002 ldn [%g1 + T_PROCP], %g1 2003 mov 1, %g2 2004 stb %g2, [%g1 + P_FIXALIGNMENT] 2005 FAST_TRAP_DONE 2006 2007#define STDF_REG(REG, ADDR, TMP) \ 2008 sll REG, 3, REG ;\ 2009mark1: set start1, TMP ;\ 2010 jmp REG + TMP ;\ 2011 nop ;\ 2012start1: ba,pt %xcc, done1 ;\ 2013 std %f0, [ADDR + CPU_TMP1] ;\ 2014 ba,pt %xcc, done1 ;\ 2015 std %f32, [ADDR + CPU_TMP1] ;\ 2016 ba,pt %xcc, done1 ;\ 2017 std %f2, [ADDR + CPU_TMP1] ;\ 2018 ba,pt %xcc, done1 ;\ 2019 std %f34, [ADDR + CPU_TMP1] ;\ 2020 ba,pt %xcc, done1 ;\ 2021 std %f4, [ADDR + CPU_TMP1] ;\ 2022 ba,pt %xcc, done1 ;\ 2023 std %f36, [ADDR + CPU_TMP1] ;\ 2024 ba,pt %xcc, done1 ;\ 2025 std %f6, [ADDR + CPU_TMP1] ;\ 2026 ba,pt %xcc, done1 ;\ 2027 std %f38, [ADDR + CPU_TMP1] ;\ 2028 ba,pt %xcc, done1 ;\ 2029 std %f8, [ADDR + CPU_TMP1] ;\ 2030 ba,pt %xcc, done1 ;\ 2031 std %f40, [ADDR + CPU_TMP1] ;\ 2032 ba,pt %xcc, done1 ;\ 2033 std %f10, [ADDR + CPU_TMP1] ;\ 2034 ba,pt %xcc, done1 ;\ 2035 std %f42, [ADDR + CPU_TMP1] ;\ 2036 ba,pt %xcc, done1 ;\ 2037 std %f12, [ADDR + CPU_TMP1] ;\ 2038 ba,pt %xcc, done1 ;\ 2039 std %f44, [ADDR + CPU_TMP1] ;\ 2040 ba,pt %xcc, done1 ;\ 2041 std %f14, [ADDR + CPU_TMP1] ;\ 2042 ba,pt %xcc, done1 ;\ 2043 std %f46, [ADDR + CPU_TMP1] ;\ 2044 ba,pt %xcc, done1 ;\ 2045 std %f16, [ADDR + CPU_TMP1] ;\ 2046 ba,pt %xcc, done1 ;\ 2047 std %f48, [ADDR + CPU_TMP1] ;\ 2048 ba,pt %xcc, done1 ;\ 2049 std %f18, [ADDR + CPU_TMP1] ;\ 2050 ba,pt %xcc, done1 ;\ 2051 std %f50, [ADDR + CPU_TMP1] ;\ 2052 ba,pt %xcc, done1 ;\ 2053 std %f20, [ADDR + CPU_TMP1] ;\ 2054 ba,pt %xcc, done1 ;\ 2055 std %f52, [ADDR + CPU_TMP1] ;\ 2056 ba,pt %xcc, done1 ;\ 2057 std %f22, [ADDR + CPU_TMP1] ;\ 2058 ba,pt %xcc, done1 ;\ 2059 std %f54, [ADDR + CPU_TMP1] ;\ 2060 ba,pt %xcc, done1 ;\ 2061 std %f24, [ADDR + CPU_TMP1] ;\ 2062 ba,pt %xcc, done1 ;\ 2063 std %f56, [ADDR + CPU_TMP1] ;\ 2064 ba,pt %xcc, done1 ;\ 2065 std %f26, [ADDR + CPU_TMP1] ;\ 2066 ba,pt %xcc, done1 ;\ 2067 std %f58, [ADDR + CPU_TMP1] ;\ 2068 ba,pt %xcc, done1 ;\ 2069 std %f28, [ADDR + CPU_TMP1] ;\ 2070 ba,pt %xcc, done1 ;\ 2071 std %f60, [ADDR + CPU_TMP1] ;\ 2072 ba,pt %xcc, done1 ;\ 2073 std %f30, [ADDR + CPU_TMP1] ;\ 2074 ba,pt %xcc, done1 ;\ 2075 std %f62, [ADDR + CPU_TMP1] ;\ 2076done1: 2077 2078#define LDDF_REG(REG, ADDR, TMP) \ 2079 sll REG, 3, REG ;\ 2080mark2: set start2, TMP ;\ 2081 jmp REG + TMP ;\ 2082 nop ;\ 2083start2: ba,pt %xcc, done2 ;\ 2084 ldd [ADDR + CPU_TMP1], %f0 ;\ 2085 ba,pt %xcc, done2 ;\ 2086 ldd [ADDR + CPU_TMP1], %f32 ;\ 2087 ba,pt %xcc, done2 ;\ 2088 ldd [ADDR + CPU_TMP1], %f2 ;\ 2089 ba,pt %xcc, done2 ;\ 2090 ldd [ADDR + CPU_TMP1], %f34 ;\ 2091 ba,pt %xcc, done2 ;\ 2092 ldd [ADDR + CPU_TMP1], %f4 ;\ 2093 ba,pt %xcc, done2 ;\ 2094 ldd [ADDR + CPU_TMP1], %f36 ;\ 2095 ba,pt %xcc, done2 ;\ 2096 ldd [ADDR + CPU_TMP1], %f6 ;\ 2097 ba,pt %xcc, done2 ;\ 2098 ldd [ADDR + CPU_TMP1], %f38 ;\ 2099 ba,pt %xcc, done2 ;\ 2100 ldd [ADDR + CPU_TMP1], %f8 ;\ 2101 ba,pt %xcc, done2 ;\ 2102 ldd [ADDR + CPU_TMP1], %f40 ;\ 2103 ba,pt %xcc, done2 ;\ 2104 ldd [ADDR + CPU_TMP1], %f10 ;\ 2105 ba,pt %xcc, done2 ;\ 2106 ldd [ADDR + CPU_TMP1], %f42 ;\ 2107 ba,pt %xcc, done2 ;\ 2108 ldd [ADDR + CPU_TMP1], %f12 ;\ 2109 ba,pt %xcc, done2 ;\ 2110 ldd [ADDR + CPU_TMP1], %f44 ;\ 2111 ba,pt %xcc, done2 ;\ 2112 ldd [ADDR + CPU_TMP1], %f14 ;\ 2113 ba,pt %xcc, done2 ;\ 2114 ldd [ADDR + CPU_TMP1], %f46 ;\ 2115 ba,pt %xcc, done2 ;\ 2116 ldd [ADDR + CPU_TMP1], %f16 ;\ 2117 ba,pt %xcc, done2 ;\ 2118 ldd [ADDR + CPU_TMP1], %f48 ;\ 2119 ba,pt %xcc, done2 ;\ 2120 ldd [ADDR + CPU_TMP1], %f18 ;\ 2121 ba,pt %xcc, done2 ;\ 2122 ldd [ADDR + CPU_TMP1], %f50 ;\ 2123 ba,pt %xcc, done2 ;\ 2124 ldd [ADDR + CPU_TMP1], %f20 ;\ 2125 ba,pt %xcc, done2 ;\ 2126 ldd [ADDR + CPU_TMP1], %f52 ;\ 2127 ba,pt %xcc, done2 ;\ 2128 ldd [ADDR + CPU_TMP1], %f22 ;\ 2129 ba,pt %xcc, done2 ;\ 2130 ldd [ADDR + CPU_TMP1], %f54 ;\ 2131 ba,pt %xcc, done2 ;\ 2132 ldd [ADDR + CPU_TMP1], %f24 ;\ 2133 ba,pt %xcc, done2 ;\ 2134 ldd [ADDR + CPU_TMP1], %f56 ;\ 2135 ba,pt %xcc, done2 ;\ 2136 ldd [ADDR + CPU_TMP1], %f26 ;\ 2137 ba,pt %xcc, done2 ;\ 2138 ldd [ADDR + CPU_TMP1], %f58 ;\ 2139 ba,pt %xcc, done2 ;\ 2140 ldd [ADDR + CPU_TMP1], %f28 ;\ 2141 ba,pt %xcc, done2 ;\ 2142 ldd [ADDR + CPU_TMP1], %f60 ;\ 2143 ba,pt %xcc, done2 ;\ 2144 ldd [ADDR + CPU_TMP1], %f30 ;\ 2145 ba,pt %xcc, done2 ;\ 2146 ldd [ADDR + CPU_TMP1], %f62 ;\ 2147done2: 2148 2149.lddf_exception_not_aligned: 2150 /* %g2 = sfar, %g3 = sfsr */ 2151 mov %g2, %g5 ! stash sfar 2152#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2153 sethi %hi(fpu_exists), %g2 ! check fpu_exists 2154 ld [%g2 + %lo(fpu_exists)], %g2 2155 brz,a,pn %g2, 4f 2156 nop 2157#endif 2158 CPU_ADDR(%g1, %g4) 2159 or %g0, 1, %g4 2160 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2161 2162 rdpr %tpc, %g2 2163 lda [%g2]ASI_AIUP, %g6 ! get the user's lddf instruction 2164 srl %g6, 23, %g1 ! using ldda or not? 2165 and %g1, 1, %g1 2166 brz,a,pt %g1, 2f ! check for ldda instruction 2167 nop 2168 srl %g6, 13, %g1 ! check immflag 2169 and %g1, 1, %g1 2170 rdpr %tstate, %g2 ! %tstate in %g2 2171 brnz,a,pn %g1, 1f 2172 srl %g2, 31, %g1 ! get asi from %tstate 2173 srl %g6, 5, %g1 ! get asi from instruction 2174 and %g1, 0xFF, %g1 ! imm_asi field 21751: 2176 cmp %g1, ASI_P ! primary address space 2177 be,a,pt %icc, 2f 2178 nop 2179 cmp %g1, ASI_PNF ! primary no fault address space 2180 be,a,pt %icc, 2f 2181 nop 2182 cmp %g1, ASI_S ! secondary address space 2183 be,a,pt %icc, 2f 2184 nop 2185 cmp %g1, ASI_SNF ! secondary no fault address space 2186 bne,a,pn %icc, 3f 2187 nop 21882: 2189 lduwa [%g5]ASI_USER, %g7 ! get first half of misaligned data 2190 add %g5, 4, %g5 ! increment misaligned data address 2191 lduwa [%g5]ASI_USER, %g5 ! get second half of misaligned data 2192 2193 sllx %g7, 32, %g7 2194 or %g5, %g7, %g5 ! combine data 2195 CPU_ADDR(%g7, %g1) ! save data on a per-cpu basis 2196 stx %g5, [%g7 + CPU_TMP1] ! save in cpu_tmp1 2197 2198 srl %g6, 25, %g3 ! %g6 has the instruction 2199 and %g3, 0x1F, %g3 ! %g3 has rd 2200 LDDF_REG(%g3, %g7, %g4) 2201 2202 CPU_ADDR(%g1, %g4) 2203 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2204 FAST_TRAP_DONE 22053: 2206 CPU_ADDR(%g1, %g4) 2207 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 22084: 2209 set T_USER, %g3 ! trap type in %g3 2210 or %g3, T_LDDF_ALIGN, %g3 2211 mov %g5, %g2 ! misaligned vaddr in %g2 2212 set fpu_trap, %g1 ! goto C for the little and 2213 ba,pt %xcc, sys_trap ! no fault little asi's 2214 sub %g0, 1, %g4 2215 2216.stdf_exception_not_aligned: 2217 /* %g2 = sfar, %g3 = sfsr */ 2218 mov %g2, %g5 2219 2220#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2221 sethi %hi(fpu_exists), %g7 ! check fpu_exists 2222 ld [%g7 + %lo(fpu_exists)], %g3 2223 brz,a,pn %g3, 4f 2224 nop 2225#endif 2226 CPU_ADDR(%g1, %g4) 2227 or %g0, 1, %g4 2228 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2229 2230 rdpr %tpc, %g2 2231 lda [%g2]ASI_AIUP, %g6 ! get the user's stdf instruction 2232 2233 srl %g6, 23, %g1 ! using stda or not? 2234 and %g1, 1, %g1 2235 brz,a,pt %g1, 2f ! check for stda instruction 2236 nop 2237 srl %g6, 13, %g1 ! check immflag 2238 and %g1, 1, %g1 2239 rdpr %tstate, %g2 ! %tstate in %g2 2240 brnz,a,pn %g1, 1f 2241 srl %g2, 31, %g1 ! get asi from %tstate 2242 srl %g6, 5, %g1 ! get asi from instruction 2243 and %g1, 0xff, %g1 ! imm_asi field 22441: 2245 cmp %g1, ASI_P ! primary address space 2246 be,a,pt %icc, 2f 2247 nop 2248 cmp %g1, ASI_S ! secondary address space 2249 bne,a,pn %icc, 3f 2250 nop 22512: 2252 srl %g6, 25, %g6 2253 and %g6, 0x1F, %g6 ! %g6 has rd 2254 CPU_ADDR(%g7, %g1) 2255 STDF_REG(%g6, %g7, %g4) ! STDF_REG(REG, ADDR, TMP) 2256 2257 ldx [%g7 + CPU_TMP1], %g6 2258 srlx %g6, 32, %g7 2259 stuwa %g7, [%g5]ASI_USER ! first half 2260 add %g5, 4, %g5 ! increment misaligned data address 2261 stuwa %g6, [%g5]ASI_USER ! second half 2262 2263 CPU_ADDR(%g1, %g4) 2264 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2265 FAST_TRAP_DONE 22663: 2267 CPU_ADDR(%g1, %g4) 2268 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 22694: 2270 set T_USER, %g3 ! trap type in %g3 2271 or %g3, T_STDF_ALIGN, %g3 2272 mov %g5, %g2 ! misaligned vaddr in %g2 2273 set fpu_trap, %g1 ! goto C for the little and 2274 ba,pt %xcc, sys_trap ! nofault little asi's 2275 sub %g0, 1, %g4 2276 2277#ifdef DEBUG_USER_TRAPTRACECTL 2278 2279.traptrace_freeze: 2280 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2281 TT_TRACE_L(trace_win) 2282 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2283 set trap_freeze, %g1 2284 mov 1, %g2 2285 st %g2, [%g1] 2286 FAST_TRAP_DONE 2287 2288.traptrace_unfreeze: 2289 set trap_freeze, %g1 2290 st %g0, [%g1] 2291 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2292 TT_TRACE_L(trace_win) 2293 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2294 FAST_TRAP_DONE 2295 2296#endif /* DEBUG_USER_TRAPTRACECTL */ 2297 2298.getcc: 2299 CPU_ADDR(%g1, %g2) 2300 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2301 rdpr %tstate, %g3 ! get tstate 2302 srlx %g3, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2303 set PSR_ICC, %g2 2304 and %o0, %g2, %o0 ! mask out the rest 2305 srl %o0, PSR_ICC_SHIFT, %o0 ! right justify 2306 wrpr %g0, 0, %gl 2307 mov %o0, %g1 ! move ccr to normal %g1 2308 wrpr %g0, 1, %gl 2309 ! cannot assume globals retained their values after increasing %gl 2310 CPU_ADDR(%g1, %g2) 2311 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2312 FAST_TRAP_DONE 2313 2314.setcc: 2315 CPU_ADDR(%g1, %g2) 2316 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2317 wrpr %g0, 0, %gl 2318 mov %g1, %o0 2319 wrpr %g0, 1, %gl 2320 ! cannot assume globals retained their values after increasing %gl 2321 CPU_ADDR(%g1, %g2) 2322 sll %o0, PSR_ICC_SHIFT, %g2 2323 set PSR_ICC, %g3 2324 and %g2, %g3, %g2 ! mask out rest 2325 sllx %g2, PSR_TSTATE_CC_SHIFT, %g2 2326 rdpr %tstate, %g3 ! get tstate 2327 srl %g3, 0, %g3 ! clear upper word 2328 or %g3, %g2, %g3 ! or in new bits 2329 wrpr %g3, %tstate 2330 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2331 FAST_TRAP_DONE 2332 2333/* 2334 * getpsr(void) 2335 * Note that the xcc part of the ccr is not provided. 2336 * The V8 code shows why the V9 trap is not faster: 2337 * #define GETPSR_TRAP() \ 2338 * mov %psr, %i0; jmp %l2; rett %l2+4; nop; 2339 */ 2340 2341 .type .getpsr, #function 2342.getpsr: 2343 rdpr %tstate, %g1 ! get tstate 2344 srlx %g1, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2345 set PSR_ICC, %g2 2346 and %o0, %g2, %o0 ! mask out the rest 2347 2348 rd %fprs, %g1 ! get fprs 2349 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower 2350 sllx %g2, PSR_FPRS_FEF_SHIFT, %g2 ! shift fef to V8 psr.ef 2351 or %o0, %g2, %o0 ! or result into psr.ef 2352 2353 set V9_PSR_IMPLVER, %g2 ! SI assigned impl/ver: 0xef 2354 or %o0, %g2, %o0 ! or psr.impl/ver 2355 FAST_TRAP_DONE 2356 SET_SIZE(.getpsr) 2357 2358/* 2359 * setpsr(newpsr) 2360 * Note that there is no support for ccr.xcc in the V9 code. 2361 */ 2362 2363 .type .setpsr, #function 2364.setpsr: 2365 rdpr %tstate, %g1 ! get tstate 2366! setx TSTATE_V8_UBITS, %g2 2367 or %g0, CCR_ICC, %g3 2368 sllx %g3, TSTATE_CCR_SHIFT, %g2 2369 2370 andn %g1, %g2, %g1 ! zero current user bits 2371 set PSR_ICC, %g2 2372 and %g2, %o0, %g2 ! clear all but psr.icc bits 2373 sllx %g2, PSR_TSTATE_CC_SHIFT, %g3 ! shift to tstate.ccr.icc 2374 wrpr %g1, %g3, %tstate ! write tstate 2375 2376 set PSR_EF, %g2 2377 and %g2, %o0, %g2 ! clear all but fp enable bit 2378 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef 2379 wr %g0, %g4, %fprs ! write fprs 2380 2381 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 2382 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2383 ldn [%g2 + T_LWP], %g3 ! load klwp pointer 2384 ldn [%g3 + LWP_FPU], %g2 ! get lwp_fpu pointer 2385 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs 2386 srlx %g4, 2, %g4 ! shift fef value to bit 0 2387 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en 2388 FAST_TRAP_DONE 2389 SET_SIZE(.setpsr) 2390 2391/* 2392 * getlgrp 2393 * get home lgrpid on which the calling thread is currently executing. 2394 */ 2395 .type .getlgrp, #function 2396.getlgrp: 2397 ! Thanks for the incredibly helpful comments 2398 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2399 ld [%g1 + CPU_ID], %o0 ! load cpu_id 2400 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2401 ldn [%g2 + T_LPL], %g2 ! load lpl pointer 2402 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid 2403 sra %g1, 0, %o1 2404 FAST_TRAP_DONE 2405 SET_SIZE(.getlgrp) 2406 2407/* 2408 * Entry for old 4.x trap (trap 0). 2409 */ 2410 ENTRY_NP(syscall_trap_4x) 2411 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2412 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2413 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2414 ld [%g2 + PCB_TRAP0], %g2 ! lwp->lwp_pcb.pcb_trap0addr 2415 brz,pn %g2, 1f ! has it been set? 2416 st %l0, [%g1 + CPU_TMP1] ! delay - save some locals 2417 st %l1, [%g1 + CPU_TMP2] 2418 rdpr %tnpc, %l1 ! save old tnpc 2419 wrpr %g0, %g2, %tnpc ! setup tnpc 2420 2421 mov %g1, %l0 ! save CPU struct addr 2422 wrpr %g0, 0, %gl 2423 mov %l1, %g6 ! pass tnpc to user code in %g6 2424 wrpr %g0, 1, %gl 2425 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2426 ld [%l0 + CPU_TMP1], %l0 2427 FAST_TRAP_DONE_CHK_INTR 24281: 2429 ! 2430 ! check for old syscall mmap which is the only different one which 2431 ! must be the same. Others are handled in the compatibility library. 2432 ! 2433 mov %g1, %l0 ! save CPU struct addr 2434 wrpr %g0, 0, %gl 2435 cmp %g1, OSYS_mmap ! compare to old 4.x mmap 2436 movz %icc, SYS_mmap, %g1 2437 wrpr %g0, 1, %gl 2438 ld [%l0 + CPU_TMP1], %l0 2439 SYSCALL(syscall_trap32) 2440 SET_SIZE(syscall_trap_4x) 2441 2442/* 2443 * Handler for software trap 9. 2444 * Set trap0 emulation address for old 4.x system call trap. 2445 * XXX - this should be a system call. 2446 */ 2447 ENTRY_NP(set_trap0_addr) 2448 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2449 st %l0, [%g1 + CPU_TMP1] ! save some locals 2450 st %l1, [%g1 + CPU_TMP2] 2451 mov %g1, %l0 ! preserve CPU addr 2452 wrpr %g0, 0, %gl 2453 mov %g1, %l1 2454 wrpr %g0, 1, %gl 2455 ! cannot assume globals retained their values after increasing %gl 2456 ldn [%l0 + CPU_THREAD], %g2 ! load thread pointer 2457 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2458 andn %l1, 3, %l1 ! force alignment 2459 st %l1, [%g2 + PCB_TRAP0] ! lwp->lwp_pcb.pcb_trap0addr 2460 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2461 ld [%l0 + CPU_TMP1], %l0 2462 FAST_TRAP_DONE 2463 SET_SIZE(set_trap0_addr) 2464 2465/* 2466 * mmu_trap_tl1 2467 * trap handler for unexpected mmu traps. 2468 * simply checks if the trap was a user lddf/stdf alignment trap, in which 2469 * case we go to fpu_trap or a user trap from the window handler, in which 2470 * case we go save the state on the pcb. Otherwise, we go to ptl1_panic. 2471 */ 2472 .type mmu_trap_tl1, #function 2473mmu_trap_tl1: 2474#ifdef TRAPTRACE 2475 TRACE_PTR(%g5, %g6) 2476 GET_TRACE_TICK(%g6) 2477 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2478 TRACE_SAVE_TL_GL_REGS(%g5, %g6) 2479 rdpr %tt, %g6 2480 stha %g6, [%g5 + TRAP_ENT_TT]%asi 2481 rdpr %tstate, %g6 2482 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi 2483 stna %sp, [%g5 + TRAP_ENT_SP]%asi 2484 stna %g0, [%g5 + TRAP_ENT_TR]%asi 2485 rdpr %tpc, %g6 2486 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2487 MMU_FAULT_STATUS_AREA(%g6) 2488 ldx [%g6 + MMFSA_D_ADDR], %g6 2489 stna %g6, [%g5 + TRAP_ENT_F1]%asi ! MMU fault address 2490 CPU_PADDR(%g7, %g6); 2491 add %g7, CPU_TL1_HDLR, %g7 2492 lda [%g7]ASI_MEM, %g6 2493 stna %g6, [%g5 + TRAP_ENT_F2]%asi 2494 MMU_FAULT_STATUS_AREA(%g6) 2495 ldx [%g6 + MMFSA_D_TYPE], %g7 ! XXXQ should be a MMFSA_F_ constant? 2496 ldx [%g6 + MMFSA_D_CTX], %g6 2497 sllx %g6, SFSR_CTX_SHIFT, %g6 2498 or %g6, %g7, %g6 2499 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! MMU context/type 2500 set 0xdeadbeef, %g6 2501 stna %g6, [%g5 + TRAP_ENT_F4]%asi 2502 TRACE_NEXT(%g5, %g6, %g7) 2503#endif /* TRAPTRACE */ 2504 CPU_PADDR(%g7, %g6); 2505 add %g7, CPU_TL1_HDLR, %g7 ! %g7 = &cpu_m.tl1_hdlr (PA) 2506 lda [%g7]ASI_MEM, %g6 2507 brz,a,pt %g6, 1f 2508 nop 2509 sta %g0, [%g7]ASI_MEM 2510 ! XXXQ need to setup registers for sfmmu_mmu_trap? 2511 ba,a,pt %xcc, sfmmu_mmu_trap ! handle page faults 25121: 2513 rdpr %tpc, %g7 2514 /* in user_rtt? */ 2515 set rtt_fill_start, %g6 2516 cmp %g7, %g6 2517 blu,pn %xcc, 6f 2518 .empty 2519 set rtt_fill_end, %g6 2520 cmp %g7, %g6 2521 bgeu,pn %xcc, 6f 2522 nop 2523 set fault_rtt_fn1, %g7 2524 ba,a 7f 25256: 2526 ! check to see if the trap pc is in a window spill/fill handling 2527 rdpr %tpc, %g7 2528 /* tpc should be in the trap table */ 2529 set trap_table, %g6 2530 cmp %g7, %g6 2531 blu,a,pn %xcc, ptl1_panic 2532 mov PTL1_BAD_MMUTRAP, %g1 2533 set etrap_table, %g6 2534 cmp %g7, %g6 2535 bgeu,a,pn %xcc, ptl1_panic 2536 mov PTL1_BAD_MMUTRAP, %g1 2537 ! pc is inside the trap table, convert to trap type 2538 srl %g7, 5, %g6 ! XXXQ need #define 2539 and %g6, 0x1ff, %g6 ! XXXQ need #define 2540 ! and check for a window trap type 2541 and %g6, WTRAP_TTMASK, %g6 2542 cmp %g6, WTRAP_TYPE 2543 bne,a,pn %xcc, ptl1_panic 2544 mov PTL1_BAD_MMUTRAP, %g1 2545 andn %g7, WTRAP_ALIGN, %g7 /* 128 byte aligned */ 2546 add %g7, WTRAP_FAULTOFF, %g7 2547 25487: 2549 ! Arguments are passed in the global set active after the 2550 ! 'done' instruction. Before switching sets, must save 2551 ! the calculated next pc 2552 wrpr %g0, %g7, %tnpc 2553 wrpr %g0, 1, %gl 2554 rdpr %tt, %g5 2555 MMU_FAULT_STATUS_AREA(%g7) 2556 cmp %g5, T_ALIGNMENT 2557 be,pn %xcc, 1f 2558 ldx [%g7 + MMFSA_D_ADDR], %g6 2559 ldx [%g7 + MMFSA_D_CTX], %g7 2560 srlx %g6, MMU_PAGESHIFT, %g6 /* align address */ 2561 sllx %g6, MMU_PAGESHIFT, %g6 2562 or %g6, %g7, %g6 /* TAG_ACCESS */ 25631: 2564 done 2565 SET_SIZE(mmu_trap_tl1) 2566 2567/* 2568 * Several traps use kmdb_trap and kmdb_trap_tl1 as their handlers. These 2569 * traps are valid only when kmdb is loaded. When the debugger is active, 2570 * the code below is rewritten to transfer control to the appropriate 2571 * debugger entry points. 2572 */ 2573 .global kmdb_trap 2574 .align 8 2575kmdb_trap: 2576 ba,a trap_table0 2577 jmp %g1 + 0 2578 nop 2579 2580 .global kmdb_trap_tl1 2581 .align 8 2582kmdb_trap_tl1: 2583 ba,a trap_table0 2584 jmp %g1 + 0 2585 nop 2586 2587/* 2588 * This entry is copied from OBP's trap table during boot. 2589 */ 2590 .global obp_bpt 2591 .align 8 2592obp_bpt: 2593 NOT 2594 2595 2596 2597#ifdef TRAPTRACE 2598/* 2599 * TRAPTRACE support. 2600 * labels here are branched to with "rd %pc, %g7" in the delay slot. 2601 * Return is done by "jmp %g7 + 4". 2602 */ 2603 2604trace_dmmu: 2605 TRACE_PTR(%g3, %g6) 2606 GET_TRACE_TICK(%g6) 2607 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2608 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2609 rdpr %tt, %g6 2610 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2611 rdpr %tstate, %g6 2612 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2613 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2614 rdpr %tpc, %g6 2615 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2616 MMU_FAULT_STATUS_AREA(%g6) 2617 ldx [%g6 + MMFSA_D_ADDR], %g4 2618 stxa %g4, [%g3 + TRAP_ENT_TR]%asi 2619 ldx [%g6 + MMFSA_D_CTX], %g4 2620 stxa %g4, [%g3 + TRAP_ENT_F1]%asi 2621 ldx [%g6 + MMFSA_D_TYPE], %g4 2622 stxa %g4, [%g3 + TRAP_ENT_F2]%asi 2623 stxa %g6, [%g3 + TRAP_ENT_F3]%asi 2624 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2625 TRACE_NEXT(%g3, %g4, %g5) 2626 jmp %g7 + 4 2627 nop 2628 2629trace_immu: 2630 TRACE_PTR(%g3, %g6) 2631 GET_TRACE_TICK(%g6) 2632 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2633 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2634 rdpr %tt, %g6 2635 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2636 rdpr %tstate, %g6 2637 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2638 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2639 rdpr %tpc, %g6 2640 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2641 MMU_FAULT_STATUS_AREA(%g6) 2642 ldx [%g6 + MMFSA_I_ADDR], %g4 2643 stxa %g4, [%g3 + TRAP_ENT_TR]%asi 2644 ldx [%g6 + MMFSA_I_CTX], %g4 2645 stxa %g4, [%g3 + TRAP_ENT_F1]%asi 2646 ldx [%g6 + MMFSA_I_TYPE], %g4 2647 stxa %g4, [%g3 + TRAP_ENT_F2]%asi 2648 stxa %g6, [%g3 + TRAP_ENT_F3]%asi 2649 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2650 TRACE_NEXT(%g3, %g4, %g5) 2651 jmp %g7 + 4 2652 nop 2653 2654trace_gen: 2655 TRACE_PTR(%g3, %g6) 2656 GET_TRACE_TICK(%g6) 2657 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2658 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2659 rdpr %tt, %g6 2660 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2661 rdpr %tstate, %g6 2662 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2663 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2664 rdpr %tpc, %g6 2665 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2666 stna %g0, [%g3 + TRAP_ENT_TR]%asi 2667 stna %g0, [%g3 + TRAP_ENT_F1]%asi 2668 stna %g0, [%g3 + TRAP_ENT_F2]%asi 2669 stna %g0, [%g3 + TRAP_ENT_F3]%asi 2670 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2671 TRACE_NEXT(%g3, %g4, %g5) 2672 jmp %g7 + 4 2673 nop 2674 2675trace_win: 2676 TRACE_WIN_INFO(0, %l0, %l1, %l2) 2677 ! Keep the locals as clean as possible, caller cleans %l4 2678 clr %l2 2679 clr %l1 2680 jmp %l4 + 4 2681 clr %l0 2682 2683/* 2684 * Trace a tsb hit 2685 * g1 = tsbe pointer (in/clobbered) 2686 * g2 = tag access register (in) 2687 * g3 - g4 = scratch (clobbered) 2688 * g5 = tsbe data (in) 2689 * g6 = scratch (clobbered) 2690 * g7 = pc we jumped here from (in) 2691 */ 2692 2693 ! Do not disturb %g5, it will be used after the trace 2694 ALTENTRY(trace_tsbhit) 2695 TRACE_TSBHIT(0) 2696 jmp %g7 + 4 2697 nop 2698 2699/* 2700 * Trace a TSB miss 2701 * 2702 * g1 = tsb8k pointer (in) 2703 * g2 = tag access register (in) 2704 * g3 = tsb4m pointer (in) 2705 * g4 = tsbe tag (in/clobbered) 2706 * g5 - g6 = scratch (clobbered) 2707 * g7 = pc we jumped here from (in) 2708 */ 2709 .global trace_tsbmiss 2710trace_tsbmiss: 2711 membar #Sync 2712 sethi %hi(FLUSH_ADDR), %g6 2713 flush %g6 2714 TRACE_PTR(%g5, %g6) 2715 GET_TRACE_TICK(%g6) 2716 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2717 stna %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access 2718 stna %g4, [%g5 + TRAP_ENT_F1]%asi ! XXX? tsb tag 2719 rdpr %tnpc, %g6 2720 stna %g6, [%g5 + TRAP_ENT_F2]%asi 2721 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer 2722 srlx %g1, 32, %g6 2723 stna %g6, [%g5 + TRAP_ENT_F4]%asi ! huh? 2724 rdpr %tpc, %g6 2725 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2726 TRACE_SAVE_TL_GL_REGS(%g5, %g6) 2727 rdpr %tt, %g6 2728 or %g6, TT_MMU_MISS, %g4 2729 stha %g4, [%g5 + TRAP_ENT_TT]%asi 2730 mov MMFSA_D_ADDR, %g4 2731 cmp %g6, FAST_IMMU_MISS_TT 2732 move %xcc, MMFSA_I_ADDR, %g4 2733 cmp %g6, T_INSTR_MMU_MISS 2734 move %xcc, MMFSA_I_ADDR, %g4 2735 MMU_FAULT_STATUS_AREA(%g6) 2736 ldx [%g6 + %g4], %g6 2737 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! tag target 2738 stna %g3, [%g5 + TRAP_ENT_TR]%asi ! tsb4m pointer 2739 TRACE_NEXT(%g5, %g4, %g6) 2740 jmp %g7 + 4 2741 nop 2742 2743/* 2744 * g2 = tag access register (in) 2745 * g3 = ctx number (in) 2746 */ 2747trace_dataprot: 2748 membar #Sync 2749 sethi %hi(FLUSH_ADDR), %g6 2750 flush %g6 2751 TRACE_PTR(%g1, %g6) 2752 GET_TRACE_TICK(%g6) 2753 stxa %g6, [%g1 + TRAP_ENT_TICK]%asi 2754 rdpr %tpc, %g6 2755 stna %g6, [%g1 + TRAP_ENT_TPC]%asi 2756 rdpr %tstate, %g6 2757 stxa %g6, [%g1 + TRAP_ENT_TSTATE]%asi 2758 stna %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg 2759 stna %g0, [%g1 + TRAP_ENT_TR]%asi 2760 stna %g0, [%g1 + TRAP_ENT_F1]%asi 2761 stna %g0, [%g1 + TRAP_ENT_F2]%asi 2762 stna %g0, [%g1 + TRAP_ENT_F3]%asi 2763 stna %g0, [%g1 + TRAP_ENT_F4]%asi 2764 TRACE_SAVE_TL_GL_REGS(%g1, %g6) 2765 rdpr %tt, %g6 2766 stha %g6, [%g1 + TRAP_ENT_TT]%asi 2767 TRACE_NEXT(%g1, %g4, %g5) 2768 jmp %g7 + 4 2769 nop 2770 2771#endif /* TRAPTRACE */ 2772 2773/* 2774 * synthesize for trap(): SFAR in %g2, SFSR in %g3 2775 */ 2776 .type .dmmu_exc_lddf_not_aligned, #function 2777.dmmu_exc_lddf_not_aligned: 2778 MMU_FAULT_STATUS_AREA(%g3) 2779 ldx [%g3 + MMFSA_D_ADDR], %g2 2780 /* Fault type not available in MMU fault status area */ 2781 mov MMFSA_F_UNALIGN, %g1 2782 ldx [%g3 + MMFSA_D_CTX], %g3 2783 sllx %g3, SFSR_CTX_SHIFT, %g3 2784 btst 1, %sp 2785 bnz,pt %xcc, .lddf_exception_not_aligned 2786 or %g3, %g1, %g3 /* SFSR */ 2787 ba,a,pt %xcc, .mmu_exception_not_aligned 2788 SET_SIZE(.dmmu_exc_lddf_not_aligned) 2789 2790/* 2791 * synthesize for trap(): SFAR in %g2, SFSR in %g3 2792 */ 2793 .type .dmmu_exc_stdf_not_aligned, #function 2794.dmmu_exc_stdf_not_aligned: 2795 MMU_FAULT_STATUS_AREA(%g3) 2796 ldx [%g3 + MMFSA_D_ADDR], %g2 2797 /* Fault type not available in MMU fault status area */ 2798 mov MMFSA_F_UNALIGN, %g1 2799 ldx [%g3 + MMFSA_D_CTX], %g3 2800 sllx %g3, SFSR_CTX_SHIFT, %g3 2801 btst 1, %sp 2802 bnz,pt %xcc, .stdf_exception_not_aligned 2803 or %g3, %g1, %g3 /* SFSR */ 2804 ba,a,pt %xcc, .mmu_exception_not_aligned 2805 SET_SIZE(.dmmu_exc_stdf_not_aligned) 2806 2807 .type .dmmu_exception, #function 2808.dmmu_exception: 2809 MMU_FAULT_STATUS_AREA(%g3) 2810 ldx [%g3 + MMFSA_D_ADDR], %g2 2811 ldx [%g3 + MMFSA_D_TYPE], %g1 2812 ldx [%g3 + MMFSA_D_CTX], %g3 2813 srlx %g2, MMU_PAGESHIFT, %g2 /* align address */ 2814 sllx %g2, MMU_PAGESHIFT, %g2 2815 or %g2, %g3, %g2 /* TAG_ACCESS */ 2816 sllx %g3, SFSR_CTX_SHIFT, %g3 2817 or %g3, %g1, %g3 /* SFSR */ 2818 ba,pt %xcc, .mmu_exception_end 2819 mov T_DATA_EXCEPTION, %g1 2820 SET_SIZE(.dmmu_exception) 2821/* 2822 * expects offset into tsbmiss area in %g1 and return pc in %g7 2823 */ 2824stat_mmu: 2825 CPU_INDEX(%g5, %g6) 2826 sethi %hi(tsbmiss_area), %g6 2827 sllx %g5, TSBMISS_SHIFT, %g5 2828 or %g6, %lo(tsbmiss_area), %g6 2829 add %g6, %g5, %g6 /* g6 = tsbmiss area */ 2830 ld [%g6 + %g1], %g5 2831 add %g5, 1, %g5 2832 jmp %g7 + 4 2833 st %g5, [%g6 + %g1] 2834 2835 2836/* 2837 * fast_trap_done, fast_trap_done_chk_intr: 2838 * 2839 * Due to the design of UltraSPARC pipeline, pending interrupts are not 2840 * taken immediately after a RETRY or DONE instruction which causes IE to 2841 * go from 0 to 1. Instead, the instruction at %tpc or %tnpc is allowed 2842 * to execute first before taking any interrupts. If that instruction 2843 * results in other traps, and if the corresponding trap handler runs 2844 * entirely at TL=1 with interrupts disabled, then pending interrupts 2845 * won't be taken until after yet another instruction following the %tpc 2846 * or %tnpc. 2847 * 2848 * A malicious user program can use this feature to block out interrupts 2849 * for extended durations, which can result in send_mondo_timeout kernel 2850 * panic. 2851 * 2852 * This problem is addressed by servicing any pending interrupts via 2853 * sys_trap before returning back to the user mode from a fast trap 2854 * handler. The "done" instruction within a fast trap handler, which 2855 * runs entirely at TL=1 with interrupts disabled, is replaced with the 2856 * FAST_TRAP_DONE macro, which branches control to this fast_trap_done 2857 * entry point. 2858 * 2859 * We check for any pending interrupts here and force a sys_trap to 2860 * service those interrupts, if any. To minimize overhead, pending 2861 * interrupts are checked if the %tpc happens to be at 16K boundary, 2862 * which allows a malicious program to execute at most 4K consecutive 2863 * instructions before we service any pending interrupts. If a worst 2864 * case fast trap handler takes about 2 usec, then interrupts will be 2865 * blocked for at most 8 msec, less than a clock tick. 2866 * 2867 * For the cases where we don't know if the %tpc will cross a 16K 2868 * boundary, we can't use the above optimization and always process 2869 * any pending interrupts via fast_frap_done_chk_intr entry point. 2870 * 2871 * Entry Conditions: 2872 * %pstate am:0 priv:1 ie:0 2873 * globals are AG (not normal globals) 2874 */ 2875 2876 .global fast_trap_done, fast_trap_done_chk_intr 2877fast_trap_done: 2878 rdpr %tpc, %g5 2879 sethi %hi(0xffffc000), %g6 ! 1's complement of 0x3fff 2880 andncc %g5, %g6, %g0 ! check lower 14 bits of %tpc 2881 bz,pn %icc, 1f ! branch if zero (lower 32 bits only) 2882 nop 2883 done 2884 2885fast_trap_done_chk_intr: 28861: rd SOFTINT, %g6 2887 brnz,pn %g6, 2f ! branch if any pending intr 2888 nop 2889 done 2890 28912: 2892 /* 2893 * We get here if there are any pending interrupts. 2894 * Adjust %tpc/%tnpc as we'll be resuming via "retry" 2895 * instruction. 2896 */ 2897 rdpr %tnpc, %g5 2898 wrpr %g0, %g5, %tpc 2899 add %g5, 4, %g5 2900 wrpr %g0, %g5, %tnpc 2901 2902 /* 2903 * Force a dummy sys_trap call so that interrupts can be serviced. 2904 */ 2905 set fast_trap_dummy_call, %g1 2906 ba,pt %xcc, sys_trap 2907 mov -1, %g4 2908 2909fast_trap_dummy_call: 2910 retl 2911 nop 2912 2913#endif /* lint */ 2914