1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Tables to drive the N2 PIU performance counter driver. 31 * 32 * Please see n2piupc-tables.h for an explanation of how the table is put 33 * together. 34 */ 35 36 #include <sys/types.h> 37 #include <sys/kstat.h> 38 #include "n2piupc_tables.h" 39 #include "n2piupc.h" 40 #include "n2piupc_biterr.h" 41 42 static n2piu_event_t imu_ctr_1_evts[] = { 43 { IMU01_S_EVT_NONE, IMU01_EVT_NONE }, 44 { IMU01_S_EVT_CLK, IMU01_EVT_CLK }, 45 { IMU01_S_EVT_TOTAL_MONDO, IMU01_EVT_TOTAL_MONDO }, 46 { IMU01_S_EVT_TOTAL_MSI, IMU01_EVT_TOTAL_MSI }, 47 { IMU01_S_EVT_NAK_MONDO, IMU01_EVT_NAK_MONDO }, 48 { IMU01_S_EVT_EQ_WR, IMU01_EVT_EQ_WR }, 49 { IMU01_S_EVT_EQ_MONDO, IMU01_EVT_EQ_MONDO }, 50 { COMMON_S_CLEAR_PIC, IMU_CTR_EVT_MASK } 51 }; 52 53 static n2piu_event_t imu_ctr_0_evts[] = { 54 { IMU01_S_EVT_NONE, IMU01_EVT_NONE }, 55 { IMU01_S_EVT_CLK, IMU01_EVT_CLK }, 56 { IMU01_S_EVT_TOTAL_MONDO, IMU01_EVT_TOTAL_MONDO }, 57 { IMU01_S_EVT_TOTAL_MSI, IMU01_EVT_TOTAL_MSI }, 58 { IMU01_S_EVT_NAK_MONDO, IMU01_EVT_NAK_MONDO }, 59 { IMU01_S_EVT_EQ_WR, IMU01_EVT_EQ_WR }, 60 { IMU01_S_EVT_EQ_MONDO, IMU01_EVT_EQ_MONDO }, 61 { COMMON_S_CLEAR_PIC, IMU_CTR_EVT_MASK } 62 }; 63 64 static n2piu_event_t mmu_ctr_1_evts[] = { 65 { MMU01_S_EVT_NONE, MMU01_EVT_NONE }, 66 { MMU01_S_EVT_CLK, MMU01_EVT_CLK }, 67 { MMU01_S_EVT_TRANS, MMU01_EVT_TRANS }, 68 { MMU01_S_EVT_STALL, MMU01_EVT_STALL }, 69 { MMU01_S_EVT_TRANS_MISS, MMU01_EVT_TRANS_MISS }, 70 { MMU01_S_EVT_TBLWLK_STALL, MMU01_EVT_TBLWLK_STALL }, 71 { MMU01_S_EVT_BYPASS_TRANSL, MMU01_EVT_BYPASS_TRANSL }, 72 { MMU01_S_EVT_TRANSL_TRANSL, MMU01_EVT_TRANSL_TRANSL }, 73 { MMU01_S_EVT_FLOW_CNTL_STALL, MMU01_EVT_FLOW_CNTL_STALL }, 74 { MMU01_S_EVT_FLUSH_CACHE_ENT, MMU01_EVT_FLUSH_CACHE_ENT }, 75 { COMMON_S_CLEAR_PIC, MMU_CTR_EVT_MASK } 76 }; 77 78 static n2piu_event_t mmu_ctr_0_evts[] = { 79 { MMU01_S_EVT_NONE, MMU01_EVT_NONE }, 80 { MMU01_S_EVT_CLK, MMU01_EVT_CLK }, 81 { MMU01_S_EVT_TRANS, MMU01_EVT_TRANS }, 82 { MMU01_S_EVT_STALL, MMU01_EVT_STALL }, 83 { MMU01_S_EVT_TRANS_MISS, MMU01_EVT_TRANS_MISS }, 84 { MMU01_S_EVT_TBLWLK_STALL, MMU01_EVT_TBLWLK_STALL }, 85 { MMU01_S_EVT_BYPASS_TRANSL, MMU01_EVT_BYPASS_TRANSL }, 86 { MMU01_S_EVT_TRANSL_TRANSL, MMU01_EVT_TRANSL_TRANSL }, 87 { MMU01_S_EVT_FLOW_CNTL_STALL, MMU01_EVT_FLOW_CNTL_STALL }, 88 { MMU01_S_EVT_FLUSH_CACHE_ENT, MMU01_EVT_FLUSH_CACHE_ENT }, 89 { COMMON_S_CLEAR_PIC, MMU_CTR_EVT_MASK } 90 }; 91 92 static n2piu_event_t peu_ctr_2_evts[] = { 93 { PEU2_S_EVT_NONE, PEU2_EVT_NONE }, 94 { PEU2_S_EVT_NONPST_CMPL_TIME, PEU2_EVT_NONPST_CMPL_TIME }, 95 { PEU2_S_EVT_XMIT_DATA, PEU2_EVT_XMIT_DATA }, 96 { PEU2_S_EVT_RCVD_DATA, PEU2_EVT_RCVD_DATA }, 97 { COMMON_S_CLEAR_PIC, PEU_CTR_2_EVT_MASK } 98 }; 99 100 static n2piu_event_t peu_ctr_1_evts[] = { 101 { PEU01_S_EVT_NONE, PEU01_EVT_NONE }, 102 { PEU01_S_EVT_CLK, PEU01_EVT_CLK }, 103 { PEU01_S_EVT_COMPL, PEU01_EVT_COMPL }, 104 { PEU01_S_EVT_XMT_POST_CR_UNAV, PEU01_EVT_XMT_POST_CR_UNAV }, 105 { PEU01_S_EVT_XMT_NPOST_CR_UNAV, PEU01_EVT_XMT_NPOST_CR_UNAV }, 106 { PEU01_S_EVT_XMT_CMPL_CR_UNAV, PEU01_EVT_XMT_CMPL_CR_UNAV }, 107 { PEU01_S_EVT_XMT_ANY_CR_UNAV, PEU01_EVT_XMT_ANY_CR_UNAV }, 108 { PEU01_S_EVT_RETRY_CR_UNAV, PEU01_EVT_RETRY_CR_UNAV }, 109 { PEU01_S_EVT_MEMRD_PKT_RCVD, PEU01_EVT_MEMRD_PKT_RCVD }, 110 { PEU01_S_EVT_MEMWR_PKT_RCVD, PEU01_EVT_MEMWR_PKT_RCVD }, 111 { PEU01_S_EVT_RCV_CR_THRESH, PEU01_EVT_RCV_CR_THRESH }, 112 { PEU01_S_EVT_RCV_PST_HDR_CR_EXH, PEU01_EVT_RCV_PST_HDR_CR_EXH }, 113 { PEU01_S_EVT_RCV_PST_DA_CR_MPS, PEU01_EVT_RCV_PST_DA_CR_MPS }, 114 { PEU01_S_EVT_RCV_NPST_HDR_CR_EXH, PEU01_EVT_RCV_NPST_HDR_CR_EXH }, 115 { PEU01_S_EVT_RCVR_L0S, PEU01_EVT_RCVR_L0S }, 116 { PEU01_S_EVT_RCVR_L0S_TRANS, PEU01_EVT_RCVR_L0S_TRANS }, 117 { PEU01_S_EVT_XMTR_L0S, PEU01_EVT_XMTR_L0S }, 118 { PEU01_S_EVT_XMTR_L0S_TRANS, PEU01_EVT_XMTR_L0S_TRANS }, 119 { PEU01_S_EVT_RCVR_ERR, PEU01_EVT_RCVR_ERR }, 120 { PEU01_S_EVT_BAD_TLP, PEU01_EVT_BAD_TLP }, 121 { PEU01_S_EVT_BAD_DLLP, PEU01_EVT_BAD_DLLP }, 122 { PEU01_S_EVT_REPLAY_ROLLOVER, PEU01_EVT_REPLAY_ROLLOVER }, 123 { PEU01_S_EVT_REPLAY_TMO, PEU01_EVT_REPLAY_TMO }, 124 { COMMON_S_CLEAR_PIC, PEU_CTR_01_EVT_MASK } 125 }; 126 127 static n2piu_event_t peu_ctr_0_evts[] = { 128 { PEU01_S_EVT_NONE, PEU01_EVT_NONE }, 129 { PEU01_S_EVT_CLK, PEU01_EVT_CLK }, 130 { PEU01_S_EVT_COMPL, PEU01_EVT_COMPL }, 131 { PEU01_S_EVT_XMT_POST_CR_UNAV, PEU01_EVT_XMT_POST_CR_UNAV }, 132 { PEU01_S_EVT_XMT_NPOST_CR_UNAV, PEU01_EVT_XMT_NPOST_CR_UNAV }, 133 { PEU01_S_EVT_XMT_CMPL_CR_UNAV, PEU01_EVT_XMT_CMPL_CR_UNAV }, 134 { PEU01_S_EVT_XMT_ANY_CR_UNAV, PEU01_EVT_XMT_ANY_CR_UNAV }, 135 { PEU01_S_EVT_RETRY_CR_UNAV, PEU01_EVT_RETRY_CR_UNAV }, 136 { PEU01_S_EVT_MEMRD_PKT_RCVD, PEU01_EVT_MEMRD_PKT_RCVD }, 137 { PEU01_S_EVT_MEMWR_PKT_RCVD, PEU01_EVT_MEMWR_PKT_RCVD }, 138 { PEU01_S_EVT_RCV_CR_THRESH, PEU01_EVT_RCV_CR_THRESH }, 139 { PEU01_S_EVT_RCV_PST_HDR_CR_EXH, PEU01_EVT_RCV_PST_HDR_CR_EXH }, 140 { PEU01_S_EVT_RCV_PST_DA_CR_MPS, PEU01_EVT_RCV_PST_DA_CR_MPS }, 141 { PEU01_S_EVT_RCV_NPST_HDR_CR_EXH, PEU01_EVT_RCV_NPST_HDR_CR_EXH }, 142 { PEU01_S_EVT_RCVR_L0S, PEU01_EVT_RCVR_L0S }, 143 { PEU01_S_EVT_RCVR_L0S_TRANS, PEU01_EVT_RCVR_L0S_TRANS }, 144 { PEU01_S_EVT_XMTR_L0S, PEU01_EVT_XMTR_L0S }, 145 { PEU01_S_EVT_XMTR_L0S_TRANS, PEU01_EVT_XMTR_L0S_TRANS }, 146 { PEU01_S_EVT_RCVR_ERR, PEU01_EVT_RCVR_ERR }, 147 { PEU01_S_EVT_BAD_TLP, PEU01_EVT_BAD_TLP }, 148 { PEU01_S_EVT_BAD_DLLP, PEU01_EVT_BAD_DLLP }, 149 { PEU01_S_EVT_REPLAY_ROLLOVER, PEU01_EVT_REPLAY_ROLLOVER }, 150 { PEU01_S_EVT_REPLAY_TMO, PEU01_EVT_REPLAY_TMO }, 151 { COMMON_S_CLEAR_PIC, PEU_CTR_01_EVT_MASK } 152 }; 153 154 static n2piu_event_t bterr_ctr_3_evts[] = { 155 { BTERR3_S_EVT_NONE, BTERR3_EVT_ENC_NONE }, 156 { BTERR3_S_EVT_ENC_ALL, BTERR3_EVT_ENC_ALL }, 157 { BTERR3_S_EVT_ENC_LANE_0, BTERR3_EVT_ENC_LANE_0 }, 158 { BTERR3_S_EVT_ENC_LANE_1, BTERR3_EVT_ENC_LANE_1 }, 159 { BTERR3_S_EVT_ENC_LANE_2, BTERR3_EVT_ENC_LANE_2 }, 160 { BTERR3_S_EVT_ENC_LANE_3, BTERR3_EVT_ENC_LANE_3 }, 161 { BTERR3_S_EVT_ENC_LANE_4, BTERR3_EVT_ENC_LANE_4 }, 162 { BTERR3_S_EVT_ENC_LANE_5, BTERR3_EVT_ENC_LANE_5 }, 163 { BTERR3_S_EVT_ENC_LANE_6, BTERR3_EVT_ENC_LANE_6 }, 164 { BTERR3_S_EVT_ENC_LANE_7, BTERR3_EVT_ENC_LANE_7 }, 165 { COMMON_S_CLEAR_PIC, BTERR_CTR_3_EVT_MASK } 166 }; 167 168 static n2piu_event_t bterr_ctr_2_evts[] = { 169 { BTERR2_S_EVT_PRE, BTERR2_EVT_PRE }, 170 { COMMON_S_CLEAR_PIC, NONPROG_DUMMY_MASK } 171 }; 172 173 static n2piu_event_t bterr_ctr_1_evts[] = { 174 { BTERR1_S_EVT_BTLP, BTERR1_EVT_BTLP }, 175 { COMMON_S_CLEAR_PIC, NONPROG_DUMMY_MASK } 176 }; 177 178 static n2piu_event_t bterr_ctr_0_evts[] = { 179 { BTERR0_S_EVT_RESET, BTERR0_EVT_RESET }, 180 { BTERR0_S_EVT_BDLLP, BTERR0_EVT_BDLLP }, 181 { COMMON_S_CLEAR_PIC, BTERR_CTR_0_EVT_MASK } 182 }; 183 184 static n2piu_regsel_fld_t imu_regsel_flds[] = { 185 { imu_ctr_0_evts, NUM_EVTS(imu_ctr_0_evts), 186 IMU_CTR_EVT_MASK, IMU_CTR_0_EVT_OFF }, 187 { imu_ctr_1_evts, NUM_EVTS(imu_ctr_1_evts), 188 IMU_CTR_EVT_MASK, IMU_CTR_1_EVT_OFF } 189 }; 190 191 static n2piu_regsel_fld_t mmu_regsel_flds[] = { 192 { mmu_ctr_0_evts, NUM_EVTS(mmu_ctr_0_evts), 193 MMU_CTR_EVT_MASK, MMU_CTR_0_EVT_OFF }, 194 { mmu_ctr_1_evts, NUM_EVTS(mmu_ctr_1_evts), 195 MMU_CTR_EVT_MASK, MMU_CTR_1_EVT_OFF } 196 }; 197 198 static n2piu_regsel_fld_t peu_regsel_flds[] = { 199 { peu_ctr_0_evts, NUM_EVTS(peu_ctr_0_evts), 200 PEU_CTR_01_EVT_MASK, PEU_CTR_0_EVT_OFF }, 201 { peu_ctr_1_evts, NUM_EVTS(peu_ctr_1_evts), 202 PEU_CTR_01_EVT_MASK, PEU_CTR_1_EVT_OFF }, 203 { peu_ctr_2_evts, NUM_EVTS(peu_ctr_2_evts), 204 PEU_CTR_2_EVT_MASK, PEU_CTR_2_EVT_OFF } 205 }; 206 207 static n2piu_regsel_fld_t bterr_regsel_flds[] = { 208 { bterr_ctr_0_evts, NUM_EVTS(bterr_ctr_0_evts), 209 BTERR_CTR_ENABLE_MASK, BTERR_CTR_ENABLE_OFF }, 210 { bterr_ctr_1_evts, NUM_EVTS(bterr_ctr_1_evts), 211 NONPROG_DUMMY_MASK, NONPROG_DUMMY_OFF }, 212 { bterr_ctr_2_evts, NUM_EVTS(bterr_ctr_2_evts), 213 NONPROG_DUMMY_MASK, NONPROG_DUMMY_OFF }, 214 { bterr_ctr_3_evts, NUM_EVTS(bterr_ctr_3_evts), 215 BTERR_CTR_3_EVT_MASK, BTERR_CTR_3_EVT_OFF } 216 }; 217 218 static n2piu_regsel_t imu_regsel = { 219 HVIO_N2PIU_PERFREG_IMU_SEL, 220 imu_regsel_flds, 221 NUM_FLDS(imu_regsel_flds) 222 }; 223 224 static n2piu_regsel_t mmu_regsel = { 225 HVIO_N2PIU_PERFREG_MMU_SEL, 226 mmu_regsel_flds, 227 NUM_FLDS(mmu_regsel_flds) 228 }; 229 230 static n2piu_regsel_t peu_regsel = { 231 HVIO_N2PIU_PERFREG_PEU_SEL, 232 peu_regsel_flds, 233 NUM_FLDS(peu_regsel_flds) 234 }; 235 236 static n2piu_regsel_t bit_err_regsel = { 237 SW_N2PIU_BITERR_SEL, 238 bterr_regsel_flds, 239 NUM_FLDS(bterr_regsel_flds) 240 }; 241 242 /* reg off, reg size, field mask */ 243 static n2piu_cntr_t imu_cntrs[] = { 244 { HVIO_N2PIU_PERFREG_IMU_CNT0, FULL64BIT, 245 HVIO_N2PIU_PERFREG_IMU_CNT0, 0ULL}, 246 { HVIO_N2PIU_PERFREG_IMU_CNT1, FULL64BIT, 247 HVIO_N2PIU_PERFREG_IMU_CNT1, 0ULL} 248 }; 249 250 static n2piu_cntr_t mmu_cntrs[] = { 251 { HVIO_N2PIU_PERFREG_MMU_CNT0, FULL64BIT, 252 HVIO_N2PIU_PERFREG_MMU_CNT0, 0ULL}, 253 { HVIO_N2PIU_PERFREG_MMU_CNT1, FULL64BIT, 254 HVIO_N2PIU_PERFREG_MMU_CNT1, 0ULL} 255 }; 256 257 static n2piu_cntr_t peu_cntrs[] = { 258 { HVIO_N2PIU_PERFREG_PEU_CNT0, FULL64BIT, 259 HVIO_N2PIU_PERFREG_PEU_CNT0, 0ULL}, 260 { HVIO_N2PIU_PERFREG_PEU_CNT1, FULL64BIT, 261 HVIO_N2PIU_PERFREG_PEU_CNT1, 0ULL}, 262 { HVIO_N2PIU_PERFREG_PEU_CNT2, FULL64BIT, 263 HVIO_N2PIU_PERFREG_PEU_CNT2, 0ULL} 264 }; 265 266 static n2piu_cntr_t bit_err_cntrs[] = { 267 { SW_N2PIU_BITERR_CNT1_DATA, BE1_BAD_DLLP_MASK, 268 SW_N2PIU_BITERR_CLR, BTERR_CTR_CLR}, 269 { SW_N2PIU_BITERR_CNT1_DATA, BE1_BAD_TLP_MASK, NO_REGISTER, 0}, 270 { SW_N2PIU_BITERR_CNT1_DATA, BE1_BAD_PRE_MASK, NO_REGISTER, 0}, 271 272 /* Note: this register is a layered SW-implemented register. */ 273 { SW_N2PIU_BITERR_CNT2_DATA, BE2_8_10_MASK, NO_REGISTER, 0}, 274 }; 275 276 static n2piu_grp_t imu_grp = { 277 "imu", 278 &imu_regsel, 279 imu_cntrs, 280 NUM_CTRS(imu_cntrs), 281 NULL /* Name kstats pointer, filled in at runtime. */ 282 }; 283 284 static n2piu_grp_t mmu_grp = { 285 "mmu", 286 &mmu_regsel, 287 mmu_cntrs, 288 NUM_CTRS(mmu_cntrs), 289 NULL /* Name kstats pointer, filled in at runtime. */ 290 }; 291 292 static n2piu_grp_t peu_grp = { 293 "peu", 294 &peu_regsel, 295 peu_cntrs, 296 NUM_CTRS(peu_cntrs), 297 NULL /* Name kstats pointer, filled in at runtime. */ 298 }; 299 300 static n2piu_grp_t bit_err_grp = { 301 "bterr", 302 &bit_err_regsel, 303 bit_err_cntrs, 304 NUM_CTRS(bit_err_cntrs), 305 NULL /* Name kstats pointer, filled in at runtime. */ 306 }; 307 308 n2piu_grp_t *leaf_grps[] = { 309 &imu_grp, 310 &mmu_grp, 311 &peu_grp, 312 &bit_err_grp, 313 NULL 314 }; 315