1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29#if !defined(lint) 30#include "assym.h" 31#endif 32 33/* 34 * Niagara processor specific assembly routines 35 */ 36 37#include <sys/asm_linkage.h> 38#include <sys/machasi.h> 39#include <sys/machparam.h> 40#include <sys/hypervisor_api.h> 41#include <sys/niagararegs.h> 42#include <sys/machasi.h> 43#include <sys/niagaraasi.h> 44#include <vm/hat_sfmmu.h> 45 46#if defined(lint) 47/*ARGSUSED*/ 48uint64_t 49hv_niagara_getperf(uint64_t perfreg, uint64_t *datap) 50{ return (0); } 51 52/*ARGSUSED*/ 53uint64_t 54hv_niagara_setperf(uint64_t perfreg, uint64_t data) 55{ return (0); } 56 57#else /* lint */ 58 59 /* 60 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap) 61 */ 62 ENTRY(hv_niagara_getperf) 63 mov %o1, %o4 ! save datap 64 mov HV_NIAGARA_GETPERF, %o5 65 ta FAST_TRAP 66 brz,a %o0, 1f 67 stx %o1, [%o4] 681: 69 retl 70 nop 71 SET_SIZE(hv_niagara_getperf) 72 73 /* 74 * hv_niagara_setperf(uint64_t perfreg, uint64_t data) 75 */ 76 ENTRY(hv_niagara_setperf) 77 mov HV_NIAGARA_SETPERF, %o5 78 ta FAST_TRAP 79 retl 80 nop 81 SET_SIZE(hv_niagara_setperf) 82 83#endif /* !lint */ 84 85#if defined (lint) 86/* 87 * Invalidate all of the entries within the TSB, by setting the inv bit 88 * in the tte_tag field of each tsbe. 89 * 90 * We take advantage of the fact that the TSBs are page aligned and a 91 * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI. 92 * 93 * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice 94 * (in short, we set all bits in the upper word of the tag, and we give the 95 * invalid bit precedence over other tag bits in both places). 96 */ 97/*ARGSUSED*/ 98void 99cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes) 100{} 101 102#else /* lint */ 103 104 ENTRY(cpu_inv_tsb) 105 106 /* 107 * The following code assumes that the tsb_base (%o0) is 256 bytes 108 * aligned and the tsb_bytes count is multiple of 256 bytes. 109 */ 110 111 wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi 112 set TSBTAG_INVALID, %o2 113 sllx %o2, 32, %o2 ! INV bit in upper 32 bits of the tag 1141: 115 stxa %o2, [%o0+0x0]%asi 116 stxa %o2, [%o0+0x40]%asi 117 stxa %o2, [%o0+0x80]%asi 118 stxa %o2, [%o0+0xc0]%asi 119 120 stxa %o2, [%o0+0x10]%asi 121 stxa %o2, [%o0+0x20]%asi 122 stxa %o2, [%o0+0x30]%asi 123 124 stxa %o2, [%o0+0x50]%asi 125 stxa %o2, [%o0+0x60]%asi 126 stxa %o2, [%o0+0x70]%asi 127 128 stxa %o2, [%o0+0x90]%asi 129 stxa %o2, [%o0+0xa0]%asi 130 stxa %o2, [%o0+0xb0]%asi 131 132 stxa %o2, [%o0+0xd0]%asi 133 stxa %o2, [%o0+0xe0]%asi 134 stxa %o2, [%o0+0xf0]%asi 135 136 subcc %o1, 0x100, %o1 137 bgu,pt %ncc, 1b 138 add %o0, 0x100, %o0 139 140 membar #Sync 141 retl 142 nop 143 144 SET_SIZE(cpu_inv_tsb) 145#endif /* lint */ 146 147#ifdef NIAGARA_CHK_VERSION 148 149/* 150 * This workaround will be removed prior to the FCS release. 151 */ 152 153#if defined(lint) 154 155/*ARGSUSED*/ 156uint64_t 157niagara_getver(uint64_t ni_getver_ra, uint64_t *cpu_version) 158{ return (0); } 159 160#else /* lint */ 161 162/* 163 * The following hypervisor calls are used to get the CPU version register 164 * for the workaround. 165 */ 166#define HV_DIAG_RA2PA 0x200 167#define HV_DIAG_HEXEC 0x201 168 169 /* 170 * niagara_getver(uint64_t ni_getver_ra, uint64_t *cpu_version) 171 */ 172 ENTRY(niagara_getver) 173 mov %o1, %o4 ! save cpu_version pointer 174 mov HV_DIAG_RA2PA, %o5 ! get PA of ni_getver routine 175 ta FAST_TRAP 176 brnz,pn %o0, 2f ! return error in not successful 177 nop 178 179 mov %o1, %o0 ! move ni_getver PA to %o0 180 mov HV_DIAG_HEXEC, %o5 181 ta FAST_TRAP 182 brnz,pn %o0, 2f 183 nop 184 185 stx %o1, [%o4] ! copy version 1862: 187 retl 188 nop 189 SET_SIZE(niagara_getver) 190 191 /* 192 * Hypervisor code sequence to get chip version via HV_DIAG_HEXEC. 193 * Returns E_HOK in %o0 and %hver register value in %o1. 194 */ 195 .global ni_getver 196 .align 16 197ni_getver: 198 mov H_EOK, %o0 199 rdhpr %hver, %o1 200 done 201 202#endif /* lint */ 203 204#endif /* NIAGARA_CHK_VERSION */ 205 206#if defined(lint) 207/*ARGSUSED*/ 208uint64_t 209hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf) 210{ return (0); } 211 212/*ARGSUSED*/ 213uint64_t 214hv_niagara_mmustat_info(uint64_t *buf) 215{ return (0); } 216 217#else /* lint */ 218 219 /* 220 * hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf) 221 */ 222 ENTRY(hv_niagara_mmustat_conf) 223 mov %o1, %o4 ! save prev_buf 224 mov HV_NIAGARA_MMUSTAT_CONF, %o5 225 ta FAST_TRAP 226 retl 227 stx %o1, [%o4] 228 SET_SIZE(hv_niagara_mmustat_conf) 229 230 /* 231 * hv_niagara_mmustat_info(uint64_t *buf) 232 */ 233 ENTRY(hv_niagara_mmustat_info) 234 mov %o0, %o4 ! save buf 235 mov HV_NIAGARA_MMUSTAT_INFO, %o5 236 ta FAST_TRAP 237 retl 238 stx %o1, [%o4] 239 SET_SIZE(hv_niagara_mmustat_info) 240 241#endif /* !lint */ 242