1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <vm/vm_dep.h> 39 #include <sys/cpuvar.h> 40 #include <sys/async.h> 41 #include <sys/cmn_err.h> 42 #include <sys/debug.h> 43 #include <sys/dditypes.h> 44 #include <sys/sunddi.h> 45 #include <sys/cpu_module.h> 46 #include <sys/prom_debug.h> 47 #include <sys/vmsystm.h> 48 #include <sys/prom_plat.h> 49 #include <sys/sysmacros.h> 50 #include <sys/intreg.h> 51 #include <sys/machtrap.h> 52 #include <sys/ontrap.h> 53 #include <sys/ivintr.h> 54 #include <sys/atomic.h> 55 #include <sys/panic.h> 56 #include <sys/dtrace.h> 57 #include <vm/seg_spt.h> 58 #include <sys/simulate.h> 59 #include <sys/fault.h> 60 61 62 uint_t root_phys_addr_lo_mask = 0xffffffffU; 63 64 void 65 cpu_setup(void) 66 { 67 extern int mmu_exported_pagesize_mask; 68 char *generic_isa_set[] = { 69 "sparcv9+vis", 70 "sparcv8plus+vis", 71 NULL 72 }; 73 74 /* 75 * The setup common to all CPU modules is done in cpu_setup_common 76 * routine. 77 */ 78 cpu_setup_common(generic_isa_set); 79 80 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 81 82 if (broken_md_flag) { 83 /* 84 * Turn on the missing bits supported by sun4v architecture in 85 * MMU pagesize mask returned by MD. 86 */ 87 mmu_exported_pagesize_mask |= DEFAULT_SUN4V_MMU_PAGESIZE_MASK; 88 } else { 89 /* 90 * According to sun4v architecture each processor must 91 * support 8K, 64K and 4M page sizes. If any of the page 92 * size is missing from page size mask, then panic. 93 */ 94 if ((mmu_exported_pagesize_mask & 95 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 96 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 97 cmn_err(CE_PANIC, "machine description" 98 " does not have required sun4v page sizes" 99 " 8K, 64K and 4M: MD mask is 0x%x", 100 mmu_exported_pagesize_mask); 101 } 102 103 /* 104 * If processor supports the subset of full 64-bit virtual 105 * address space, then set VA hole accordingly. 106 */ 107 if (va_bits < VA_ADDRESS_SPACE_BITS) { 108 hole_start = (caddr_t)(1ull << (va_bits - 1)); 109 hole_end = (caddr_t)(0ull - (1ull << (va_bits - 1))); 110 } else { 111 hole_start = hole_end = 0; 112 } 113 } 114 115 void 116 cpu_fiximp(struct cpu_node *cpunode) 117 { 118 /* 119 * The Cache node is optional in MD. Therefore in case "Cache" 120 * does not exists in MD, set the default L2 cache associativity, 121 * size, linesize for generic CPU module. 122 */ 123 if (cpunode->ecache_size == 0) 124 cpunode->ecache_size = 0x100000; 125 if (cpunode->ecache_linesize == 0) 126 cpunode->ecache_linesize = 64; 127 if (cpunode->ecache_associativity == 0) 128 cpunode->ecache_associativity = 1; 129 } 130 131 void 132 dtrace_flush_sec(uintptr_t addr) 133 { 134 pfn_t pfn; 135 proc_t *procp = ttoproc(curthread); 136 page_t *pp; 137 caddr_t va; 138 139 pfn = hat_getpfnum(procp->p_as->a_hat, (void *)addr); 140 if (pfn != -1) { 141 ASSERT(pf_is_memory(pfn)); 142 pp = page_numtopp_noreclaim(pfn, SE_SHARED); 143 if (pp != NULL) { 144 va = ppmapin(pp, PROT_READ | PROT_WRITE, (void *)addr); 145 /* sparc needs 8-byte align */ 146 doflush((caddr_t)((uintptr_t)va & -8l)); 147 ppmapout(va); 148 page_unlock(pp); 149 } 150 } 151 } 152 153 void 154 cpu_map_exec_units(struct cpu *cp) 155 { 156 ASSERT(MUTEX_HELD(&cpu_lock)); 157 158 /* 159 * The cpu_ipipe and cpu_fpu fields are initialized based on 160 * the execution unit sharing information from the MD. They 161 * default to the CPU id in the absence of such information. 162 */ 163 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 164 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 165 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 166 167 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 168 if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 169 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 170 171 /* 172 * The cpu_chip field is initialized based on the information 173 * in the MD and assume that all cpus within a chip 174 * share the same L2 cache. If no such info is available, we 175 * set the cpu to belong to the defacto chip 0. 176 */ 177 cp->cpu_m.cpu_mpipe = cpunodes[cp->cpu_id].l2_cache_mapping; 178 if (cp->cpu_m.cpu_mpipe == NO_L2_CACHE_MAPPING_FOUND) 179 cp->cpu_m.cpu_mpipe = CPU_L2_CACHEID_INVALID; 180 181 cp->cpu_m.cpu_core = (id_t)(cp->cpu_id); 182 183 /* 184 * The cpu_chip field is set to invalid(unknown) for generic cpu. 185 */ 186 cp->cpu_m.cpu_chip = CPU_CHIPID_INVALID; 187 } 188 189 void 190 cpu_init_private(struct cpu *cp) 191 { 192 cpu_map_exec_units(cp); 193 } 194 195 /*ARGSUSED*/ 196 void 197 cpu_uninit_private(struct cpu *cp) 198 {} 199 200 /* 201 * Invalidate a TSB. Since this needs to work on all sun4v 202 * architecture compliant processors, we use the old method of 203 * walking the TSB, setting each tag to TSBTAG_INVALID. 204 */ 205 void 206 cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes) 207 { 208 struct tsbe *tsbaddr; 209 210 for (tsbaddr = (struct tsbe *)tsb_base; 211 (uintptr_t)tsbaddr < (uintptr_t)(tsb_base + tsb_bytes); 212 tsbaddr++) { 213 tsbaddr->tte_tag.tag_inthi = TSBTAG_INVALID; 214 } 215 } 216 217 /* 218 * Sun4v kernel must emulate code a generic sun4v processor may not support 219 * i.e. VIS1 and VIS2. 220 */ 221 #define IS_FLOAT(i) (((i) & 0x1000000) != 0) 222 #define IS_IBIT_SET(x) (x & 0x2000) 223 #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 224 #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 225 (op == 3 && (op3 == IOP_V8_LDDFA || \ 226 op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 227 int 228 vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault) 229 { 230 char *badaddr; 231 int instr; 232 uint_t optype, op3, asi; 233 uint_t rd, ignor; 234 235 if (!USERMODE(rp->r_tstate)) 236 return (-1); 237 238 instr = fetch_user_instr((caddr_t)rp->r_pc); 239 240 rd = (instr >> 25) & 0x1f; 241 optype = (instr >> 30) & 0x3; 242 op3 = (instr >> 19) & 0x3f; 243 ignor = (instr >> 5) & 0xff; 244 if (IS_IBIT_SET(instr)) { 245 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 246 TSTATE_ASI_MASK); 247 } else { 248 asi = ignor; 249 } 250 251 if (!IS_VIS1(optype, op3) && 252 !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 253 return (-1); 254 } 255 switch (simulate_unimp(rp, &badaddr)) { 256 case SIMU_RETRY: 257 break; /* regs are already set up */ 258 /*NOTREACHED*/ 259 260 case SIMU_SUCCESS: 261 /* 262 * skip the successfully 263 * simulated instruction 264 */ 265 rp->r_pc = rp->r_npc; 266 rp->r_npc += 4; 267 break; 268 /*NOTREACHED*/ 269 270 case SIMU_FAULT: 271 siginfo->si_signo = SIGSEGV; 272 siginfo->si_code = SEGV_MAPERR; 273 siginfo->si_addr = badaddr; 274 *fault = FLTBOUNDS; 275 break; 276 277 case SIMU_DZERO: 278 siginfo->si_signo = SIGFPE; 279 siginfo->si_code = FPE_INTDIV; 280 siginfo->si_addr = (caddr_t)rp->r_pc; 281 *fault = FLTIZDIV; 282 break; 283 284 case SIMU_UNALIGN: 285 siginfo->si_signo = SIGBUS; 286 siginfo->si_code = BUS_ADRALN; 287 siginfo->si_addr = badaddr; 288 *fault = FLTACCESS; 289 break; 290 291 case SIMU_ILLEGAL: 292 default: 293 siginfo->si_signo = SIGILL; 294 op3 = (instr >> 19) & 0x3F; 295 if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) || 296 (op3 == IOP_V8_STDFA))) 297 siginfo->si_code = ILL_ILLADR; 298 else 299 siginfo->si_code = ILL_ILLOPC; 300 siginfo->si_addr = (caddr_t)rp->r_pc; 301 *fault = FLTILL; 302 break; 303 } 304 return (0); 305 } 306 307 /* 308 * Trapstat support for generic sun4v processor 309 */ 310 int 311 cpu_trapstat_conf(int cmd) 312 { 313 int status; 314 315 switch (cmd) { 316 case CPU_TSTATCONF_INIT: 317 case CPU_TSTATCONF_FINI: 318 case CPU_TSTATCONF_ENABLE: 319 case CPU_TSTATCONF_DISABLE: 320 status = ENOTSUP; 321 break; 322 323 default: 324 status = EINVAL; 325 break; 326 } 327 return (status); 328 } 329 330 /*ARGSUSED*/ 331 void 332 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 333 { 334 } 335