1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/machsystm.h> 30 #include <sys/x_call.h> 31 #include <sys/cmp.h> 32 #include <sys/debug.h> 33 #include <sys/chip.h> 34 #include <sys/disp.h> 35 #include <sys/cheetahregs.h> 36 37 /* 38 * Note: We assume that chipid == portid. This is not necessarily true. 39 * We buried it down here in the implementation, and not in the 40 * interfaces, so that we can change it later. 41 */ 42 43 /* 44 * pre-alloc'ed because this is used early in boot (before the memory 45 * allocator is available). 46 */ 47 static cpuset_t chips[MAX_CPU_CHIPID]; 48 49 /* 50 * Returns 1 if cpuid is CMP-capable, 0 otherwise. 51 */ 52 int 53 cmp_cpu_is_cmp(processorid_t cpuid) 54 { 55 chipid_t chipid; 56 57 /* N.B. We're assuming that the cpunode[].portid is still intact */ 58 chipid = cpunodes[cpuid].portid; 59 return (!CPUSET_ISNULL(chips[chipid])); 60 } 61 62 /* 63 * Indicate that this core (cpuid) resides on the chip indicated by chipid. 64 * Called during boot and DR add. 65 */ 66 void 67 cmp_add_cpu(chipid_t chipid, processorid_t cpuid) 68 { 69 CPUSET_ADD(chips[chipid], cpuid); 70 } 71 72 /* 73 * Indicate that this core (cpuid) is being DR removed. 74 */ 75 void 76 cmp_delete_cpu(processorid_t cpuid) 77 { 78 chipid_t chipid; 79 80 /* N.B. We're assuming that the cpunode[].portid is still intact */ 81 chipid = cpunodes[cpuid].portid; 82 CPUSET_DEL(chips[chipid], cpuid); 83 } 84 85 /* 86 * Called when cpuid is being onlined or offlined. If the offlined 87 * processor is CMP-capable then current target of the CMP Error Steering 88 * Register is set to either the lowest numbered on-line sibling core, if 89 * one exists, or else to this core. 90 */ 91 /* ARGSUSED */ 92 void 93 cmp_error_resteer(processorid_t cpuid) 94 { 95 #ifndef _CMP_NO_ERROR_STEERING 96 cpuset_t mycores; 97 cpu_t *cpu; 98 chipid_t chipid; 99 int i; 100 101 if (!cmp_cpu_is_cmp(cpuid)) 102 return; 103 104 ASSERT(MUTEX_HELD(&cpu_lock)); 105 chipid = cpunodes[cpuid].portid; 106 mycores = chips[chipid]; 107 108 /* Look for an online sibling core */ 109 for (i = 0; i < NCPU; i++) { 110 if (i == cpuid) 111 continue; 112 113 if (CPU_IN_SET(mycores, i) && 114 (cpu = cpu_get(i)) != NULL && cpu_is_active(cpu)) { 115 /* Found one, reset error steering */ 116 xc_one(i, (xcfunc_t *)set_cmp_error_steering, 0, 0); 117 break; 118 } 119 } 120 121 /* No online sibling cores, point to this core. */ 122 if (i == NCPU) { 123 xc_one(cpuid, (xcfunc_t *)set_cmp_error_steering, 0, 0); 124 } 125 #else 126 /* Not all CMP's support (e.g. Olympus-C by Fujitsu) error steering */ 127 return; 128 #endif /* _CMP_NO_ERROR_STEERING */ 129 } 130 131 chipid_t 132 cmp_cpu_to_chip(processorid_t cpuid) 133 { 134 if (!cmp_cpu_is_cmp(cpuid)) { 135 /* This CPU is not a CMP, so by definition chipid==cpuid */ 136 ASSERT(cpuid < MAX_CPU_CHIPID && CPUSET_ISNULL(chips[cpuid])); 137 return (cpuid); 138 } 139 140 /* N.B. We're assuming that the cpunode[].portid is still intact */ 141 return (cpunodes[cpuid].portid); 142 } 143 144 /* 145 * Return a chip "id" for the given cpu_t 146 * cpu_t's residing on the same physical processor 147 * should map to the same "id" 148 */ 149 chipid_t 150 chip_plat_get_chipid(cpu_t *cp) 151 { 152 return (cmp_cpu_to_chip(cp->cpu_id)); 153 } 154 155 /* 156 * Return the "core id" for the given cpu_t 157 * The "core id" space spans uniquely across all 158 * cpu chips. 159 */ 160 id_t 161 chip_plat_get_coreid(cpu_t *cp) 162 { 163 int impl; 164 165 impl = cpunodes[cp->cpu_id].implementation; 166 167 if (IS_OLYMPUS_C(impl)) { 168 /* 169 * Currently only Fujitsu Olympus-c processor supports 170 * multi-stranded cores. Return the cpu_id with 171 * the strand bit masked out. 172 */ 173 return ((id_t)((uint_t)cp->cpu_id & ~(0x1))); 174 } else { 175 return (cp->cpu_id); 176 } 177 } 178 179 void 180 chip_plat_define_chip(cpu_t *cp, chip_def_t *cd) 181 { 182 int impl; 183 184 /* 185 * Define the chip's type 186 */ 187 impl = cpunodes[cp->cpu_id].implementation; 188 189 if (IS_JAGUAR(impl)) { 190 cd->chipd_type = CHIP_CMP_SPLIT_CACHE; 191 } else if (IS_PANTHER(impl) || IS_OLYMPUS_C(impl)) { 192 cd->chipd_type = CHIP_CMP_SHARED_CACHE; 193 } else { 194 cd->chipd_type = CHIP_DEFAULT; 195 } 196 197 /* 198 * Define any needed adjustment of rechoose_interval 199 * For now, all chips use the default. This 200 * will change with future processors. 201 */ 202 cd->chipd_rechoose_adj = 0; 203 cd->chipd_nosteal = 100000ULL; /* 100 usecs */ 204 } 205