xref: /titanic_51/usr/src/uts/sun4u/os/cmp.c (revision 821da340f9590922ba8761a64fadda18843a0e88)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <sys/types.h>
29 #include <sys/machsystm.h>
30 #include <sys/x_call.h>
31 #include <sys/cmp.h>
32 #include <sys/cmt.h>
33 #include <sys/debug.h>
34 #include <sys/disp.h>
35 #include <sys/cheetahregs.h>
36 
37 /*
38  * Note: We assume that chipid == portid.  This is not necessarily true.
39  * We buried it down here in the implementation, and not in the
40  * interfaces, so that we can change it later.
41  */
42 
43 /*
44  * pre-alloc'ed because this is used early in boot (before the memory
45  * allocator is available).
46  */
47 static cpuset_t chips[MAX_CPU_CHIPID];
48 
49 /*
50  * Returns 1 if cpuid is CMP-capable, 0 otherwise.
51  */
52 int
53 cmp_cpu_is_cmp(processorid_t cpuid)
54 {
55 	chipid_t chipid;
56 
57 	/* N.B. We're assuming that the cpunode[].portid is still intact */
58 	chipid = cpunodes[cpuid].portid;
59 	return (!CPUSET_ISNULL(chips[chipid]));
60 }
61 
62 /*
63  * Indicate that this core (cpuid) resides on the chip indicated by chipid.
64  * Called during boot and DR add.
65  */
66 void
67 cmp_add_cpu(chipid_t chipid, processorid_t cpuid)
68 {
69 	CPUSET_ADD(chips[chipid], cpuid);
70 }
71 
72 /*
73  * Indicate that this core (cpuid) is being DR removed.
74  */
75 void
76 cmp_delete_cpu(processorid_t cpuid)
77 {
78 	chipid_t chipid;
79 
80 	/* N.B. We're assuming that the cpunode[].portid is still intact */
81 	chipid = cpunodes[cpuid].portid;
82 	CPUSET_DEL(chips[chipid], cpuid);
83 }
84 
85 /*
86  * Called when cpuid is being onlined or offlined.  If the offlined
87  * processor is CMP-capable then current target of the CMP Error Steering
88  * Register is set to either the lowest numbered on-line sibling core, if
89  * one exists, or else to this core.
90  */
91 /* ARGSUSED */
92 void
93 cmp_error_resteer(processorid_t cpuid)
94 {
95 #ifndef	_CMP_NO_ERROR_STEERING
96 	cpuset_t mycores;
97 	cpu_t *cpu;
98 	chipid_t chipid;
99 	int i;
100 
101 	if (!cmp_cpu_is_cmp(cpuid))
102 		return;
103 
104 	ASSERT(MUTEX_HELD(&cpu_lock));
105 	chipid = cpunodes[cpuid].portid;
106 	mycores = chips[chipid];
107 
108 	/* Look for an online sibling core */
109 	for (i = 0; i < NCPU; i++) {
110 		if (i == cpuid)
111 			continue;
112 
113 		if (CPU_IN_SET(mycores, i) &&
114 		    (cpu = cpu_get(i)) != NULL && cpu_is_active(cpu)) {
115 			/* Found one, reset error steering  */
116 			xc_one(i, (xcfunc_t *)set_cmp_error_steering, 0, 0);
117 			break;
118 		}
119 	}
120 
121 	/* No online sibling cores, point to this core.  */
122 	if (i == NCPU) {
123 		xc_one(cpuid, (xcfunc_t *)set_cmp_error_steering, 0, 0);
124 	}
125 #else
126 	/* Not all CMP's support (e.g. Olympus-C by Fujitsu) error steering */
127 	return;
128 #endif /* _CMP_NO_ERROR_STEERING */
129 }
130 
131 chipid_t
132 cmp_cpu_to_chip(processorid_t cpuid)
133 {
134 	if (!cmp_cpu_is_cmp(cpuid)) {
135 		/* This CPU is not a CMP, so by definition chipid==cpuid */
136 		ASSERT(cpuid < MAX_CPU_CHIPID && CPUSET_ISNULL(chips[cpuid]));
137 		return (cpuid);
138 	}
139 
140 	/* N.B. We're assuming that the cpunode[].portid is still intact */
141 	return (cpunodes[cpuid].portid);
142 }
143 
144 /* ARGSUSED */
145 int
146 pg_plat_hw_shared(cpu_t *cp, pghw_type_t hw)
147 {
148 	int impl;
149 
150 	impl = cpunodes[cp->cpu_id].implementation;
151 
152 	switch (hw) {
153 	case PGHW_IPIPE:
154 		if (IS_OLYMPUS_C(impl))
155 			return (1);
156 		break;
157 	case PGHW_CHIP:
158 		if (IS_JAGUAR(impl) || IS_PANTHER(impl) || IS_OLYMPUS_C(impl))
159 			return (1);
160 		break;
161 	case PGHW_CACHE:
162 		if (IS_PANTHER(impl) || IS_OLYMPUS_C(impl))
163 			return (1);
164 		break;
165 	}
166 	return (0);
167 }
168 
169 int
170 pg_plat_cpus_share(cpu_t *cpu_a, cpu_t *cpu_b, pghw_type_t hw)
171 {
172 	int impl;
173 
174 	impl = cpunodes[cpu_a->cpu_id].implementation;
175 
176 	switch (hw) {
177 	case PGHW_IPIPE:
178 	case PGHW_CHIP:
179 		return (pg_plat_hw_instance_id(cpu_a, hw) ==
180 		    pg_plat_hw_instance_id(cpu_b, hw));
181 	case PGHW_CACHE:
182 		if ((IS_PANTHER(impl) || IS_OLYMPUS_C(impl)) &&
183 		    pg_plat_cpus_share(cpu_a, cpu_b, PGHW_CHIP)) {
184 			return (1);
185 		} else {
186 			return (0);
187 		}
188 	}
189 	return (0);
190 }
191 
192 id_t
193 pg_plat_hw_instance_id(cpu_t *cpu, pghw_type_t hw)
194 {
195 	int impl;
196 
197 	impl = cpunodes[cpu->cpu_id].implementation;
198 
199 	switch (hw) {
200 	case PGHW_IPIPE:
201 		if (IS_OLYMPUS_C(impl)) {
202 			/*
203 			 * Currently only Fujitsu Olympus-c processor supports
204 			 * multi-stranded cores. Return the cpu_id with
205 			 * the strand bit masked out.
206 			 */
207 			return ((id_t)((uint_t)cpu->cpu_id & ~(0x1)));
208 		} else {
209 			return (cpu->cpu_id);
210 		}
211 	case PGHW_CHIP:
212 		return (cmp_cpu_to_chip(cpu->cpu_id));
213 	case PGHW_CACHE:
214 		if (IS_PANTHER(impl) || IS_OLYMPUS_C(impl))
215 			return (pg_plat_hw_instance_id(cpu, PGHW_CHIP));
216 		else
217 			return (cpu->cpu_id);
218 	default:
219 		return (-1);
220 	}
221 }
222 
223 int
224 pg_plat_hw_level(pghw_type_t hw)
225 {
226 	int i;
227 	static pghw_type_t hw_hier[] = {
228 		PGHW_IPIPE,
229 		PGHW_CHIP,
230 		PGHW_CACHE,
231 		PGHW_NUM_COMPONENTS
232 	};
233 
234 	for (i = 0; hw_hier[i] != PGHW_NUM_COMPONENTS; i++) {
235 		if (hw_hier[i] == hw)
236 			return (i);
237 	}
238 	return (-1);
239 }
240 
241 /*
242  * Return 1 if CMT load balancing policies should be
243  * implemented across instances of the specified hardware
244  * sharing relationship.
245  */
246 int
247 pg_plat_cmt_load_bal_hw(pghw_type_t hw)
248 {
249 	if (hw == PGHW_IPIPE ||
250 	    hw == PGHW_FPU ||
251 	    hw == PGHW_CHIP)
252 		return (1);
253 	else
254 		return (0);
255 }
256 
257 
258 /*
259  * Return 1 if thread affinity polices should be implemented
260  * for instances of the specifed hardware sharing relationship.
261  */
262 int
263 pg_plat_cmt_affinity_hw(pghw_type_t hw)
264 {
265 	if (hw == PGHW_CACHE)
266 		return (1);
267 	else
268 		return (0);
269 }
270 
271 id_t
272 pg_plat_get_core_id(cpu_t *cp)
273 {
274 	return (pg_plat_hw_instance_id(cp, PGHW_IPIPE));
275 }
276 
277 void
278 cmp_set_nosteal_interval(void)
279 {
280 	/* Set the nosteal interval (used by disp_getbest()) to 100us */
281 	nosteal_nsec = 100000UL;
282 }
283 /*
284  * Return 1 if CMT load balancing policies should be
285  * implemented across instances of the specified hardware
286  * sharing relationship.
287  */
288 int
289 pg_cmt_load_bal_hw(pghw_type_t hw)
290 {
291 	if (hw == PGHW_IPIPE ||
292 	    hw == PGHW_FPU ||
293 	    hw == PGHW_CHIP)
294 		return (1);
295 	else
296 		return (0);
297 }
298 /*
299  * Return 1 if thread affinity polices should be implemented
300  * for instances of the specifed hardware sharing relationship.
301  */
302 int
303 pg_cmt_affinity_hw(pghw_type_t hw)
304 {
305 	if (hw == PGHW_CACHE)
306 		return (1);
307 	else
308 		return (0);
309 }
310