xref: /titanic_51/usr/src/uts/sun4u/opl/os/opl.c (revision b9ccdc5a0f0a722ae408b257a831b90011369316)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <sys/cpuvar.h>
29 #include <sys/systm.h>
30 #include <sys/sysmacros.h>
31 #include <sys/promif.h>
32 #include <sys/platform_module.h>
33 #include <sys/cmn_err.h>
34 #include <sys/errno.h>
35 #include <sys/machsystm.h>
36 #include <sys/bootconf.h>
37 #include <sys/nvpair.h>
38 #include <sys/kobj.h>
39 #include <sys/mem_cage.h>
40 #include <sys/opl.h>
41 #include <sys/scfd/scfostoescf.h>
42 #include <sys/cpu_sgnblk_defs.h>
43 #include <sys/utsname.h>
44 #include <sys/ddi.h>
45 #include <sys/sunndi.h>
46 #include <sys/lgrp.h>
47 #include <sys/memnode.h>
48 #include <sys/sysmacros.h>
49 #include <sys/time.h>
50 #include <sys/cpu.h>
51 #include <vm/vm_dep.h>
52 
53 int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *);
54 int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp);
55 int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp);
56 int (*opl_get_mem_addr)(char *unum, char *sid,
57     uint64_t offset, uint64_t *paddr);
58 
59 /* Memory for fcode claims.  16k times # maximum possible IO units */
60 #define	EFCODE_SIZE	(OPL_MAX_BOARDS * OPL_MAX_IO_UNITS_PER_BOARD * 0x4000)
61 int efcode_size = EFCODE_SIZE;
62 
63 #define	OPL_MC_MEMBOARD_SHIFT 38	/* Boards on 256BG boundary */
64 
65 /* Set the maximum number of boards for DR */
66 int opl_boards = OPL_MAX_BOARDS;
67 
68 void sgn_update_all_cpus(ushort_t, uchar_t, uchar_t);
69 
70 extern int tsb_lgrp_affinity;
71 
72 int opl_tsb_spares = (OPL_MAX_BOARDS) * (OPL_MAX_PCICH_UNITS_PER_BOARD) *
73 	(OPL_MAX_TSBS_PER_PCICH);
74 
75 pgcnt_t opl_startup_cage_size = 0;
76 
77 /*
78  * The length of the delay in seconds in communication with XSCF after
79  * which the warning message will be logged.
80  */
81 uint_t	xscf_connect_delay = 60 * 15;
82 
83 static opl_model_info_t opl_models[] = {
84 	{ "FF1", OPL_MAX_BOARDS_FF1, FF1, STD_DISPATCH_TABLE },
85 	{ "FF2", OPL_MAX_BOARDS_FF2, FF2, STD_DISPATCH_TABLE },
86 	{ "DC1", OPL_MAX_BOARDS_DC1, DC1, STD_DISPATCH_TABLE },
87 	{ "DC2", OPL_MAX_BOARDS_DC2, DC2, EXT_DISPATCH_TABLE },
88 	{ "DC3", OPL_MAX_BOARDS_DC3, DC3, EXT_DISPATCH_TABLE },
89 	{ "IKKAKU", OPL_MAX_BOARDS_IKKAKU, IKKAKU, STD_DISPATCH_TABLE },
90 };
91 static	int	opl_num_models = sizeof (opl_models)/sizeof (opl_model_info_t);
92 
93 /*
94  * opl_cur_model
95  */
96 static	opl_model_info_t *opl_cur_model = NULL;
97 
98 static struct memlist *opl_memlist_per_board(struct memlist *ml);
99 static void post_xscf_msg(char *, int);
100 static void pass2xscf_thread();
101 
102 /*
103  * Note FF/DC out-of-order instruction engine takes only a
104  * single cycle to execute each spin loop
105  * for comparison, Panther takes 6 cycles for same loop
106  * OPL_BOFF_SPIN = base spin loop, roughly one memory reference time
107  * OPL_BOFF_TM = approx nsec for OPL sleep instruction (1600 for OPL-C)
108  * OPL_BOFF_SLEEP = approx number of SPIN iterations to equal one sleep
109  * OPL_BOFF_MAX_SCALE - scaling factor for max backoff based on active cpus
110  * Listed values tuned for 2.15GHz to 2.64GHz systems
111  * Value may change for future systems
112  */
113 #define	OPL_BOFF_SPIN 7
114 #define	OPL_BOFF_SLEEP 4
115 #define	OPL_BOFF_TM 1600
116 #define	OPL_BOFF_MAX_SCALE 8
117 
118 #define	OPL_CLOCK_TICK_THRESHOLD	128
119 #define	OPL_CLOCK_TICK_NCPUS		64
120 
121 extern int	clock_tick_threshold;
122 extern int	clock_tick_ncpus;
123 
124 int
125 set_platform_max_ncpus(void)
126 {
127 	return (OPL_MAX_CPU_PER_BOARD * OPL_MAX_BOARDS);
128 }
129 
130 int
131 set_platform_tsb_spares(void)
132 {
133 	return (MIN(opl_tsb_spares, MAX_UPA));
134 }
135 
136 static void
137 set_model_info()
138 {
139 	extern int ts_dispatch_extended;
140 	char	name[MAXSYSNAME];
141 	int	i;
142 
143 	/*
144 	 * Get model name from the root node.
145 	 *
146 	 * We are using the prom device tree since, at this point,
147 	 * the Solaris device tree is not yet setup.
148 	 */
149 	(void) prom_getprop(prom_rootnode(), "model", (caddr_t)name);
150 
151 	for (i = 0; i < opl_num_models; i++) {
152 		if (strncmp(name, opl_models[i].model_name, MAXSYSNAME) == 0) {
153 			opl_cur_model = &opl_models[i];
154 			break;
155 		}
156 	}
157 
158 	/*
159 	 * If model not matched, it's an unknown model.
160 	 * Just return.  It will default to standard dispatch tables.
161 	 */
162 	if (i == opl_num_models)
163 		return;
164 
165 	if ((opl_cur_model->model_cmds & EXT_DISPATCH_TABLE) &&
166 	    (ts_dispatch_extended == -1)) {
167 		/*
168 		 * Based on a platform model, select a dispatch table.
169 		 * Only DC2 and DC3 systems uses the alternate/extended
170 		 * TS dispatch table.
171 		 * IKKAKU, FF1, FF2 and DC1 systems use standard dispatch
172 		 * tables.
173 		 */
174 		ts_dispatch_extended = 1;
175 	}
176 
177 }
178 
179 static void
180 set_max_mmu_ctxdoms()
181 {
182 	extern uint_t	max_mmu_ctxdoms;
183 	int		max_boards;
184 
185 	/*
186 	 * From the model, get the maximum number of boards
187 	 * supported and set the value accordingly. If the model
188 	 * could not be determined or recognized, we assume the max value.
189 	 */
190 	if (opl_cur_model == NULL)
191 		max_boards = OPL_MAX_BOARDS;
192 	else
193 		max_boards = opl_cur_model->model_max_boards;
194 
195 	/*
196 	 * On OPL, cores and MMUs are one-to-one.
197 	 */
198 	max_mmu_ctxdoms = OPL_MAX_CORE_UNITS_PER_BOARD * max_boards;
199 }
200 
201 #pragma weak mmu_init_large_pages
202 
203 void
204 set_platform_defaults(void)
205 {
206 	extern char *tod_module_name;
207 	extern void cpu_sgn_update(ushort_t, uchar_t, uchar_t, int);
208 	extern void mmu_init_large_pages(size_t);
209 
210 	/* Set the CPU signature function pointer */
211 	cpu_sgn_func = cpu_sgn_update;
212 
213 	/* Set appropriate tod module for OPL platform */
214 	ASSERT(tod_module_name == NULL);
215 	tod_module_name = "todopl";
216 
217 	if ((mmu_page_sizes == max_mmu_page_sizes) &&
218 	    (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) {
219 		if (&mmu_init_large_pages)
220 			mmu_init_large_pages(mmu_ism_pagesize);
221 	}
222 
223 	tsb_lgrp_affinity = 1;
224 
225 	set_max_mmu_ctxdoms();
226 }
227 
228 /*
229  * Convert logical a board number to a physical one.
230  */
231 
232 #define	LSBPROP		"board#"
233 #define	PSBPROP		"physical-board#"
234 
235 int
236 opl_get_physical_board(int id)
237 {
238 	dev_info_t	*root_dip, *dip = NULL;
239 	char		*dname = NULL;
240 	int		circ;
241 
242 	pnode_t		pnode;
243 	char		pname[MAXSYSNAME] = {0};
244 
245 	int		lsb_id;	/* Logical System Board ID */
246 	int		psb_id;	/* Physical System Board ID */
247 
248 
249 	/*
250 	 * This function is called on early stage of bootup when the
251 	 * kernel device tree is not initialized yet, and also
252 	 * later on when the device tree is up. We want to try
253 	 * the fast track first.
254 	 */
255 	root_dip = ddi_root_node();
256 	if (root_dip) {
257 		/* Get from devinfo node */
258 		ndi_devi_enter(root_dip, &circ);
259 		for (dip = ddi_get_child(root_dip); dip;
260 		    dip = ddi_get_next_sibling(dip)) {
261 
262 			dname = ddi_node_name(dip);
263 			if (strncmp(dname, "pseudo-mc", 9) != 0)
264 				continue;
265 
266 			if ((lsb_id = (int)ddi_getprop(DDI_DEV_T_ANY, dip,
267 			    DDI_PROP_DONTPASS, LSBPROP, -1)) == -1)
268 				continue;
269 
270 			if (id == lsb_id) {
271 				if ((psb_id = (int)ddi_getprop(DDI_DEV_T_ANY,
272 				    dip, DDI_PROP_DONTPASS, PSBPROP, -1))
273 				    == -1) {
274 					ndi_devi_exit(root_dip, circ);
275 					return (-1);
276 				} else {
277 					ndi_devi_exit(root_dip, circ);
278 					return (psb_id);
279 				}
280 			}
281 		}
282 		ndi_devi_exit(root_dip, circ);
283 	}
284 
285 	/*
286 	 * We do not have the kernel device tree, or we did not
287 	 * find the node for some reason (let's say the kernel
288 	 * device tree was modified), let's try the OBP tree.
289 	 */
290 	pnode = prom_rootnode();
291 	for (pnode = prom_childnode(pnode); pnode;
292 	    pnode = prom_nextnode(pnode)) {
293 
294 		if ((prom_getprop(pnode, "name", (caddr_t)pname) == -1) ||
295 		    (strncmp(pname, "pseudo-mc", 9) != 0))
296 			continue;
297 
298 		if (prom_getprop(pnode, LSBPROP, (caddr_t)&lsb_id) == -1)
299 			continue;
300 
301 		if (id == lsb_id) {
302 			if (prom_getprop(pnode, PSBPROP,
303 			    (caddr_t)&psb_id) == -1) {
304 				return (-1);
305 			} else {
306 				return (psb_id);
307 			}
308 		}
309 	}
310 
311 	return (-1);
312 }
313 
314 /*
315  * For OPL it's possible that memory from two or more successive boards
316  * will be contiguous across the boards, and therefore represented as a
317  * single chunk.
318  * This function splits such chunks down the board boundaries.
319  */
320 static struct memlist *
321 opl_memlist_per_board(struct memlist *ml)
322 {
323 	uint64_t ssize, low, high, boundary;
324 	struct memlist *head, *tail, *new;
325 
326 	ssize = (1ull << OPL_MC_MEMBOARD_SHIFT);
327 
328 	head = tail = NULL;
329 
330 	for (; ml; ml = ml->next) {
331 		low  = (uint64_t)ml->address;
332 		high = low+(uint64_t)(ml->size);
333 		while (low < high) {
334 			boundary = roundup(low+1, ssize);
335 			boundary = MIN(high, boundary);
336 			new = kmem_zalloc(sizeof (struct memlist), KM_SLEEP);
337 			new->address = low;
338 			new->size = boundary - low;
339 			if (head == NULL)
340 				head = new;
341 			if (tail) {
342 				tail->next = new;
343 				new->prev = tail;
344 			}
345 			tail = new;
346 			low = boundary;
347 		}
348 	}
349 	return (head);
350 }
351 
352 void
353 set_platform_cage_params(void)
354 {
355 	extern pgcnt_t total_pages;
356 	extern struct memlist *phys_avail;
357 	struct memlist *ml, *tml;
358 
359 	if (kernel_cage_enable) {
360 		pgcnt_t preferred_cage_size;
361 
362 		preferred_cage_size = MAX(opl_startup_cage_size,
363 		    total_pages / 256);
364 
365 		ml = opl_memlist_per_board(phys_avail);
366 
367 		/*
368 		 * Note: we are assuming that post has load the
369 		 * whole show in to the high end of memory. Having
370 		 * taken this leap, we copy the whole of phys_avail
371 		 * the glist and arrange for the cage to grow
372 		 * downward (descending pfns).
373 		 */
374 		kcage_range_init(ml, KCAGE_DOWN, preferred_cage_size);
375 
376 		/* free the memlist */
377 		do {
378 			tml = ml->next;
379 			kmem_free(ml, sizeof (struct memlist));
380 			ml = tml;
381 		} while (ml != NULL);
382 	}
383 
384 	if (kcage_on)
385 		cmn_err(CE_NOTE, "!DR Kernel Cage is ENABLED");
386 	else
387 		cmn_err(CE_NOTE, "!DR Kernel Cage is DISABLED");
388 }
389 
390 /*ARGSUSED*/
391 int
392 plat_cpu_poweron(struct cpu *cp)
393 {
394 	int (*opl_cpu_poweron)(struct cpu *) = NULL;
395 
396 	opl_cpu_poweron =
397 	    (int (*)(struct cpu *))kobj_getsymvalue("drmach_cpu_poweron", 0);
398 
399 	if (opl_cpu_poweron == NULL)
400 		return (ENOTSUP);
401 	else
402 		return ((opl_cpu_poweron)(cp));
403 
404 }
405 
406 /*ARGSUSED*/
407 int
408 plat_cpu_poweroff(struct cpu *cp)
409 {
410 	int (*opl_cpu_poweroff)(struct cpu *) = NULL;
411 
412 	opl_cpu_poweroff =
413 	    (int (*)(struct cpu *))kobj_getsymvalue("drmach_cpu_poweroff", 0);
414 
415 	if (opl_cpu_poweroff == NULL)
416 		return (ENOTSUP);
417 	else
418 		return ((opl_cpu_poweroff)(cp));
419 
420 }
421 
422 int
423 plat_max_boards(void)
424 {
425 	/*
426 	 * If the model cannot be determined, default to the max value.
427 	 * Otherwise, Ikkaku model only supports 1 system board.
428 	 */
429 	if ((opl_cur_model != NULL) && (opl_cur_model->model_type == IKKAKU))
430 		return (OPL_MAX_BOARDS_IKKAKU);
431 	else
432 		return (OPL_MAX_BOARDS);
433 }
434 
435 int
436 plat_max_cpu_units_per_board(void)
437 {
438 	return (OPL_MAX_CPU_PER_BOARD);
439 }
440 
441 int
442 plat_max_mem_units_per_board(void)
443 {
444 	return (OPL_MAX_MEM_UNITS_PER_BOARD);
445 }
446 
447 int
448 plat_max_io_units_per_board(void)
449 {
450 	return (OPL_MAX_IO_UNITS_PER_BOARD);
451 }
452 
453 int
454 plat_max_cmp_units_per_board(void)
455 {
456 	return (OPL_MAX_CMP_UNITS_PER_BOARD);
457 }
458 
459 int
460 plat_max_core_units_per_board(void)
461 {
462 	return (OPL_MAX_CORE_UNITS_PER_BOARD);
463 }
464 
465 int
466 plat_pfn_to_mem_node(pfn_t pfn)
467 {
468 	return (pfn >> mem_node_pfn_shift);
469 }
470 
471 /* ARGSUSED */
472 void
473 plat_build_mem_nodes(prom_memlist_t *list, size_t nelems)
474 {
475 	size_t	elem;
476 	pfn_t	basepfn;
477 	pgcnt_t	npgs;
478 	uint64_t	boundary, ssize;
479 	uint64_t	low, high;
480 
481 	/*
482 	 * OPL mem slices are always aligned on a 256GB boundary.
483 	 */
484 	mem_node_pfn_shift = OPL_MC_MEMBOARD_SHIFT - MMU_PAGESHIFT;
485 	mem_node_physalign = 0;
486 
487 	/*
488 	 * Boot install lists are arranged <addr, len>, <addr, len>, ...
489 	 */
490 	ssize = (1ull << OPL_MC_MEMBOARD_SHIFT);
491 	for (elem = 0; elem < nelems; list++, elem++) {
492 		low  = list->addr;
493 		high = low + list->size;
494 		while (low < high) {
495 			boundary = roundup(low+1, ssize);
496 			boundary = MIN(high, boundary);
497 			basepfn = btop(low);
498 			npgs = btop(boundary - low);
499 			mem_node_add_slice(basepfn, basepfn + npgs - 1);
500 			low = boundary;
501 		}
502 	}
503 }
504 
505 /*
506  * Find the CPU associated with a slice at boot-time.
507  */
508 void
509 plat_fill_mc(pnode_t nodeid)
510 {
511 	int board;
512 	int memnode;
513 	struct {
514 		uint64_t	addr;
515 		uint64_t	size;
516 	} mem_range;
517 
518 	if (prom_getprop(nodeid, "board#", (caddr_t)&board) < 0) {
519 		panic("Can not find board# property in mc node %x", nodeid);
520 	}
521 	if (prom_getprop(nodeid, "sb-mem-ranges", (caddr_t)&mem_range) < 0) {
522 		panic("Can not find sb-mem-ranges property in mc node %x",
523 		    nodeid);
524 	}
525 	memnode = mem_range.addr >> OPL_MC_MEMBOARD_SHIFT;
526 	plat_assign_lgrphand_to_mem_node(board, memnode);
527 }
528 
529 /*
530  * Return the platform handle for the lgroup containing the given CPU
531  *
532  * For OPL, lgroup platform handle == board #.
533  */
534 
535 extern int mpo_disabled;
536 extern lgrp_handle_t lgrp_default_handle;
537 
538 lgrp_handle_t
539 plat_lgrp_cpu_to_hand(processorid_t id)
540 {
541 	lgrp_handle_t plathand;
542 
543 	/*
544 	 * Return the real platform handle for the CPU until
545 	 * such time as we know that MPO should be disabled.
546 	 * At that point, we set the "mpo_disabled" flag to true,
547 	 * and from that point on, return the default handle.
548 	 *
549 	 * By the time we know that MPO should be disabled, the
550 	 * first CPU will have already been added to a leaf
551 	 * lgroup, but that's ok. The common lgroup code will
552 	 * double check that the boot CPU is in the correct place,
553 	 * and in the case where mpo should be disabled, will move
554 	 * it to the root if necessary.
555 	 */
556 	if (mpo_disabled) {
557 		/* If MPO is disabled, return the default (UMA) handle */
558 		plathand = lgrp_default_handle;
559 	} else
560 		plathand = (lgrp_handle_t)LSB_ID(id);
561 	return (plathand);
562 }
563 
564 /*
565  * Platform specific lgroup initialization
566  */
567 void
568 plat_lgrp_init(void)
569 {
570 	extern uint32_t lgrp_expand_proc_thresh;
571 	extern uint32_t lgrp_expand_proc_diff;
572 	const uint_t m = LGRP_LOADAVG_THREAD_MAX;
573 
574 	/*
575 	 * Set tuneables for the OPL architecture
576 	 *
577 	 * lgrp_expand_proc_thresh is the threshold load on the set of
578 	 * lgroups a process is currently using on before considering
579 	 * adding another lgroup to the set.  For Oly-C and Jupiter
580 	 * systems, there are four sockets per lgroup. Setting
581 	 * lgrp_expand_proc_thresh to add lgroups when the load reaches
582 	 * four threads will spread the load when it exceeds one thread
583 	 * per socket, optimizing memory bandwidth and L2 cache space.
584 	 *
585 	 * lgrp_expand_proc_diff determines how much less another lgroup
586 	 * must be loaded before shifting the start location of a thread
587 	 * to it.
588 	 *
589 	 * lgrp_loadavg_tolerance is the threshold where two lgroups are
590 	 * considered to have different loads.  It is set to be less than
591 	 * 1% so that even a small residual load will be considered different
592 	 * from no residual load.
593 	 *
594 	 * We note loadavg values are not precise.
595 	 * Every 1/10 of a second loadavg values are reduced by 5%.
596 	 * This adjustment can come in the middle of the lgroup selection
597 	 * process, and for larger parallel apps with many threads can
598 	 * frequently occur between the start of the second thread
599 	 * placement and the finish of the last thread placement.
600 	 * We also must be careful to not use too small of a threshold
601 	 * since the cumulative decay for 1 second idle time is 40%.
602 	 * That is, the residual load from completed threads will still
603 	 * be 60% one second after the proc goes idle or 8% after 5 seconds.
604 	 *
605 	 * To allow for lag time in loadavg calculations
606 	 * remote thresh = 3.75 * LGRP_LOADAVG_THREAD_MAX
607 	 * local thresh  = 0.75 * LGRP_LOADAVG_THREAD_MAX
608 	 * tolerance	 = 0.0078 * LGRP_LOADAVG_THREAD_MAX
609 	 *
610 	 * The load placement algorithms consider LGRP_LOADAVG_THREAD_MAX
611 	 * as the equivalent of a load of 1. To make the code more compact,
612 	 * we set m = LGRP_LOADAVG_THREAD_MAX.
613 	 */
614 	lgrp_expand_proc_thresh = (m * 3) + (m >> 1) + (m >> 2);
615 	lgrp_expand_proc_diff = (m >> 1) + (m >> 2);
616 	lgrp_loadavg_tolerance = (m >> 7);
617 }
618 
619 /*
620  * Platform notification of lgroup (re)configuration changes
621  */
622 /*ARGSUSED*/
623 void
624 plat_lgrp_config(lgrp_config_flag_t evt, uintptr_t arg)
625 {
626 	update_membounds_t *umb;
627 	lgrp_config_mem_rename_t lmr;
628 	int sbd, tbd;
629 	lgrp_handle_t hand, shand, thand;
630 	int mnode, snode, tnode;
631 	pfn_t start, end;
632 
633 	if (mpo_disabled)
634 		return;
635 
636 	switch (evt) {
637 
638 	case LGRP_CONFIG_MEM_ADD:
639 		/*
640 		 * Establish the lgroup handle to memnode translation.
641 		 */
642 		umb = (update_membounds_t *)arg;
643 
644 		hand = umb->u_board;
645 		mnode = plat_pfn_to_mem_node(umb->u_base >> MMU_PAGESHIFT);
646 		plat_assign_lgrphand_to_mem_node(hand, mnode);
647 
648 		break;
649 
650 	case LGRP_CONFIG_MEM_DEL:
651 		/*
652 		 * Special handling for possible memory holes.
653 		 */
654 		umb = (update_membounds_t *)arg;
655 		hand = umb->u_board;
656 		if ((mnode = plat_lgrphand_to_mem_node(hand)) != -1) {
657 			if (mem_node_config[mnode].exists) {
658 				start = mem_node_config[mnode].physbase;
659 				end = mem_node_config[mnode].physmax;
660 				mem_node_pre_del_slice(start, end);
661 				mem_node_post_del_slice(start, end, 0);
662 			}
663 		}
664 
665 		break;
666 
667 	case LGRP_CONFIG_MEM_RENAME:
668 		/*
669 		 * During a DR copy-rename operation, all of the memory
670 		 * on one board is moved to another board -- but the
671 		 * addresses/pfns and memnodes don't change. This means
672 		 * the memory has changed locations without changing identity.
673 		 *
674 		 * Source is where we are copying from and target is where we
675 		 * are copying to.  After source memnode is copied to target
676 		 * memnode, the physical addresses of the target memnode are
677 		 * renamed to match what the source memnode had.  Then target
678 		 * memnode can be removed and source memnode can take its
679 		 * place.
680 		 *
681 		 * To do this, swap the lgroup handle to memnode mappings for
682 		 * the boards, so target lgroup will have source memnode and
683 		 * source lgroup will have empty target memnode which is where
684 		 * its memory will go (if any is added to it later).
685 		 *
686 		 * Then source memnode needs to be removed from its lgroup
687 		 * and added to the target lgroup where the memory was living
688 		 * but under a different name/memnode.  The memory was in the
689 		 * target memnode and now lives in the source memnode with
690 		 * different physical addresses even though it is the same
691 		 * memory.
692 		 */
693 		sbd = arg & 0xffff;
694 		tbd = (arg & 0xffff0000) >> 16;
695 		shand = sbd;
696 		thand = tbd;
697 		snode = plat_lgrphand_to_mem_node(shand);
698 		tnode = plat_lgrphand_to_mem_node(thand);
699 
700 		/*
701 		 * Special handling for possible memory holes.
702 		 */
703 		if (tnode != -1 && mem_node_config[tnode].exists) {
704 			start = mem_node_config[tnode].physbase;
705 			end = mem_node_config[tnode].physmax;
706 			mem_node_pre_del_slice(start, end);
707 			mem_node_post_del_slice(start, end, 0);
708 		}
709 
710 		plat_assign_lgrphand_to_mem_node(thand, snode);
711 		plat_assign_lgrphand_to_mem_node(shand, tnode);
712 
713 		lmr.lmem_rename_from = shand;
714 		lmr.lmem_rename_to = thand;
715 
716 		/*
717 		 * Remove source memnode of copy rename from its lgroup
718 		 * and add it to its new target lgroup
719 		 */
720 		lgrp_config(LGRP_CONFIG_MEM_RENAME, (uintptr_t)snode,
721 		    (uintptr_t)&lmr);
722 
723 		break;
724 
725 	default:
726 		break;
727 	}
728 }
729 
730 /*
731  * Return latency between "from" and "to" lgroups
732  *
733  * This latency number can only be used for relative comparison
734  * between lgroups on the running system, cannot be used across platforms,
735  * and may not reflect the actual latency.  It is platform and implementation
736  * specific, so platform gets to decide its value.  It would be nice if the
737  * number was at least proportional to make comparisons more meaningful though.
738  * NOTE: The numbers below are supposed to be load latencies for uncached
739  * memory divided by 10.
740  *
741  */
742 int
743 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to)
744 {
745 	/*
746 	 * Return min remote latency when there are more than two lgroups
747 	 * (root and child) and getting latency between two different lgroups
748 	 * or root is involved
749 	 */
750 	if (lgrp_optimizations() && (from != to ||
751 	    from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE))
752 		return (42);
753 	else
754 		return (35);
755 }
756 
757 /*
758  * Return platform handle for root lgroup
759  */
760 lgrp_handle_t
761 plat_lgrp_root_hand(void)
762 {
763 	if (mpo_disabled)
764 		return (lgrp_default_handle);
765 
766 	return (LGRP_DEFAULT_HANDLE);
767 }
768 
769 /*ARGSUSED*/
770 void
771 plat_freelist_process(int mnode)
772 {
773 }
774 
775 void
776 load_platform_drivers(void)
777 {
778 	(void) i_ddi_attach_pseudo_node("dr");
779 }
780 
781 /*
782  * No platform drivers on this platform
783  */
784 char *platform_module_list[] = {
785 	(char *)0
786 };
787 
788 /*ARGSUSED*/
789 void
790 plat_tod_fault(enum tod_fault_type tod_bad)
791 {
792 }
793 
794 /*ARGSUSED*/
795 void
796 cpu_sgn_update(ushort_t sgn, uchar_t state, uchar_t sub_state, int cpuid)
797 {
798 	static void (*scf_panic_callback)(int);
799 	static void (*scf_shutdown_callback)(int);
800 
801 	/*
802 	 * This is for notifing system panic/shutdown to SCF.
803 	 * In case of shutdown and panic, SCF call back
804 	 * function should be called.
805 	 *  <SCF call back functions>
806 	 *   scf_panic_callb()   : panicsys()->panic_quiesce_hw()
807 	 *   scf_shutdown_callb(): halt() or power_down() or reboot_machine()
808 	 * cpuid should be -1 and state should be SIGST_EXIT.
809 	 */
810 	if (state == SIGST_EXIT && cpuid == -1) {
811 
812 		/*
813 		 * find the symbol for the SCF panic callback routine in driver
814 		 */
815 		if (scf_panic_callback == NULL)
816 			scf_panic_callback = (void (*)(int))
817 			    modgetsymvalue("scf_panic_callb", 0);
818 		if (scf_shutdown_callback == NULL)
819 			scf_shutdown_callback = (void (*)(int))
820 			    modgetsymvalue("scf_shutdown_callb", 0);
821 
822 		switch (sub_state) {
823 		case SIGSUBST_PANIC:
824 			if (scf_panic_callback == NULL) {
825 				cmn_err(CE_NOTE, "!cpu_sgn_update: "
826 				    "scf_panic_callb not found\n");
827 				return;
828 			}
829 			scf_panic_callback(SIGSUBST_PANIC);
830 			break;
831 
832 		case SIGSUBST_HALT:
833 			if (scf_shutdown_callback == NULL) {
834 				cmn_err(CE_NOTE, "!cpu_sgn_update: "
835 				    "scf_shutdown_callb not found\n");
836 				return;
837 			}
838 			scf_shutdown_callback(SIGSUBST_HALT);
839 			break;
840 
841 		case SIGSUBST_ENVIRON:
842 			if (scf_shutdown_callback == NULL) {
843 				cmn_err(CE_NOTE, "!cpu_sgn_update: "
844 				    "scf_shutdown_callb not found\n");
845 				return;
846 			}
847 			scf_shutdown_callback(SIGSUBST_ENVIRON);
848 			break;
849 
850 		case SIGSUBST_REBOOT:
851 			if (scf_shutdown_callback == NULL) {
852 				cmn_err(CE_NOTE, "!cpu_sgn_update: "
853 				    "scf_shutdown_callb not found\n");
854 				return;
855 			}
856 			scf_shutdown_callback(SIGSUBST_REBOOT);
857 			break;
858 		}
859 	}
860 }
861 
862 /*ARGSUSED*/
863 int
864 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id,
865 	int flt_in_memory, ushort_t flt_status,
866 	char *buf, int buflen, int *lenp)
867 {
868 	/*
869 	 * check if it's a Memory error.
870 	 */
871 	if (flt_in_memory) {
872 		if (opl_get_mem_unum != NULL) {
873 			return (opl_get_mem_unum(synd_code, flt_addr, buf,
874 			    buflen, lenp));
875 		} else {
876 			return (ENOTSUP);
877 		}
878 	} else {
879 		return (ENOTSUP);
880 	}
881 }
882 
883 /*ARGSUSED*/
884 int
885 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
886 {
887 	int	ret = 0;
888 	int	sb;
889 	int	plen;
890 
891 	sb = opl_get_physical_board(LSB_ID(cpuid));
892 	if (sb == -1) {
893 		return (ENXIO);
894 	}
895 
896 	/*
897 	 * opl_cur_model is assigned here
898 	 */
899 	if (opl_cur_model == NULL) {
900 		set_model_info();
901 
902 		/*
903 		 * if not matched, return
904 		 */
905 		if (opl_cur_model == NULL)
906 			return (ENODEV);
907 	}
908 
909 	ASSERT((opl_cur_model - opl_models) == (opl_cur_model->model_type));
910 
911 	switch (opl_cur_model->model_type) {
912 	case FF1:
913 		plen = snprintf(buf, buflen, "/%s/CPUM%d", "MBU_A",
914 		    CHIP_ID(cpuid) / 2);
915 		break;
916 
917 	case FF2:
918 		plen = snprintf(buf, buflen, "/%s/CPUM%d", "MBU_B",
919 		    (CHIP_ID(cpuid) / 2) + (sb * 2));
920 		break;
921 
922 	case DC1:
923 	case DC2:
924 	case DC3:
925 		plen = snprintf(buf, buflen, "/%s%02d/CPUM%d", "CMU", sb,
926 		    CHIP_ID(cpuid));
927 		break;
928 
929 	case IKKAKU:
930 		plen = snprintf(buf, buflen, "/%s", "MBU_A");
931 		break;
932 
933 	default:
934 		/* This should never happen */
935 		return (ENODEV);
936 	}
937 
938 	if (plen >= buflen) {
939 		ret = ENOSPC;
940 	} else {
941 		if (lenp)
942 			*lenp = strlen(buf);
943 	}
944 	return (ret);
945 }
946 
947 void
948 plat_nodename_set(void)
949 {
950 	post_xscf_msg((char *)&utsname, sizeof (struct utsname));
951 }
952 
953 caddr_t	efcode_vaddr = NULL;
954 
955 /*
956  * Preallocate enough memory for fcode claims.
957  */
958 
959 caddr_t
960 efcode_alloc(caddr_t alloc_base)
961 {
962 	caddr_t efcode_alloc_base = (caddr_t)roundup((uintptr_t)alloc_base,
963 	    MMU_PAGESIZE);
964 	caddr_t vaddr;
965 
966 	/*
967 	 * allocate the physical memory for the Oberon fcode.
968 	 */
969 	if ((vaddr = (caddr_t)BOP_ALLOC(bootops, efcode_alloc_base,
970 	    efcode_size, MMU_PAGESIZE)) == NULL)
971 		cmn_err(CE_PANIC, "Cannot allocate Efcode Memory");
972 
973 	efcode_vaddr = vaddr;
974 
975 	return (efcode_alloc_base + efcode_size);
976 }
977 
978 caddr_t
979 plat_startup_memlist(caddr_t alloc_base)
980 {
981 	caddr_t tmp_alloc_base;
982 
983 	tmp_alloc_base = efcode_alloc(alloc_base);
984 	tmp_alloc_base =
985 	    (caddr_t)roundup((uintptr_t)tmp_alloc_base, ecache_alignsize);
986 	return (tmp_alloc_base);
987 }
988 
989 /* need to forward declare these */
990 static void plat_lock_delay(uint_t);
991 
992 void
993 startup_platform(void)
994 {
995 	if (clock_tick_threshold == 0)
996 		clock_tick_threshold = OPL_CLOCK_TICK_THRESHOLD;
997 	if (clock_tick_ncpus == 0)
998 		clock_tick_ncpus = OPL_CLOCK_TICK_NCPUS;
999 	mutex_lock_delay = plat_lock_delay;
1000 	mutex_cap_factor = OPL_BOFF_MAX_SCALE;
1001 }
1002 
1003 static uint_t
1004 get_mmu_id(processorid_t cpuid)
1005 {
1006 	int pb = opl_get_physical_board(LSB_ID(cpuid));
1007 
1008 	if (pb == -1) {
1009 		cmn_err(CE_PANIC,
1010 		    "opl_get_physical_board failed (cpu %d LSB %u)",
1011 		    cpuid, LSB_ID(cpuid));
1012 	}
1013 	return (pb * OPL_MAX_COREID_PER_BOARD) + (CHIP_ID(cpuid) *
1014 	    OPL_MAX_COREID_PER_CMP) + CORE_ID(cpuid);
1015 }
1016 
1017 void
1018 plat_cpuid_to_mmu_ctx_info(processorid_t cpuid, mmu_ctx_info_t *info)
1019 {
1020 	int	impl;
1021 
1022 	impl = cpunodes[cpuid].implementation;
1023 	if (IS_OLYMPUS_C(impl) || IS_JUPITER(impl)) {
1024 		info->mmu_idx = get_mmu_id(cpuid);
1025 		info->mmu_nctxs = 8192;
1026 	} else {
1027 		cmn_err(CE_PANIC, "Unknown processor %d", impl);
1028 	}
1029 }
1030 
1031 int
1032 plat_get_mem_sid(char *unum, char *buf, int buflen, int *lenp)
1033 {
1034 	if (opl_get_mem_sid == NULL) {
1035 		return (ENOTSUP);
1036 	}
1037 	return (opl_get_mem_sid(unum, buf, buflen, lenp));
1038 }
1039 
1040 int
1041 plat_get_mem_offset(uint64_t paddr, uint64_t *offp)
1042 {
1043 	if (opl_get_mem_offset == NULL) {
1044 		return (ENOTSUP);
1045 	}
1046 	return (opl_get_mem_offset(paddr, offp));
1047 }
1048 
1049 int
1050 plat_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp)
1051 {
1052 	if (opl_get_mem_addr == NULL) {
1053 		return (ENOTSUP);
1054 	}
1055 	return (opl_get_mem_addr(unum, sid, offset, addrp));
1056 }
1057 
1058 void
1059 plat_lock_delay(uint_t backoff)
1060 {
1061 	int i;
1062 	uint_t cnt, remcnt;
1063 	int ctr;
1064 	hrtime_t delay_start, rem_delay;
1065 	/*
1066 	 * Platform specific lock delay code for OPL
1067 	 *
1068 	 * Using staged linear increases in the delay.
1069 	 * The sleep instruction is the preferred method of delay,
1070 	 * but is too large of granularity for the initial backoff.
1071 	 */
1072 
1073 	if (backoff < 100) {
1074 		/*
1075 		 * If desired backoff is long enough,
1076 		 * use sleep for most of it
1077 		 */
1078 		for (cnt = backoff;
1079 		    cnt >= OPL_BOFF_SLEEP;
1080 		    cnt -= OPL_BOFF_SLEEP) {
1081 			cpu_smt_pause();
1082 		}
1083 		/*
1084 		 * spin for small remainder of backoff
1085 		 */
1086 		for (ctr = cnt * OPL_BOFF_SPIN; ctr; ctr--) {
1087 			mutex_delay_default();
1088 		}
1089 	} else {
1090 		/* backoff is large.  Fill it by sleeping */
1091 		delay_start = gethrtime_waitfree();
1092 		cnt = backoff / OPL_BOFF_SLEEP;
1093 		/*
1094 		 * use sleep instructions for delay
1095 		 */
1096 		for (i = 0; i < cnt; i++) {
1097 			cpu_smt_pause();
1098 		}
1099 
1100 		/*
1101 		 * Note: if the other strand executes a sleep instruction,
1102 		 * then the sleep ends immediately with a minimum time of
1103 		 * 42 clocks.  We check gethrtime to insure we have
1104 		 * waited long enough.  And we include both a short
1105 		 * spin loop and a sleep for repeated delay times.
1106 		 */
1107 
1108 		rem_delay = gethrtime_waitfree() - delay_start;
1109 		while (rem_delay < cnt * OPL_BOFF_TM) {
1110 			remcnt = cnt - (rem_delay / OPL_BOFF_TM);
1111 			for (i = 0; i < remcnt; i++) {
1112 				cpu_smt_pause();
1113 				for (ctr = OPL_BOFF_SPIN; ctr; ctr--) {
1114 					mutex_delay_default();
1115 				}
1116 			}
1117 			rem_delay = gethrtime_waitfree() - delay_start;
1118 		}
1119 	}
1120 }
1121 
1122 /*
1123  * The following code implements asynchronous call to XSCF to setup the
1124  * domain node name.
1125  */
1126 
1127 #define	FREE_MSG(m)		kmem_free((m), NM_LEN((m)->len))
1128 
1129 /*
1130  * The following three macros define the all operations on the request
1131  * list we are using here, and hide the details of the list
1132  * implementation from the code.
1133  */
1134 #define	PUSH(m) \
1135 	{ \
1136 		(m)->next = ctl_msg.head; \
1137 		(m)->prev = NULL; \
1138 		if ((m)->next != NULL) \
1139 			(m)->next->prev = (m); \
1140 		ctl_msg.head = (m); \
1141 	}
1142 
1143 #define	REMOVE(m) \
1144 	{ \
1145 		if ((m)->prev != NULL) \
1146 			(m)->prev->next = (m)->next; \
1147 		else \
1148 			ctl_msg.head = (m)->next; \
1149 		if ((m)->next != NULL) \
1150 			(m)->next->prev = (m)->prev; \
1151 	}
1152 
1153 #define	FREE_THE_TAIL(head) \
1154 	{ \
1155 		nm_msg_t *n_msg, *m; \
1156 		m = (head)->next; \
1157 		(head)->next = NULL; \
1158 		while (m != NULL) { \
1159 			n_msg = m->next; \
1160 			FREE_MSG(m); \
1161 			m = n_msg; \
1162 		} \
1163 	}
1164 
1165 #define	SCF_PUTINFO(f, s, p) \
1166 	f(KEY_ESCF, 0x01, 0, s, p)
1167 
1168 #define	PASS2XSCF(m, r)	((r = SCF_PUTINFO(ctl_msg.scf_service_function, \
1169 					    (m)->len, (m)->data)) == 0)
1170 
1171 /*
1172  * The value of the following macro loosely depends on the
1173  * value of the "device busy" timeout used in the SCF driver.
1174  * (See pass2xscf_thread()).
1175  */
1176 #define	SCF_DEVBUSY_DELAY	10
1177 
1178 /*
1179  * The default number of attempts to contact the scf driver
1180  * if we cannot fetch any information about the timeout value
1181  * it uses.
1182  */
1183 
1184 #define	REPEATS		4
1185 
1186 typedef struct nm_msg {
1187 	struct nm_msg *next;
1188 	struct nm_msg *prev;
1189 	int len;
1190 	char data[1];
1191 } nm_msg_t;
1192 
1193 #define	NM_LEN(len)		(sizeof (nm_msg_t) + (len) - 1)
1194 
1195 static struct ctlmsg {
1196 	nm_msg_t	*head;
1197 	nm_msg_t	*now_serving;
1198 	kmutex_t	nm_lock;
1199 	kthread_t	*nmt;
1200 	int		cnt;
1201 	int (*scf_service_function)(uint32_t, uint8_t,
1202 				    uint32_t, uint32_t, void *);
1203 } ctl_msg;
1204 
1205 static void
1206 post_xscf_msg(char *dp, int len)
1207 {
1208 	nm_msg_t *msg;
1209 
1210 	msg = (nm_msg_t *)kmem_zalloc(NM_LEN(len), KM_SLEEP);
1211 
1212 	bcopy(dp, msg->data, len);
1213 	msg->len = len;
1214 
1215 	mutex_enter(&ctl_msg.nm_lock);
1216 	if (ctl_msg.nmt == NULL) {
1217 		ctl_msg.nmt =  thread_create(NULL, 0, pass2xscf_thread,
1218 		    NULL, 0, &p0, TS_RUN, minclsyspri);
1219 	}
1220 
1221 	PUSH(msg);
1222 	ctl_msg.cnt++;
1223 	mutex_exit(&ctl_msg.nm_lock);
1224 }
1225 
1226 static void
1227 pass2xscf_thread()
1228 {
1229 	nm_msg_t *msg;
1230 	int ret;
1231 	uint_t i, msg_sent, xscf_driver_delay;
1232 	static uint_t repeat_cnt;
1233 	uint_t *scf_wait_cnt;
1234 
1235 	mutex_enter(&ctl_msg.nm_lock);
1236 
1237 	/*
1238 	 * Find the address of the SCF put routine if it's not done yet.
1239 	 */
1240 	if (ctl_msg.scf_service_function == NULL) {
1241 		if ((ctl_msg.scf_service_function =
1242 		    (int (*)(uint32_t, uint8_t, uint32_t, uint32_t, void *))
1243 		    modgetsymvalue("scf_service_putinfo", 0)) == NULL) {
1244 			cmn_err(CE_NOTE, "pass2xscf_thread: "
1245 			    "scf_service_putinfo not found\n");
1246 			ctl_msg.nmt = NULL;
1247 			mutex_exit(&ctl_msg.nm_lock);
1248 			return;
1249 		}
1250 	}
1251 
1252 	/*
1253 	 * Calculate the number of attempts to connect XSCF based on the
1254 	 * scf driver delay (which is
1255 	 * SCF_DEVBUSY_DELAY*scf_online_wait_rcnt seconds) and the value
1256 	 * of xscf_connect_delay (the total number of seconds to wait
1257 	 * till xscf get ready.)
1258 	 */
1259 	if (repeat_cnt == 0) {
1260 		if ((scf_wait_cnt =
1261 		    (uint_t *)
1262 		    modgetsymvalue("scf_online_wait_rcnt", 0)) == NULL) {
1263 			repeat_cnt = REPEATS;
1264 		} else {
1265 
1266 			xscf_driver_delay = *scf_wait_cnt *
1267 			    SCF_DEVBUSY_DELAY;
1268 			repeat_cnt = (xscf_connect_delay/xscf_driver_delay) + 1;
1269 		}
1270 	}
1271 
1272 	while (ctl_msg.cnt != 0) {
1273 
1274 		/*
1275 		 * Take the very last request from the queue,
1276 		 */
1277 		ctl_msg.now_serving = ctl_msg.head;
1278 		ASSERT(ctl_msg.now_serving != NULL);
1279 
1280 		/*
1281 		 * and discard all the others if any.
1282 		 */
1283 		FREE_THE_TAIL(ctl_msg.now_serving);
1284 		ctl_msg.cnt = 1;
1285 		mutex_exit(&ctl_msg.nm_lock);
1286 
1287 		/*
1288 		 * Pass the name to XSCF. Note please, we do not hold the
1289 		 * mutex while we are doing this.
1290 		 */
1291 		msg_sent = 0;
1292 		for (i = 0; i < repeat_cnt; i++) {
1293 			if (PASS2XSCF(ctl_msg.now_serving, ret)) {
1294 				msg_sent = 1;
1295 				break;
1296 			} else {
1297 				if (ret != EBUSY) {
1298 					cmn_err(CE_NOTE, "pass2xscf_thread:"
1299 					    " unexpected return code"
1300 					    " from scf_service_putinfo():"
1301 					    " %d\n", ret);
1302 				}
1303 			}
1304 		}
1305 
1306 		if (msg_sent) {
1307 
1308 			/*
1309 			 * Remove the request from the list
1310 			 */
1311 			mutex_enter(&ctl_msg.nm_lock);
1312 			msg = ctl_msg.now_serving;
1313 			ctl_msg.now_serving = NULL;
1314 			REMOVE(msg);
1315 			ctl_msg.cnt--;
1316 			mutex_exit(&ctl_msg.nm_lock);
1317 			FREE_MSG(msg);
1318 		} else {
1319 
1320 			/*
1321 			 * If while we have tried to communicate with
1322 			 * XSCF there were any other requests we are
1323 			 * going to drop this one and take the latest
1324 			 * one.  Otherwise we will try to pass this one
1325 			 * again.
1326 			 */
1327 			cmn_err(CE_NOTE,
1328 			    "pass2xscf_thread: "
1329 			    "scf_service_putinfo "
1330 			    "not responding\n");
1331 		}
1332 		mutex_enter(&ctl_msg.nm_lock);
1333 	}
1334 
1335 	/*
1336 	 * The request queue is empty, exit.
1337 	 */
1338 	ctl_msg.nmt = NULL;
1339 	mutex_exit(&ctl_msg.nm_lock);
1340 }
1341