xref: /titanic_51/usr/src/uts/sun4u/ngdr/io/dr_cpu.c (revision 2917a9c9c3eee6fcaedb239f5f68da01f4ed0da9)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  * CPU support routines for DR
30  */
31 
32 #include <sys/note.h>
33 #include <sys/debug.h>
34 #include <sys/types.h>
35 #include <sys/errno.h>
36 #include <sys/cred.h>
37 #include <sys/dditypes.h>
38 #include <sys/devops.h>
39 #include <sys/modctl.h>
40 #include <sys/poll.h>
41 #include <sys/conf.h>
42 #include <sys/ddi.h>
43 #include <sys/sunddi.h>
44 #include <sys/sunndi.h>
45 #include <sys/ndi_impldefs.h>
46 #include <sys/stat.h>
47 #include <sys/kmem.h>
48 #include <sys/processor.h>
49 #include <sys/cpuvar.h>
50 #include <sys/mem_config.h>
51 #include <sys/promif.h>
52 #include <sys/x_call.h>
53 #include <sys/cpu_sgnblk_defs.h>
54 #include <sys/membar.h>
55 #include <sys/stack.h>
56 #include <sys/sysmacros.h>
57 #include <sys/machsystm.h>
58 #include <sys/spitregs.h>
59 
60 #include <sys/archsystm.h>
61 #include <vm/hat_sfmmu.h>
62 #include <sys/pte.h>
63 #include <sys/mmu.h>
64 #include <sys/x_call.h>
65 #include <sys/cpu_module.h>
66 #include <sys/cpu_impl.h>
67 
68 #include <sys/autoconf.h>
69 #include <sys/cmn_err.h>
70 
71 #include <sys/dr.h>
72 #include <sys/dr_util.h>
73 
74 #ifdef _STARFIRE
75 #include <sys/starfire.h>
76 extern struct cpu	*SIGBCPU;
77 #else
78 /* for the DR*INTERNAL_ERROR macros.  see sys/dr.h. */
79 static char *dr_ie_fmt = "dr_cpu.c %d";
80 #endif /* _STARFIRE */
81 
82 int
83 dr_cpu_unit_is_sane(dr_board_t *bp, dr_cpu_unit_t *cp)
84 {
85 #ifdef DEBUG
86 	processorid_t	cpuid;
87 
88 	/*
89 	 * cpuid and unit number should never be different
90 	 * than they were at discovery/connect time
91 	 */
92 	ASSERT(drmach_cpu_get_id(cp->sbc_cm.sbdev_id, &cpuid) == 0);
93 
94 	ASSERT(cp->sbc_cm.sbdev_bp == bp);
95 	ASSERT(cp->sbc_cm.sbdev_type == SBD_COMP_CPU);
96 	ASSERT(cp->sbc_cpu_id == cpuid);
97 #else
98 	_NOTE(ARGUNUSED(bp))
99 	_NOTE(ARGUNUSED(cp))
100 #endif
101 
102 	return (1);
103 }
104 
105 static int
106 dr_errno2ecode(int error)
107 {
108 	int	rv;
109 
110 	switch (error) {
111 	case EBUSY:
112 		rv = ESBD_BUSY;
113 		break;
114 	case EINVAL:
115 		rv = ESBD_INVAL;
116 		break;
117 	case EALREADY:
118 		rv = ESBD_ALREADY;
119 		break;
120 	case ENODEV:
121 		rv = ESBD_NODEV;
122 		break;
123 	case ENOMEM:
124 		rv = ESBD_NOMEM;
125 		break;
126 	default:
127 		rv = ESBD_INVAL;
128 	}
129 
130 	return (rv);
131 }
132 
133 static void
134 dr_cpu_set_prop(dr_cpu_unit_t *cp)
135 {
136 	sbd_error_t	*err;
137 	dev_info_t	*dip;
138 	uint64_t	clock_freq;
139 	int		ecache_size = 0;
140 	char		*cache_str = NULL;
141 
142 	err = drmach_get_dip(cp->sbc_cm.sbdev_id, &dip);
143 	if (err) {
144 		DRERR_SET_C(&cp->sbc_cm.sbdev_error, &err);
145 		return;
146 	}
147 
148 	if (dip == NULL) {
149 #ifndef _STARFIRE
150 		/*
151 		 * Do not report an error on Starfire since
152 		 * the dip will not be created until after
153 		 * the CPU has been configured.
154 		 */
155 		DR_DEV_INTERNAL_ERROR(&cp->sbc_cm);
156 #endif /* !_STARFIRE */
157 		return;
158 	}
159 
160 	/* read in the CPU speed */
161 
162 	/*
163 	 * If the property is not found in the CPU node, it has to be
164 	 * kept in the core or cmp node so we just keep looking.
165 	 */
166 	clock_freq = (unsigned int)ddi_prop_get_int(DDI_DEV_T_ANY,
167 		dip, 0, "clock-frequency", 0);
168 
169 	ASSERT(clock_freq != 0);
170 
171 	/*
172 	 * The ecache property string is not the same
173 	 * for all CPU implementations.
174 	 */
175 
176 	switch (cp->sbc_cpu_impl) {
177 	case BLACKBIRD_IMPL:
178 	case CHEETAH_IMPL:
179 	case CHEETAH_PLUS_IMPL:
180 		cache_str = "ecache-size";
181 		break;
182 	case JAGUAR_IMPL:
183 	case OLYMPUS_C_IMPL:
184 		cache_str = "l2-cache-size";
185 		break;
186 	case PANTHER_IMPL:
187 		cache_str = "l3-cache-size";
188 		break;
189 	default:
190 		cmn_err(CE_WARN, "Unknown cpu implementation=0x%x",
191 		    cp->sbc_cpu_impl);
192 		ASSERT(0);
193 		break;
194 	}
195 
196 	if (cache_str != NULL) {
197 		/* read in the ecache size */
198 		/*
199 		 * If the property is not found in the CPU node,
200 		 * it has to be kept in the core or cmp node so
201 		 * we just keep looking.
202 		 */
203 
204 		ecache_size = ddi_prop_get_int(DDI_DEV_T_ANY,
205 			dip, 0, cache_str, 0);
206 	}
207 
208 	ASSERT(ecache_size != 0);
209 
210 	/* convert to the proper units */
211 	cp->sbc_speed = (clock_freq + 500000) / 1000000;
212 	cp->sbc_ecache = ecache_size / (1024 * 1024);
213 }
214 
215 void
216 dr_init_cpu_unit(dr_cpu_unit_t *cp)
217 {
218 	sbd_error_t	*err;
219 	dr_state_t	new_state;
220 	int		cpuid;
221 	int		impl;
222 
223 	if (DR_DEV_IS_ATTACHED(&cp->sbc_cm)) {
224 		new_state = DR_STATE_CONFIGURED;
225 		cp->sbc_cm.sbdev_cond = SBD_COND_OK;
226 	} else if (DR_DEV_IS_PRESENT(&cp->sbc_cm)) {
227 		new_state = DR_STATE_CONNECTED;
228 		cp->sbc_cm.sbdev_cond = SBD_COND_OK;
229 	} else {
230 		new_state = DR_STATE_EMPTY;
231 		cp->sbc_cm.sbdev_cond = SBD_COND_UNKNOWN;
232 	}
233 
234 	if (DR_DEV_IS_PRESENT(&cp->sbc_cm)) {
235 		err = drmach_cpu_get_id(cp->sbc_cm.sbdev_id, &cpuid);
236 		if (err) {
237 			DRERR_SET_C(&cp->sbc_cm.sbdev_error, &err);
238 			new_state = DR_STATE_FATAL;
239 			goto done;
240 		}
241 
242 		err = drmach_cpu_get_impl(cp->sbc_cm.sbdev_id, &impl);
243 		if (err) {
244 			DRERR_SET_C(&cp->sbc_cm.sbdev_error, &err);
245 			new_state = DR_STATE_FATAL;
246 			goto done;
247 		}
248 	} else {
249 		cp->sbc_cpu_id = -1;
250 		cp->sbc_cpu_impl = -1;
251 		goto done;
252 	}
253 
254 	cp->sbc_cpu_id = cpuid;
255 	cp->sbc_cpu_impl = impl;
256 
257 	/* if true at init time, it must always be true */
258 	ASSERT(dr_cpu_unit_is_sane(cp->sbc_cm.sbdev_bp, cp));
259 
260 	mutex_enter(&cpu_lock);
261 	if ((cpuid >= 0) && cpu[cpuid])
262 		cp->sbc_cpu_flags = cpu[cpuid]->cpu_flags;
263 	else
264 		cp->sbc_cpu_flags = P_OFFLINE | P_POWEROFF;
265 	mutex_exit(&cpu_lock);
266 
267 	dr_cpu_set_prop(cp);
268 
269 done:
270 	/* delay transition until fully initialized */
271 	dr_device_transition(&cp->sbc_cm, new_state);
272 }
273 
274 int
275 dr_pre_attach_cpu(dr_handle_t *hp, dr_common_unit_t **devlist, int devnum)
276 {
277 	int		i;
278 	int		curr_cpu;
279 	int		next_cpu;
280 	static fn_t	f = "dr_pre_attach_cpu";
281 
282 	PR_CPU("%s...\n", f);
283 
284 	for (next_cpu = 0, i = 0; i < devnum; i++) {
285 		dr_cpu_unit_t *up = (dr_cpu_unit_t *)devlist[i];
286 
287 		ASSERT(dr_cpu_unit_is_sane(hp->h_bd, up));
288 
289 		/*
290 		 * Print a console message for each attachment
291 		 * point. For CMP devices, this means that only
292 		 * one message should be printed, no matter how
293 		 * many cores are actually present.
294 		 */
295 		curr_cpu = DR_UNUM2SBD_UNUM(up->sbc_cm.sbdev_unum,
296 			SBD_COMP_CPU);
297 		if (curr_cpu >= next_cpu) {
298 			cmn_err(CE_CONT, "OS configure %s",
299 			    up->sbc_cm.sbdev_path);
300 			next_cpu = curr_cpu + 1;
301 		}
302 
303 		if (up->sbc_cm.sbdev_state == DR_STATE_UNCONFIGURED) {
304 			/*
305 			 * If we're coming from the UNCONFIGURED
306 			 * state then the cpu's sigblock will
307 			 * still be mapped in.  Need to unmap it
308 			 * before continuing with attachment.
309 			 */
310 			PR_CPU("%s: unmapping sigblk for cpu %d\n",
311 				f, up->sbc_cpu_id);
312 
313 			CPU_SGN_MAPOUT(up->sbc_cpu_id);
314 		}
315 	}
316 
317 	/*
318 	 * Block out status threads while creating
319 	 * devinfo tree branches
320 	 */
321 	dr_lock_status(hp->h_bd);
322 	ndi_devi_enter(ddi_root_node(), (int *)(&hp->h_ndi));
323 	mutex_enter(&cpu_lock);
324 
325 	return (0);
326 }
327 
328 /*ARGSUSED*/
329 void
330 dr_attach_cpu(dr_handle_t *hp, dr_common_unit_t *cp)
331 {
332 	sbd_error_t	*err;
333 	processorid_t	 cpuid;
334 	int		 rv;
335 
336 	ASSERT(MUTEX_HELD(&cpu_lock));
337 
338 	err = drmach_configure(cp->sbdev_id, 0);
339 	if (err) {
340 		DRERR_SET_C(&cp->sbdev_error, &err);
341 		return;
342 	}
343 
344 	err = drmach_cpu_get_id(cp->sbdev_id, &cpuid);
345 	if (err) {
346 		DRERR_SET_C(&cp->sbdev_error, &err);
347 
348 		err = drmach_unconfigure(cp->sbdev_id, DEVI_BRANCH_DESTROY);
349 		if (err)
350 			sbd_err_clear(&err);
351 	} else if ((rv = cpu_configure(cpuid)) != 0) {
352 		dr_dev_err(CE_WARN, cp, dr_errno2ecode(rv));
353 		err = drmach_unconfigure(cp->sbdev_id, DEVI_BRANCH_DESTROY);
354 		if (err)
355 			sbd_err_clear(&err);
356 	}
357 }
358 
359 /*
360  * dr_post_attach_cpu
361  *
362  * sbd error policy: Does not stop on error.  Processes all units in list.
363  */
364 int
365 dr_post_attach_cpu(dr_handle_t *hp, dr_common_unit_t **devlist, int devnum)
366 {
367 	int		i;
368 	int		errflag = 0;
369 	static fn_t	f = "dr_post_attach_cpu";
370 
371 	PR_CPU("%s...\n", f);
372 
373 	/* Startup and online newly-attached CPUs */
374 	for (i = 0; i < devnum; i++) {
375 		dr_cpu_unit_t *up = (dr_cpu_unit_t *)devlist[i];
376 		struct cpu	*cp;
377 
378 		ASSERT(dr_cpu_unit_is_sane(hp->h_bd, up));
379 
380 		cp = cpu_get(up->sbc_cpu_id);
381 		if (cp == NULL) {
382 			cmn_err(CE_WARN, "%s: cpu_get failed for cpu %d",
383 			    f, up->sbc_cpu_id);
384 			continue;
385 		}
386 
387 		if (cpu_is_poweredoff(cp)) {
388 			if (cpu_poweron(cp) != 0) {
389 				dr_dev_err(CE_WARN, &up->sbc_cm, ESBD_CPUSTART);
390 				errflag = 1;
391 			}
392 			PR_CPU("%s: cpu %d powered ON\n", f, up->sbc_cpu_id);
393 		}
394 
395 		if (cpu_is_offline(cp)) {
396 			PR_CPU("%s: onlining cpu %d...\n", f, up->sbc_cpu_id);
397 
398 			if (cpu_online(cp) != 0) {
399 				dr_dev_err(CE_WARN, &up->sbc_cm, ESBD_ONLINE);
400 				errflag = 1;
401 			}
402 		}
403 
404 	}
405 
406 	mutex_exit(&cpu_lock);
407 	ndi_devi_exit(ddi_root_node(), hp->h_ndi);
408 	dr_unlock_status(hp->h_bd);
409 
410 	if (errflag)
411 		return (-1);
412 	else
413 		return (0);
414 }
415 
416 /*
417  * dr_pre_release_cpu
418  *
419  * sbd error policy: Stops on first error.
420  */
421 int
422 dr_pre_release_cpu(dr_handle_t *hp, dr_common_unit_t **devlist, int devnum)
423 {
424 	int		c, cix, i, lastoffline = -1, rv = 0;
425 	processorid_t	cpuid;
426 	struct cpu	*cp;
427 	dr_cpu_unit_t	*up;
428 	dr_devset_t	devset;
429 	sbd_dev_stat_t	*ds;
430 	static fn_t	f = "dr_pre_release_cpu";
431 	int		cpu_flags = 0;
432 
433 	devset = DR_DEVS_PRESENT(hp->h_bd);
434 
435 	/* allocate status struct storage. */
436 	ds = (sbd_dev_stat_t *) kmem_zalloc(sizeof (sbd_dev_stat_t) *
437 		MAX_CPU_UNITS_PER_BOARD, KM_SLEEP);
438 
439 	cix = dr_cpu_status(hp, devset, ds);
440 
441 	mutex_enter(&cpu_lock);
442 
443 	for (i = 0; i < devnum; i++) {
444 		up = (dr_cpu_unit_t *)devlist[i];
445 		ASSERT(dr_cpu_unit_is_sane(hp->h_bd, up));
446 
447 		/*
448 		 * The STARCAT platform borrows cpus for use by POST in
449 		 * iocage testing.  These cpus cannot be unconfigured
450 		 * while they are in use for the iocage.
451 		 * This check determines if a CPU is currently in use
452 		 * for iocage testing, and if so, returns a "Device busy"
453 		 * error.
454 		 */
455 		for (c = 0; c < cix; c++) {
456 			if (ds[c].d_cpu.cs_unit == up->sbc_cm.sbdev_unum) {
457 				if (ds[c].d_cpu.cs_busy) {
458 					dr_dev_err(CE_WARN,
459 						&up->sbc_cm, ESBD_BUSY);
460 					rv = -1;
461 					break;
462 				}
463 			}
464 		}
465 		if (c < cix)
466 			break;
467 		cpuid = up->sbc_cpu_id;
468 		if ((cp = cpu_get(cpuid)) == NULL) {
469 			dr_dev_err(CE_WARN, &up->sbc_cm, ESBD_OFFLINE);
470 			rv = -1;
471 			break;
472 		}
473 
474 		/* used by dr_cancel_cpu during error flow */
475 		up->sbc_cpu_flags = cp->cpu_flags;
476 
477 		if (CPU_ACTIVE(cp)) {
478 			if (dr_cmd_flags(hp) & SBD_FLAG_FORCE)
479 				cpu_flags = CPU_FORCED;
480 
481 			PR_CPU("%s: offlining cpu %d\n", f, cpuid);
482 			if (cpu_offline(cp, cpu_flags)) {
483 				PR_CPU("%s: failed to offline cpu %d\n",
484 					f, cpuid);
485 				dr_dev_err(CE_WARN, &up->sbc_cm, ESBD_OFFLINE);
486 				if (disp_bound_threads(cp, 0)) {
487 					cmn_err(CE_WARN, "%s: thread(s) "
488 						"bound to cpu %d",
489 							f, cp->cpu_id);
490 				}
491 				rv = -1;
492 				break;
493 			} else
494 				lastoffline = i;
495 		}
496 
497 		if (!rv) {
498 			sbd_error_t *err;
499 
500 			err = drmach_release(up->sbc_cm.sbdev_id);
501 			if (err) {
502 				DRERR_SET_C(&up->sbc_cm.sbdev_error, &err);
503 				rv = -1;
504 				break;
505 			}
506 		}
507 	}
508 
509 	mutex_exit(&cpu_lock);
510 
511 	if (rv) {
512 		/*
513 		 * Need to unwind others since at this level (pre-release)
514 		 * the device state has not yet transitioned and failures
515 		 * will prevent us from reaching the "post" release
516 		 * function where states are normally transitioned.
517 		 */
518 		for (i = lastoffline; i >= 0; i--) {
519 			up = (dr_cpu_unit_t *)devlist[i];
520 			(void) dr_cancel_cpu(up);
521 		}
522 	}
523 
524 	kmem_free(ds, sizeof (sbd_dev_stat_t) * MAX_CPU_UNITS_PER_BOARD);
525 	return (rv);
526 }
527 
528 /*
529  * dr_pre_detach_cpu
530  *
531  * sbd error policy: Stops on first error.
532  */
533 int
534 dr_pre_detach_cpu(dr_handle_t *hp, dr_common_unit_t **devlist, int devnum)
535 {
536 	_NOTE(ARGUNUSED(hp))
537 
538 	int		i;
539 	int		curr_cpu;
540 	int		next_cpu;
541 	int		cpu_flags = 0;
542 	static fn_t	f = "dr_pre_detach_cpu";
543 
544 	PR_CPU("%s...\n", f);
545 
546 	/*
547 	 * Block out status threads while destroying devinfo tree
548 	 * branches
549 	 */
550 	dr_lock_status(hp->h_bd);
551 	mutex_enter(&cpu_lock);
552 
553 	for (next_cpu = 0, i = 0; i < devnum; i++) {
554 		dr_cpu_unit_t *up = (dr_cpu_unit_t *)devlist[i];
555 		struct cpu	*cp;
556 
557 		ASSERT(dr_cpu_unit_is_sane(hp->h_bd, up));
558 
559 		cp = cpu_get(up->sbc_cpu_id);
560 		if (cp == NULL)
561 			continue;
562 
563 		/*
564 		 * Print a console message for each attachment
565 		 * point. For CMP devices, this means that only
566 		 * one message should be printed, no matter how
567 		 * many cores are actually present.
568 		 */
569 		curr_cpu = DR_UNUM2SBD_UNUM(up->sbc_cm.sbdev_unum,
570 			SBD_COMP_CPU);
571 		if (curr_cpu >= next_cpu) {
572 			cmn_err(CE_CONT, "OS unconfigure %s\n",
573 			    up->sbc_cm.sbdev_path);
574 			next_cpu = curr_cpu + 1;
575 		}
576 
577 		/*
578 		 * CPUs were offlined during Release.
579 		 */
580 		if (cpu_is_poweredoff(cp)) {
581 			PR_CPU("%s: cpu %d already powered OFF\n",
582 			    f, up->sbc_cpu_id);
583 			continue;
584 		}
585 
586 		if (!cpu_is_offline(cp)) {
587 			if (dr_cmd_flags(hp) & SBD_FLAG_FORCE)
588 				cpu_flags = CPU_FORCED;
589 			/* cpu was onlined after release.  Offline it again */
590 			PR_CPU("%s: offlining cpu %d\n", f, up->sbc_cpu_id);
591 			if (cpu_offline(cp, cpu_flags)) {
592 				PR_CPU("%s: failed to offline cpu %d\n",
593 				    f, up->sbc_cpu_id);
594 				dr_dev_err(CE_WARN, &up->sbc_cm, ESBD_OFFLINE);
595 				if (disp_bound_threads(cp, 0)) {
596 					cmn_err(CE_WARN, "%s: thread(s) "
597 						"bound to cpu %d",
598 							f, cp->cpu_id);
599 				}
600 				goto err;
601 			}
602 		}
603 		if (cpu_poweroff(cp) != 0) {
604 			dr_dev_err(CE_WARN, &up->sbc_cm, ESBD_CPUSTOP);
605 			goto err;
606 		} else {
607 			PR_CPU("%s: cpu %d powered OFF\n", f, up->sbc_cpu_id);
608 		}
609 	}
610 
611 	return (0);
612 
613 err:
614 	mutex_exit(&cpu_lock);
615 	dr_unlock_status(hp->h_bd);
616 	return (-1);
617 }
618 
619 /*ARGSUSED*/
620 void
621 dr_detach_cpu(dr_handle_t *hp, dr_common_unit_t *cp)
622 {
623 	sbd_error_t	*err;
624 	processorid_t	 cpuid;
625 	int		 rv;
626 
627 	ASSERT(MUTEX_HELD(&cpu_lock));
628 
629 	err = drmach_cpu_get_id(cp->sbdev_id, &cpuid);
630 	if (err) {
631 		DRERR_SET_C(&cp->sbdev_error, &err);
632 	} else if ((rv = cpu_unconfigure(cpuid)) != 0) {
633 		dr_dev_err(CE_IGNORE, cp, dr_errno2ecode(rv));
634 	} else {
635 		err = drmach_unconfigure(cp->sbdev_id, DEVI_BRANCH_DESTROY);
636 		if (err) {
637 			DRERR_SET_C(&cp->sbdev_error, &err);
638 		}
639 	}
640 }
641 
642 /*ARGSUSED1*/
643 int
644 dr_post_detach_cpu(dr_handle_t *hp, dr_common_unit_t **devlist, int devnum)
645 {
646 	static fn_t	f = "dr_post_detach_cpu";
647 
648 	PR_CPU("%s...\n", f);
649 	hp->h_ndi = 0;
650 
651 	mutex_exit(&cpu_lock);
652 	dr_unlock_status(hp->h_bd);
653 
654 	return (0);
655 }
656 
657 static void
658 dr_fill_cpu_stat(dr_cpu_unit_t *cp, drmach_status_t *pstat, sbd_cpu_stat_t *csp)
659 {
660 	ASSERT(cp && pstat && csp);
661 
662 	/* Fill in the common status information */
663 	bzero((caddr_t)csp, sizeof (*csp));
664 	csp->cs_type = cp->sbc_cm.sbdev_type;
665 	csp->cs_unit = cp->sbc_cm.sbdev_unum;
666 	strncpy(csp->cs_name, pstat->type, sizeof (csp->cs_name));
667 	csp->cs_cond = cp->sbc_cm.sbdev_cond;
668 	csp->cs_busy = cp->sbc_cm.sbdev_busy | pstat->busy;
669 	csp->cs_time = cp->sbc_cm.sbdev_time;
670 	csp->cs_ostate = cp->sbc_cm.sbdev_ostate;
671 	csp->cs_suspend = 0;
672 
673 	/* CPU specific status data */
674 	csp->cs_cpuid = cp->sbc_cpu_id;
675 
676 #ifdef _STARFIRE
677 	csp->cs_isbootproc = (SIGBCPU->cpu_id == cp->sbc_cpu_id) ? 1 : 0;
678 #endif /* _STARFIRE */
679 
680 	/*
681 	 * If the speed and ecache properties have not been
682 	 * cached yet, read them in from the device tree.
683 	 */
684 	if ((cp->sbc_speed == 0) || (cp->sbc_ecache == 0))
685 		dr_cpu_set_prop(cp);
686 
687 	/* use the cached speed and ecache values */
688 	csp->cs_speed = cp->sbc_speed;
689 	csp->cs_ecache = cp->sbc_ecache;
690 
691 	mutex_enter(&cpu_lock);
692 	if (!cpu_get(csp->cs_cpuid)) {
693 		/* ostate must be UNCONFIGURED */
694 		csp->cs_cm.c_ostate = SBD_STAT_UNCONFIGURED;
695 	}
696 	mutex_exit(&cpu_lock);
697 }
698 
699 static void
700 dr_fill_cmp_stat(sbd_cpu_stat_t *csp, int ncores, int impl, sbd_cmp_stat_t *psp)
701 {
702 	int	core;
703 
704 	ASSERT(csp && psp && (ncores >= 1));
705 
706 	bzero((caddr_t)psp, sizeof (*psp));
707 
708 	/*
709 	 * Fill in the common status information based
710 	 * on the data for the first core.
711 	 */
712 	psp->ps_type = SBD_COMP_CMP;
713 	psp->ps_unit = DR_UNUM2SBD_UNUM(csp->cs_unit, SBD_COMP_CMP);
714 	strncpy(psp->ps_name, csp->cs_name, sizeof (psp->ps_name));
715 	psp->ps_cond = csp->cs_cond;
716 	psp->ps_busy = csp->cs_busy;
717 	psp->ps_time = csp->cs_time;
718 	psp->ps_ostate = csp->cs_ostate;
719 	psp->ps_suspend = csp->cs_suspend;
720 
721 	/* CMP specific status data */
722 	*psp->ps_cpuid = csp->cs_cpuid;
723 	psp->ps_ncores = 1;
724 	psp->ps_speed = csp->cs_speed;
725 	psp->ps_ecache = csp->cs_ecache;
726 
727 	/*
728 	 * Walk through the data for the remaining cores.
729 	 * Make any adjustments to the common status data,
730 	 * or the shared CMP specific data if necessary.
731 	 */
732 	for (core = 1; core < ncores; core++) {
733 
734 		/*
735 		 * The following properties should be the same
736 		 * for all the cores of the CMP.
737 		 */
738 		ASSERT(psp->ps_unit == DR_UNUM2SBD_UNUM(
739 			csp[core].cs_unit, SBD_COMP_CMP));
740 		ASSERT(psp->ps_speed == csp[core].cs_speed);
741 
742 		psp->ps_cpuid[core] = csp[core].cs_cpuid;
743 		psp->ps_ncores++;
744 
745 		/*
746 		 * Jaguar has a split ecache, so the ecache
747 		 * for each core must be added together to
748 		 * get the total ecache for the whole chip.
749 		 */
750 		if (IS_JAGUAR(impl)) {
751 			psp->ps_ecache += csp[core].cs_ecache;
752 		}
753 
754 		/* adjust time if necessary */
755 		if (csp[core].cs_time > psp->ps_time) {
756 			psp->ps_time = csp[core].cs_time;
757 		}
758 
759 		psp->ps_busy |= csp[core].cs_busy;
760 
761 		/*
762 		 * If any of the cores are configured, the
763 		 * entire CMP is marked as configured.
764 		 */
765 		if (csp[core].cs_ostate == SBD_STAT_CONFIGURED) {
766 			psp->ps_ostate = csp[core].cs_ostate;
767 		}
768 	}
769 }
770 
771 int
772 dr_cpu_status(dr_handle_t *hp, dr_devset_t devset, sbd_dev_stat_t *dsp)
773 {
774 	int		cmp;
775 	int		core;
776 	int		ncpu;
777 	dr_board_t	*bp;
778 	sbd_cpu_stat_t	cstat[MAX_CORES_PER_CMP];
779 	int		impl;
780 
781 	bp = hp->h_bd;
782 	ncpu = 0;
783 
784 	devset &= DR_DEVS_PRESENT(bp);
785 
786 	/*
787 	 * Treat every CPU as a CMP. In the case where the
788 	 * device is not a CMP, treat it as a CMP with only
789 	 * one core.
790 	 */
791 	for (cmp = 0; cmp < MAX_CMP_UNITS_PER_BOARD; cmp++) {
792 
793 		int		ncores;
794 		dr_cpu_unit_t	*cp;
795 		drmach_status_t	pstat;
796 		sbd_error_t	*err;
797 		sbd_cmp_stat_t	*psp;
798 
799 		if ((devset & DEVSET(SBD_COMP_CMP, cmp)) == 0) {
800 			continue;
801 		}
802 
803 		ncores = 0;
804 
805 		for (core = 0; core < MAX_CORES_PER_CMP; core++) {
806 
807 			cp = dr_get_cpu_unit(bp, DR_CMP_CORE_UNUM(cmp, core));
808 
809 			if (cp->sbc_cm.sbdev_state == DR_STATE_EMPTY) {
810 				/* present, but not fully initialized */
811 				continue;
812 			}
813 
814 			ASSERT(dr_cpu_unit_is_sane(hp->h_bd, cp));
815 
816 			/* skip if not present */
817 			if (cp->sbc_cm.sbdev_id == (drmachid_t)0) {
818 				continue;
819 			}
820 
821 			/* fetch platform status */
822 			err = drmach_status(cp->sbc_cm.sbdev_id, &pstat);
823 			if (err) {
824 				DRERR_SET_C(&cp->sbc_cm.sbdev_error, &err);
825 				continue;
826 			}
827 
828 			dr_fill_cpu_stat(cp, &pstat, &cstat[ncores++]);
829 			/*
830 			 * We should set impl here because the last core
831 			 * found might be EMPTY or not present.
832 			 */
833 			impl = cp->sbc_cpu_impl;
834 		}
835 
836 		if (ncores == 0) {
837 			continue;
838 		}
839 
840 		/*
841 		 * Store the data to the outgoing array. If the
842 		 * device is a CMP, combine all the data for the
843 		 * cores into a single stat structure.
844 		 *
845 		 * The check for a CMP device uses the last core
846 		 * found, assuming that all cores will have the
847 		 * same implementation.
848 		 */
849 
850 		if (CPU_IMPL_IS_CMP(impl)) {
851 			psp = (sbd_cmp_stat_t *)dsp;
852 			dr_fill_cmp_stat(cstat, ncores, impl, psp);
853 		} else {
854 			ASSERT(ncores == 1);
855 			bcopy(cstat, dsp, sizeof (sbd_cpu_stat_t));
856 		}
857 
858 		dsp++;
859 		ncpu++;
860 	}
861 
862 	return (ncpu);
863 }
864 
865 /*
866  * Cancel previous release operation for cpu.
867  * For cpus this means simply bringing cpus that
868  * were offline back online.  Note that they had
869  * to have been online at the time there were
870  * released.
871  */
872 int
873 dr_cancel_cpu(dr_cpu_unit_t *up)
874 {
875 	int		rv = 0;
876 	static fn_t	f = "dr_cancel_cpu";
877 
878 	ASSERT(dr_cpu_unit_is_sane(up->sbc_cm.sbdev_bp, up));
879 
880 	if (cpu_flagged_active(up->sbc_cpu_flags)) {
881 		struct cpu	*cp;
882 
883 		/*
884 		 * CPU had been online, go ahead
885 		 * bring it back online.
886 		 */
887 		PR_CPU("%s: bringing cpu %d back ONLINE\n",
888 			f, up->sbc_cpu_id);
889 
890 		mutex_enter(&cpu_lock);
891 		cp = cpu[up->sbc_cpu_id];
892 
893 		if (cpu_is_poweredoff(cp)) {
894 			if (cpu_poweron(cp)) {
895 				cmn_err(CE_WARN, "%s: failed to power-on "
896 				    "cpu %d", f, up->sbc_cpu_id);
897 				rv = -1;
898 			}
899 		}
900 
901 		if (cpu_is_offline(cp)) {
902 			if (cpu_online(cp)) {
903 				cmn_err(CE_WARN, "%s: failed to online cpu %d",
904 				    f, up->sbc_cpu_id);
905 				rv = -1;
906 			}
907 		}
908 
909 		if (cpu_is_online(cp)) {
910 			if (cpu_flagged_nointr(up->sbc_cpu_flags)) {
911 				if (cpu_intr_disable(cp) != 0) {
912 					cmn_err(CE_WARN, "%s: failed to "
913 					"disable interrupts on cpu %d",
914 						f, up->sbc_cpu_id);
915 				}
916 			}
917 		}
918 
919 		mutex_exit(&cpu_lock);
920 	}
921 
922 	return (rv);
923 }
924 
925 int
926 dr_disconnect_cpu(dr_cpu_unit_t *up)
927 {
928 	sbd_error_t	*err;
929 	static fn_t	f = "dr_disconnect_cpu";
930 
931 	PR_CPU("%s...\n", f);
932 
933 	ASSERT((up->sbc_cm.sbdev_state == DR_STATE_CONNECTED) ||
934 		(up->sbc_cm.sbdev_state == DR_STATE_UNCONFIGURED));
935 
936 	ASSERT(dr_cpu_unit_is_sane(up->sbc_cm.sbdev_bp, up));
937 
938 	if (up->sbc_cm.sbdev_state == DR_STATE_CONNECTED) {
939 		/*
940 		 * Cpus were never brought in and so are still
941 		 * effectively disconnected, so nothing to do here.
942 		 */
943 		PR_CPU("%s: cpu %d never brought in\n",
944 			f, up->sbc_cpu_id);
945 		return (0);
946 	}
947 
948 	err = drmach_cpu_disconnect(up->sbc_cm.sbdev_id);
949 	if (err == NULL)
950 		return (0);
951 	else {
952 		DRERR_SET_C(&up->sbc_cm.sbdev_error, &err);
953 		return (-1);
954 	}
955 	/*NOTREACHED*/
956 }
957