1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/time.h> 30 #include <sys/cpuvar.h> 31 #include <sys/dditypes.h> 32 #include <sys/ddipropdefs.h> 33 #include <sys/ddi_impldefs.h> 34 #include <sys/sunddi.h> 35 #include <sys/esunddi.h> 36 #include <sys/sunndi.h> 37 #include <sys/platform_module.h> 38 #include <sys/errno.h> 39 #include <sys/conf.h> 40 #include <sys/modctl.h> 41 #include <sys/promif.h> 42 #include <sys/promimpl.h> 43 #include <sys/prom_plat.h> 44 #include <sys/cmn_err.h> 45 #include <sys/sysmacros.h> 46 #include <sys/mem_cage.h> 47 #include <sys/kobj.h> 48 #include <sys/utsname.h> 49 #include <sys/cpu_sgnblk_defs.h> 50 #include <sys/atomic.h> 51 #include <sys/kdi_impl.h> 52 53 #include <sys/sgsbbc.h> 54 #include <sys/sgsbbc_iosram.h> 55 #include <sys/sgsbbc_iosram_priv.h> 56 #include <sys/sgsbbc_mailbox.h> 57 #include <sys/sgsgn.h> 58 #include <sys/serengeti.h> 59 #include <sys/sgfrutypes.h> 60 #include <sys/machsystm.h> 61 #include <sys/sbd_ioctl.h> 62 #include <sys/sbd.h> 63 #include <sys/sbdp_mem.h> 64 #include <sys/sgcn.h> 65 66 #include <sys/memnode.h> 67 #include <vm/vm_dep.h> 68 #include <vm/page.h> 69 70 #include <sys/cheetahregs.h> 71 #include <sys/plat_ecc_unum.h> 72 #include <sys/plat_ecc_dimm.h> 73 74 #include <sys/lgrp.h> 75 76 static int sg_debug = 0; 77 78 #ifdef DEBUG 79 #define DCMNERR if (sg_debug) cmn_err 80 #else 81 #define DCMNERR 82 #endif 83 84 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 85 86 /* local functions */ 87 static void cpu_sgn_update(ushort_t sgn, uchar_t state, 88 uchar_t sub_state, int cpuid); 89 90 91 /* 92 * Local data. 93 * 94 * iosram_write_ptr is a pointer to iosram_write(). Because of 95 * kernel dynamic linking, we can't get to the function by name, 96 * but we can look up its address, and store it in this variable 97 * instead. 98 * 99 * We include the extern for iosram_write() here not because we call 100 * it, but to force compilation errors if its prototype doesn't 101 * match the prototype of iosram_write_ptr. 102 * 103 * The same issues apply to iosram_read() and iosram_read_ptr. 104 */ 105 /*CSTYLED*/ 106 extern int iosram_write (int, uint32_t, caddr_t, uint32_t); 107 static int (*iosram_write_ptr)(int, uint32_t, caddr_t, uint32_t) = NULL; 108 /*CSTYLED*/ 109 extern int iosram_read (int, uint32_t, caddr_t, uint32_t); 110 static int (*iosram_read_ptr)(int, uint32_t, caddr_t, uint32_t) = NULL; 111 112 113 /* 114 * Variable to indicate if the date should be obtained from the SC or not. 115 */ 116 int todsg_use_sc = FALSE; /* set the false at the beginning */ 117 118 /* 119 * Preallocation of spare tsb's for DR 120 * 121 * We don't allocate spares for Wildcat since TSBs should come 122 * out of memory local to the node. 123 */ 124 #define IOMMU_PER_SCHIZO 2 125 int serengeti_tsb_spares = (SG_MAX_IO_BDS * SG_SCHIZO_PER_IO_BD * 126 IOMMU_PER_SCHIZO); 127 128 /* 129 * sg_max_ncpus is the maximum number of CPUs supported on lw8. 130 * sg_max_ncpus is set to be smaller than NCPU to reduce the amount of 131 * memory the logs take up until we have a dynamic log memory allocation 132 * solution. 133 */ 134 int sg_max_ncpus = (12 * 2); /* (max # of processors * # of cores/proc) */ 135 136 /* 137 * variables to control mailbox message timeouts. 138 * These can be patched via /etc/system or mdb. 139 */ 140 int sbbc_mbox_default_timeout = MBOX_DEFAULT_TIMEOUT; 141 int sbbc_mbox_min_timeout = MBOX_MIN_TIMEOUT; 142 143 /* cached 'chosen' node_id */ 144 pnode_t chosen_nodeid = (pnode_t)0; 145 146 /* 147 * Table that maps memory slices to a specific memnode. 148 */ 149 int slice_to_memnode[SG_MAX_SLICE]; 150 151 /* 152 * We define and use LW8_MAX_CPU_BDS here instead of SG_MAX_CPU_BDS 153 * since a LW8 machine will never have a CPU/Mem board #5 (SB5). 154 * A LW8 machine can only have a maximum of three CPU/Mem boards, but 155 * the board numbers assigned are 0, 2, and 4. LW8_MAX_CPU_BDS is 156 * defined to be 5 since the entries in the domain_dimm_sids array 157 * are keyed by board number. Not perfect but some wasted space 158 * is avoided. 159 */ 160 #define LW8_MAX_CPU_BDS 5 161 162 plat_dimm_sid_board_t domain_dimm_sids[LW8_MAX_CPU_BDS]; 163 164 int 165 set_platform_tsb_spares() 166 { 167 return (MIN(serengeti_tsb_spares, MAX_UPA)); 168 } 169 170 #pragma weak mmu_init_large_pages 171 172 void 173 set_platform_defaults(void) 174 { 175 extern int watchdog_enable; 176 extern uint64_t xc_tick_limit_scale; 177 extern void mmu_init_large_pages(size_t); 178 179 #ifdef DEBUG 180 char *todsg_name = "todsg"; 181 ce_verbose_memory = 2; 182 ce_verbose_other = 2; 183 #endif /* DEBUG */ 184 185 watchdog_enable = TRUE; 186 watchdog_available = TRUE; 187 188 cpu_sgn_func = cpu_sgn_update; 189 190 #ifdef DEBUG 191 /* tod_module_name should be set to "todsg" from OBP property */ 192 if (tod_module_name && (strcmp(tod_module_name, todsg_name) == 0)) 193 prom_printf("Using todsg driver\n"); 194 else { 195 prom_printf("Force using todsg driver\n"); 196 tod_module_name = todsg_name; 197 } 198 #endif /* DEBUG */ 199 200 /* lw8 does not support forthdebug */ 201 forthdebug_supported = 0; 202 203 204 /* 205 * Some DR operations require the system to be sync paused. 206 * Sync pause on Serengeti could potentially take up to 4 207 * seconds to complete depending on the load on the SC. To 208 * avoid send_mond panics during such operations, we need to 209 * increase xc_tick_limit to a larger value on Serengeti by 210 * setting xc_tick_limit_scale to 5. 211 */ 212 xc_tick_limit_scale = 5; 213 214 if ((mmu_page_sizes == max_mmu_page_sizes) && 215 (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) { 216 if (&mmu_init_large_pages) 217 mmu_init_large_pages(mmu_ism_pagesize); 218 } 219 } 220 221 void 222 load_platform_modules(void) 223 { 224 if (modload("misc", "pcihp") < 0) { 225 cmn_err(CE_NOTE, "pcihp driver failed to load"); 226 } 227 } 228 229 /*ARGSUSED*/ 230 int 231 plat_cpu_poweron(struct cpu *cp) 232 { 233 int (*serengeti_cpu_poweron)(struct cpu *) = NULL; 234 235 serengeti_cpu_poweron = 236 (int (*)(struct cpu *))modgetsymvalue("sbdp_cpu_poweron", 0); 237 238 if (serengeti_cpu_poweron == NULL) 239 return (ENOTSUP); 240 else 241 return ((serengeti_cpu_poweron)(cp)); 242 } 243 244 /*ARGSUSED*/ 245 int 246 plat_cpu_poweroff(struct cpu *cp) 247 { 248 int (*serengeti_cpu_poweroff)(struct cpu *) = NULL; 249 250 serengeti_cpu_poweroff = 251 (int (*)(struct cpu *))modgetsymvalue("sbdp_cpu_poweroff", 0); 252 253 if (serengeti_cpu_poweroff == NULL) 254 return (ENOTSUP); 255 else 256 return ((serengeti_cpu_poweroff)(cp)); 257 } 258 259 #ifdef DEBUG 260 pgcnt_t serengeti_cage_size_limit; 261 #endif 262 263 /* Preferred minimum cage size (expressed in pages)... for DR */ 264 pgcnt_t serengeti_minimum_cage_size = 0; 265 266 void 267 set_platform_cage_params(void) 268 { 269 extern pgcnt_t total_pages; 270 extern struct memlist *phys_avail; 271 272 if (kernel_cage_enable) { 273 pgcnt_t preferred_cage_size; 274 275 preferred_cage_size = 276 MAX(serengeti_minimum_cage_size, total_pages / 256); 277 #ifdef DEBUG 278 if (serengeti_cage_size_limit) 279 preferred_cage_size = serengeti_cage_size_limit; 280 #endif 281 /* 282 * Post copies obp into the lowest slice. This requires the 283 * cage to grow upwards 284 */ 285 kcage_range_init(phys_avail, KCAGE_UP, preferred_cage_size); 286 } 287 288 /* Only note when the cage is off since it should always be on. */ 289 if (!kcage_on) 290 cmn_err(CE_NOTE, "!DR Kernel Cage is DISABLED"); 291 } 292 293 #define ALIGN(x, a) ((a) == 0 ? (uint64_t)(x) : \ 294 (((uint64_t)(x) + (uint64_t)(a) - 1l) & ~((uint64_t)(a) - 1l))) 295 296 void 297 update_mem_bounds(int brd, uint64_t base, uint64_t sz) 298 { 299 uint64_t end; 300 int mnode; 301 302 end = base + sz - 1; 303 304 /* 305 * First see if this board already has a memnode associated 306 * with it. If not, see if this slice has a memnode. This 307 * covers the cases where a single slice covers multiple 308 * boards (cross-board interleaving) and where a single 309 * board has multiple slices (1+GB DIMMs). 310 */ 311 if ((mnode = plat_lgrphand_to_mem_node(brd)) == -1) { 312 if ((mnode = slice_to_memnode[PA_2_SLICE(base)]) == -1) 313 mnode = mem_node_alloc(); 314 plat_assign_lgrphand_to_mem_node(brd, mnode); 315 } 316 317 /* 318 * Align base at 16GB boundary 319 */ 320 base = ALIGN(base, (1ul << PA_SLICE_SHIFT)); 321 322 while (base < end) { 323 slice_to_memnode[PA_2_SLICE(base)] = mnode; 324 base += (1ul << PA_SLICE_SHIFT); 325 } 326 } 327 328 /* 329 * Dynamically detect memory slices in the system by decoding 330 * the cpu memory decoder registers at boot time. 331 */ 332 void 333 plat_fill_mc(pnode_t nodeid) 334 { 335 uint64_t mc_addr, mask; 336 uint64_t mc_decode[SG_MAX_BANKS_PER_MC]; 337 uint64_t base, size; 338 uint32_t regs[4]; 339 int len; 340 int local_mc; 341 int portid; 342 int boardid; 343 int i; 344 345 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) < 0) || 346 (portid == -1)) 347 return; 348 349 /* 350 * Decode the board number from the MC portid 351 */ 352 boardid = SG_PORTID_TO_BOARD_NUM(portid); 353 354 /* 355 * The "reg" property returns 4 32-bit values. The first two are 356 * combined to form a 64-bit address. The second two are for a 357 * 64-bit size, but we don't actually need to look at that value. 358 */ 359 len = prom_getproplen(nodeid, "reg"); 360 if (len != (sizeof (uint32_t) * 4)) { 361 prom_printf("Warning: malformed 'reg' property\n"); 362 return; 363 } 364 if (prom_getprop(nodeid, "reg", (caddr_t)regs) < 0) 365 return; 366 mc_addr = ((uint64_t)regs[0]) << 32; 367 mc_addr |= (uint64_t)regs[1]; 368 369 /* 370 * Figure out whether the memory controller we are examining 371 * belongs to this CPU or a different one. 372 */ 373 if (portid == cpunodes[CPU->cpu_id].portid) 374 local_mc = 1; 375 else 376 local_mc = 0; 377 378 for (i = 0; i < SG_MAX_BANKS_PER_MC; i++) { 379 mask = SG_REG_2_OFFSET(i); 380 381 /* 382 * If the memory controller is local to this CPU, we use 383 * the special ASI to read the decode registers. 384 * Otherwise, we load the values from a magic address in 385 * I/O space. 386 */ 387 if (local_mc) 388 mc_decode[i] = lddmcdecode(mask & MC_OFFSET_MASK); 389 else 390 mc_decode[i] = lddphysio((mc_addr | mask)); 391 392 if (mc_decode[i] >> MC_VALID_SHIFT) { 393 /* 394 * The memory decode register is a bitmask field, 395 * so we can decode that into both a base and 396 * a span. 397 */ 398 base = MC_BASE(mc_decode[i]) << PHYS2UM_SHIFT; 399 size = MC_UK2SPAN(mc_decode[i]); 400 update_mem_bounds(boardid, base, size); 401 } 402 } 403 } 404 405 /* 406 * This routine is run midway through the boot process. By the time we get 407 * here, we know about all the active CPU boards in the system, and we have 408 * extracted information about each board's memory from the memory 409 * controllers. We have also figured out which ranges of memory will be 410 * assigned to which memnodes, so we walk the slice table to build the table 411 * of memnodes. 412 */ 413 /* ARGSUSED */ 414 void 415 plat_build_mem_nodes(prom_memlist_t *list, size_t nelems) 416 { 417 int slice; 418 pfn_t basepfn; 419 pgcnt_t npgs; 420 421 mem_node_pfn_shift = PFN_SLICE_SHIFT; 422 mem_node_physalign = (1ull << PA_SLICE_SHIFT); 423 424 for (slice = 0; slice < SG_MAX_SLICE; slice++) { 425 if (slice_to_memnode[slice] == -1) 426 continue; 427 basepfn = (uint64_t)slice << PFN_SLICE_SHIFT; 428 npgs = 1ull << PFN_SLICE_SHIFT; 429 mem_node_add_slice(basepfn, basepfn + npgs - 1); 430 } 431 } 432 433 int 434 plat_pfn_to_mem_node(pfn_t pfn) 435 { 436 int node; 437 438 node = slice_to_memnode[PFN_2_SLICE(pfn)]; 439 440 return (node); 441 } 442 443 /* 444 * Serengeti support for lgroups. 445 * 446 * On Serengeti, an lgroup platform handle == board number. 447 * 448 * Mappings between lgroup handles and memnodes are managed 449 * in addition to mappings between memory slices and memnodes 450 * to support cross-board interleaving as well as multiple 451 * slices per board (e.g. >1GB DIMMs). The initial mapping 452 * of memnodes to lgroup handles is determined at boot time. 453 * A DR addition of memory adds a new mapping. A DR copy-rename 454 * swaps mappings. 455 */ 456 457 /* 458 * Macro for extracting the board number from the CPU id 459 */ 460 #define CPUID_TO_BOARD(id) (((id) >> 2) & 0x7) 461 462 /* 463 * Return the platform handle for the lgroup containing the given CPU 464 * 465 * For Serengeti, lgroup platform handle == board number 466 */ 467 lgrp_handle_t 468 plat_lgrp_cpu_to_hand(processorid_t id) 469 { 470 return (CPUID_TO_BOARD(id)); 471 } 472 473 /* 474 * Platform specific lgroup initialization 475 */ 476 void 477 plat_lgrp_init(void) 478 { 479 int i; 480 extern uint32_t lgrp_expand_proc_thresh; 481 extern uint32_t lgrp_expand_proc_diff; 482 483 /* 484 * Initialize lookup tables to invalid values so we catch 485 * any illegal use of them. 486 */ 487 for (i = 0; i < SG_MAX_SLICE; i++) { 488 slice_to_memnode[i] = -1; 489 } 490 491 /* 492 * Set tuneables for Serengeti architecture 493 * 494 * lgrp_expand_proc_thresh is the minimum load on the lgroups 495 * this process is currently running on before considering 496 * expanding threads to another lgroup. 497 * 498 * lgrp_expand_proc_diff determines how much less the remote lgroup 499 * must be loaded before expanding to it. 500 * 501 * Bandwidth is maximized on Serengeti by spreading load across 502 * the machine. The impact to inter-thread communication isn't 503 * too costly since remote latencies are relatively low. These 504 * values equate to one CPU's load and so attempt to spread the 505 * load out across as many lgroups as possible one CPU at a time. 506 */ 507 lgrp_expand_proc_thresh = LGRP_LOADAVG_THREAD_MAX; 508 lgrp_expand_proc_diff = LGRP_LOADAVG_THREAD_MAX; 509 } 510 511 /* 512 * Platform notification of lgroup (re)configuration changes 513 */ 514 /*ARGSUSED*/ 515 void 516 plat_lgrp_config(lgrp_config_flag_t evt, uintptr_t arg) 517 { 518 update_membounds_t *umb; 519 lgrp_config_mem_rename_t lmr; 520 lgrp_handle_t shand, thand; 521 int snode, tnode; 522 523 switch (evt) { 524 525 case LGRP_CONFIG_MEM_ADD: 526 umb = (update_membounds_t *)arg; 527 update_mem_bounds(umb->u_board, umb->u_base, umb->u_len); 528 529 break; 530 531 case LGRP_CONFIG_MEM_DEL: 532 /* We don't have to do anything */ 533 534 break; 535 536 case LGRP_CONFIG_MEM_RENAME: 537 /* 538 * During a DR copy-rename operation, all of the memory 539 * on one board is moved to another board -- but the 540 * addresses/pfns and memnodes don't change. This means 541 * the memory has changed locations without changing identity. 542 * 543 * Source is where we are copying from and target is where we 544 * are copying to. After source memnode is copied to target 545 * memnode, the physical addresses of the target memnode are 546 * renamed to match what the source memnode had. Then target 547 * memnode can be removed and source memnode can take its 548 * place. 549 * 550 * To do this, swap the lgroup handle to memnode mappings for 551 * the boards, so target lgroup will have source memnode and 552 * source lgroup will have empty target memnode which is where 553 * its memory will go (if any is added to it later). 554 * 555 * Then source memnode needs to be removed from its lgroup 556 * and added to the target lgroup where the memory was living 557 * but under a different name/memnode. The memory was in the 558 * target memnode and now lives in the source memnode with 559 * different physical addresses even though it is the same 560 * memory. 561 */ 562 shand = arg & 0xffff; 563 thand = (arg & 0xffff0000) >> 16; 564 snode = plat_lgrphand_to_mem_node(shand); 565 tnode = plat_lgrphand_to_mem_node(thand); 566 567 plat_assign_lgrphand_to_mem_node(thand, snode); 568 plat_assign_lgrphand_to_mem_node(shand, tnode); 569 570 /* 571 * Remove source memnode of copy rename from its lgroup 572 * and add it to its new target lgroup 573 */ 574 lmr.lmem_rename_from = shand; 575 lmr.lmem_rename_to = thand; 576 577 lgrp_config(LGRP_CONFIG_MEM_RENAME, (uintptr_t)snode, 578 (uintptr_t)&lmr); 579 580 break; 581 582 default: 583 break; 584 } 585 } 586 587 /* 588 * Return latency between "from" and "to" lgroups 589 * 590 * This latency number can only be used for relative comparison 591 * between lgroups on the running system, cannot be used across platforms, 592 * and may not reflect the actual latency. It is platform and implementation 593 * specific, so platform gets to decide its value. It would be nice if the 594 * number was at least proportional to make comparisons more meaningful though. 595 * NOTE: The numbers below are supposed to be load latencies for uncached 596 * memory divided by 10. 597 */ 598 int 599 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to) 600 { 601 /* 602 * Return min remote latency when there are more than two lgroups 603 * (root and child) and getting latency between two different lgroups 604 * or root is involved 605 */ 606 if (lgrp_optimizations() && (from != to || 607 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE)) 608 return (28); 609 else 610 return (23); 611 } 612 613 /* ARGSUSED */ 614 void 615 plat_freelist_process(int mnode) 616 { 617 } 618 619 /* 620 * Find dip for chosen IOSRAM 621 */ 622 dev_info_t * 623 find_chosen_dip(void) 624 { 625 dev_info_t *dip; 626 char master_sbbc[MAXNAMELEN]; 627 int nodeid; 628 uint_t tunnel; 629 630 /* 631 * find the /chosen SBBC node, prom interface will handle errors 632 */ 633 nodeid = prom_chosennode(); 634 /* 635 * get the 'iosram' property from the /chosen node 636 */ 637 if (prom_getprop(nodeid, IOSRAM_CHOSEN_PROP, (caddr_t)&tunnel) <= 0) { 638 SBBC_ERR(CE_PANIC, "No iosram property found! \n"); 639 } 640 641 if (prom_phandle_to_path((phandle_t)tunnel, master_sbbc, 642 sizeof (master_sbbc)) < 0) { 643 SBBC_ERR1(CE_PANIC, "prom_phandle_to_path(%d) failed\n", 644 tunnel); 645 } 646 647 chosen_nodeid = nodeid; 648 649 /* 650 * load and attach the sgsbbc driver. 651 * This will also attach all the sgsbbc driver instances 652 */ 653 if (i_ddi_attach_hw_nodes("sgsbbc") != DDI_SUCCESS) { 654 cmn_err(CE_WARN, "sgsbbc failed to load\n"); 655 } 656 /* translate a path name to a dev_info_t */ 657 dip = e_ddi_hold_devi_by_path(master_sbbc, 0); 658 if ((dip == NULL) || (ddi_get_nodeid(dip) != tunnel)) { 659 cmn_err(CE_PANIC, 660 "e_ddi_hold_devi_by_path(%x) failed for SBBC\n", tunnel); 661 } 662 663 /* make sure devi_ref is ZERO */ 664 ndi_rele_devi(dip); 665 DCMNERR(CE_CONT, "Chosen IOSRAM is at %s \n", master_sbbc); 666 667 return (dip); 668 } 669 670 void 671 load_platform_drivers(void) 672 { 673 int ret; 674 675 /* 676 * Load the mc-us3 memory driver. 677 */ 678 if (i_ddi_attach_hw_nodes("mc-us3") != DDI_SUCCESS) 679 cmn_err(CE_WARN, "mc-us3 failed to load"); 680 else 681 (void) ddi_hold_driver(ddi_name_to_major("mc-us3")); 682 683 /* 684 * Initialize the chosen IOSRAM before its clients 685 * are loaded. 686 */ 687 (void) find_chosen_dip(); 688 689 /* 690 * Load the environmentals driver (sgenv) 691 * 692 * We need this driver to handle events from the SC when state 693 * changes occur in the environmental data. 694 */ 695 if (i_ddi_attach_hw_nodes("sgenv") != DDI_SUCCESS) 696 cmn_err(CE_WARN, "sgenv failed to load"); 697 698 /* 699 * Ideally, we'd do this in set_platform_defaults(), but 700 * at that point it's too early to look up symbols. 701 */ 702 iosram_write_ptr = (int (*)(int, uint32_t, caddr_t, uint32_t)) 703 modgetsymvalue("iosram_write", 0); 704 705 if (iosram_write_ptr == NULL) { 706 DCMNERR(CE_WARN, "load_platform_defaults: iosram_write()" 707 " not found; signatures will not be updated\n"); 708 } else { 709 /* 710 * The iosram read ptr is only needed if we can actually 711 * write CPU signatures, so only bother setting it if we 712 * set a valid write pointer, above. 713 */ 714 iosram_read_ptr = (int (*)(int, uint32_t, caddr_t, uint32_t)) 715 modgetsymvalue("iosram_read", 0); 716 717 if (iosram_read_ptr == NULL) 718 DCMNERR(CE_WARN, "load_platform_defaults: iosram_read()" 719 " not found\n"); 720 } 721 722 /* 723 * Set todsg_use_sc to TRUE so that we will be getting date 724 * from the SC. 725 */ 726 todsg_use_sc = TRUE; 727 728 /* 729 * Now is a good time to activate hardware watchdog (if one exists). 730 */ 731 mutex_enter(&tod_lock); 732 if (watchdog_enable) 733 ret = tod_ops.tod_set_watchdog_timer(watchdog_timeout_seconds); 734 mutex_exit(&tod_lock); 735 if (ret != 0) 736 printf("Hardware watchdog enabled\n"); 737 738 plat_ecc_init(); 739 } 740 741 /* 742 * No platform drivers on this platform 743 */ 744 char *platform_module_list[] = { 745 (char *)0 746 }; 747 748 /*ARGSUSED*/ 749 void 750 plat_tod_fault(enum tod_fault_type tod_bad) 751 { 752 } 753 int 754 plat_max_boards() 755 { 756 return (SG_MAX_BDS); 757 } 758 int 759 plat_max_io_units_per_board() 760 { 761 return (SG_MAX_IO_PER_BD); 762 } 763 int 764 plat_max_cmp_units_per_board() 765 { 766 return (SG_MAX_CMPS_PER_BD); 767 } 768 int 769 plat_max_cpu_units_per_board() 770 { 771 return (SG_MAX_CPUS_PER_BD); 772 } 773 774 int 775 plat_max_mc_units_per_board() 776 { 777 return (SG_MAX_CMPS_PER_BD); /* each CPU die has a memory controller */ 778 } 779 780 int 781 plat_max_mem_units_per_board() 782 { 783 return (SG_MAX_MEM_PER_BD); 784 } 785 786 int 787 plat_max_cpumem_boards(void) 788 { 789 return (LW8_MAX_CPU_BDS); 790 } 791 792 int 793 set_platform_max_ncpus(void) 794 { 795 return (sg_max_ncpus); 796 } 797 798 void 799 plat_dmv_params(uint_t *hwint, uint_t *swint) 800 { 801 *hwint = MAX_UPA; 802 *swint = 0; 803 } 804 805 static int (*sg_mbox)(sbbc_msg_t *, sbbc_msg_t *, time_t) = NULL; 806 807 /* 808 * Our nodename has been set, pass it along to the SC. 809 */ 810 void 811 plat_nodename_set(void) 812 { 813 sbbc_msg_t req; /* request */ 814 sbbc_msg_t resp; /* response */ 815 int rv; /* return value from call to mbox */ 816 struct nodename_info { 817 int32_t namelen; 818 char nodename[_SYS_NMLN]; 819 } nni; 820 821 /* 822 * find the symbol for the mailbox routine 823 */ 824 if (sg_mbox == NULL) 825 sg_mbox = (int (*)(sbbc_msg_t *, sbbc_msg_t *, time_t)) 826 modgetsymvalue("sbbc_mbox_request_response", 0); 827 828 if (sg_mbox == NULL) { 829 cmn_err(CE_NOTE, "!plat_nodename_set: sg_mbox not found\n"); 830 return; 831 } 832 833 /* 834 * construct the message telling the SC our nodename 835 */ 836 (void) strcpy(nni.nodename, utsname.nodename); 837 nni.namelen = (int32_t)strlen(nni.nodename); 838 839 req.msg_type.type = INFO_MBOX; 840 req.msg_type.sub_type = INFO_MBOX_NODENAME; 841 req.msg_status = 0; 842 req.msg_len = (int)(nni.namelen + sizeof (nni.namelen)); 843 req.msg_bytes = 0; 844 req.msg_buf = (caddr_t)&nni; 845 req.msg_data[0] = 0; 846 req.msg_data[1] = 0; 847 848 /* 849 * initialize the response back from the SC 850 */ 851 resp.msg_type.type = INFO_MBOX; 852 resp.msg_type.sub_type = INFO_MBOX_NODENAME; 853 resp.msg_status = 0; 854 resp.msg_len = 0; 855 resp.msg_bytes = 0; 856 resp.msg_buf = (caddr_t)0; 857 resp.msg_data[0] = 0; 858 resp.msg_data[1] = 0; 859 860 /* 861 * ship it and check for success 862 */ 863 rv = (sg_mbox)(&req, &resp, sbbc_mbox_default_timeout); 864 865 if (rv != 0) { 866 cmn_err(CE_NOTE, "!plat_nodename_set: sg_mbox retval %d\n", rv); 867 } else if (resp.msg_status != 0) { 868 cmn_err(CE_NOTE, "!plat_nodename_set: msg_status %d\n", 869 resp.msg_status); 870 } else { 871 DCMNERR(CE_NOTE, "!plat_nodename_set was successful\n"); 872 873 /* 874 * It is necessary to exchange capability the bitmap 875 * with SC before sending any ecc error information and 876 * indictment. We are calling the plat_ecc_capability_send() 877 * here just after sending the nodename successfully. 878 */ 879 rv = plat_ecc_capability_send(); 880 if (rv == 0) { 881 DCMNERR(CE_NOTE, "!plat_ecc_capability_send was" 882 "successful\n"); 883 } 884 } 885 } 886 887 /* 888 * flag to allow users switch between using OBP's 889 * prom_get_unum() and mc-us3 driver's p2get_mem_unum() 890 * (for main memory errors only). 891 */ 892 int sg_use_prom_get_unum = 0; 893 894 /* 895 * Debugging flag: set to 1 to call into obp for get_unum, or set it to 0 896 * to call into the unum cache system. This is the E$ equivalent of 897 * sg_use_prom_get_unum. 898 */ 899 int sg_use_prom_ecache_unum = 0; 900 901 /* used for logging ECC errors to the SC */ 902 #define SG_MEMORY_ECC 1 903 #define SG_ECACHE_ECC 2 904 #define SG_UNKNOWN_ECC (-1) 905 906 /* 907 * plat_get_mem_unum() generates a string identifying either the 908 * memory or E$ DIMM(s) during error logging. Depending on whether 909 * the error is E$ or memory related, the appropriate support 910 * routine is called to assist in the string generation. 911 * 912 * - For main memory errors we can use the mc-us3 drivers p2getunum() 913 * (or prom_get_unum() for debugging purposes). 914 * 915 * - For E$ errors we call sg_get_ecacheunum() to generate the unum (or 916 * prom_serengeti_get_ecacheunum() for debugging purposes). 917 */ 918 919 static int 920 sg_prom_get_unum(int synd_code, uint64_t paddr, char *buf, int buflen, 921 int *lenp) 922 { 923 if ((prom_get_unum(synd_code, (unsigned long long)paddr, 924 buf, buflen, lenp)) != 0) 925 return (EIO); 926 else if (*lenp <= 1) 927 return (EINVAL); 928 else 929 return (0); 930 } 931 932 /*ARGSUSED*/ 933 int 934 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 935 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 936 { 937 /* 938 * unum_func will either point to the memory drivers p2get_mem_unum() 939 * or to prom_get_unum() for memory errors. 940 */ 941 int (*unum_func)(int synd_code, uint64_t paddr, char *buf, 942 int buflen, int *lenp) = p2get_mem_unum; 943 944 /* 945 * check if it's a Memory or an Ecache error. 946 */ 947 if (flt_in_memory) { 948 /* 949 * It's a main memory error. 950 * 951 * For debugging we allow the user to switch between 952 * using OBP's get_unum and the memory driver's get_unum 953 * so we create a pointer to the functions and switch 954 * depending on the sg_use_prom_get_unum flag. 955 */ 956 if (sg_use_prom_get_unum) { 957 DCMNERR(CE_NOTE, "Using prom_get_unum from OBP"); 958 return (sg_prom_get_unum(synd_code, 959 P2ALIGN(flt_addr, 8), buf, buflen, lenp)); 960 } else if (unum_func != NULL) { 961 return (unum_func(synd_code, P2ALIGN(flt_addr, 8), 962 buf, buflen, lenp)); 963 } else { 964 return (ENOTSUP); 965 } 966 } else if (flt_status & ECC_ECACHE) { 967 /* 968 * It's an E$ error. 969 */ 970 if (sg_use_prom_ecache_unum) { 971 /* 972 * We call to OBP to handle this. 973 */ 974 DCMNERR(CE_NOTE, 975 "Using prom_serengeti_get_ecacheunum from OBP"); 976 if (prom_serengeti_get_ecacheunum(flt_bus_id, 977 P2ALIGN(flt_addr, 8), buf, buflen, lenp) != 0) { 978 return (EIO); 979 } 980 } else { 981 return (sg_get_ecacheunum(flt_bus_id, flt_addr, 982 buf, buflen, lenp)); 983 } 984 } else { 985 return (ENOTSUP); 986 } 987 988 return (0); 989 } 990 991 /* 992 * This platform hook gets called from mc_add_mem_unum_label() in the mc-us3 993 * driver giving each platform the opportunity to add platform 994 * specific label information to the unum for ECC error logging purposes. 995 */ 996 void 997 plat_add_mem_unum_label(char *unum, int mcid, int bank, int dimm) 998 { 999 char new_unum[UNUM_NAMLEN] = ""; 1000 int node = SG_PORTID_TO_NODEID(mcid); 1001 int board = SG_CPU_BD_PORTID_TO_BD_NUM(mcid); 1002 int position = SG_PORTID_TO_CPU_POSN(mcid); 1003 1004 /* 1005 * The mc-us3 driver deals with logical banks but for unum 1006 * purposes we need to use physical banks so that the correct 1007 * dimm can be physically located. Logical banks 0 and 2 1008 * make up physical bank 0. Logical banks 1 and 3 make up 1009 * physical bank 1. Here we do the necessary conversion. 1010 */ 1011 bank = (bank % 2); 1012 1013 if (dimm == -1) { 1014 SG_SET_FRU_NAME_NODE(new_unum, node); 1015 SG_SET_FRU_NAME_CPU_BOARD(new_unum, board); 1016 SG_SET_FRU_NAME_MODULE(new_unum, position); 1017 SG_SET_FRU_NAME_BANK(new_unum, bank); 1018 1019 } else { 1020 SG_SET_FRU_NAME_NODE(new_unum, node); 1021 SG_SET_FRU_NAME_CPU_BOARD(new_unum, board); 1022 SG_SET_FRU_NAME_MODULE(new_unum, position); 1023 SG_SET_FRU_NAME_BANK(new_unum, bank); 1024 SG_SET_FRU_NAME_DIMM(new_unum, dimm); 1025 1026 strcat(new_unum, " "); 1027 strcat(new_unum, unum); 1028 } 1029 1030 strcpy(unum, new_unum); 1031 } 1032 1033 int 1034 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 1035 { 1036 int node = SG_PORTID_TO_NODEID(cpuid); 1037 int board = SG_CPU_BD_PORTID_TO_BD_NUM(cpuid); 1038 1039 if (snprintf(buf, buflen, "/N%d/%s%d", node, 1040 SG_HPU_TYPE_CPU_BOARD_ID, board) >= buflen) { 1041 return (ENOSPC); 1042 } else { 1043 *lenp = strlen(buf); 1044 return (0); 1045 } 1046 } 1047 1048 static void (*sg_ecc_taskq_func)(sbbc_ecc_mbox_t *) = NULL; 1049 static int (*sg_ecc_mbox_func)(sbbc_ecc_mbox_t *) = NULL; 1050 1051 /* 1052 * We log all ECC errors to the SC so we send a mailbox 1053 * message to the SC passing it the relevant data. 1054 * ECC mailbox messages are sent via a taskq mechanism to 1055 * prevent impaired system performance during ECC floods. 1056 * Indictments have already passed through a taskq, so they 1057 * are not queued here. 1058 */ 1059 int 1060 plat_send_ecc_mailbox_msg(plat_ecc_message_type_t msg_type, void *datap) 1061 { 1062 sbbc_ecc_mbox_t *msgp; 1063 uint16_t msg_subtype; 1064 int sleep_flag, log_error; 1065 size_t msg_size; 1066 1067 if (sg_ecc_taskq_func == NULL) { 1068 sg_ecc_taskq_func = (void (*)(sbbc_ecc_mbox_t *)) 1069 modgetsymvalue("sbbc_mbox_queue_ecc_event", 0); 1070 if (sg_ecc_taskq_func == NULL) { 1071 cmn_err(CE_NOTE, "!plat_send_ecc_mailbox_msg: " 1072 "sbbc_mbox_queue_ecc_event not found"); 1073 return (ENODEV); 1074 } 1075 } 1076 if (sg_ecc_mbox_func == NULL) { 1077 sg_ecc_mbox_func = (int (*)(sbbc_ecc_mbox_t *)) 1078 modgetsymvalue("sbbc_mbox_ecc_output", 0); 1079 if (sg_ecc_mbox_func == NULL) { 1080 cmn_err(CE_NOTE, "!plat_send_ecc_mailbox_msg: " 1081 "sbbc_mbox_ecc_output not found"); 1082 return (ENODEV); 1083 } 1084 } 1085 1086 /* 1087 * Initialize the request and response structures 1088 */ 1089 switch (msg_type) { 1090 case PLAT_ECC_ERROR_MESSAGE: 1091 msg_subtype = INFO_MBOX_ERROR_ECC; 1092 msg_size = sizeof (plat_ecc_error_data_t); 1093 sleep_flag = KM_NOSLEEP; 1094 log_error = 1; 1095 break; 1096 case PLAT_ECC_ERROR2_MESSAGE: 1097 msg_subtype = INFO_MBOX_ECC; 1098 msg_size = sizeof (plat_ecc_error2_data_t); 1099 sleep_flag = KM_NOSLEEP; 1100 log_error = 1; 1101 break; 1102 case PLAT_ECC_INDICTMENT_MESSAGE: 1103 msg_subtype = INFO_MBOX_ERROR_INDICT; 1104 msg_size = sizeof (plat_ecc_indictment_data_t); 1105 sleep_flag = KM_SLEEP; 1106 log_error = 0; 1107 break; 1108 case PLAT_ECC_INDICTMENT2_MESSAGE: 1109 msg_subtype = INFO_MBOX_ECC; 1110 msg_size = sizeof (plat_ecc_indictment2_data_t); 1111 sleep_flag = KM_SLEEP; 1112 log_error = 0; 1113 break; 1114 case PLAT_ECC_CAPABILITY_MESSAGE: 1115 msg_subtype = INFO_MBOX_ECC_CAP; 1116 msg_size = sizeof (plat_capability_data_t) + 1117 strlen(utsname.release) + strlen(utsname.version) + 2; 1118 sleep_flag = KM_SLEEP; 1119 log_error = 0; 1120 break; 1121 case PLAT_ECC_DIMM_SID_MESSAGE: 1122 msg_subtype = INFO_MBOX_ECC; 1123 msg_size = sizeof (plat_dimm_sid_request_data_t); 1124 sleep_flag = KM_SLEEP; 1125 log_error = 0; 1126 break; 1127 default: 1128 return (EINVAL); 1129 } 1130 1131 msgp = (sbbc_ecc_mbox_t *)kmem_zalloc(sizeof (sbbc_ecc_mbox_t), 1132 sleep_flag); 1133 if (msgp == NULL) { 1134 cmn_err(CE_NOTE, "!plat_send_ecc_mailbox_msg: " 1135 "unable to allocate sbbc_ecc_mbox"); 1136 return (ENOMEM); 1137 } 1138 1139 msgp->ecc_log_error = log_error; 1140 1141 msgp->ecc_req.msg_type.type = INFO_MBOX; 1142 msgp->ecc_req.msg_type.sub_type = msg_subtype; 1143 msgp->ecc_req.msg_status = 0; 1144 msgp->ecc_req.msg_len = (int)msg_size; 1145 msgp->ecc_req.msg_bytes = 0; 1146 msgp->ecc_req.msg_buf = (caddr_t)kmem_zalloc(msg_size, sleep_flag); 1147 msgp->ecc_req.msg_data[0] = 0; 1148 msgp->ecc_req.msg_data[1] = 0; 1149 1150 if (msgp->ecc_req.msg_buf == NULL) { 1151 cmn_err(CE_NOTE, "!plat_send_ecc_mailbox_msg: " 1152 "unable to allocate request msg_buf"); 1153 kmem_free((void *)msgp, sizeof (sbbc_ecc_mbox_t)); 1154 return (ENOMEM); 1155 } 1156 1157 bcopy(datap, (void *)msgp->ecc_req.msg_buf, msg_size); 1158 1159 /* 1160 * initialize the response back from the SC 1161 */ 1162 msgp->ecc_resp.msg_type.type = INFO_MBOX; 1163 msgp->ecc_resp.msg_type.sub_type = msg_subtype; 1164 msgp->ecc_resp.msg_status = 0; 1165 msgp->ecc_resp.msg_len = 0; 1166 msgp->ecc_resp.msg_bytes = 0; 1167 msgp->ecc_resp.msg_buf = NULL; 1168 msgp->ecc_resp.msg_data[0] = 0; 1169 msgp->ecc_resp.msg_data[1] = 0; 1170 1171 switch (msg_type) { 1172 case PLAT_ECC_ERROR_MESSAGE: 1173 case PLAT_ECC_ERROR2_MESSAGE: 1174 /* 1175 * For Error Messages, we go through a taskq. 1176 * Queue up message for processing 1177 */ 1178 (*sg_ecc_taskq_func)(msgp); 1179 return (0); 1180 1181 case PLAT_ECC_CAPABILITY_MESSAGE: 1182 /* 1183 * For indictment and capability messages, we've already gone 1184 * through the taskq, so we can call the mailbox routine 1185 * directly. Find the symbol for the routine that sends 1186 * the mailbox msg 1187 */ 1188 msgp->ecc_resp.msg_len = (int)msg_size; 1189 msgp->ecc_resp.msg_buf = (caddr_t)kmem_zalloc(msg_size, 1190 sleep_flag); 1191 /* FALLTHRU */ 1192 1193 case PLAT_ECC_INDICTMENT_MESSAGE: 1194 case PLAT_ECC_INDICTMENT2_MESSAGE: 1195 return ((*sg_ecc_mbox_func)(msgp)); 1196 1197 case PLAT_ECC_DIMM_SID_MESSAGE: 1198 msgp->ecc_resp.msg_len = sizeof (plat_dimm_sid_board_data_t); 1199 msgp->ecc_resp.msg_buf = (caddr_t)kmem_zalloc( 1200 sizeof (plat_dimm_sid_board_data_t), sleep_flag); 1201 1202 return ((*sg_ecc_mbox_func)(msgp)); 1203 1204 default: 1205 ASSERT(0); 1206 return (EINVAL); 1207 } 1208 } 1209 1210 /* 1211 * m is redundant on serengeti as the multiplyer is always 4 1212 */ 1213 /*ARGSUSED*/ 1214 int 1215 plat_make_fru_cpuid(int sb, int m, int proc) 1216 { 1217 return (MAKE_CPUID(sb, proc)); 1218 } 1219 1220 /* 1221 * board number for a given proc 1222 */ 1223 int 1224 plat_make_fru_boardnum(int proc) 1225 { 1226 return (SG_PORTID_TO_BOARD_NUM(proc)); 1227 } 1228 1229 static 1230 void 1231 cpu_sgn_update(ushort_t sig, uchar_t state, uchar_t sub_state, int cpuid) 1232 { 1233 uint32_t signature = CPU_SIG_BLD(sig, state, sub_state); 1234 sig_state_t current_sgn; 1235 int i; 1236 1237 if (iosram_write_ptr == NULL) { 1238 /* 1239 * If the IOSRAM write pointer isn't set, we won't be able 1240 * to write signatures to ANYTHING, so we may as well just 1241 * write out an error message (if desired) and exit this 1242 * routine now... 1243 */ 1244 DCMNERR(CE_WARN, 1245 "cpu_sgn_update: iosram_write() not found;" 1246 " cannot write signature 0x%x for CPU(s) or domain\n", 1247 signature); 1248 return; 1249 } 1250 1251 1252 /* 1253 * Differentiate a panic reboot from a non-panic reboot in the 1254 * setting of the substate of the signature. 1255 * 1256 * If the new substate is REBOOT and we're rebooting due to a panic, 1257 * then set the new substate to a special value indicating a panic 1258 * reboot, SIGSUBST_PANIC_REBOOT. 1259 * 1260 * A panic reboot is detected by a current (previous) domain signature 1261 * state of SIGST_EXIT, and a new signature substate of SIGSUBST_REBOOT. 1262 * The domain signature state SIGST_EXIT is used as the panic flow 1263 * progresses. 1264 * 1265 * At the end of the panic flow, the reboot occurs but we should now 1266 * one that was involuntary, something that may be quite useful to know 1267 * at OBP level. 1268 */ 1269 if (sub_state == SIGSUBST_REBOOT) { 1270 if (iosram_read_ptr == NULL) { 1271 DCMNERR(CE_WARN, 1272 "cpu_sgn_update: iosram_read() not found;" 1273 " could not check current domain signature\n"); 1274 } else { 1275 (void) (*iosram_read_ptr)(SBBC_SIGBLCK_KEY, 1276 SG_SGNBLK_DOMAINSIG_OFFSET, 1277 (char *)¤t_sgn, sizeof (current_sgn)); 1278 if (current_sgn.state_t.state == SIGST_EXIT) 1279 signature = CPU_SIG_BLD(sig, state, 1280 SIGSUBST_PANIC_REBOOT); 1281 } 1282 } 1283 1284 /* 1285 * cpuid == -1 indicates that the operation applies to all cpus. 1286 */ 1287 if (cpuid >= 0) { 1288 (void) (*iosram_write_ptr)(SBBC_SIGBLCK_KEY, 1289 SG_SGNBLK_CPUSIG_OFFSET(cpuid), (char *)&signature, 1290 sizeof (signature)); 1291 } else { 1292 for (i = 0; i < NCPU; i++) { 1293 if (cpu[i] == NULL || !(cpu[i]->cpu_flags & 1294 (CPU_EXISTS|CPU_QUIESCED))) { 1295 continue; 1296 } 1297 (void) (*iosram_write_ptr)(SBBC_SIGBLCK_KEY, 1298 SG_SGNBLK_CPUSIG_OFFSET(i), (char *)&signature, 1299 sizeof (signature)); 1300 } 1301 } 1302 1303 if (state == SIGST_OFFLINE || state == SIGST_DETACHED) { 1304 return; 1305 } 1306 1307 (void) (*iosram_write_ptr)(SBBC_SIGBLCK_KEY, 1308 SG_SGNBLK_DOMAINSIG_OFFSET, (char *)&signature, 1309 sizeof (signature)); 1310 } 1311 1312 void 1313 startup_platform(void) 1314 { 1315 } 1316 1317 /* 1318 * A routine to convert a number (represented as a string) to 1319 * the integer value it represents. 1320 */ 1321 1322 static int 1323 isdigit(int ch) 1324 { 1325 return (ch >= '0' && ch <= '9'); 1326 } 1327 1328 #define isspace(c) ((c) == ' ' || (c) == '\t' || (c) == '\n') 1329 1330 static int 1331 strtoi(char *p, char **pos) 1332 { 1333 int n; 1334 int c, neg = 0; 1335 1336 if (!isdigit(c = *p)) { 1337 while (isspace(c)) 1338 c = *++p; 1339 switch (c) { 1340 case '-': 1341 neg++; 1342 /* FALLTHROUGH */ 1343 case '+': 1344 c = *++p; 1345 } 1346 if (!isdigit(c)) { 1347 if (pos != NULL) 1348 *pos = p; 1349 return (0); 1350 } 1351 } 1352 for (n = '0' - c; isdigit(c = *++p); ) { 1353 n *= 10; /* two steps to avoid unnecessary overflow */ 1354 n += '0' - c; /* accum neg to avoid surprises at MAX */ 1355 } 1356 if (pos != NULL) 1357 *pos = p; 1358 return (neg ? n : -n); 1359 } 1360 1361 /* 1362 * Get the three parts of the Serengeti PROM version. 1363 * Used for feature readiness tests. 1364 * 1365 * Return 0 if version extracted successfully, -1 otherwise. 1366 */ 1367 1368 int 1369 sg_get_prom_version(int *sysp, int *intfp, int *bldp) 1370 { 1371 int plen; 1372 char vers[512]; 1373 static pnode_t node; 1374 static char version[] = "version"; 1375 char *verp, *ep; 1376 1377 node = prom_finddevice("/openprom"); 1378 if (node == OBP_BADNODE) 1379 return (-1); 1380 1381 plen = prom_getproplen(node, version); 1382 if (plen <= 0 || plen >= sizeof (vers)) 1383 return (-1); 1384 (void) prom_getprop(node, version, vers); 1385 vers[plen] = '\0'; 1386 1387 /* Make sure it's an OBP flashprom */ 1388 if (vers[0] != 'O' && vers[1] != 'B' && vers[2] != 'P') { 1389 cmn_err(CE_WARN, "sg_get_prom_version: " 1390 "unknown <version> string in </openprom>\n"); 1391 return (-1); 1392 } 1393 verp = &vers[4]; 1394 1395 *sysp = strtoi(verp, &ep); 1396 if (ep == verp || *ep != '.') 1397 return (-1); 1398 verp = ep + 1; 1399 1400 *intfp = strtoi(verp, &ep); 1401 if (ep == verp || *ep != '.') 1402 return (-1); 1403 verp = ep + 1; 1404 1405 *bldp = strtoi(verp, &ep); 1406 if (ep == verp || (*ep != '\0' && !isspace(*ep))) 1407 return (-1); 1408 return (0); 1409 } 1410 1411 /* 1412 * Return 0 if system board Dynamic Reconfiguration 1413 * is supported by the firmware, -1 otherwise. 1414 */ 1415 int 1416 sg_prom_sb_dr_check(void) 1417 { 1418 static int prom_res = 1; 1419 1420 if (prom_res == 1) { 1421 int sys, intf, bld; 1422 int rv; 1423 1424 rv = sg_get_prom_version(&sys, &intf, &bld); 1425 if (rv == 0 && sys == 5 && 1426 (intf >= 12 || (intf == 11 && bld >= 200))) { 1427 prom_res = 0; 1428 } else { 1429 prom_res = -1; 1430 } 1431 } 1432 return (prom_res); 1433 } 1434 1435 /* 1436 * Return 0 if cPCI Dynamic Reconfiguration 1437 * is supported by the firmware, -1 otherwise. 1438 */ 1439 int 1440 sg_prom_cpci_dr_check(void) 1441 { 1442 /* 1443 * The version check is currently the same as for 1444 * system boards. Since the two DR sub-systems are 1445 * independent, this could change. 1446 */ 1447 return (sg_prom_sb_dr_check()); 1448 } 1449 1450 /* 1451 * Our implementation of this KDI op updates the CPU signature in the system 1452 * controller. Note that we set the signature to OBP_SIG, rather than DBG_SIG. 1453 * The Forth words we execute will, among other things, transform our OBP_SIG 1454 * into DBG_SIG. They won't function properly if we try to use DBG_SIG. 1455 */ 1456 static void 1457 sg_system_claim(void) 1458 { 1459 prom_interpret("sigb-sig! my-sigb-sig!", OBP_SIG, OBP_SIG, 0, 0, 0); 1460 } 1461 1462 static void 1463 sg_system_release(void) 1464 { 1465 prom_interpret("sigb-sig! my-sigb-sig!", OS_SIG, OS_SIG, 0, 0, 0); 1466 } 1467 1468 static void 1469 sg_console_claim(void) 1470 { 1471 prom_serengeti_set_console_input(SGCN_OBP_STR); 1472 } 1473 1474 static void 1475 sg_console_release(void) 1476 { 1477 prom_serengeti_set_console_input(SGCN_CLNT_STR); 1478 } 1479 1480 void 1481 plat_kdi_init(kdi_t *kdi) 1482 { 1483 kdi->pkdi_system_claim = sg_system_claim; 1484 kdi->pkdi_system_release = sg_system_release; 1485 kdi->pkdi_console_claim = sg_console_claim; 1486 kdi->pkdi_console_release = sg_console_release; 1487 } 1488