1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * sun4u Fire Error Handling 31 */ 32 33 #include <sys/types.h> 34 #include <sys/ddi.h> 35 #include <sys/sunddi.h> 36 #include <sys/fm/protocol.h> 37 #include <sys/fm/util.h> 38 #include <sys/pcie.h> 39 #include <sys/pcie_impl.h> 40 #include "px_obj.h" 41 #include <px_regs.h> 42 #include <px_csr.h> 43 #include <sys/membar.h> 44 #include "px_lib4u.h" 45 #include "px_err.h" 46 #include "px_err_impl.h" 47 48 /* 49 * JBC error bit table 50 */ 51 #define JBC_BIT_DESC(bit, hdl, erpt) \ 52 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 53 0, \ 54 PX_ERR_BIT_HANDLE(hdl), \ 55 PX_ERPT_SEND(erpt), \ 56 PX_ERR_JBC_CLASS(bit) 57 px_err_bit_desc_t px_err_cb_tbl[] = { 58 /* JBC FATAL - see io erpt doc, section 1.1 */ 59 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 60 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 61 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 62 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 63 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 64 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 65 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 66 67 /* JBC MERGE - see io erpt doc, section 1.2 */ 68 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 69 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 70 71 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 72 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 73 { JBC_BIT_DESC(CE_ASYN, jbc_jbusint_in, jbc_in) }, 74 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 75 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 76 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 77 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 78 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 79 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 80 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 81 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 82 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 83 84 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 85 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 86 87 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 88 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_dmcint_odcd, jbc_odcd) }, 89 { JBC_BIT_DESC(ILL_ACC_RD, jbc_dmcint_odcd, jbc_odcd) }, 90 { JBC_BIT_DESC(PIO_UNMAP, jbc_dmcint_odcd, jbc_odcd) }, 91 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 92 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 93 { JBC_BIT_DESC(ILL_ACC, jbc_dmcint_odcd, jbc_odcd) }, 94 95 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 96 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 97 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 98 99 /* JBC CSR - see io erpt doc, section 1.7 */ 100 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 101 }; 102 103 #define px_err_cb_keys \ 104 (sizeof (px_err_cb_tbl)) / (sizeof (px_err_bit_desc_t)) 105 106 /* 107 * DMC error bit tables 108 */ 109 #define IMU_BIT_DESC(bit, hdl, erpt) \ 110 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 111 0, \ 112 PX_ERR_BIT_HANDLE(hdl), \ 113 PX_ERPT_SEND(erpt), \ 114 PX_ERR_DMC_CLASS(bit) 115 px_err_bit_desc_t px_err_imu_tbl[] = { 116 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 117 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 118 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 119 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 120 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_rbne, imu_rds) }, 121 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 122 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 123 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 124 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 125 126 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 127 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 128 129 /* DMC IMU - see io erpt doc, section 2.3 */ 130 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 131 }; 132 133 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 134 135 /* mmu errors */ 136 #define MMU_BIT_DESC(bit, hdl, erpt) \ 137 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 138 0, \ 139 PX_ERR_BIT_HANDLE(hdl), \ 140 PX_ERPT_SEND(erpt), \ 141 PX_ERR_DMC_CLASS(bit) 142 px_err_bit_desc_t px_err_mmu_tbl[] = { 143 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 144 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 145 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 146 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 147 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 148 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 149 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 150 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 151 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 152 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 153 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 154 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 155 156 /* DMC MMU - see io erpt doc, section 2.5 */ 157 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 158 }; 159 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 160 161 /* 162 * PEC error bit tables 163 */ 164 #define ILU_BIT_DESC(bit, hdl, erpt) \ 165 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 166 0, \ 167 PX_ERR_BIT_HANDLE(hdl), \ 168 PX_ERPT_SEND(erpt), \ 169 PX_ERR_PEC_CLASS(bit) 170 px_err_bit_desc_t px_err_ilu_tbl[] = { 171 /* PEC ILU none - see io erpt doc, section 3.1 */ 172 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 173 }; 174 #define px_err_ilu_keys \ 175 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 176 177 /* 178 * PEC UE errors implementation is incomplete pending PCIE generic 179 * fabric rules. 180 */ 181 /* pec ue errors */ 182 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 183 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 184 0, \ 185 NULL, \ 186 NULL, \ 187 "" 188 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 189 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 190 { TLU_UC_BIT_DESC(UR, NULL, NULL) }, 191 { TLU_UC_BIT_DESC(ROF, NULL, NULL) }, 192 { TLU_UC_BIT_DESC(UC, NULL, NULL) }, 193 194 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 195 { TLU_UC_BIT_DESC(CTO, NULL, NULL) }, 196 197 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 198 { TLU_UC_BIT_DESC(MFP, NULL, NULL) }, 199 { TLU_UC_BIT_DESC(PP, NULL, NULL) }, 200 201 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 202 { TLU_UC_BIT_DESC(FCP, NULL, NULL) }, 203 { TLU_UC_BIT_DESC(DLP, NULL, NULL) }, 204 { TLU_UC_BIT_DESC(TE, NULL, NULL) }, 205 { TLU_UC_BIT_DESC(CA, NULL, NULL) } 206 }; 207 #define px_err_tlu_ue_keys \ 208 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 209 210 /* 211 * PEC CE errors implementation is incomplete pending PCIE generic 212 * fabric rules. 213 */ 214 /* pec ce errors */ 215 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 216 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 217 0, \ 218 NULL, \ 219 NULL, \ 220 "" 221 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 222 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 223 { TLU_CE_BIT_DESC(RTO, NULL, NULL) }, 224 { TLU_CE_BIT_DESC(RNR, NULL, NULL) }, 225 { TLU_CE_BIT_DESC(BDP, NULL, NULL) }, 226 { TLU_CE_BIT_DESC(BTP, NULL, NULL) }, 227 { TLU_CE_BIT_DESC(RE, NULL, NULL) } 228 }; 229 #define px_err_tlu_ce_keys \ 230 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 231 232 /* pec oe errors */ 233 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 234 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 235 0, \ 236 PX_ERR_BIT_HANDLE(hdl), \ 237 PX_ERPT_SEND(erpt), \ 238 PX_ERR_PEC_CLASS(bit) 239 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 240 /* 241 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 242 */ 243 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 244 245 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 246 { TLU_OE_BIT_DESC(WUC, fatal_stuck, pciex_rx_tx_oe) }, 247 { TLU_OE_BIT_DESC(RUC, fatal_stuck, pciex_rx_tx_oe) }, 248 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 249 250 /* TLU Other Event - see io erpt doc, section 3.9 */ 251 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 252 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 253 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 254 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 255 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 256 { TLU_OE_BIT_DESC(LDN, non_fatal, pciex_oe) }, 257 { TLU_OE_BIT_DESC(LUP, non_fatal, pciex_oe) }, 258 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 259 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 260 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 261 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 262 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 263 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 264 }; 265 266 #define px_err_tlu_oe_keys \ 267 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 268 269 /* 270 * All the following tables below are for LPU Interrupts. These interrupts 271 * are *NOT* error interrupts, but event status interrupts. 272 * 273 * These events are probably of most interest to: 274 * o Hotplug 275 * o Power Management 276 * o etc... 277 * 278 * There are also a few events that would be interresting for FMA. 279 * Again none of the regiseters below state that an error has occured 280 * or that data has been lost. If anything, they give status that an 281 * error is *about* to occur. examples 282 * o INT_SKP_ERR - indicates clock between fire and child is too far 283 * off and is most unlikely able to compensate 284 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 285 * HW recoverable, but will like end up as a future 286 * fabric error as well. 287 * 288 * For now, we don't care about any of these errors and should be ignore, 289 * but cleared. 290 */ 291 292 /* LPU Link Interrupt Table */ 293 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 294 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 295 0, \ 296 NULL, \ 297 NULL, \ 298 "" 299 px_err_bit_desc_t px_err_lpul_tbl[] = { 300 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 301 }; 302 #define px_err_lpul_keys \ 303 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 304 305 /* LPU Physical Interrupt Table */ 306 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 307 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 308 0, \ 309 NULL, \ 310 NULL, \ 311 "" 312 px_err_bit_desc_t px_err_lpup_tbl[] = { 313 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 314 }; 315 #define px_err_lpup_keys \ 316 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 317 318 /* LPU Receive Interrupt Table */ 319 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 320 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 321 0, \ 322 NULL, \ 323 NULL, \ 324 "" 325 px_err_bit_desc_t px_err_lpur_tbl[] = { 326 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 327 }; 328 #define px_err_lpur_keys \ 329 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 330 331 /* LPU Transmit Interrupt Table */ 332 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 333 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 334 0, \ 335 NULL, \ 336 NULL, \ 337 "" 338 px_err_bit_desc_t px_err_lpux_tbl[] = { 339 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 340 }; 341 #define px_err_lpux_keys \ 342 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 343 344 /* LPU LTSSM Interrupt Table */ 345 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 346 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 347 0, \ 348 NULL, \ 349 NULL, \ 350 "" 351 px_err_bit_desc_t px_err_lpus_tbl[] = { 352 { LPUS_BIT_DESC(ANY, NULL, NULL) } 353 }; 354 #define px_err_lpus_keys \ 355 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 356 357 /* LPU Gigablaze Glue Interrupt Table */ 358 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 359 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 360 0, \ 361 NULL, \ 362 NULL, \ 363 "" 364 px_err_bit_desc_t px_err_lpug_tbl[] = { 365 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 366 }; 367 #define px_err_lpug_keys \ 368 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 369 370 371 /* Mask and Tables */ 372 #define MnT6(pre) \ 373 B_FALSE, \ 374 &px_ ## pre ## _intr_mask, \ 375 &px_ ## pre ## _log_mask, \ 376 &px_ ## pre ## _count_mask, \ 377 px_err_ ## pre ## _tbl, \ 378 px_err_ ## pre ## _keys, \ 379 0 380 381 /* LPU Registers Addresses */ 382 #define LR4(pre) \ 383 NULL, \ 384 LPU_ ## pre ## _INTERRUPT_MASK, \ 385 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 386 LPU_ ## pre ## _INTERRUPT_AND_STATUS 387 388 /* LPU Registers Addresses with Irregularities */ 389 #define LR4_FIXME(pre) \ 390 NULL, \ 391 LPU_ ## pre ## _INTERRUPT_MASK, \ 392 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 393 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 394 395 /* TLU Registers Addresses */ 396 #define TR4(pre) \ 397 TLU_ ## pre ## _LOG_ENABLE, \ 398 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 399 TLU_ ## pre ## _INTERRUPT_STATUS, \ 400 TLU_ ## pre ## _STATUS_CLEAR 401 402 /* Registers Addresses for JBC, MMU, IMU and ILU */ 403 #define R4(pre) \ 404 pre ## _ERROR_LOG_ENABLE, \ 405 pre ## _INTERRUPT_ENABLE, \ 406 pre ## _INTERRUPT_STATUS, \ 407 pre ## _ERROR_STATUS_CLEAR 408 409 /* 410 * Register error handling tables. 411 * The ID Field (first field) is identified by an enum px_err_id_t. 412 * It is located in px_err.h 413 */ 414 px_err_reg_desc_t px_err_reg_tbl[] = { 415 { MnT6(cb), R4(JBC), "JBC Error"}, 416 { MnT6(mmu), R4(MMU), "IMU Error"}, 417 { MnT6(imu), R4(IMU), "ILU Error"}, 418 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 419 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 420 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 421 { MnT6(ilu), R4(ILU), "MMU Error"}, 422 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 423 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 424 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 425 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 426 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 427 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"} 428 }; 429 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 430 431 typedef struct px_err_ss { 432 uint64_t err_status[PX_ERR_REG_KEYS]; 433 } px_err_ss_t; 434 435 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc); 436 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 437 px_err_ss_t *ss); 438 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 439 int err, int caller); 440 441 /* 442 * px_err_cb_intr: 443 * Interrupt handler for the JBC block. 444 * o lock 445 * o create derr 446 * o px_err_handle(leaf1, with jbc) 447 * o px_err_handle(leaf2, without jbc) 448 * o dispatch (leaf1) 449 * o dispatch (leaf2) 450 * o unlock 451 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 452 */ 453 uint_t 454 px_err_cb_intr(caddr_t arg) 455 { 456 px_fault_t *px_fault_p = (px_fault_t *)arg; 457 dev_info_t *rpdip = px_fault_p->px_fh_dip; 458 dev_info_t *leafdip; 459 px_t *px_p = DIP_TO_STATE(rpdip); 460 px_cb_t *cb_p = px_p->px_cb_p; 461 int err = PX_OK, ret; 462 int fatal = 0; 463 int nonfatal = 0; 464 int unknown = 0; 465 int i; 466 boolean_t chkjbc = B_TRUE; 467 ddi_fm_error_t derr; 468 469 /* Create the derr */ 470 bzero(&derr, sizeof (ddi_fm_error_t)); 471 derr.fme_version = DDI_FME_VERSION; 472 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 473 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 474 475 mutex_enter(&cb_p->xbc_fm_mutex); 476 477 /* send ereport/handle/clear for ALL fire leaves */ 478 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 479 if ((px_p = cb_p->xbc_px_list[i]) == NULL) 480 continue; 481 482 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, chkjbc); 483 chkjbc = B_FALSE; 484 } 485 486 /* Check all child devices for errors on ALL fire leaves */ 487 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 488 if ((px_p = cb_p->xbc_px_list[i]) != NULL) { 489 leafdip = px_p->px_dip; 490 ret = ndi_fm_handler_dispatch(leafdip, NULL, &derr); 491 switch (ret) { 492 case DDI_FM_FATAL: 493 fatal++; 494 break; 495 case DDI_FM_NONFATAL: 496 nonfatal++; 497 break; 498 case DDI_FM_UNKNOWN: 499 unknown++; 500 break; 501 default: 502 break; 503 } 504 } 505 } 506 507 /* Set the intr state to idle for the leaf that received the mondo */ 508 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 509 INTR_IDLE_STATE); 510 511 mutex_exit(&cb_p->xbc_fm_mutex); 512 513 /* 514 * PX_FATAL_HW error is diagnosed after system recovered from 515 * HW initiated reset, therefore no furthur handling is required. 516 */ 517 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 518 fm_panic("Fatal System Bus Error has occurred\n"); 519 520 return (DDI_INTR_CLAIMED); 521 } 522 523 /* 524 * px_err_dmc_pec_intr: 525 * Interrupt handler for the DMC/PEC block. 526 * o lock 527 * o create derr 528 * o px_err_handle(leaf, with jbc) 529 * o dispatch (leaf) 530 * o unlock 531 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 532 */ 533 uint_t 534 px_err_dmc_pec_intr(caddr_t arg) 535 { 536 px_fault_t *px_fault_p = (px_fault_t *)arg; 537 dev_info_t *rpdip = px_fault_p->px_fh_dip; 538 px_t *px_p = DIP_TO_STATE(rpdip); 539 px_cb_t *cb_p = px_p->px_cb_p; 540 int err = PX_OK, ret; 541 ddi_fm_error_t derr; 542 543 /* Create the derr */ 544 bzero(&derr, sizeof (ddi_fm_error_t)); 545 derr.fme_version = DDI_FME_VERSION; 546 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 547 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 548 549 mutex_enter(&cb_p->xbc_fm_mutex); 550 551 /* send ereport/handle/clear fire registers */ 552 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 553 554 /* Check all child devices for errors */ 555 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 556 557 /* Set the interrupt state to idle */ 558 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 559 INTR_IDLE_STATE); 560 561 mutex_exit(&cb_p->xbc_fm_mutex); 562 563 /* 564 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 565 * therefore it does not cause panic. 566 */ 567 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 568 fm_panic("Fatal System Port Error has occurred\n"); 569 570 return (DDI_INTR_CLAIMED); 571 } 572 573 /* 574 * Error register are being handled by px_hlib xxx_init functions. 575 * They are also called again by px_err_add_intr for mondo62 and 63 576 * from px_cb_attach and px_attach 577 */ 578 void 579 px_err_reg_enable(px_t *px_p, px_err_id_t id) 580 { 581 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 582 uint64_t intr_mask = *reg_desc->intr_mask_p; 583 uint64_t log_mask = *reg_desc->log_mask_p; 584 caddr_t csr_base; 585 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 586 587 if (id == PX_ERR_JBC) 588 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 589 else 590 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 591 592 reg_desc->enabled = B_TRUE; 593 594 /* Enable logs if it exists */ 595 if (reg_desc->log_addr != NULL) 596 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 597 598 /* 599 * For readability you in code you set 1 to enable an interrupt. 600 * But in Fire it's backwards. You set 1 to *disable* an intr. 601 * Reverse the user tunable intr mask field. 602 * 603 * Disable All Errors 604 * Clear All Errors 605 * Enable Errors 606 */ 607 CSR_XS(csr_base, reg_desc->enable_addr, 0); 608 CSR_XS(csr_base, reg_desc->clear_addr, -1); 609 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 610 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 611 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 612 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 613 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 614 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 615 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 616 if (reg_desc->log_addr != NULL) { 617 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 618 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 619 } 620 } 621 622 void 623 px_err_reg_disable(px_t *px_p, px_err_id_t id) 624 { 625 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 626 caddr_t csr_base; 627 628 if (id == PX_ERR_JBC) 629 csr_base = (caddr_t)px_p->px_inos[PX_INTR_XBC]; 630 else 631 csr_base = (caddr_t)px_p->px_inos[PX_INTR_PEC]; 632 633 reg_desc->enabled = B_FALSE; 634 635 switch (id) { 636 case PX_ERR_JBC: 637 case PX_ERR_MMU: 638 case PX_ERR_IMU: 639 case PX_ERR_TLU_UE: 640 case PX_ERR_TLU_CE: 641 case PX_ERR_TLU_OE: 642 case PX_ERR_ILU: 643 if (reg_desc->log_addr != NULL) { 644 CSR_XS(csr_base, reg_desc->log_addr, 0); 645 } 646 CSR_XS(csr_base, reg_desc->enable_addr, 0); 647 break; 648 case PX_ERR_LPU_LINK: 649 case PX_ERR_LPU_PHY: 650 case PX_ERR_LPU_RX: 651 case PX_ERR_LPU_TX: 652 case PX_ERR_LPU_LTSSM: 653 case PX_ERR_LPU_GIGABLZ: 654 if (reg_desc->log_addr != NULL) { 655 CSR_XS(csr_base, reg_desc->log_addr, -1); 656 } 657 CSR_XS(csr_base, reg_desc->enable_addr, -1); 658 break; 659 } 660 } 661 662 /* 663 * px_err_handle: 664 * Common function called by trap, mondo and fabric intr. 665 * o Snap shot current fire registers 666 * o check for safe access 667 * o send ereport and clear snap shot registers 668 * o check severity of snap shot registers 669 * 670 * @param px_p leaf in which to check access 671 * @param derr fm err data structure to be updated 672 * @param caller PX_TRAP_CALL | PX_INTR_CALL 673 * @param chkjbc whether to handle jbc registers 674 * @return err PX_OK | PX_NONFATAL | 675 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 676 */ 677 int 678 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 679 boolean_t chkjbc) 680 { 681 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 682 px_err_ss_t ss; 683 int err; 684 685 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 686 687 /* snap shot the current fire registers */ 688 px_err_snapshot(px_p, &ss, chkjbc); 689 690 /* check for safe access */ 691 px_err_safeacc_check(px_p, derr); 692 693 /* send ereports/handle/clear registers */ 694 err = px_err_erpt_and_clr(px_p, derr, &ss); 695 696 /* check for error severity */ 697 err = px_err_check_severity(px_p, derr, err, caller); 698 699 /* Mark the On Trap Handle if an error occured */ 700 if (err != PX_OK) { 701 px_pec_t *pec_p = px_p->px_pec_p; 702 on_trap_data_t *otd = pec_p->pec_ontrap_data; 703 704 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) { 705 otd->ot_trap |= OT_DATA_ACCESS; 706 } 707 } 708 709 return (err); 710 } 711 712 /* 713 * Static function 714 */ 715 716 /* 717 * px_err_snapshot: 718 * Take a current snap shot of all the fire error registers. This includes 719 * JBC, DMC, and PEC, unless chkjbc == false; 720 * 721 * @param px_p leaf in which to take the snap shot. 722 * @param ss pre-allocated memory to store the snap shot. 723 * @param chkjbc boolean on whether to store jbc register. 724 */ 725 static void 726 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc) 727 { 728 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 729 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 730 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 731 px_err_reg_desc_t *reg_desc; 732 int reg_id; 733 734 /* snapshot JBC interrupt status */ 735 reg_id = PX_ERR_JBC; 736 if (chkjbc == B_TRUE) { 737 reg_desc = &px_err_reg_tbl[reg_id]; 738 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 739 reg_desc->status_addr); 740 } else { 741 ss->err_status[reg_id] = 0; 742 } 743 744 /* snapshot DMC/PEC interrupt status */ 745 for (reg_id = 1; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 746 reg_desc = &px_err_reg_tbl[reg_id]; 747 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 748 reg_desc->status_addr); 749 } 750 } 751 752 /* 753 * px_err_erpt_and_clr: 754 * This function does the following thing to all the fire registers based 755 * on an earlier snap shot. 756 * o Send ereport 757 * o Handle the error 758 * o Clear the error 759 * 760 * @param px_p leaf in which to take the snap shot. 761 * @param derr fm err in which the ereport is to be based on 762 * @param ss pre-allocated memory to store the snap shot. 763 */ 764 static int 765 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 766 { 767 dev_info_t *rpdip = px_p->px_dip; 768 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 769 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 770 caddr_t csr_base; 771 px_err_reg_desc_t *err_reg_tbl; 772 px_err_bit_desc_t *err_bit_tbl; 773 px_err_bit_desc_t *err_bit_desc; 774 775 uint64_t *log_mask, *count_mask; 776 uint64_t status_addr, clear_addr; 777 uint64_t ss_reg; 778 779 int (*err_handler)(); 780 int (*erpt_handler)(); 781 int reg_id, key; 782 int err = PX_OK; 783 784 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 785 786 /* send erport/handle/clear JBC errors */ 787 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 788 /* Get the correct register description table */ 789 err_reg_tbl = &px_err_reg_tbl[reg_id]; 790 791 /* Get the correct CSR BASE */ 792 if (reg_id == PX_ERR_JBC) { 793 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 794 } else { 795 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 796 } 797 798 /* Get pointers to masks and register addresses */ 799 log_mask = err_reg_tbl->log_mask_p; 800 count_mask = err_reg_tbl->count_mask_p; 801 status_addr = err_reg_tbl->status_addr; 802 clear_addr = err_reg_tbl->clear_addr; 803 ss_reg = ss->err_status[reg_id]; 804 805 /* Get the register BIT description table */ 806 err_bit_tbl = err_reg_tbl->err_bit_tbl; 807 808 /* For each known bit in the register send erpt and handle */ 809 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 810 /* Get the bit description table for this register */ 811 err_bit_desc = &err_bit_tbl[key]; 812 813 /* 814 * If the ss_reg is set for this bit, 815 * send ereport and handle 816 */ 817 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 818 /* Increment the counter if necessary */ 819 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 820 err_bit_desc->counter++; 821 } 822 823 /* Error Handle for this bit */ 824 err_handler = err_bit_desc->err_handler; 825 if (err_handler) 826 err |= err_handler(rpdip, 827 csr_base, 828 derr, 829 err_reg_tbl, 830 err_bit_desc); 831 832 /* Send the ereport for this bit */ 833 erpt_handler = err_bit_desc->erpt_handler; 834 if (erpt_handler) 835 (void) erpt_handler(rpdip, 836 csr_base, 837 ss_reg, 838 derr, 839 err_bit_desc->class_name); 840 } 841 } 842 /* Log register status */ 843 if ((px_err_log_all) || (ss_reg & *log_mask)) 844 LOG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 845 status_addr, ss_reg, err_reg_tbl->msg); 846 847 /* Clear the register and error */ 848 CSR_XS(csr_base, clear_addr, ss_reg); 849 } 850 851 return (err); 852 } 853 854 /* 855 * px_err_check_severity: 856 * Check the severity of the fire error based on an earlier snapshot 857 * 858 * @param px_p leaf in which to take the snap shot. 859 * @param derr fm err in which the ereport is to be based on 860 * @param ss pre-allocated memory to store the snap shot. 861 */ 862 static int 863 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 864 { 865 px_pec_t *pec_p = px_p->px_pec_p; 866 boolean_t is_safeacc = B_FALSE; 867 int ret = err; 868 869 /* Cautious access error handling */ 870 switch (derr->fme_flag) { 871 case DDI_FM_ERR_EXPECTED: 872 if (caller == PX_TRAP_CALL) { 873 /* 874 * for ddi_caut_get treat all events as nonfatal 875 * The trampoline will set err_ena = 0, 876 * err_status = NONFATAL. 877 */ 878 derr->fme_status = DDI_FM_NONFATAL; 879 is_safeacc = B_TRUE; 880 } else { 881 /* 882 * For ddi_caut_put treat all events as nonfatal. Here 883 * we have the handle and can call ndi_fm_acc_err_set(). 884 */ 885 derr->fme_status = DDI_FM_NONFATAL; 886 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 887 is_safeacc = B_TRUE; 888 } 889 break; 890 case DDI_FM_ERR_PEEK: 891 case DDI_FM_ERR_POKE: 892 /* 893 * For ddi_peek/poke treat all events as nonfatal. 894 */ 895 is_safeacc = B_TRUE; 896 break; 897 default: 898 is_safeacc = B_FALSE; 899 } 900 901 /* 902 * The third argument "err" is passed in as error status from checking 903 * Fire register, re-adjust error status from safe access. 904 */ 905 if (is_safeacc && !(err & PX_FATAL_GOS)) 906 ret = PX_NONFATAL; 907 908 if (err & PX_FATAL_GOS) 909 ret = PX_FATAL_GOS; 910 else if (err & (PX_STUCK_FATAL | PX_FATAL_SW)) 911 err &= (PX_STUCK_FATAL | PX_FATAL_SW); 912 else if (err & (PX_NONFATAL | PX_FATAL_HW)) 913 ret = PX_NONFATAL; 914 else 915 ret = PX_OK; 916 917 return (ret); 918 } 919 920 /* predefined convenience functions */ 921 /* ARGSUSED */ 922 int 923 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 924 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 925 px_err_bit_desc_t *err_bit_descr) 926 { 927 return (PX_FATAL_HW); 928 } 929 930 /* ARGSUSED */ 931 int 932 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 933 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 934 px_err_bit_desc_t *err_bit_descr) 935 { 936 return (PX_FATAL_GOS); 937 } 938 939 /* ARGSUSED */ 940 int 941 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 942 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 943 px_err_bit_desc_t *err_bit_descr) 944 { 945 return (PX_STUCK_FATAL); 946 } 947 948 /* ARGSUSED */ 949 int 950 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 951 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 952 px_err_bit_desc_t *err_bit_descr) 953 { 954 return (PX_FATAL_SW); 955 } 956 957 /* ARGSUSED */ 958 int 959 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 960 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 961 px_err_bit_desc_t *err_bit_descr) 962 { 963 return (PX_NONFATAL); 964 } 965 966 /* ARGSUSED */ 967 int 968 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 969 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 970 { 971 return (PX_OK); 972 } 973 974 /* ARGSUSED */ 975 int 976 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 977 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 978 { 979 return (PX_ERR_UNKNOWN); 980 } 981 982 /* JBC FATAL - see io erpt doc, section 1.1 */ 983 PX_ERPT_SEND_DEC(jbc_fatal) 984 { 985 char buf[FM_MAX_CLASS]; 986 987 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 988 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 989 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 990 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 991 FIRE_JBC_ELE, DATA_TYPE_UINT64, 992 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 993 FIRE_JBC_IE, DATA_TYPE_UINT64, 994 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 995 FIRE_JBC_IS, DATA_TYPE_UINT64, 996 ss_reg, 997 FIRE_JBC_ESS, DATA_TYPE_UINT64, 998 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 999 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1000 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1001 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1002 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1003 NULL); 1004 1005 return (PX_OK); 1006 } 1007 1008 /* JBC MERGE - see io erpt doc, section 1.2 */ 1009 PX_ERPT_SEND_DEC(jbc_merge) 1010 { 1011 char buf[FM_MAX_CLASS]; 1012 1013 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1014 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1015 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1016 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1017 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1018 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1019 FIRE_JBC_IE, DATA_TYPE_UINT64, 1020 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1021 FIRE_JBC_IS, DATA_TYPE_UINT64, 1022 ss_reg, 1023 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1024 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1025 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1026 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1027 NULL); 1028 1029 return (PX_OK); 1030 } 1031 1032 /* 1033 * JBC Merge buffer nonfatal errors: 1034 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1035 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1036 */ 1037 /* ARGSUSED */ 1038 int 1039 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1040 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1041 px_err_bit_desc_t *err_bit_descr) 1042 { 1043 uint64_t paddr; 1044 int ret; 1045 1046 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1047 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1048 1049 ret = px_handle_lookup( 1050 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1051 1052 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1053 } 1054 1055 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1056 PX_ERPT_SEND_DEC(jbc_in) 1057 { 1058 char buf[FM_MAX_CLASS]; 1059 1060 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1061 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1062 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1063 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1064 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1065 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1066 FIRE_JBC_IE, DATA_TYPE_UINT64, 1067 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1068 FIRE_JBC_IS, DATA_TYPE_UINT64, 1069 ss_reg, 1070 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1071 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1072 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1073 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1074 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1075 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1076 NULL); 1077 1078 return (PX_OK); 1079 } 1080 1081 /* 1082 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1083 * Log Reg[42:0]. 1084 * CE async fault error: nonfatal 1085 * Jbus bus error: dma::nonfatal 1086 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1087 * Write data parity error: pio/write:M:nonfatal 1088 * Read data parity error: pio/read:M:nonfatal 1089 * Illegal NCWR bytemask: pio:write:M:nonfatal 1090 * Illegal NCRD bytemask: pio:write:M:nonfatal 1091 * Invalid jbus transaction: nonfatal 1092 */ 1093 /* ARGSUSED */ 1094 int 1095 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1096 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1097 px_err_bit_desc_t *err_bit_descr) 1098 { 1099 uint64_t paddr; 1100 int ret; 1101 1102 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1103 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1104 1105 ret = px_handle_lookup( 1106 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1107 1108 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1109 } 1110 1111 1112 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1113 PX_ERPT_SEND_DEC(jbc_out) 1114 { 1115 char buf[FM_MAX_CLASS]; 1116 1117 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1118 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1119 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1120 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1121 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1122 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1123 FIRE_JBC_IE, DATA_TYPE_UINT64, 1124 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1125 FIRE_JBC_IS, DATA_TYPE_UINT64, 1126 ss_reg, 1127 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1128 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1129 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1130 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1131 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1132 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1133 NULL); 1134 1135 return (PX_OK); 1136 } 1137 1138 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1139 PX_ERPT_SEND_DEC(jbc_odcd) 1140 { 1141 char buf[FM_MAX_CLASS]; 1142 1143 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1144 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1145 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1146 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1147 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1148 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1149 FIRE_JBC_IE, DATA_TYPE_UINT64, 1150 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1151 FIRE_JBC_IS, DATA_TYPE_UINT64, 1152 ss_reg, 1153 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1154 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1155 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1156 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1157 NULL); 1158 1159 return (PX_OK); 1160 } 1161 1162 /* 1163 * JBC Dmcint ODCO nonfatal errer handling - 1164 * Unmapped PIO read error: pio:read:M:nonfatal 1165 * Unmapped PIO write error: pio:write:M:nonfatal 1166 * PIO data parity error: pio:write:M:nonfatal 1167 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1168 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1169 */ 1170 /* ARGSUSED */ 1171 int 1172 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1173 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1174 px_err_bit_desc_t *err_bit_descr) 1175 { 1176 uint64_t paddr; 1177 int ret; 1178 1179 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1180 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1181 1182 ret = px_handle_lookup( 1183 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1184 1185 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1186 } 1187 1188 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1189 PX_ERPT_SEND_DEC(jbc_idc) 1190 { 1191 char buf[FM_MAX_CLASS]; 1192 1193 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1194 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1195 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1196 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1197 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1198 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1199 FIRE_JBC_IE, DATA_TYPE_UINT64, 1200 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1201 FIRE_JBC_IS, DATA_TYPE_UINT64, 1202 ss_reg, 1203 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1204 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1205 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1206 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1207 NULL); 1208 1209 return (PX_OK); 1210 } 1211 1212 /* JBC CSR - see io erpt doc, section 1.7 */ 1213 PX_ERPT_SEND_DEC(jbc_csr) 1214 { 1215 char buf[FM_MAX_CLASS]; 1216 1217 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1218 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1219 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1220 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1221 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1222 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1223 FIRE_JBC_IE, DATA_TYPE_UINT64, 1224 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1225 FIRE_JBC_IS, DATA_TYPE_UINT64, 1226 ss_reg, 1227 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1228 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1229 "jbc-error-reg", DATA_TYPE_UINT64, 1230 CSR_XR(csr_base, CSR_ERROR_LOG), 1231 NULL); 1232 1233 return (PX_OK); 1234 } 1235 1236 /* 1237 * JBC CSR errer handling - 1238 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1239 */ 1240 /* ARGSUSED */ 1241 int 1242 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1243 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1244 px_err_bit_desc_t *err_bit_descr) 1245 { 1246 uint64_t paddr; 1247 int ret; 1248 1249 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1250 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1251 1252 ret = px_handle_lookup( 1253 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1254 1255 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1256 } 1257 1258 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1259 1260 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1261 PX_ERPT_SEND_DEC(imu_rds) 1262 { 1263 char buf[FM_MAX_CLASS]; 1264 1265 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1266 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1267 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1268 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1269 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1270 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1271 FIRE_IMU_IE, DATA_TYPE_UINT64, 1272 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1273 FIRE_IMU_IS, DATA_TYPE_UINT64, 1274 ss_reg, 1275 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1276 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1277 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1278 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1279 NULL); 1280 1281 return (PX_OK); 1282 } 1283 1284 /* imu function to handle all Received but Not Enabled errors */ 1285 /* ARGSUSED */ 1286 int 1287 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1288 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1289 px_err_bit_desc_t *err_bit_descr) 1290 { 1291 uint64_t imu_log_enable, imu_intr_enable; 1292 int mask = BITMASK(err_bit_descr->bit); 1293 int err = PX_NONFATAL; 1294 1295 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1296 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1297 1298 if (imu_log_enable & imu_intr_enable & mask) { 1299 err = PX_FATAL_SW; 1300 } else { 1301 /* 1302 * S/W bug - this error should always be enabled 1303 */ 1304 1305 /* enable error & intr reporting for this bit */ 1306 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, imu_log_enable | mask); 1307 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, imu_intr_enable | mask); 1308 err = PX_NONFATAL; 1309 } 1310 1311 return (err); 1312 } 1313 1314 /* handle EQ overflow */ 1315 /* ARGSUSED */ 1316 int 1317 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1318 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1319 px_err_bit_desc_t *err_bit_descr) 1320 { 1321 px_t *px_p = DIP_TO_STATE(rpdip); 1322 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1323 msiqid_t eqno; 1324 pci_msiq_state_t msiq_state; 1325 int err = PX_NONFATAL; 1326 int i; 1327 1328 eqno = msiq_state_p->msiq_1st_msiq_id; 1329 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1330 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1331 DDI_SUCCESS) { 1332 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1333 err = PX_FATAL_SW; 1334 } 1335 } 1336 } 1337 1338 return (err); 1339 } 1340 1341 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1342 PX_ERPT_SEND_DEC(imu_scs) 1343 { 1344 char buf[FM_MAX_CLASS]; 1345 1346 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1347 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1348 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1349 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1350 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1351 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1352 FIRE_IMU_IE, DATA_TYPE_UINT64, 1353 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1354 FIRE_IMU_IS, DATA_TYPE_UINT64, 1355 ss_reg, 1356 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1357 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1358 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1359 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1360 NULL); 1361 1362 return (PX_OK); 1363 } 1364 1365 /* DMC IMU - see io erpt doc, section 2.3 */ 1366 PX_ERPT_SEND_DEC(imu) 1367 { 1368 char buf[FM_MAX_CLASS]; 1369 1370 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1371 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1372 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1373 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1374 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1375 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1376 FIRE_IMU_IE, DATA_TYPE_UINT64, 1377 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1378 FIRE_IMU_IS, DATA_TYPE_UINT64, 1379 ss_reg, 1380 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1381 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1382 NULL); 1383 1384 return (PX_OK); 1385 } 1386 1387 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1388 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1389 { 1390 char buf[FM_MAX_CLASS]; 1391 1392 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1393 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1394 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1395 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1396 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1397 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1398 FIRE_MMU_IE, DATA_TYPE_UINT64, 1399 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1400 FIRE_MMU_IS, DATA_TYPE_UINT64, 1401 ss_reg, 1402 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1403 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1404 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1405 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1406 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1407 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1408 NULL); 1409 1410 return (PX_OK); 1411 } 1412 1413 /* DMC MMU - see io erpt doc, section 2.5 */ 1414 PX_ERPT_SEND_DEC(mmu) 1415 { 1416 char buf[FM_MAX_CLASS]; 1417 1418 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1419 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1420 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1421 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1422 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1423 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1424 FIRE_MMU_IE, DATA_TYPE_UINT64, 1425 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1426 FIRE_MMU_IS, DATA_TYPE_UINT64, 1427 ss_reg, 1428 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1429 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1430 NULL); 1431 1432 return (PX_OK); 1433 } 1434 1435 /* imu function to handle all Received but Not Enabled errors */ 1436 int 1437 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1438 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1439 px_err_bit_desc_t *err_bit_descr) 1440 { 1441 uint64_t mmu_log_enable, mmu_intr_enable, mmu_tfa; 1442 uint64_t mask = BITMASK(err_bit_descr->bit); 1443 int err = PX_NONFATAL; 1444 int ret; 1445 1446 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1447 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1448 1449 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1450 1451 if (mmu_log_enable & mmu_intr_enable & mask) { 1452 err = PX_FATAL_SW; 1453 } else { 1454 ret = px_handle_lookup( 1455 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1456 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1457 1458 /* 1459 * S/W bug - this error should always be enabled 1460 */ 1461 1462 /* enable error & intr reporting for this bit */ 1463 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1464 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1465 } 1466 1467 return (err); 1468 } 1469 1470 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1471 /* ARGSUSED */ 1472 int 1473 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1474 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1475 px_err_bit_desc_t *err_bit_descr) 1476 { 1477 uint64_t mmu_tfa; 1478 uint_t ret; 1479 1480 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1481 ret = px_handle_lookup( 1482 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1483 1484 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1485 } 1486 1487 /* MMU Table walk errors */ 1488 /* ARGSUSED */ 1489 int 1490 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1491 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1492 px_err_bit_desc_t *err_bit_descr) 1493 { 1494 uint64_t mmu_tfa; 1495 uint_t ret; 1496 1497 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1498 ret = px_handle_lookup( 1499 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1500 1501 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1502 } 1503 1504 /* PEC ILU none - see io erpt doc, section 3.1 */ 1505 PX_ERPT_SEND_DEC(pec_ilu) 1506 { 1507 char buf[FM_MAX_CLASS]; 1508 1509 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1510 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1511 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1512 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1513 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1514 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1515 FIRE_ILU_IE, DATA_TYPE_UINT64, 1516 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1517 FIRE_ILU_IS, DATA_TYPE_UINT64, 1518 ss_reg, 1519 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1520 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1521 NULL); 1522 1523 return (PX_OK); 1524 } 1525 1526 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 1527 PX_ERPT_SEND_DEC(pciex_ce) 1528 { 1529 char buf[FM_MAX_CLASS]; 1530 1531 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1532 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1533 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1534 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1535 FIRE_TLU_CELE, DATA_TYPE_UINT64, 1536 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 1537 FIRE_TLU_CIE, DATA_TYPE_UINT64, 1538 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 1539 FIRE_TLU_CIS, DATA_TYPE_UINT64, 1540 ss_reg, 1541 FIRE_TLU_CESS, DATA_TYPE_UINT64, 1542 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 1543 NULL); 1544 1545 return (PX_OK); 1546 } 1547 1548 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 1549 PX_ERPT_SEND_DEC(pciex_rx_oe) 1550 { 1551 char buf[FM_MAX_CLASS]; 1552 1553 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1554 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1555 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1556 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1557 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1558 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1559 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1560 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1561 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1562 ss_reg, 1563 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1564 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1565 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1566 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1567 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1568 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1569 NULL); 1570 1571 return (PX_OK); 1572 } 1573 1574 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 1575 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 1576 { 1577 char buf[FM_MAX_CLASS]; 1578 1579 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1580 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1581 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1582 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1583 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1584 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1585 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1586 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1587 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1588 ss_reg, 1589 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1590 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1591 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 1592 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1593 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 1594 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1595 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 1596 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 1597 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 1598 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 1599 NULL); 1600 1601 return (PX_OK); 1602 } 1603 1604 /* TLU Other Event - see io erpt doc, section 3.9 */ 1605 PX_ERPT_SEND_DEC(pciex_oe) 1606 { 1607 char buf[FM_MAX_CLASS]; 1608 1609 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1610 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1611 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1612 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1613 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1614 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1615 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1616 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1617 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1618 ss_reg, 1619 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1620 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1621 NULL); 1622 1623 return (PX_OK); 1624 } 1625