xref: /titanic_51/usr/src/uts/intel/io/pci/pci_boot.c (revision 7f79af0b29c00a006403444f61b261219f63cfbf)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #include <sys/types.h>
27 #include <sys/stat.h>
28 #include <sys/sunndi.h>
29 #include <sys/pci.h>
30 #include <sys/pci_impl.h>
31 #include <sys/pci_cfgspace.h>
32 #include <sys/memlist.h>
33 #include <sys/bootconf.h>
34 #include <io/pci/mps_table.h>
35 #include <sys/pci_cfgspace.h>
36 #include <sys/pci_cfgspace_impl.h>
37 #include <sys/psw.h>
38 #include "../../../../common/pci/pci_strings.h"
39 #include <sys/apic.h>
40 #include <io/pciex/pcie_nvidia.h>
41 #include <io/hotplug/pciehpc/pciehpc_acpi.h>
42 #include <sys/acpi/acpi.h>
43 #include <sys/acpica.h>
44 #include <sys/intel_iommu.h>
45 
46 #define	pci_getb	(*pci_getb_func)
47 #define	pci_getw	(*pci_getw_func)
48 #define	pci_getl	(*pci_getl_func)
49 #define	pci_putb	(*pci_putb_func)
50 #define	pci_putw	(*pci_putw_func)
51 #define	pci_putl	(*pci_putl_func)
52 #define	dcmn_err	if (pci_boot_debug) cmn_err
53 
54 #define	CONFIG_INFO	0
55 #define	CONFIG_UPDATE	1
56 #define	CONFIG_NEW	2
57 #define	CONFIG_FIX	3
58 #define	COMPAT_BUFSIZE	512
59 
60 #define	PPB_IO_ALIGNMENT	0x1000		/* 4K aligned */
61 #define	PPB_MEM_ALIGNMENT	0x100000	/* 1M aligned */
62 
63 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */
64 #define	LPC_IO_CONTROL_REG_1	0x40
65 #define	AMD8111_ENABLENMI	(uint8_t)0x80
66 #define	DEVID_AMD8111_LPC	0x7468
67 
68 struct pci_fixundo {
69 	uint8_t			bus;
70 	uint8_t			dev;
71 	uint8_t			fn;
72 	void			(*undofn)(uint8_t, uint8_t, uint8_t);
73 	struct pci_fixundo	*next;
74 };
75 
76 struct pci_devfunc {
77 	struct pci_devfunc *next;
78 	dev_info_t *dip;
79 	uchar_t dev;
80 	uchar_t func;
81 	boolean_t reprogram;	/* this device needs to be reprogrammed */
82 };
83 
84 extern int pci_bios_nbus;
85 static uchar_t max_dev_pci = 32;	/* PCI standard */
86 int pci_boot_debug = 0;
87 extern struct memlist *find_bus_res(int, int);
88 static struct pci_fixundo *undolist = NULL;
89 static int num_root_bus = 0;	/* count of root buses */
90 
91 /*
92  * Module prototypes
93  */
94 static void enumerate_bus_devs(uchar_t bus, int config_op);
95 static void create_root_bus_dip(uchar_t bus);
96 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t,
97     ushort_t, int);
98 static void add_compatible(dev_info_t *, ushort_t, ushort_t,
99     ushort_t, ushort_t, uchar_t, uint_t, int);
100 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int);
101 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int,
102     ushort_t);
103 static void add_model_prop(dev_info_t *, uint_t);
104 static void add_bus_range_prop(int);
105 static void add_bus_slot_names_prop(int);
106 static void add_ppb_ranges_prop(int);
107 static void add_bus_available_prop(int);
108 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id);
109 static void fix_ppb_res(uchar_t, boolean_t);
110 static void alloc_res_array();
111 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
112     ushort_t deviceid);
113 static void pciex_slot_names_prop(dev_info_t *, ushort_t);
114 
115 extern int pci_slot_names_prop(int, char *, int);
116 
117 /* set non-zero to force PCI peer-bus renumbering */
118 int pci_bus_always_renumber = 0;
119 
120 /* get the subordinate bus # for a root/peer bus */
121 static int
122 pci_root_subbus(int bus, uchar_t *subbus)
123 {
124 	ACPI_HANDLE	hdl;
125 	ACPI_BUFFER	rb;
126 	ACPI_RESOURCE	*rp;
127 	int	rv;
128 
129 	if (pci_bus_res[bus].dip == NULL) {
130 		/* non-used bus # */
131 		return (AE_ERROR);
132 	}
133 	if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) {
134 		cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus);
135 		return (AE_ERROR);
136 	}
137 
138 	rb.Length = ACPI_ALLOCATE_BUFFER;
139 	if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) {
140 		cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus);
141 		return (AE_ERROR);
142 	}
143 
144 	rv = AE_ERROR;
145 
146 	for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG;
147 	    rp = ACPI_NEXT_RESOURCE(rp)) {
148 
149 		switch (rp->Type) {
150 		case ACPI_RESOURCE_TYPE_ADDRESS16:
151 			if (rp->Data.Address.ResourceType !=
152 			    ACPI_BUS_NUMBER_RANGE)
153 				continue;
154 			*subbus = (uchar_t)rp->Data.Address16.Maximum;
155 			dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus);
156 			break;
157 		case ACPI_RESOURCE_TYPE_ADDRESS32:
158 			if (rp->Data.Address.ResourceType !=
159 			    ACPI_BUS_NUMBER_RANGE)
160 				continue;
161 			*subbus = (uchar_t)rp->Data.Address32.Maximum;
162 			dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus);
163 			break;
164 		case ACPI_RESOURCE_TYPE_ADDRESS64:
165 			if (rp->Data.Address.ResourceType !=
166 			    ACPI_BUS_NUMBER_RANGE)
167 				continue;
168 			*subbus = (uchar_t)rp->Data.Address64.Maximum;
169 			dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus);
170 			break;
171 		case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64:
172 			if (rp->Data.Address.ResourceType !=
173 			    ACPI_BUS_NUMBER_RANGE)
174 				continue;
175 			*subbus = (uchar_t)rp->Data.ExtAddress64.Maximum;
176 			dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus);
177 			break;
178 		default:
179 			dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type);
180 			continue;
181 		}
182 
183 		/* found the bus-range resource */
184 		dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus);
185 		rv = AE_OK;
186 
187 		/* This breaks out of the resource scanning loop */
188 		break;
189 	}
190 
191 	AcpiOsFree(rb.Pointer);
192 	if (rv != AE_OK)
193 		cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus);
194 
195 	return (rv);
196 
197 }
198 
199 /*
200  * Enumerate all PCI devices
201  */
202 void
203 pci_setup_tree()
204 {
205 	uchar_t i, root_bus_addr = 0;
206 
207 	alloc_res_array();
208 	for (i = 0; i <= pci_bios_nbus; i++) {
209 		pci_bus_res[i].par_bus = (uchar_t)-1;
210 		pci_bus_res[i].root_addr = (uchar_t)-1;
211 		pci_bus_res[i].sub_bus = i;
212 	}
213 
214 	pci_bus_res[0].root_addr = root_bus_addr++;
215 	create_root_bus_dip(0);
216 	enumerate_bus_devs(0, CONFIG_INFO);
217 
218 	/*
219 	 * Now enumerate peer busses
220 	 *
221 	 * We loop till pci_bios_nbus. On most systems, there is
222 	 * one more bus at the high end, which implements the ISA
223 	 * compatibility bus. We don't care about that.
224 	 *
225 	 * Note: In the old (bootconf) enumeration, the peer bus
226 	 *	address did not use the bus number, and there were
227 	 *	too many peer busses created. The root_bus_addr is
228 	 *	used to maintain the old peer bus address assignment.
229 	 *	However, we stop enumerating phantom peers with no
230 	 *	device below.
231 	 */
232 	for (i = 1; i <= pci_bios_nbus; i++) {
233 		if (pci_bus_res[i].dip == NULL) {
234 			pci_bus_res[i].root_addr = root_bus_addr++;
235 		}
236 		enumerate_bus_devs(i, CONFIG_INFO);
237 
238 		/* add slot-names property for named pci hot-plug slots */
239 		add_bus_slot_names_prop(i);
240 	}
241 
242 }
243 
244 /*
245  * >0 = present, 0 = not present, <0 = error
246  */
247 static int
248 pci_bbn_present(int bus)
249 {
250 	ACPI_HANDLE	hdl;
251 	int	rv;
252 
253 	/* no dip means no _BBN */
254 	if (pci_bus_res[bus].dip == NULL)
255 		return (0);
256 
257 	rv = -1;	/* default return value in case of error below */
258 	if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) {
259 		switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) {
260 		case AE_OK:
261 			rv = 1;
262 			break;
263 		case AE_NOT_FOUND:
264 			rv = 0;
265 			break;
266 		default:
267 			break;
268 		}
269 	}
270 
271 	return (rv);
272 }
273 
274 /*
275  * Return non-zero if any PCI bus in the system has an associated
276  * _BBN object, 0 otherwise.
277  */
278 static int
279 pci_roots_have_bbn(void)
280 {
281 	int	i;
282 
283 	/*
284 	 * Scan the PCI busses and look for at least 1 _BBN
285 	 */
286 	for (i = 0; i <= pci_bios_nbus; i++) {
287 		/* skip non-root (peer) PCI busses */
288 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
289 			continue;
290 
291 		if (pci_bbn_present(i) > 0)
292 			return (1);
293 	}
294 	return (0);
295 
296 }
297 
298 /*
299  * return non-zero if the machine is one on which we renumber
300  * the internal pci unit-addresses
301  */
302 static int
303 pci_bus_renumber()
304 {
305 	ACPI_TABLE_HEADER *fadt;
306 
307 	if (pci_bus_always_renumber)
308 		return (1);
309 
310 	/* get the FADT */
311 	if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) !=
312 	    AE_OK)
313 		return (0);
314 
315 	/* compare OEM Table ID to "SUNm31" */
316 	if (strncmp("SUNm31", fadt->OemId, 6))
317 		return (0);
318 	else
319 		return (1);
320 }
321 
322 /*
323  * Initial enumeration of the physical PCI bus hierarchy can
324  * leave 'gaps' in the order of peer PCI bus unit-addresses.
325  * Systems with more than one peer PCI bus *must* have an ACPI
326  * _BBN object associated with each peer bus; use the presence
327  * of this object to remove gaps in the numbering of the peer
328  * PCI bus unit-addresses - only peer busses with an associated
329  * _BBN are counted.
330  */
331 static void
332 pci_renumber_root_busses(void)
333 {
334 	int pci_regs[] = {0, 0, 0};
335 	int	i, root_addr = 0;
336 
337 	/*
338 	 * Currently, we only enable the re-numbering on specific
339 	 * Sun machines; this is a work-around for the more complicated
340 	 * issue of upgrade changing physical device paths
341 	 */
342 	if (!pci_bus_renumber())
343 		return;
344 
345 	/*
346 	 * If we find no _BBN objects at all, we either don't need
347 	 * to do anything or can't do anything anyway
348 	 */
349 	if (!pci_roots_have_bbn())
350 		return;
351 
352 	for (i = 0; i <= pci_bios_nbus; i++) {
353 		/* skip non-root (peer) PCI busses */
354 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
355 			continue;
356 
357 		if (pci_bbn_present(i) < 1) {
358 			pci_bus_res[i].root_addr = (uchar_t)-1;
359 			continue;
360 		}
361 
362 		ASSERT(pci_bus_res[i].dip != NULL);
363 		if (pci_bus_res[i].root_addr != root_addr) {
364 			/* update reg property for node */
365 			pci_bus_res[i].root_addr = root_addr;
366 			pci_regs[0] = pci_bus_res[i].root_addr;
367 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
368 			    pci_bus_res[i].dip, "reg", (int *)pci_regs, 3);
369 		}
370 		root_addr++;
371 	}
372 }
373 
374 static void
375 remove_resource_range(struct memlist **list, int *ranges, int range_count)
376 {
377 	struct range {
378 		uint32_t base;
379 		uint32_t len;
380 	};
381 	int index;
382 
383 	for (index = 0; index < range_count; index++) {
384 		/* all done if list is or has become empty */
385 		if (*list == NULL)
386 			break;
387 		(void) memlist_remove(list,
388 		    (uint64_t)((struct range *)ranges)[index].base,
389 		    (uint64_t)((struct range *)ranges)[index].len);
390 	}
391 }
392 
393 static void
394 remove_used_resources()
395 {
396 	dev_info_t *used;
397 	int	*narray;
398 	uint_t	ncount;
399 	int	status;
400 	int	bus;
401 
402 	used = ddi_find_devinfo("used-resources", -1, 0);
403 	if (used == NULL)
404 		return;
405 
406 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
407 	    DDI_PROP_DONTPASS, "io-space", &narray, &ncount);
408 	if (status == DDI_PROP_SUCCESS) {
409 		for (bus = 0; bus <= pci_bios_nbus; bus++)
410 			remove_resource_range(&pci_bus_res[bus].io_ports,
411 			    narray, ncount / 2);
412 		ddi_prop_free(narray);
413 	}
414 
415 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
416 	    DDI_PROP_DONTPASS, "device-memory", &narray, &ncount);
417 	if (status == DDI_PROP_SUCCESS) {
418 		for (bus = 0; bus <= pci_bios_nbus; bus++)
419 			remove_resource_range(&pci_bus_res[bus].mem_space,
420 			    narray, ncount / 2);
421 		ddi_prop_free(narray);
422 	}
423 }
424 
425 /*
426  * Remove the resources which are already used by devices under a subtractive
427  * bridge from the bus's resources lists, because they're not available, and
428  * shouldn't be allocated to other buses.  This is necessary because tracking
429  * resources for subtractive bridges is not complete.  (Subtractive bridges only
430  * track some of their claimed resources, not "the rest of the address space" as
431  * they should, so that allocation to peer non-subtractive PPBs is easier.  We
432  * need a fully-capable global resource allocator).
433  */
434 static void
435 remove_subtractive_res()
436 {
437 	int i, j;
438 	struct memlist *list;
439 
440 	for (i = 0; i <= pci_bios_nbus; i++) {
441 		if (pci_bus_res[i].subtractive) {
442 			/* remove used io ports */
443 			list = pci_bus_res[i].io_ports_used;
444 			while (list) {
445 				for (j = 0; j <= pci_bios_nbus; j++) {
446 					if (pci_bus_res[j].io_ports)
447 						(void) memlist_remove(
448 						    &pci_bus_res[j].io_ports,
449 						    list->address, list->size);
450 				}
451 				list = list->next;
452 			}
453 			/* remove used mem resource */
454 			list = pci_bus_res[i].mem_space_used;
455 			while (list) {
456 				for (j = 0; j <= pci_bios_nbus; j++) {
457 					if (pci_bus_res[j].mem_space)
458 						(void) memlist_remove(
459 						    &pci_bus_res[j].mem_space,
460 						    list->address, list->size);
461 					if (pci_bus_res[j].pmem_space)
462 						(void) memlist_remove(
463 						    &pci_bus_res[j].pmem_space,
464 						    list->address, list->size);
465 				}
466 				list = list->next;
467 			}
468 			/* remove used prefetchable mem resource */
469 			list = pci_bus_res[i].pmem_space_used;
470 			while (list) {
471 				for (j = 0; j <= pci_bios_nbus; j++) {
472 					if (pci_bus_res[j].pmem_space)
473 						(void) memlist_remove(
474 						    &pci_bus_res[j].pmem_space,
475 						    list->address, list->size);
476 					if (pci_bus_res[j].mem_space)
477 						(void) memlist_remove(
478 						    &pci_bus_res[j].mem_space,
479 						    list->address, list->size);
480 				}
481 				list = list->next;
482 			}
483 		}
484 	}
485 }
486 
487 /* Set up this bus's "bus_space" resource list */
488 static void
489 setup_bus_res(int bus)
490 {
491 	uchar_t par_bus;
492 	uchar_t sub_bus;
493 
494 	if (pci_bus_res[bus].dip == NULL)	/* unused bus */
495 		return;
496 
497 	sub_bus = pci_bus_res[bus].sub_bus;
498 	ASSERT(sub_bus >= bus);
499 	ASSERT(pci_bus_res[bus].bus_space == NULL);
500 	if (sub_bus > bus) {
501 		/*
502 		 * Keep the remaining available bus range in bus_space.
503 		 * ('bus' is already allocated)
504 		 */
505 		memlist_insert(&pci_bus_res[bus].bus_space, bus + 1,
506 		    sub_bus - bus);
507 	}
508 
509 	/*
510 	 * Remove resources from parent bus node if this is not a
511 	 * root bus.
512 	 */
513 	par_bus = pci_bus_res[bus].par_bus;
514 	if (par_bus != (uchar_t)-1) {
515 		ASSERT(pci_bus_res[par_bus].bus_space != NULL);
516 		(void) memlist_remove(&pci_bus_res[par_bus].bus_space,
517 		    bus, sub_bus - bus + 1);
518 	}
519 }
520 
521 static uint64_t
522 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
523 {
524 	uint64_t addr = 0;
525 	uchar_t res_bus;
526 
527 	/*
528 	 * Skip root(peer) buses in multiple-root-bus systems, as currently
529 	 * the initial resources set on each root bus might not be correctly
530 	 * accounted for.  (We need to read resources from ACPI as well as
531 	 * the MP tables and hotplug tables.)
532 	 */
533 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
534 	    (num_root_bus > 1))
535 		return (0);
536 
537 	res_bus = parbus;
538 	while (pci_bus_res[res_bus].subtractive) {
539 		if (pci_bus_res[res_bus].io_ports)
540 			break;
541 		res_bus = pci_bus_res[res_bus].par_bus;
542 		if (res_bus == (uchar_t)-1)
543 			break; /* root bus already */
544 	}
545 
546 	if (pci_bus_res[res_bus].io_ports) {
547 		addr = memlist_find(&pci_bus_res[res_bus].io_ports,
548 		    size, align);
549 		if (addr) {
550 			memlist_insert(&pci_bus_res[res_bus].io_ports_used,
551 			    addr, size);
552 			/* free the old resource */
553 			memlist_free_all(&pci_bus_res[bus].io_ports);
554 			/* add the new resource */
555 			memlist_insert(&pci_bus_res[bus].io_ports, addr, size);
556 		}
557 	}
558 
559 	return (addr);
560 }
561 
562 static uint64_t
563 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
564 {
565 	uint64_t addr = 0;
566 	uchar_t res_bus;
567 
568 	/*
569 	 * Skip root(peer) buses in multiple-root-bus systems, as currently
570 	 * the initial resources set on each root bus might not be correctly
571 	 * accounted for.  (We need to read resources from ACPI as well as
572 	 * the MP tables and hotplug tables.)
573 	 */
574 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
575 	    (num_root_bus > 1))
576 		return (0);
577 
578 	res_bus = parbus;
579 	while (pci_bus_res[res_bus].subtractive) {
580 		if (pci_bus_res[res_bus].mem_space)
581 			break;
582 		res_bus = pci_bus_res[res_bus].par_bus;
583 		if (res_bus == (uchar_t)-1)
584 			break; /* root bus already */
585 	}
586 
587 	if (pci_bus_res[res_bus].mem_space) {
588 		addr = memlist_find(&pci_bus_res[res_bus].mem_space,
589 		    size, align);
590 		if (addr) {
591 			memlist_insert(&pci_bus_res[res_bus].mem_space_used,
592 			    addr, size);
593 			/* remove it from PMEM resource also */
594 			if (pci_bus_res[res_bus].pmem_space)
595 				(void) memlist_remove(
596 				    &pci_bus_res[res_bus].pmem_space,
597 				    addr, size);
598 			/* free the old resource */
599 			memlist_free_all(&pci_bus_res[bus].mem_space);
600 			/* add the new resource */
601 			memlist_insert(&pci_bus_res[bus].mem_space, addr, size);
602 		}
603 	}
604 
605 	return (addr);
606 }
607 
608 /*
609  * given a cap_id, return its cap_id location in config space
610  */
611 static int
612 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id)
613 {
614 	uint8_t curcap, cap_id_loc;
615 	uint16_t status;
616 	int location = -1;
617 
618 	/*
619 	 * Need to check the Status register for ECP support first.
620 	 * Also please note that for type 1 devices, the
621 	 * offset could change. Should support type 1 next.
622 	 */
623 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
624 	if (!(status & PCI_STAT_CAP)) {
625 		return (-1);
626 	}
627 	cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
628 
629 	/* Walk the list of capabilities */
630 	while (cap_id_loc && cap_id_loc != (uint8_t)-1) {
631 		curcap = pci_getb(bus, dev, func, cap_id_loc);
632 
633 		if (curcap == cap_id) {
634 			location = cap_id_loc;
635 			break;
636 		}
637 		cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1);
638 	}
639 	return (location);
640 }
641 
642 /*
643  * Assign valid resources to unconfigured pci(e) bridges. We are trying
644  * to reprogram the bridge when its
645  * 		i)   SECBUS == SUBBUS	||
646  * 		ii)  IOBASE > IOLIM	||
647  * 		iii) MEMBASE > MEMLIM
648  * This must be done after one full pass through the PCI tree to collect
649  * all BIOS-configured resources, so that we know what resources are
650  * free and available to assign to the unconfigured PPBs.
651  */
652 static void
653 fix_ppb_res(uchar_t secbus, boolean_t prog_sub)
654 {
655 	uchar_t bus, dev, func;
656 	uchar_t parbus, subbus;
657 	uint_t io_base, io_limit, mem_base, mem_limit;
658 	uint_t io_size, mem_size;
659 	uint64_t addr = 0;
660 	int *regp = NULL;
661 	uint_t reglen;
662 	int rv, cap_ptr, physhi;
663 	dev_info_t *dip;
664 	uint16_t cmd_reg;
665 	struct memlist *list;
666 
667 	/* skip root (peer) PCI busses */
668 	if (pci_bus_res[secbus].par_bus == (uchar_t)-1)
669 		return;
670 
671 	/* skip subtractive PPB when prog_sub is not TRUE */
672 	if (pci_bus_res[secbus].subtractive && !prog_sub)
673 		return;
674 
675 	/* some entries may be empty due to discontiguous bus numbering */
676 	dip = pci_bus_res[secbus].dip;
677 	if (dip == NULL)
678 		return;
679 
680 	rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
681 	    "reg", &regp, &reglen);
682 	ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0);
683 	physhi = regp[0];
684 	ddi_prop_free(regp);
685 
686 	func = (uchar_t)PCI_REG_FUNC_G(physhi);
687 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
688 	bus = (uchar_t)PCI_REG_BUS_G(physhi);
689 
690 	/*
691 	 * If pcie bridge, check to see if link is enabled
692 	 */
693 	cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E);
694 	if (cap_ptr != -1) {
695 		cmd_reg = pci_getw(bus, dev, func,
696 		    (uint16_t)cap_ptr + PCIE_LINKCTL);
697 		if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
698 			dcmn_err(CE_NOTE,
699 			    "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n",
700 			    bus, dev, func);
701 			return;
702 		}
703 	}
704 
705 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
706 	parbus = pci_bus_res[secbus].par_bus;
707 	ASSERT(parbus == bus);
708 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
709 
710 	/*
711 	 * If we have a Cardbus bridge, but no bus space
712 	 */
713 	if (pci_bus_res[secbus].num_cbb != 0 &&
714 	    pci_bus_res[secbus].bus_space == NULL) {
715 		uchar_t range;
716 
717 		/* normally there are 2 buses under a cardbus bridge */
718 		range = pci_bus_res[secbus].num_cbb * 2;
719 
720 		/*
721 		 * Try to find and allocate a bus-range starting at subbus+1
722 		 * from the parent of the PPB.
723 		 */
724 		for (; range != 0; range--) {
725 			if (memlist_find_with_startaddr(
726 			    &pci_bus_res[parbus].bus_space,
727 			    subbus + 1, range, 1) != NULL)
728 				break; /* find bus range resource at parent */
729 		}
730 		if (range != 0) {
731 			memlist_insert(&pci_bus_res[secbus].bus_space,
732 			    subbus + 1, range);
733 			subbus = subbus + range;
734 			pci_bus_res[secbus].sub_bus = subbus;
735 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
736 			add_bus_range_prop(secbus);
737 
738 			cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
739 			    "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
740 			    secbus, subbus);
741 		}
742 	}
743 
744 	/*
745 	 * Calculate required IO size
746 	 * We are going to assign 512 bytes per bus. The size needs to be
747 	 * 4K aligned and the maximum size is 16K.
748 	 */
749 	io_size = (subbus - secbus + 1) * 0x200;
750 	io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1));
751 	if (io_size > 0x4 * PPB_IO_ALIGNMENT)
752 		io_size = 0x4 * PPB_IO_ALIGNMENT;
753 	/*
754 	 * Calculate required MEM size
755 	 * We are going to assign 1M bytes per bus. The size needs to be
756 	 * 1M aligned and the maximum size is 8M.
757 	 */
758 	mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT;
759 	if (mem_size > 0x8 * PPB_MEM_ALIGNMENT)
760 		mem_size = 0x8 * PPB_MEM_ALIGNMENT;
761 
762 	/* Subtractive bridge */
763 	if (pci_bus_res[secbus].subtractive && prog_sub) {
764 		/*
765 		 * We program an arbitrary amount of I/O and memory resource
766 		 * for the subtractive bridge so that child dynamic-resource-
767 		 * allocating devices (such as Cardbus bridges) have a chance
768 		 * of success.  Until we have full-tree resource rebalancing,
769 		 * dynamic resource allocation (thru busra) only looks at the
770 		 * parent bridge, so all PPBs must have some allocatable
771 		 * resource.  For non-subtractive bridges, the resources come
772 		 * from the base/limit register "windows", but subtractive
773 		 * bridges often don't program those (since they don't need to).
774 		 * If we put all the remaining resources on the subtractive
775 		 * bridge, then peer non-subtractive bridges can't allocate
776 		 * more space (even though this is probably most correct).
777 		 * If we put the resources only on the parent, then allocations
778 		 * from children of subtractive bridges will fail without
779 		 * special-case code for bypassing the subtractive bridge.
780 		 * This solution is the middle-ground temporary solution until
781 		 * we have fully-capable resource allocation.
782 		 */
783 
784 		/*
785 		 * Add an arbitrary I/O resource to the subtractive PPB
786 		 */
787 		if (pci_bus_res[secbus].io_ports == NULL) {
788 			addr = get_parbus_io_res(parbus, secbus, io_size,
789 			    PPB_IO_ALIGNMENT);
790 			if (addr) {
791 				add_ppb_ranges_prop(secbus);
792 				pci_bus_res[secbus].io_reprogram =
793 				    pci_bus_res[parbus].io_reprogram;
794 
795 				cmn_err(CE_NOTE, "!add io-range on subtractive"
796 				    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
797 				    bus, dev, func, (uint32_t)addr,
798 				    (uint32_t)addr + io_size - 1);
799 			}
800 		}
801 		/*
802 		 * Add an arbitrary memory resource to the subtractive PPB
803 		 */
804 		if (pci_bus_res[secbus].mem_space == NULL) {
805 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
806 			    PPB_MEM_ALIGNMENT);
807 			if (addr) {
808 				add_ppb_ranges_prop(secbus);
809 				pci_bus_res[secbus].mem_reprogram =
810 				    pci_bus_res[parbus].mem_reprogram;
811 
812 				cmn_err(CE_NOTE, "!add mem-range on "
813 				    "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
814 				    bus, dev, func, (uint32_t)addr,
815 				    (uint32_t)addr + mem_size - 1);
816 			}
817 		}
818 
819 		goto cmd_enable;
820 	}
821 
822 	/*
823 	 * Check to see if we need to reprogram I/O space, either because the
824 	 * parent bus needed reprogramming and so do we, or because I/O space is
825 	 * disabled in base/limit or command register.
826 	 */
827 	io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
828 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
829 	io_base = (io_base & 0xf0) << 8;
830 	io_limit = ((io_limit & 0xf0) << 8) | 0xfff;
831 
832 	if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) ||
833 	    (!(cmd_reg & PCI_COMM_IO))) {
834 		if (pci_bus_res[secbus].io_ports_used) {
835 			memlist_merge(&pci_bus_res[secbus].io_ports_used,
836 			    &pci_bus_res[secbus].io_ports);
837 		}
838 		if (pci_bus_res[secbus].io_ports &&
839 		    (!pci_bus_res[parbus].io_reprogram) &&
840 		    (!pci_bus_res[parbus].subtractive)) {
841 			/* rechoose old io ports info */
842 			list = pci_bus_res[secbus].io_ports;
843 			io_base = (uint_t)list->address;
844 			/* 4K aligned */
845 			io_base = io_base & (~(PPB_IO_ALIGNMENT - 1));
846 			io_limit = (uint_t)(list->address + list->size);
847 			while (list->next) {
848 				list = list->next;
849 				if ((list->address + list->size) > io_limit)
850 					io_limit = (uint_t)
851 					    (list->address + list->size);
852 			}
853 			io_limit = io_limit - 1;
854 			/* 4K aligned */
855 			io_limit = (io_limit + PPB_IO_ALIGNMENT) &
856 			    (~(PPB_IO_ALIGNMENT - 1));
857 			io_size = io_limit - io_base;
858 			io_limit = io_limit - 1;
859 			ASSERT(io_base <= io_limit);
860 			memlist_free_all(&pci_bus_res[secbus].io_ports);
861 			memlist_insert(&pci_bus_res[secbus].io_ports,
862 			    io_base, io_size);
863 			memlist_insert(&pci_bus_res[parbus].io_ports_used,
864 			    io_base, io_size);
865 			if (pci_bus_res[parbus].io_ports)
866 				(void) memlist_remove(
867 				    &pci_bus_res[parbus].io_ports,
868 				    io_base, io_size);
869 			pci_bus_res[secbus].io_reprogram = B_TRUE;
870 		} else {
871 			/* get new io ports from parent bus */
872 			addr = get_parbus_io_res(parbus, secbus, io_size,
873 			    PPB_IO_ALIGNMENT);
874 			if (addr) {
875 				io_base = addr;
876 				io_limit = addr + io_size - 1;
877 				pci_bus_res[secbus].io_reprogram = B_TRUE;
878 			}
879 		}
880 		if (pci_bus_res[secbus].io_reprogram) {
881 			/* reprogram PPB regs */
882 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
883 			    (uchar_t)((io_base>>8) & 0xf0));
884 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
885 			    (uchar_t)((io_limit>>8) & 0xf0));
886 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
887 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
888 			add_ppb_ranges_prop(secbus);
889 
890 			cmn_err(CE_NOTE, "!reprogram io-range on"
891 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
892 			    bus, dev, func, io_base, io_limit);
893 		}
894 	}
895 
896 	/*
897 	 * Check memory space as we did I/O space.
898 	 */
899 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
900 	mem_base = (mem_base & 0xfff0) << 16;
901 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
902 	mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff;
903 
904 	if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) ||
905 	    (!(cmd_reg & PCI_COMM_MAE))) {
906 		if (pci_bus_res[secbus].mem_space_used) {
907 			memlist_merge(&pci_bus_res[secbus].mem_space_used,
908 			    &pci_bus_res[secbus].mem_space);
909 		}
910 		if (pci_bus_res[secbus].mem_space &&
911 		    (!pci_bus_res[parbus].mem_reprogram) &&
912 		    (!pci_bus_res[parbus].subtractive)) {
913 			/* rechoose old mem resource */
914 			list = pci_bus_res[secbus].mem_space;
915 			mem_base = (uint_t)list->address;
916 			/* 1M aligned */
917 			mem_base = mem_base & (~0xfffff);
918 			mem_limit = (uint_t)(list->address + list->size);
919 			while (list->next) {
920 				list = list->next;
921 				if ((list->address + list->size) > mem_limit)
922 					mem_limit = (uint_t)
923 					    (list->address + list->size);
924 			}
925 			mem_limit = mem_limit - 1;
926 			/* 1M aligned */
927 			mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) &
928 			    (~(PPB_MEM_ALIGNMENT - 1));
929 			mem_size = mem_limit - mem_base;
930 			mem_limit = mem_limit - 1;
931 			ASSERT(mem_base <= mem_limit);
932 			memlist_free_all(&pci_bus_res[secbus].mem_space);
933 			memlist_insert(&pci_bus_res[secbus].mem_space,
934 			    mem_base, mem_size);
935 			memlist_insert(&pci_bus_res[parbus].mem_space_used,
936 			    mem_base, mem_size);
937 			if (pci_bus_res[parbus].mem_space)
938 				(void) memlist_remove(
939 				    &pci_bus_res[parbus].mem_space,
940 				    mem_base, mem_size);
941 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
942 		} else {
943 			/* get new mem resource from parent bus */
944 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
945 			    PPB_MEM_ALIGNMENT);
946 			if (addr) {
947 				mem_base = addr;
948 				mem_limit = addr + mem_size - 1;
949 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
950 			}
951 		}
952 
953 		if (pci_bus_res[secbus].mem_reprogram) {
954 			/* reprogram PPB regs */
955 			pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
956 			    (uint16_t)((mem_base>>16) & 0xfff0));
957 			pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
958 			    (uint16_t)((mem_limit>>16) & 0xfff0));
959 			add_ppb_ranges_prop(secbus);
960 
961 			cmn_err(CE_NOTE, "!reprogram mem-range on"
962 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
963 			    bus, dev, func, mem_base, mem_limit);
964 		}
965 	}
966 
967 cmd_enable:
968 	if (pci_bus_res[secbus].io_ports)
969 		cmd_reg |= PCI_COMM_IO | PCI_COMM_ME;
970 	if (pci_bus_res[secbus].mem_space)
971 		cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME;
972 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
973 }
974 
975 void
976 pci_reprogram(void)
977 {
978 	int i, pci_reconfig = 1;
979 	char *onoff;
980 
981 	/*
982 	 * Excise phantom roots if possible
983 	 */
984 	pci_renumber_root_busses();
985 
986 	/* add bus-range property for root/peer bus nodes */
987 	for (i = 0; i <= pci_bios_nbus; i++) {
988 		if (pci_bus_res[i].par_bus == (uchar_t)-1) {
989 			uchar_t subbus;
990 			if (pci_root_subbus(i, &subbus) == AE_OK)
991 				pci_bus_res[i].sub_bus = subbus;
992 			add_bus_range_prop(i);
993 		}
994 		/* setup bus range resource on each bus */
995 		setup_bus_res(i);
996 	}
997 
998 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(),
999 	    DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) {
1000 		if (strcmp(onoff, "off") == 0) {
1001 			pci_reconfig = 0;
1002 			cmn_err(CE_NOTE, "pci device reprogramming disabled");
1003 		}
1004 		ddi_prop_free(onoff);
1005 	}
1006 
1007 	/* remove used-resources from PCI resource maps */
1008 	remove_used_resources();
1009 	remove_subtractive_res();
1010 
1011 	/* reprogram the non-subtractive PPB */
1012 	if (pci_reconfig)
1013 		for (i = 0; i <= pci_bios_nbus; i++)
1014 			fix_ppb_res(i, B_FALSE);
1015 
1016 	for (i = 0; i <= pci_bios_nbus; i++) {
1017 		/* configure devices not configured by BIOS */
1018 		if (pci_reconfig) {
1019 			/*
1020 			 * Reprogram the subtractive PPB. At this time, all its
1021 			 * siblings should have got their resources already.
1022 			 */
1023 			if (pci_bus_res[i].subtractive)
1024 				fix_ppb_res(i, B_TRUE);
1025 			enumerate_bus_devs(i, CONFIG_NEW);
1026 		}
1027 		/* All dev programmed, so we can create available prop */
1028 		add_bus_available_prop(i);
1029 	}
1030 }
1031 
1032 /*
1033  * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
1034  */
1035 static void
1036 create_root_bus_dip(uchar_t bus)
1037 {
1038 	int pci_regs[] = {0, 0, 0};
1039 	dev_info_t *dip;
1040 
1041 	ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
1042 
1043 	num_root_bus++;
1044 	ndi_devi_alloc_sleep(ddi_root_node(), "pci",
1045 	    (pnode_t)DEVI_SID_NODEID, &dip);
1046 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1047 	    "#address-cells", 3);
1048 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1049 	    "#size-cells", 2);
1050 	pci_regs[0] = pci_bus_res[bus].root_addr;
1051 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1052 	    "reg", (int *)pci_regs, 3);
1053 
1054 	/*
1055 	 * If system has PCIe bus, then create different properties
1056 	 */
1057 	if (create_pcie_root_bus(bus, dip) == B_FALSE)
1058 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1059 		    "device_type", "pci");
1060 
1061 	(void) ndi_devi_bind_driver(dip, 0);
1062 	pci_bus_res[bus].dip = dip;
1063 	pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE);
1064 	pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE);
1065 	pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE);
1066 
1067 	if (bus != 0)
1068 		return;
1069 
1070 	/*
1071 	 * Special treatment of bus 0:
1072 	 * If no resource from MPSPEC/HRT, copy pcimem from boot
1073 	 * and make I/O space the entire range starting at 0x100. There
1074 	 * is no difference between prefetchable memory or not.
1075 	 */
1076 	if (pci_bus_res[0].mem_space == NULL)
1077 		pci_bus_res[0].mem_space =
1078 		    memlist_dup(bootops->boot_mem->pcimem);
1079 	/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
1080 	if (pci_bus_res[0].io_ports == NULL)
1081 		memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff);
1082 }
1083 
1084 /*
1085  * For any fixed configuration (often compatability) pci devices
1086  * and those with their own expansion rom, create device nodes
1087  * to hold the already configured device details.
1088  */
1089 void
1090 enumerate_bus_devs(uchar_t bus, int config_op)
1091 {
1092 	uchar_t dev, func, nfunc, header;
1093 	ushort_t venid;
1094 	struct pci_devfunc *devlist = NULL, *entry;
1095 
1096 	if (config_op == CONFIG_NEW) {
1097 		dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1098 	} else if (config_op == CONFIG_FIX) {
1099 		dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus);
1100 	} else
1101 		dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
1102 
1103 	for (dev = 0; dev < max_dev_pci; dev++) {
1104 		nfunc = 1;
1105 		for (func = 0; func < nfunc; func++) {
1106 
1107 			dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x",
1108 			    dev, func);
1109 
1110 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1111 
1112 			if ((venid == 0xffff) || (venid == 0)) {
1113 				/* no function at this address */
1114 				continue;
1115 			}
1116 
1117 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1118 			if (header == 0xff) {
1119 				continue; /* illegal value */
1120 			}
1121 
1122 			/*
1123 			 * according to some mail from Microsoft posted
1124 			 * to the pci-drivers alias, their only requirement
1125 			 * for a multifunction device is for the 1st
1126 			 * function to have to PCI_HEADER_MULTI bit set.
1127 			 */
1128 			if ((func == 0) && (header & PCI_HEADER_MULTI)) {
1129 				nfunc = 8;
1130 			}
1131 
1132 			if (config_op == CONFIG_FIX ||
1133 			    config_op == CONFIG_INFO) {
1134 				/*
1135 				 * Create the node, unconditionally, on the
1136 				 * first pass only.  It may still need
1137 				 * resource assignment, which will be
1138 				 * done on the second, CONFIG_NEW, pass.
1139 				 */
1140 				process_devfunc(bus, dev, func, header,
1141 				    venid, config_op);
1142 
1143 			}
1144 		}
1145 	}
1146 
1147 	if (config_op == CONFIG_NEW) {
1148 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1149 		while (devlist) {
1150 			entry = devlist;
1151 			devlist = entry->next;
1152 			if (entry->reprogram ||
1153 			    pci_bus_res[bus].io_reprogram ||
1154 			    pci_bus_res[bus].mem_reprogram) {
1155 				/* reprogram device(s) */
1156 				(void) add_reg_props(entry->dip, bus,
1157 				    entry->dev, entry->func, CONFIG_NEW, 0);
1158 			}
1159 			kmem_free(entry, sizeof (*entry));
1160 		}
1161 		pci_bus_res[bus].privdata = NULL;
1162 	}
1163 }
1164 
1165 static int
1166 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid,
1167     ushort_t subvenid, ushort_t subdevid)
1168 {
1169 	static int prop_exist = -1;
1170 	static char *pciide_str;
1171 	char compat[32];
1172 
1173 	if (prop_exist == -1) {
1174 		prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY,
1175 		    ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide",
1176 		    &pciide_str) == DDI_SUCCESS);
1177 	}
1178 
1179 	if (!prop_exist)
1180 		return (0);
1181 
1182 	/* compare property value against various forms of compatible */
1183 	if (subvenid) {
1184 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x",
1185 		    venid, devid, subvenid, subdevid, revid);
1186 		if (strcmp(pciide_str, compat) == 0)
1187 			return (1);
1188 
1189 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x",
1190 		    venid, devid, subvenid, subdevid);
1191 		if (strcmp(pciide_str, compat) == 0)
1192 			return (1);
1193 
1194 		(void) snprintf(compat, sizeof (compat), "pci%x,%x",
1195 		    subvenid, subdevid);
1196 		if (strcmp(pciide_str, compat) == 0)
1197 			return (1);
1198 	}
1199 	(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x",
1200 	    venid, devid, revid);
1201 	if (strcmp(pciide_str, compat) == 0)
1202 		return (1);
1203 
1204 	(void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid);
1205 	if (strcmp(pciide_str, compat) == 0)
1206 		return (1);
1207 
1208 	return (0);
1209 }
1210 
1211 static int
1212 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid,
1213     ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid)
1214 {
1215 	struct ide_table {	/* table for PCI_MASS_OTHER */
1216 		ushort_t venid;
1217 		ushort_t devid;
1218 	} *entry;
1219 
1220 	/* XXX SATA and other devices: need a way to add dynamically */
1221 	static struct ide_table ide_other[] = {
1222 		{0x1095, 0x3112},
1223 		{0x1095, 0x3114},
1224 		{0x1095, 0x3512},
1225 		{0x1095, 0x680},	/* Sil0680 */
1226 		{0x1283, 0x8211},	/* ITE 8211F is subcl PCI_MASS_OTHER */
1227 		{0, 0}
1228 	};
1229 
1230 	if (basecl != PCI_CLASS_MASS)
1231 		return (0);
1232 
1233 	if (subcl == PCI_MASS_IDE) {
1234 		return (1);
1235 	}
1236 
1237 	if (check_pciide_prop(revid, venid, devid, subvenid, subdevid))
1238 		return (1);
1239 
1240 	if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) {
1241 		return (0);
1242 	}
1243 
1244 	entry = &ide_other[0];
1245 	while (entry->venid) {
1246 		if (entry->venid == venid && entry->devid == devid)
1247 			return (1);
1248 		entry++;
1249 	}
1250 	return (0);
1251 }
1252 
1253 static int
1254 is_display(uint_t classcode)
1255 {
1256 	static uint_t disp_classes[] = {
1257 		0x000100,
1258 		0x030000,
1259 		0x030001
1260 	};
1261 	int i, nclasses = sizeof (disp_classes) / sizeof (uint_t);
1262 
1263 	for (i = 0; i < nclasses; i++) {
1264 		if (classcode == disp_classes[i])
1265 			return (1);
1266 	}
1267 	return (0);
1268 }
1269 
1270 static void
1271 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1272     void (*undofn)(uint8_t, uint8_t, uint8_t))
1273 {
1274 	struct pci_fixundo *newundo;
1275 
1276 	newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP);
1277 
1278 	/*
1279 	 * Adding an item to this list means that we must turn its NMIENABLE
1280 	 * bit back on at a later time.
1281 	 */
1282 	newundo->bus = bus;
1283 	newundo->dev = dev;
1284 	newundo->fn = fn;
1285 	newundo->undofn = undofn;
1286 	newundo->next = undolist;
1287 
1288 	/* add to the undo list in LIFO order */
1289 	undolist = newundo;
1290 }
1291 
1292 void
1293 add_pci_fixes(void)
1294 {
1295 	int i;
1296 
1297 	for (i = 0; i <= pci_bios_nbus; i++) {
1298 		/*
1299 		 * For each bus, apply needed fixes to the appropriate devices.
1300 		 * This must be done before the main enumeration loop because
1301 		 * some fixes must be applied to devices normally encountered
1302 		 * later in the pci scan (e.g. if a fix to device 7 must be
1303 		 * applied before scanning device 6, applying fixes in the
1304 		 * normal enumeration loop would obviously be too late).
1305 		 */
1306 		enumerate_bus_devs(i, CONFIG_FIX);
1307 	}
1308 }
1309 
1310 void
1311 undo_pci_fixes(void)
1312 {
1313 	struct pci_fixundo *nextundo;
1314 	uint8_t bus, dev, fn;
1315 
1316 	/*
1317 	 * All fixes in the undo list are performed unconditionally.  Future
1318 	 * fixes may require selective undo.
1319 	 */
1320 	while (undolist != NULL) {
1321 
1322 		bus = undolist->bus;
1323 		dev = undolist->dev;
1324 		fn = undolist->fn;
1325 
1326 		(*(undolist->undofn))(bus, dev, fn);
1327 
1328 		nextundo = undolist->next;
1329 		kmem_free(undolist, sizeof (struct pci_fixundo));
1330 		undolist = nextundo;
1331 	}
1332 }
1333 
1334 static void
1335 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1336 {
1337 	uint8_t val8;
1338 
1339 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1340 	/*
1341 	 * The NMIONERR bit is turned back on to allow the SMM BIOS
1342 	 * to handle more critical PCI errors (e.g. PERR#).
1343 	 */
1344 	val8 |= AMD8111_ENABLENMI;
1345 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1346 }
1347 
1348 static void
1349 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1350 {
1351 	uint8_t val8;
1352 
1353 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1354 
1355 	if ((val8 & AMD8111_ENABLENMI) == 0)
1356 		return;
1357 
1358 	/*
1359 	 * We reset NMIONERR in the LPC because master-abort on the PCI
1360 	 * bridge side of the 8111 will cause NMI, which might cause SMI,
1361 	 * which sometimes prevents all devices from being enumerated.
1362 	 */
1363 	val8 &= ~AMD8111_ENABLENMI;
1364 
1365 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1366 
1367 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1368 }
1369 
1370 static void
1371 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1372 {
1373 	uint16_t status;
1374 	uint8_t header;
1375 	uint8_t cap_ptr;
1376 	uint8_t cap_id;
1377 	uint16_t pmcsr;
1378 
1379 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1380 	if (!(status & PCI_STAT_CAP))
1381 		return;	/* No capabilities list */
1382 
1383 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1384 	if (header == PCI_HEADER_CARDBUS)
1385 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_RESERVED1);
1386 	else
1387 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1388 	/*
1389 	 * Walk the capabilities list searching for a PM entry.
1390 	 */
1391 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {
1392 		cap_ptr &= PCI_CAP_PTR_MASK;
1393 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1394 		if (cap_id == PCI_CAP_ID_PM) {
1395 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1396 			pmcsr &= ~(PCI_PMCSR_STATE_MASK);
1397 			pmcsr |= PCI_PMCSR_D0; /* D0 state */
1398 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1399 			break;
1400 		}
1401 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1402 	}
1403 
1404 }
1405 
1406 static void
1407 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
1408     ushort_t vendorid, int config_op)
1409 {
1410 	char nodename[32], unitaddr[5];
1411 	dev_info_t *dip;
1412 	uchar_t basecl, subcl, progcl, intr, revid;
1413 	ushort_t subvenid, subdevid, status;
1414 	ushort_t slot_num;
1415 	uint_t classcode, revclass;
1416 	int reprogram = 0, pciide = 0;
1417 	int power[2] = {1, 1};
1418 	int pciex = 0;
1419 	ushort_t is_pci_bridge = 0;
1420 	struct pci_devfunc *devlist = NULL, *entry = NULL;
1421 	iommu_private_t *private;
1422 
1423 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
1424 
1425 	switch (header & PCI_HEADER_TYPE_M) {
1426 	case PCI_HEADER_ZERO:
1427 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
1428 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
1429 		break;
1430 	case PCI_HEADER_CARDBUS:
1431 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
1432 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
1433 		/* Record the # of cardbus bridges found on the bus */
1434 		if (config_op == CONFIG_INFO)
1435 			pci_bus_res[bus].num_cbb++;
1436 		break;
1437 	default:
1438 		subvenid = 0;
1439 		subdevid = 0;
1440 		break;
1441 	}
1442 
1443 	if (config_op == CONFIG_FIX) {
1444 		if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) {
1445 			pci_fix_amd8111(bus, dev, func);
1446 		}
1447 		return;
1448 	}
1449 
1450 	/* XXX should be use generic names? derive from class? */
1451 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
1452 	classcode = revclass >> 8;
1453 	revid = revclass & 0xff;
1454 
1455 	/* figure out if this is pci-ide */
1456 	basecl = classcode >> 16;
1457 	subcl = (classcode >> 8) & 0xff;
1458 	progcl = classcode & 0xff;
1459 
1460 
1461 	if (is_display(classcode))
1462 		(void) snprintf(nodename, sizeof (nodename), "display");
1463 	else if (subvenid != 0)
1464 		(void) snprintf(nodename, sizeof (nodename),
1465 		    "pci%x,%x", subvenid, subdevid);
1466 	else
1467 		(void) snprintf(nodename, sizeof (nodename),
1468 		    "pci%x,%x", vendorid, deviceid);
1469 
1470 	/* make sure parent bus dip has been created */
1471 	if (pci_bus_res[bus].dip == NULL) {
1472 		create_root_bus_dip(bus);
1473 	}
1474 
1475 	ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
1476 	    DEVI_SID_NODEID, &dip);
1477 
1478 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num,
1479 	    &is_pci_bridge) == B_TRUE)
1480 		pciex = 1;
1481 
1482 	/* add properties */
1483 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid);
1484 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid);
1485 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid);
1486 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1487 	    "class-code", classcode);
1488 	if (func == 0)
1489 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
1490 	else
1491 		(void) snprintf(unitaddr, sizeof (unitaddr),
1492 		    "%x,%x", dev, func);
1493 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1494 	    "unit-address", unitaddr);
1495 
1496 	/* add device_type for display nodes */
1497 	if (is_display(classcode)) {
1498 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1499 		    "device_type", "display");
1500 	}
1501 	/* add special stuff for header type */
1502 	if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
1503 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
1504 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
1505 
1506 		if (subvenid != 0) {
1507 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1508 			    "subsystem-id", subdevid);
1509 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1510 			    "subsystem-vendor-id", subvenid);
1511 		}
1512 		if (!pciex)
1513 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1514 			    "min-grant", mingrant);
1515 		if (!pciex)
1516 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1517 			    "max-latency", maxlatency);
1518 	}
1519 
1520 	/* interrupt, record if not 0 */
1521 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
1522 	if (intr != 0)
1523 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1524 		    "interrupts", intr);
1525 
1526 	/*
1527 	 * Add support for 133 mhz pci eventually
1528 	 */
1529 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1530 
1531 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1532 	    "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9);
1533 	if (!pciex && (status & PCI_STAT_FBBC))
1534 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1535 		    "fast-back-to-back");
1536 	if (!pciex && (status & PCI_STAT_66MHZ))
1537 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1538 		    "66mhz-capable");
1539 	if (status & PCI_STAT_UDF)
1540 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1541 		    "udf-supported");
1542 	if (pciex && slot_num) {
1543 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1544 		    "physical-slot#", slot_num);
1545 		if (!is_pci_bridge)
1546 			pciex_slot_names_prop(dip, slot_num);
1547 	}
1548 
1549 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1550 	    "power-consumption", power, 2);
1551 
1552 	/* Set the device PM state to D0 */
1553 	set_devpm_d0(bus, dev, func);
1554 
1555 	if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI))
1556 		add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge);
1557 	else {
1558 		/*
1559 		 * Record the non-PPB devices on the bus for possible
1560 		 * reprogramming at 2nd bus enumeration.
1561 		 * Note: PPB reprogramming is done in fix_ppb_res()
1562 		 */
1563 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1564 		entry = kmem_zalloc(sizeof (*entry), KM_SLEEP);
1565 		entry->dip = dip;
1566 		entry->dev = dev;
1567 		entry->func = func;
1568 		entry->next = devlist;
1569 		pci_bus_res[bus].privdata = entry;
1570 	}
1571 
1572 	if (config_op == CONFIG_INFO &&
1573 	    IS_CLASS_IOAPIC(basecl, subcl, progcl)) {
1574 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
1575 	}
1576 
1577 	/* check for ck8-04 based PCI ISA bridge only */
1578 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
1579 	    (func == 0))
1580 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
1581 
1582 	if (pciex && is_pci_bridge)
1583 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
1584 		    (char *)"PCIe-PCI bridge");
1585 	else
1586 		add_model_prop(dip, classcode);
1587 
1588 	add_compatible(dip, subvenid, subdevid, vendorid, deviceid,
1589 	    revid, classcode, pciex);
1590 
1591 	/*
1592 	 * See if this device is a controller that advertises
1593 	 * itself to be a standard ATA task file controller, or one that
1594 	 * has been hard coded.
1595 	 *
1596 	 * If it is, check if any other higher precedence driver listed in
1597 	 * driver_aliases will claim the node by calling
1598 	 * ddi_compatibile_driver_major.  If so, clear pciide and do not
1599 	 * create a pci-ide node or any other special handling.
1600 	 *
1601 	 * If another driver does not bind, set the node name to pci-ide
1602 	 * and then let the special pci-ide handling for registers and
1603 	 * child pci-ide nodes proceed below.
1604 	 */
1605 	if (is_pciide(basecl, subcl, revid, vendorid, deviceid,
1606 	    subvenid, subdevid) == 1) {
1607 		if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) {
1608 			(void) ndi_devi_set_nodename(dip, "pci-ide", 0);
1609 			pciide = 1;
1610 		}
1611 	}
1612 
1613 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
1614 	(void) ndi_devi_bind_driver(dip, 0);
1615 
1616 	/* special handling for pci-ide */
1617 	if (pciide) {
1618 		dev_info_t *cdip;
1619 
1620 		/*
1621 		 * Create properties specified by P1275 Working Group
1622 		 * Proposal #414 Version 1
1623 		 */
1624 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1625 		    "device_type", "pci-ide");
1626 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1627 		    "#address-cells", 1);
1628 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1629 		    "#size-cells", 0);
1630 
1631 		/* allocate two child nodes */
1632 		ndi_devi_alloc_sleep(dip, "ide",
1633 		    (pnode_t)DEVI_SID_NODEID, &cdip);
1634 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
1635 		    "reg", 0);
1636 		(void) ndi_devi_bind_driver(cdip, 0);
1637 		ndi_devi_alloc_sleep(dip, "ide",
1638 		    (pnode_t)DEVI_SID_NODEID, &cdip);
1639 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
1640 		    "reg", 1);
1641 		(void) ndi_devi_bind_driver(cdip, 0);
1642 
1643 		reprogram = 0;	/* don't reprogram pci-ide bridge */
1644 	}
1645 
1646 	/* allocate and set up iommu private */
1647 	private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP);
1648 	private->idp_seg = 0;
1649 	private->idp_bus = bus;
1650 	private->idp_devfn = (dev << 3) | func;
1651 	private->idp_sec = 0;
1652 	private->idp_sub = 0;
1653 	private->idp_bbp_type = IOMMU_PPB_NONE;
1654 	/* record the bridge */
1655 	private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) &&
1656 	    (subcl == PCI_BRIDGE_PCI));
1657 	if (private->idp_is_bridge) {
1658 		private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
1659 		private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
1660 		if (pciex && is_pci_bridge)
1661 			private->idp_bbp_type = IOMMU_PPB_PCIE_PCI;
1662 		else if (pciex)
1663 			private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE;
1664 		else
1665 			private->idp_bbp_type = IOMMU_PPB_PCI_PCI;
1666 	}
1667 	/* record the special devices */
1668 	private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE);
1669 	private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) &&
1670 	    (subcl == PCI_BRIDGE_ISA));
1671 	private->idp_domain = NULL;
1672 	/* hook the private to dip */
1673 	DEVI(dip)->devi_iommu_private = private;
1674 
1675 	if (reprogram && (entry != NULL))
1676 		entry->reprogram = B_TRUE;
1677 }
1678 
1679 /*
1680  * Set the compatible property to a value compliant with
1681  * rev 2.1 of the IEEE1275 PCI binding.
1682  * (Also used for PCI-Express devices).
1683  *
1684  *   pciVVVV,DDDD.SSSS.ssss.RR	(0)
1685  *   pciVVVV,DDDD.SSSS.ssss	(1)
1686  *   pciSSSS,ssss		(2)
1687  *   pciVVVV,DDDD.RR		(3)
1688  *   pciVVVV,DDDD		(4)
1689  *   pciclass,CCSSPP		(5)
1690  *   pciclass,CCSS		(6)
1691  *
1692  * The Subsystem (SSSS) forms are not inserted if
1693  * subsystem-vendor-id is 0.
1694  *
1695  * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
1696  * property 2 is not created as per "1275 bindings for PCI Express Interconnect"
1697  *
1698  * Set with setprop and \x00 between each
1699  * to generate the encoded string array form.
1700  */
1701 void
1702 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid,
1703     ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode,
1704     int pciex)
1705 {
1706 	int i = 0;
1707 	int size = COMPAT_BUFSIZE;
1708 	char *compat[13];
1709 	char *buf, *curr;
1710 
1711 	curr = buf = kmem_alloc(size, KM_SLEEP);
1712 
1713 	if (pciex) {
1714 		if (subvenid) {
1715 			compat[i++] = curr;	/* form 0 */
1716 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x",
1717 			    vendorid, deviceid, subvenid, subdevid, revid);
1718 			size -= strlen(curr) + 1;
1719 			curr += strlen(curr) + 1;
1720 
1721 			compat[i++] = curr;	/* form 1 */
1722 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x",
1723 			    vendorid, deviceid, subvenid, subdevid);
1724 			size -= strlen(curr) + 1;
1725 			curr += strlen(curr) + 1;
1726 
1727 		}
1728 		compat[i++] = curr;	/* form 3 */
1729 		(void) snprintf(curr, size, "pciex%x,%x.%x",
1730 		    vendorid, deviceid, revid);
1731 		size -= strlen(curr) + 1;
1732 		curr += strlen(curr) + 1;
1733 
1734 		compat[i++] = curr;	/* form 4 */
1735 		(void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid);
1736 		size -= strlen(curr) + 1;
1737 		curr += strlen(curr) + 1;
1738 
1739 		compat[i++] = curr;	/* form 5 */
1740 		(void) snprintf(curr, size, "pciexclass,%06x", classcode);
1741 		size -= strlen(curr) + 1;
1742 		curr += strlen(curr) + 1;
1743 
1744 		compat[i++] = curr;	/* form 6 */
1745 		(void) snprintf(curr, size, "pciexclass,%04x",
1746 		    (classcode >> 8));
1747 		size -= strlen(curr) + 1;
1748 		curr += strlen(curr) + 1;
1749 	}
1750 
1751 	if (subvenid) {
1752 		compat[i++] = curr;	/* form 0 */
1753 		(void) snprintf(curr, size, "pci%x,%x.%x.%x.%x",
1754 		    vendorid, deviceid, subvenid, subdevid, revid);
1755 		size -= strlen(curr) + 1;
1756 		curr += strlen(curr) + 1;
1757 
1758 		compat[i++] = curr;	/* form 1 */
1759 		(void) snprintf(curr, size, "pci%x,%x.%x.%x",
1760 		    vendorid, deviceid, subvenid, subdevid);
1761 		size -= strlen(curr) + 1;
1762 		curr += strlen(curr) + 1;
1763 
1764 		compat[i++] = curr;	/* form 2 */
1765 		(void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid);
1766 		size -= strlen(curr) + 1;
1767 		curr += strlen(curr) + 1;
1768 	}
1769 	compat[i++] = curr;	/* form 3 */
1770 	(void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid);
1771 	size -= strlen(curr) + 1;
1772 	curr += strlen(curr) + 1;
1773 
1774 	compat[i++] = curr;	/* form 4 */
1775 	(void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid);
1776 	size -= strlen(curr) + 1;
1777 	curr += strlen(curr) + 1;
1778 
1779 	compat[i++] = curr;	/* form 5 */
1780 	(void) snprintf(curr, size, "pciclass,%06x", classcode);
1781 	size -= strlen(curr) + 1;
1782 	curr += strlen(curr) + 1;
1783 
1784 	compat[i++] = curr;	/* form 6 */
1785 	(void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8));
1786 	size -= strlen(curr) + 1;
1787 	curr += strlen(curr) + 1;
1788 
1789 	(void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
1790 	    "compatible", compat, i);
1791 	kmem_free(buf, COMPAT_BUFSIZE);
1792 }
1793 
1794 /*
1795  * Adjust the reg properties for a dual channel PCI-IDE device.
1796  *
1797  * NOTE: don't do anything that changes the order of the hard-decodes
1798  * and programmed BARs. The kernel driver depends on these values
1799  * being in this order regardless of whether they're for a 'native'
1800  * mode BAR or not.
1801  */
1802 /*
1803  * config info for pci-ide devices
1804  */
1805 static struct {
1806 	uchar_t  native_mask;	/* 0 == 'compatibility' mode, 1 == native */
1807 	uchar_t  bar_offset;	/* offset for alt status register */
1808 	ushort_t addr;		/* compatibility mode base address */
1809 	ushort_t length;	/* number of ports for this BAR */
1810 } pciide_bar[] = {
1811 	{ 0x01, 0, 0x1f0, 8 },	/* primary lower BAR */
1812 	{ 0x01, 2, 0x3f6, 1 },	/* primary upper BAR */
1813 	{ 0x04, 0, 0x170, 8 },	/* secondary lower BAR */
1814 	{ 0x04, 2, 0x376, 1 }	/* secondary upper BAR */
1815 };
1816 
1817 static int
1818 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp)
1819 {
1820 	int hard_decode = 0;
1821 
1822 	/*
1823 	 * Adjust the base and len for the BARs of the PCI-IDE
1824 	 * device's primary and secondary controllers. The first
1825 	 * two BARs are for the primary controller and the next
1826 	 * two BARs are for the secondary controller. The fifth
1827 	 * and sixth bars are never adjusted.
1828 	 */
1829 	if (index >= 0 && index <= 3) {
1830 		*lenp = pciide_bar[index].length;
1831 
1832 		if (progcl & pciide_bar[index].native_mask) {
1833 			*basep += pciide_bar[index].bar_offset;
1834 		} else {
1835 			*basep = pciide_bar[index].addr;
1836 			hard_decode = 1;
1837 		}
1838 	}
1839 
1840 	/*
1841 	 * if either base or len is zero make certain both are zero
1842 	 */
1843 	if (*basep == 0 || *lenp == 0) {
1844 		*basep = 0;
1845 		*lenp = 0;
1846 		hard_decode = 0;
1847 	}
1848 
1849 	return (hard_decode);
1850 }
1851 
1852 
1853 /*
1854  * Add the "reg" and "assigned-addresses" property
1855  */
1856 static int
1857 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
1858     int config_op, int pciide)
1859 {
1860 	uchar_t baseclass, subclass, progclass, header;
1861 	ushort_t bar_sz;
1862 	uint_t value = 0, len, devloc;
1863 	uint_t base, base_hi, type;
1864 	ushort_t offset, end;
1865 	int max_basereg, j, reprogram = 0;
1866 	uint_t phys_hi;
1867 	struct memlist **io_res, **mres, **mem_res, **pmem_res;
1868 	struct memlist **io_res_used, **mres_used;
1869 	struct memlist **mem_res_used, **pmem_res_used;
1870 	uchar_t res_bus;
1871 
1872 	pci_regspec_t regs[16] = {{0}};
1873 	pci_regspec_t assigned[15] = {{0}};
1874 	int nreg, nasgn;
1875 
1876 	io_res = &pci_bus_res[bus].io_ports;
1877 	io_res_used = &pci_bus_res[bus].io_ports_used;
1878 	mem_res = &pci_bus_res[bus].mem_space;
1879 	mem_res_used = &pci_bus_res[bus].mem_space_used;
1880 	if (bus == 0) {	/* for bus 0, there is only mem_space */
1881 		pmem_res = mem_res;
1882 		pmem_res_used = mem_res_used;
1883 	} else {
1884 		pmem_res = &pci_bus_res[bus].pmem_space;
1885 		pmem_res_used = &pci_bus_res[bus].pmem_space_used;
1886 	}
1887 
1888 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
1889 	regs[0].pci_phys_hi = devloc;
1890 	nreg = 1;	/* rest of regs[0] is all zero */
1891 	nasgn = 0;
1892 
1893 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
1894 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
1895 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
1896 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1897 
1898 	switch (header) {
1899 	case PCI_HEADER_ZERO:
1900 		max_basereg = PCI_BASE_NUM;
1901 		break;
1902 	case PCI_HEADER_PPB:
1903 		max_basereg = PCI_BCNF_BASE_NUM;
1904 		break;
1905 	case PCI_HEADER_CARDBUS:
1906 		max_basereg = PCI_CBUS_BASE_NUM;
1907 		break;
1908 	default:
1909 		max_basereg = 0;
1910 		break;
1911 	}
1912 
1913 	/*
1914 	 * Create the register property by saving the current
1915 	 * value of the base register. Write 0xffffffff to the
1916 	 * base register.  Read the value back to determine the
1917 	 * required size of the address space.  Restore the base
1918 	 * register contents.
1919 	 *
1920 	 * Do not disable I/O and memory access; this isn't necessary
1921 	 * since no driver is yet attached to this device, and disabling
1922 	 * I/O and memory access has the side-effect of disabling PCI-PCI
1923 	 * bridge mappings, which makes the bridge transparent to secondary-
1924 	 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge
1925 	 * Spec V1.2).
1926 	 */
1927 	end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
1928 	for (j = 0, offset = PCI_CONF_BASE0; offset < end;
1929 	    j++, offset += bar_sz) {
1930 		int hard_decode = 0;
1931 
1932 		/* determine the size of the address space */
1933 		base = pci_getl(bus, dev, func, offset);
1934 		pci_putl(bus, dev, func, offset, 0xffffffff);
1935 		value = pci_getl(bus, dev, func, offset);
1936 		pci_putl(bus, dev, func, offset, base);
1937 
1938 		/* construct phys hi,med.lo, size hi, lo */
1939 		if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) {
1940 			/* i/o space */
1941 			bar_sz = PCI_BAR_SZ_32;
1942 			value &= PCI_BASE_IO_ADDR_M;
1943 			len = ((value ^ (value-1)) + 1) >> 1;
1944 
1945 			/* XXX Adjust first 4 IDE registers */
1946 			if (pciide) {
1947 				if (subclass != PCI_MASS_IDE)
1948 					progclass = (PCI_IDE_IF_NATIVE_PRI |
1949 					    PCI_IDE_IF_NATIVE_SEC);
1950 				hard_decode = pciIdeAdjustBAR(progclass, j,
1951 				    &base, &len);
1952 			} else if (value == 0) {
1953 				/* skip base regs with size of 0 */
1954 				continue;
1955 			}
1956 
1957 			regs[nreg].pci_size_low =
1958 			    assigned[nasgn].pci_size_low = len;
1959 			if (!hard_decode) {
1960 				regs[nreg].pci_phys_hi =
1961 				    (PCI_ADDR_IO | devloc) + offset;
1962 			} else {
1963 				regs[nreg].pci_phys_hi =
1964 				    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) +
1965 				    offset;
1966 				regs[nreg].pci_phys_low =
1967 				    base & PCI_BASE_IO_ADDR_M;
1968 			}
1969 			assigned[nasgn].pci_phys_hi =
1970 			    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset;
1971 			type = base & (~PCI_BASE_IO_ADDR_M);
1972 			base &= PCI_BASE_IO_ADDR_M;
1973 			/*
1974 			 * A device under a subtractive PPB can allocate
1975 			 * resources from its parent bus if there is no resource
1976 			 * available on its own bus.
1977 			 */
1978 			if ((config_op == CONFIG_NEW) && (*io_res == NULL)) {
1979 				res_bus = bus;
1980 				while (pci_bus_res[res_bus].subtractive) {
1981 					res_bus = pci_bus_res[res_bus].par_bus;
1982 					if (res_bus == (uchar_t)-1)
1983 						break; /* root bus already */
1984 					if (pci_bus_res[res_bus].io_ports) {
1985 						io_res = &pci_bus_res
1986 						    [res_bus].io_ports;
1987 						break;
1988 					}
1989 				}
1990 			}
1991 
1992 			/*
1993 			 * first pass - gather what's there
1994 			 * update/second pass - adjust/allocate regions
1995 			 *	config - allocate regions
1996 			 */
1997 			if (config_op == CONFIG_INFO) {	/* first pass */
1998 				/* take out of the resource map of the bus */
1999 				if (base != 0) {
2000 					if (*io_res)
2001 						(void) memlist_remove(io_res,
2002 						    base, len);
2003 					memlist_insert(io_res_used, base, len);
2004 				} else
2005 					reprogram = 1;
2006 			} else if ((*io_res && base == 0) ||
2007 			    pci_bus_res[bus].io_reprogram) {
2008 				base = (uint_t)memlist_find(io_res, len, len);
2009 				if (base != 0) {
2010 					memlist_insert(io_res_used, base, len);
2011 					/* XXX need to worry about 64-bit? */
2012 					pci_putl(bus, dev, func, offset,
2013 					    base | type);
2014 					base = pci_getl(bus, dev, func, offset);
2015 					base &= PCI_BASE_IO_ADDR_M;
2016 				}
2017 				if (base == 0) {
2018 					cmn_err(CE_WARN, "failed to program"
2019 					    " IO space [%d/%d/%d] BAR@0x%x"
2020 					    " length 0x%x",
2021 					    bus, dev, func, offset, len);
2022 				}
2023 			}
2024 			assigned[nasgn].pci_phys_low = base;
2025 			nreg++, nasgn++;
2026 
2027 		} else {
2028 			/* memory space */
2029 			if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) {
2030 				bar_sz = PCI_BAR_SZ_64;
2031 				base_hi = pci_getl(bus, dev, func, offset + 4);
2032 				phys_hi = PCI_ADDR_MEM64;
2033 			} else {
2034 				bar_sz = PCI_BAR_SZ_32;
2035 				base_hi = 0;
2036 				phys_hi = PCI_ADDR_MEM32;
2037 			}
2038 
2039 			/* skip base regs with size of 0 */
2040 			value &= PCI_BASE_M_ADDR_M;
2041 
2042 			if (value == 0) {
2043 				continue;
2044 			}
2045 			len = ((value ^ (value-1)) + 1) >> 1;
2046 			regs[nreg].pci_size_low =
2047 			    assigned[nasgn].pci_size_low = len;
2048 
2049 			phys_hi |= (devloc | offset);
2050 			if (base & PCI_BASE_PREF_M) {
2051 				mres = pmem_res;
2052 				mres_used = pmem_res_used;
2053 				phys_hi |= PCI_PREFETCH_B;
2054 			} else {
2055 				mres = mem_res;
2056 				mres_used = mem_res_used;
2057 			}
2058 			/*
2059 			 * A device under a subtractive PPB can allocate
2060 			 * resources from its parent bus if there is no resource
2061 			 * available on its own bus.
2062 			 */
2063 			if ((config_op == CONFIG_NEW) && (*mres == NULL)) {
2064 				res_bus = bus;
2065 				while (pci_bus_res[res_bus].subtractive) {
2066 					res_bus = pci_bus_res[res_bus].par_bus;
2067 					if (res_bus == (uchar_t)-1)
2068 						break; /* root bus already */
2069 					mem_res =
2070 					    &pci_bus_res[res_bus].mem_space;
2071 					if (res_bus == 0)
2072 						pmem_res = mem_res;
2073 					else
2074 						pmem_res = &pci_bus_res
2075 						    [res_bus].pmem_space;
2076 					if (phys_hi & PCI_PREFETCH_B)
2077 						mres = pmem_res;
2078 					else
2079 						mres = mem_res;
2080 					if (*mres)
2081 						break;
2082 				}
2083 			}
2084 
2085 			regs[nreg].pci_phys_hi =
2086 			    assigned[nasgn].pci_phys_hi = phys_hi;
2087 			assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
2088 			assigned[nasgn].pci_phys_mid = base_hi;
2089 			type = base & ~PCI_BASE_M_ADDR_M;
2090 			base &= PCI_BASE_M_ADDR_M;
2091 
2092 			if (config_op == CONFIG_INFO) {
2093 				/* take out of the resource map of the bus */
2094 				if (base != 0) {
2095 					if (*mem_res) {
2096 						/* remove it from MEM space */
2097 						(void) memlist_remove(mem_res,
2098 						    base, len);
2099 					}
2100 					if (mem_res != pmem_res && *pmem_res) {
2101 						/* remove it from PMEM space */
2102 						(void) memlist_remove(pmem_res,
2103 						    base, len);
2104 					}
2105 					memlist_insert(mres_used, base, len);
2106 				} else
2107 					reprogram = 1;
2108 			} else if ((*mres && base == 0) ||
2109 			    pci_bus_res[bus].mem_reprogram) {
2110 				base = (uint_t)memlist_find(mres, len, len);
2111 				if (base != NULL) {
2112 					if (mres != mem_res && *mem_res) {
2113 						/* remove it from MEM space */
2114 						(void) memlist_remove(mem_res,
2115 						    base, len);
2116 					} else if (mres != pmem_res &&
2117 					    *pmem_res) {
2118 						/* remove it from PMEM space */
2119 						(void) memlist_remove(pmem_res,
2120 						    base, len);
2121 					}
2122 					memlist_insert(mres_used, base, len);
2123 					pci_putl(bus, dev, func, offset,
2124 					    base | type);
2125 					base = pci_getl(bus, dev, func, offset);
2126 					base &= PCI_BASE_M_ADDR_M;
2127 				}
2128 
2129 				if (base == 0) {
2130 					cmn_err(CE_WARN, "failed to program "
2131 					    "mem space [%d/%d/%d] BAR@0x%x"
2132 					    " length 0x%x",
2133 					    bus, dev, func, offset, len);
2134 				}
2135 			}
2136 			assigned[nasgn].pci_phys_low = base;
2137 			nreg++, nasgn++;
2138 		}
2139 	}
2140 	switch (header) {
2141 	case PCI_HEADER_ZERO:
2142 		offset = PCI_CONF_ROM;
2143 		break;
2144 	case PCI_HEADER_PPB:
2145 		offset = PCI_BCNF_ROM;
2146 		break;
2147 	default: /* including PCI_HEADER_CARDBUS */
2148 		goto done;
2149 	}
2150 
2151 	/*
2152 	 * Add the expansion rom memory space
2153 	 * Determine the size of the ROM base reg; don't write reserved bits
2154 	 * ROM isn't in the PCI memory space.
2155 	 */
2156 	base = pci_getl(bus, dev, func, offset);
2157 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2158 	value = pci_getl(bus, dev, func, offset);
2159 	pci_putl(bus, dev, func, offset, base);
2160 	if (value & PCI_BASE_ROM_ENABLE)
2161 		value &= PCI_BASE_ROM_ADDR_M;
2162 	else
2163 		value = 0;
2164 
2165 	if (value != 0) {
2166 		regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
2167 		assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
2168 		    PCI_ADDR_MEM32 | devloc) + offset;
2169 		base &= PCI_BASE_ROM_ADDR_M;
2170 		assigned[nasgn].pci_phys_low = base;
2171 		len = ((value ^ (value-1)) + 1) >> 1;
2172 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len;
2173 		nreg++, nasgn++;
2174 		/* take it out of the memory resource */
2175 		if (*mem_res && base != 0)
2176 			(void) memlist_remove(mem_res, base, len);
2177 		if (base != 0)
2178 			memlist_insert(mem_res, base, len);
2179 	}
2180 
2181 	/*
2182 	 * The following are ISA resources. There are not part
2183 	 * of the PCI local bus resources. So don't attempt to
2184 	 * do resource accounting against PCI.
2185 	 */
2186 
2187 	/* add the three hard-decode, aliased address spaces for VGA */
2188 	if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) ||
2189 	    (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) {
2190 
2191 		/* VGA hard decode 0x3b0-0x3bb */
2192 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2193 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2194 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0;
2195 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc;
2196 		nreg++, nasgn++;
2197 
2198 		/* VGA hard decode 0x3c0-0x3df */
2199 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2200 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2201 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0;
2202 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20;
2203 		nreg++, nasgn++;
2204 
2205 		/* Video memory */
2206 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2207 		    (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc);
2208 		regs[nreg].pci_phys_low =
2209 		    assigned[nasgn].pci_phys_low = 0xa0000;
2210 		regs[nreg].pci_size_low =
2211 		    assigned[nasgn].pci_size_low = 0x20000;
2212 		nreg++, nasgn++;
2213 	}
2214 
2215 	/* add the hard-decode, aliased address spaces for 8514 */
2216 	if ((baseclass == PCI_CLASS_DISPLAY) &&
2217 	    (subclass == PCI_DISPLAY_VGA) &&
2218 	    (progclass & PCI_DISPLAY_IF_8514)) {
2219 
2220 		/* hard decode 0x2e8 */
2221 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2222 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2223 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8;
2224 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1;
2225 		nreg++, nasgn++;
2226 
2227 		/* hard decode 0x2ea-0x2ef */
2228 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2229 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2230 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea;
2231 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6;
2232 		nreg++, nasgn++;
2233 	}
2234 
2235 done:
2236 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
2237 	    (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int));
2238 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
2239 	    "assigned-addresses",
2240 	    (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int));
2241 
2242 	return (reprogram);
2243 }
2244 
2245 static void
2246 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2247     int pciex, ushort_t is_pci_bridge)
2248 {
2249 	char *dev_type;
2250 	int i;
2251 	uint_t val, io_range[2], mem_range[2], pmem_range[2];
2252 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2253 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2254 	uchar_t progclass;
2255 
2256 	ASSERT(secbus <= subbus);
2257 
2258 	/*
2259 	 * Check if it's a subtractive PPB.
2260 	 */
2261 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2262 	if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
2263 		pci_bus_res[secbus].subtractive = B_TRUE;
2264 
2265 	/*
2266 	 * Some BIOSes lie about max pci busses, we allow for
2267 	 * such mistakes here
2268 	 */
2269 	if (subbus > pci_bios_nbus) {
2270 		pci_bios_nbus = subbus;
2271 		alloc_res_array();
2272 	}
2273 
2274 	ASSERT(pci_bus_res[secbus].dip == NULL);
2275 	pci_bus_res[secbus].dip = dip;
2276 	pci_bus_res[secbus].par_bus = bus;
2277 
2278 	dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci";
2279 
2280 	/* setup bus number hierarchy */
2281 	pci_bus_res[secbus].sub_bus = subbus;
2282 	/*
2283 	 * Keep track of the largest subordinate bus number (this is essential
2284 	 * for peer busses because there is no other way of determining its
2285 	 * subordinate bus number).
2286 	 */
2287 	if (subbus > pci_bus_res[bus].sub_bus)
2288 		pci_bus_res[bus].sub_bus = subbus;
2289 	/*
2290 	 * Loop through subordinate busses, initializing their parent bus
2291 	 * field to this bridge's parent.  The subordinate busses' parent
2292 	 * fields may very well be further refined later, as child bridges
2293 	 * are enumerated.  (The value is to note that the subordinate busses
2294 	 * are not peer busses by changing their par_bus fields to anything
2295 	 * other than -1.)
2296 	 */
2297 	for (i = secbus + 1; i <= subbus; i++)
2298 		pci_bus_res[i].par_bus = bus;
2299 
2300 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2301 	    "device_type", dev_type);
2302 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2303 	    "#address-cells", 3);
2304 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2305 	    "#size-cells", 2);
2306 
2307 	/*
2308 	 * According to PPB spec, the base register should be programmed
2309 	 * with a value bigger than the limit register when there are
2310 	 * no resources available. This applies to io, memory, and
2311 	 * prefetchable memory.
2312 	 */
2313 
2314 	/*
2315 	 * io range
2316 	 * We determine i/o windows that are left unconfigured by BIOS
2317 	 * through its i/o enable bit as Microsoft recommends OEMs to do.
2318 	 * If it is unset, we disable i/o and mark it for reconfiguration in
2319 	 * later passes by setting the base > limit
2320 	 */
2321 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
2322 	if (val & PCI_COMM_IO) {
2323 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
2324 		io_range[0] = ((val & 0xf0) << 8);
2325 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
2326 		io_range[1]  = ((val & 0xf0) << 8) | 0xFFF;
2327 	} else {
2328 		io_range[0] = 0x9fff;
2329 		io_range[1] = 0x1000;
2330 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
2331 		    (uint8_t)((io_range[0] >> 8) & 0xf0));
2332 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
2333 		    (uint8_t)((io_range[1] >> 8) & 0xf0));
2334 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
2335 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
2336 	}
2337 
2338 	if (io_range[0] != 0 && io_range[0] < io_range[1]) {
2339 		memlist_insert(&pci_bus_res[secbus].io_ports,
2340 		    (uint64_t)io_range[0],
2341 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2342 		memlist_insert(&pci_bus_res[bus].io_ports_used,
2343 		    (uint64_t)io_range[0],
2344 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2345 		if (pci_bus_res[bus].io_ports != NULL) {
2346 			(void) memlist_remove(&pci_bus_res[bus].io_ports,
2347 			    (uint64_t)io_range[0],
2348 			    (uint64_t)(io_range[1] - io_range[0] + 1));
2349 		}
2350 		dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x",
2351 		    secbus, io_range[0], io_range[1]);
2352 		/* if 32-bit supported, make sure upper bits are not set */
2353 		if ((val & 0xf) == 1 &&
2354 		    pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) {
2355 			cmn_err(CE_NOTE, "unsupported 32-bit IO address on"
2356 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2357 		}
2358 	}
2359 
2360 	/* mem range */
2361 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
2362 	mem_range[0] = ((val & 0xFFF0) << 16);
2363 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
2364 	mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2365 	if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) {
2366 		memlist_insert(&pci_bus_res[secbus].mem_space,
2367 		    (uint64_t)mem_range[0],
2368 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2369 		memlist_insert(&pci_bus_res[bus].mem_space_used,
2370 		    (uint64_t)mem_range[0],
2371 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2372 		/* remove from parent resource list */
2373 		if (pci_bus_res[bus].mem_space != NULL) {
2374 			(void) memlist_remove(&pci_bus_res[bus].mem_space,
2375 			    (uint64_t)mem_range[0],
2376 			    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2377 		}
2378 		if (pci_bus_res[bus].pmem_space != NULL) {
2379 			(void) memlist_remove(&pci_bus_res[bus].pmem_space,
2380 			    (uint64_t)mem_range[0],
2381 			    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2382 		}
2383 		dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x",
2384 		    secbus, mem_range[0], mem_range[1]);
2385 	}
2386 
2387 	/* prefetchable memory range */
2388 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
2389 	pmem_range[0] = ((val & 0xFFF0) << 16);
2390 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
2391 	pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2392 	if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) {
2393 		memlist_insert(&pci_bus_res[secbus].pmem_space,
2394 		    (uint64_t)pmem_range[0],
2395 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2396 		memlist_insert(&pci_bus_res[bus].pmem_space_used,
2397 		    (uint64_t)pmem_range[0],
2398 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2399 		/* remove from parent resource list */
2400 		if (pci_bus_res[bus].pmem_space != NULL) {
2401 			(void) memlist_remove(&pci_bus_res[bus].pmem_space,
2402 			    (uint64_t)pmem_range[0],
2403 			    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2404 		}
2405 		if (pci_bus_res[bus].mem_space != NULL) {
2406 			(void) memlist_remove(&pci_bus_res[bus].mem_space,
2407 			    (uint64_t)pmem_range[0],
2408 			    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2409 		}
2410 		dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x",
2411 		    secbus, pmem_range[0], pmem_range[1]);
2412 		/* if 64-bit supported, make sure upper bits are not set */
2413 		if ((val & 0xf) == 1 &&
2414 		    pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) {
2415 			cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on"
2416 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2417 		}
2418 	}
2419 
2420 	add_bus_range_prop(secbus);
2421 	add_ppb_ranges_prop(secbus);
2422 }
2423 
2424 extern const struct pci_class_strings_s class_pci[];
2425 extern int class_pci_items;
2426 
2427 static void
2428 add_model_prop(dev_info_t *dip, uint_t classcode)
2429 {
2430 	const char *desc;
2431 	int i;
2432 	uchar_t baseclass = classcode >> 16;
2433 	uchar_t subclass = (classcode >> 8) & 0xff;
2434 	uchar_t progclass = classcode & 0xff;
2435 
2436 	if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) {
2437 		desc = "IDE controller";
2438 	} else {
2439 		for (desc = 0, i = 0; i < class_pci_items; i++) {
2440 			if ((baseclass == class_pci[i].base_class) &&
2441 			    (subclass == class_pci[i].sub_class) &&
2442 			    (progclass == class_pci[i].prog_class)) {
2443 				desc = class_pci[i].actual_desc;
2444 				break;
2445 			}
2446 		}
2447 		if (i == class_pci_items)
2448 			desc = "Unknown class of pci/pnpbios device";
2449 	}
2450 
2451 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
2452 	    (char *)desc);
2453 }
2454 
2455 static void
2456 add_bus_range_prop(int bus)
2457 {
2458 	int bus_range[2];
2459 
2460 	if (pci_bus_res[bus].dip == NULL)
2461 		return;
2462 	bus_range[0] = bus;
2463 	bus_range[1] = pci_bus_res[bus].sub_bus;
2464 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2465 	    "bus-range", (int *)bus_range, 2);
2466 }
2467 
2468 /*
2469  * Add slot-names property for any named pci hot-plug slots
2470  */
2471 static void
2472 add_bus_slot_names_prop(int bus)
2473 {
2474 	char slotprop[256];
2475 	int len;
2476 
2477 	if (pci_bus_res[bus].dip != NULL) {
2478 		/* simply return if the property is already defined */
2479 		if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip,
2480 		    DDI_PROP_DONTPASS, "slot-names"))
2481 			return;
2482 	}
2483 
2484 	len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop));
2485 	if (len > 0) {
2486 		/*
2487 		 * Only create a peer bus node if this bus may be a peer bus.
2488 		 * It may be a peer bus if the dip is NULL and if par_bus is
2489 		 * -1 (par_bus is -1 if this bus was not found to be
2490 		 * subordinate to any PCI-PCI bridge).
2491 		 * If it's not a peer bus, then the ACPI BBN-handling code
2492 		 * will remove it later.
2493 		 */
2494 		if (pci_bus_res[bus].par_bus == (uchar_t)-1 &&
2495 		    pci_bus_res[bus].dip == NULL) {
2496 
2497 			create_root_bus_dip(bus);
2498 		}
2499 		if (pci_bus_res[bus].dip != NULL) {
2500 			ASSERT((len % sizeof (int)) == 0);
2501 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
2502 			    pci_bus_res[bus].dip, "slot-names",
2503 			    (int *)slotprop, len / sizeof (int));
2504 		} else {
2505 			cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI "
2506 			    "IRQ routing table; Not adding slot-names "
2507 			    "property for incorrect bus %d", bus);
2508 		}
2509 	}
2510 }
2511 
2512 static int
2513 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type)
2514 {
2515 	if (entry == NULL)
2516 		return (0);
2517 
2518 	/* assume 32-bit addresses */
2519 	rp->child_high = rp->parent_high = type;
2520 	rp->child_mid = rp->parent_mid = 0;
2521 	rp->child_low = rp->parent_low = (uint32_t)entry->address;
2522 	rp->size_high = 0;
2523 	rp->size_low = (uint32_t)entry->size;
2524 	return (1);
2525 }
2526 
2527 static void
2528 add_ppb_ranges_prop(int bus)
2529 {
2530 	int i = 0;
2531 	ppb_ranges_t *rp;
2532 
2533 	rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP);
2534 
2535 	i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports,
2536 	    PCI_ADDR_IO | PCI_REG_REL_M);
2537 	i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space,
2538 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
2539 	i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space,
2540 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
2541 
2542 	if (i != 0)
2543 		(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
2544 		    pci_bus_res[bus].dip, "ranges", (int *)rp,
2545 		    i * sizeof (ppb_ranges_t) / sizeof (int));
2546 	kmem_free(rp, 3 * sizeof (*rp));
2547 }
2548 
2549 static int
2550 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type)
2551 {
2552 	int i = 0;
2553 
2554 	while (list) {
2555 		/* assume 32-bit addresses */
2556 		sp->pci_phys_hi = type;
2557 		sp->pci_phys_mid = 0;
2558 		sp->pci_phys_low = (uint32_t)list->address;
2559 		sp->pci_size_hi = 0;
2560 		sp->pci_size_low = (uint32_t)list->size;
2561 
2562 		list = list->next;
2563 		sp++, i++;
2564 	}
2565 	return (i);
2566 }
2567 
2568 static void
2569 add_bus_available_prop(int bus)
2570 {
2571 	int i, count;
2572 	struct pci_phys_spec *sp;
2573 
2574 	count = memlist_count(pci_bus_res[bus].io_ports) +
2575 	    memlist_count(pci_bus_res[bus].mem_space) +
2576 	    memlist_count(pci_bus_res[bus].pmem_space);
2577 
2578 	if (count == 0)		/* nothing available */
2579 		return;
2580 
2581 	sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP);
2582 	i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports,
2583 	    PCI_ADDR_IO | PCI_REG_REL_M);
2584 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space,
2585 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
2586 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space,
2587 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
2588 	ASSERT(i == count);
2589 
2590 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2591 	    "available", (int *)sp,
2592 	    i * sizeof (struct pci_phys_spec) / sizeof (int));
2593 	kmem_free(sp, count * sizeof (*sp));
2594 }
2595 
2596 static void
2597 alloc_res_array(void)
2598 {
2599 	static int array_max = 0;
2600 	int old_max;
2601 	void *old_res;
2602 
2603 	if (array_max > pci_bios_nbus + 1)
2604 		return;	/* array is big enough */
2605 
2606 	old_max = array_max;
2607 	old_res = pci_bus_res;
2608 
2609 	if (array_max == 0)
2610 		array_max = 16;	/* start with a reasonable number */
2611 
2612 	while (array_max < pci_bios_nbus + 1)
2613 		array_max <<= 1;
2614 	pci_bus_res = (struct pci_bus_resource *)kmem_zalloc(
2615 	    array_max * sizeof (struct pci_bus_resource), KM_SLEEP);
2616 
2617 	if (old_res) {	/* copy content and free old array */
2618 		bcopy(old_res, pci_bus_res,
2619 		    old_max * sizeof (struct pci_bus_resource));
2620 		kmem_free(old_res, old_max * sizeof (struct pci_bus_resource));
2621 	}
2622 }
2623 
2624 static void
2625 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
2626     ushort_t deviceid)
2627 {
2628 	static dev_info_t *ioapicsnode = NULL;
2629 	static int numioapics = 0;
2630 	dev_info_t *ioapic_node;
2631 	uint64_t physaddr;
2632 	uint32_t lobase, hibase = 0;
2633 
2634 	/* BAR 0 contains the IOAPIC's memory-mapped I/O address */
2635 	lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
2636 
2637 	/* We (and the rest of the world) only support memory-mapped IOAPICs */
2638 	if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM)
2639 		return;
2640 
2641 	if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL)
2642 		hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
2643 
2644 	lobase &= PCI_BASE_M_ADDR_M;
2645 
2646 	physaddr = (((uint64_t)hibase) << 32) | lobase;
2647 
2648 	/*
2649 	 * Create a nexus node for all IOAPICs under the root node.
2650 	 */
2651 	if (ioapicsnode == NULL) {
2652 		if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME,
2653 		    (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) {
2654 			return;
2655 		}
2656 		(void) ndi_devi_online(ioapicsnode, 0);
2657 	}
2658 
2659 	/*
2660 	 * Create a child node for this IOAPIC
2661 	 */
2662 	ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME,
2663 	    DEVI_SID_NODEID, numioapics++);
2664 	if (ioapic_node == NULL) {
2665 		return;
2666 	}
2667 
2668 	/* Vendor and Device ID */
2669 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2670 	    IOAPICS_PROP_VENID, vendorid);
2671 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2672 	    IOAPICS_PROP_DEVID, deviceid);
2673 
2674 	/* device_type */
2675 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node,
2676 	    "device_type", IOAPICS_DEV_TYPE);
2677 
2678 	/* reg */
2679 	(void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node,
2680 	    "reg", physaddr);
2681 }
2682 
2683 /*
2684  * NOTE: For PCIe slots, the name is generated from the slot number
2685  * information obtained from Slot Capabilities register.
2686  * For non-PCIe slots, it is generated based on the slot number
2687  * information in the PCI IRQ table.
2688  */
2689 static void
2690 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num)
2691 {
2692 	char slotprop[256];
2693 	int len;
2694 
2695 	bzero(slotprop, sizeof (slotprop));
2696 
2697 	/* set mask to 1 as there is only one slot (i.e dev 0) */
2698 	*(uint32_t *)slotprop = 1;
2699 	len = 4;
2700 	(void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d",
2701 	    slot_num);
2702 	len += strlen(slotprop + len) + 1;
2703 	len += len % 4;
2704 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names",
2705 	    (int *)slotprop, len / sizeof (int));
2706 }
2707