1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/sysmacros.h> 28 #include <sys/disp.h> 29 #include <sys/promif.h> 30 #include <sys/clock.h> 31 #include <sys/cpuvar.h> 32 #include <sys/stack.h> 33 #include <vm/as.h> 34 #include <vm/hat.h> 35 #include <sys/reboot.h> 36 #include <sys/avintr.h> 37 #include <sys/vtrace.h> 38 #include <sys/proc.h> 39 #include <sys/thread.h> 40 #include <sys/cpupart.h> 41 #include <sys/pset.h> 42 #include <sys/copyops.h> 43 #include <sys/pg.h> 44 #include <sys/disp.h> 45 #include <sys/debug.h> 46 #include <sys/sunddi.h> 47 #include <sys/x86_archext.h> 48 #include <sys/privregs.h> 49 #include <sys/machsystm.h> 50 #include <sys/ontrap.h> 51 #include <sys/bootconf.h> 52 #include <sys/kdi_machimpl.h> 53 #include <sys/archsystm.h> 54 #include <sys/promif.h> 55 #include <sys/bootconf.h> 56 #include <sys/kobj.h> 57 #include <sys/kobj_lex.h> 58 #include <sys/pci_cfgspace.h> 59 #ifdef __xpv 60 #include <sys/hypervisor.h> 61 #endif 62 63 /* 64 * some globals for patching the result of cpuid 65 * to solve problems w/ creative cpu vendors 66 */ 67 68 extern uint32_t cpuid_feature_ecx_include; 69 extern uint32_t cpuid_feature_ecx_exclude; 70 extern uint32_t cpuid_feature_edx_include; 71 extern uint32_t cpuid_feature_edx_exclude; 72 73 /* 74 * Dummy spl priority masks 75 */ 76 static unsigned char dummy_cpu_pri[MAXIPL + 1] = { 77 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 78 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf 79 }; 80 81 82 static uint32_t 83 bootprop_getval(char *name) 84 { 85 char prop[32]; 86 u_longlong_t ll; 87 extern struct bootops *bootops; 88 if ((BOP_GETPROPLEN(bootops, name) > sizeof (prop)) || 89 (BOP_GETPROP(bootops, name, prop) < 0) || 90 (kobj_getvalue(prop, &ll) == -1)) 91 return (0); 92 return ((uint32_t)ll); 93 } 94 95 /* 96 * Setup routine called right before main(). Interposing this function 97 * before main() allows us to call it in a machine-independent fashion. 98 */ 99 void 100 mlsetup(struct regs *rp) 101 { 102 extern struct classfuncs sys_classfuncs; 103 extern disp_t cpu0_disp; 104 extern char t0stack[]; 105 106 ASSERT_STACK_ALIGNED(); 107 108 /* 109 * initialize cpu_self 110 */ 111 cpu[0]->cpu_self = cpu[0]; 112 113 #if defined(__xpv) 114 /* 115 * Point at the hypervisor's virtual cpu structure 116 */ 117 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 118 #endif 119 120 /* 121 * Set up dummy cpu_pri_data values till psm spl code is 122 * installed. This allows splx() to work on amd64. 123 */ 124 125 cpu[0]->cpu_pri_data = dummy_cpu_pri; 126 127 /* 128 * check if we've got special bits to clear or set 129 * when checking cpu features 130 */ 131 132 cpuid_feature_ecx_include = 133 bootprop_getval("cpuid_feature_ecx_include"); 134 cpuid_feature_ecx_exclude = 135 bootprop_getval("cpuid_feature_ecx_exclude"); 136 cpuid_feature_edx_include = 137 bootprop_getval("cpuid_feature_edx_include"); 138 cpuid_feature_edx_exclude = 139 bootprop_getval("cpuid_feature_edx_exclude"); 140 141 /* 142 * The first lightweight pass (pass0) through the cpuid data 143 * was done in locore before mlsetup was called. Do the next 144 * pass in C code. 145 * 146 * The x86_feature bits are set here on the basis of the capabilities 147 * of the boot CPU. Note that if we choose to support CPUs that have 148 * different feature sets (at which point we would almost certainly 149 * want to set the feature bits to correspond to the feature 150 * minimum) this value may be altered. 151 */ 152 x86_feature = cpuid_pass1(cpu[0]); 153 154 /* 155 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 156 */ 157 init_desctbls(); 158 159 #if !defined(__xpv) 160 161 /* 162 * Patch the tsc_read routine with appropriate set of instructions, 163 * depending on the processor family and architecure, to read the 164 * time-stamp counter while ensuring no out-of-order execution. 165 * Patch it while the kernel text is still writable. 166 * 167 * Note: tsc_read is not patched for intel processors whose family 168 * is >6 and for amd whose family >f (in case they don't support rdtscp 169 * instruction, unlikely). By default tsc_read will use cpuid for 170 * serialization in such cases. The following code needs to be 171 * revisited if intel processors of family >= f retains the 172 * instruction serialization nature of mfence instruction. 173 * Note: tsc_read is not patched for x86 processors which do 174 * not support "mfence". By default tsc_read will use cpuid for 175 * serialization in such cases. 176 * 177 * The Xen hypervisor does not correctly report whether rdtscp is 178 * supported or not, so we must assume that it is not. 179 */ 180 if (get_hwenv() != HW_XEN_HVM && (x86_feature & X86_TSCP)) 181 patch_tsc_read(X86_HAVE_TSCP); 182 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 183 cpuid_getfamily(CPU) <= 0xf && (x86_feature & X86_SSE2) != 0) 184 patch_tsc_read(X86_TSC_MFENCE); 185 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 186 cpuid_getfamily(CPU) <= 6 && (x86_feature & X86_SSE2) != 0) 187 patch_tsc_read(X86_TSC_LFENCE); 188 189 #endif /* !__xpv */ 190 191 #if defined(__i386) && !defined(__xpv) 192 /* 193 * Some i386 processors do not implement the rdtsc instruction, 194 * or at least they do not implement it correctly. Patch them to 195 * return 0. 196 */ 197 if ((x86_feature & X86_TSC) == 0) 198 patch_tsc_read(X86_NO_TSC); 199 #endif /* __i386 && !__xpv */ 200 201 #if defined(__amd64) && !defined(__xpv) 202 patch_memops(cpuid_getvendor(CPU)); 203 #endif /* __amd64 && !__xpv */ 204 205 #if !defined(__xpv) 206 /* XXPV what, if anything, should be dorked with here under xen? */ 207 208 /* 209 * While we're thinking about the TSC, let's set up %cr4 so that 210 * userland can issue rdtsc, and initialize the TSC_AUX value 211 * (the cpuid) for the rdtscp instruction on appropriately 212 * capable hardware. 213 */ 214 if (x86_feature & X86_TSC) 215 setcr4(getcr4() & ~CR4_TSD); 216 217 if (x86_feature & X86_TSCP) 218 (void) wrmsr(MSR_AMD_TSCAUX, 0); 219 220 if (x86_feature & X86_DE) 221 setcr4(getcr4() | CR4_DE); 222 #endif /* __xpv */ 223 224 /* 225 * initialize t0 226 */ 227 t0.t_stk = (caddr_t)rp - MINFRAME; 228 t0.t_stkbase = t0stack; 229 t0.t_pri = maxclsyspri - 3; 230 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 231 t0.t_procp = &p0; 232 t0.t_plockp = &p0lock.pl_lock; 233 t0.t_lwp = &lwp0; 234 t0.t_forw = &t0; 235 t0.t_back = &t0; 236 t0.t_next = &t0; 237 t0.t_prev = &t0; 238 t0.t_cpu = cpu[0]; 239 t0.t_disp_queue = &cpu0_disp; 240 t0.t_bind_cpu = PBIND_NONE; 241 t0.t_bind_pset = PS_NONE; 242 t0.t_bindflag = (uchar_t)default_binding_mode; 243 t0.t_cpupart = &cp_default; 244 t0.t_clfuncs = &sys_classfuncs.thread; 245 t0.t_copyops = NULL; 246 THREAD_ONPROC(&t0, CPU); 247 248 lwp0.lwp_thread = &t0; 249 lwp0.lwp_regs = (void *)rp; 250 lwp0.lwp_procp = &p0; 251 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 252 253 p0.p_exec = NULL; 254 p0.p_stat = SRUN; 255 p0.p_flag = SSYS; 256 p0.p_tlist = &t0; 257 p0.p_stksize = 2*PAGESIZE; 258 p0.p_stkpageszc = 0; 259 p0.p_as = &kas; 260 p0.p_lockp = &p0lock; 261 p0.p_brkpageszc = 0; 262 p0.p_t1_lgrpid = LGRP_NONE; 263 p0.p_tr_lgrpid = LGRP_NONE; 264 sigorset(&p0.p_ignore, &ignoredefault); 265 266 CPU->cpu_thread = &t0; 267 bzero(&cpu0_disp, sizeof (disp_t)); 268 CPU->cpu_disp = &cpu0_disp; 269 CPU->cpu_disp->disp_cpu = CPU; 270 CPU->cpu_dispthread = &t0; 271 CPU->cpu_idle_thread = &t0; 272 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 273 CPU->cpu_dispatch_pri = t0.t_pri; 274 275 CPU->cpu_id = 0; 276 277 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 278 279 /* 280 * The kernel doesn't use LDTs unless a process explicitly requests one. 281 */ 282 p0.p_ldt_desc = null_sdesc; 283 284 /* 285 * Initialize thread/cpu microstate accounting 286 */ 287 init_mstate(&t0, LMS_SYSTEM); 288 init_cpu_mstate(CPU, CMS_SYSTEM); 289 290 /* 291 * Initialize lists of available and active CPUs. 292 */ 293 cpu_list_init(CPU); 294 295 pg_cpu_bootstrap(CPU); 296 297 /* 298 * Now that we have taken over the GDT, IDT and have initialized 299 * active CPU list it's time to inform kmdb if present. 300 */ 301 if (boothowto & RB_DEBUG) 302 kdi_idt_sync(); 303 304 /* 305 * If requested (boot -d) drop into kmdb. 306 * 307 * This must be done after cpu_list_init() on the 64-bit kernel 308 * since taking a trap requires that we re-compute gsbase based 309 * on the cpu list. 310 */ 311 if (boothowto & RB_DEBUGENTER) 312 kmdb_enter(); 313 314 cpu_vm_data_init(CPU); 315 316 /* lgrp_init() needs PCI config space access */ 317 #if defined(__xpv) 318 if (DOMAIN_IS_INITDOMAIN(xen_info)) 319 pci_cfgspace_init(); 320 #else 321 pci_cfgspace_init(); 322 #endif 323 324 rp->r_fp = 0; /* terminate kernel stack traces! */ 325 326 prom_init("kernel", (void *)NULL); 327 328 boot_ncpus = bootprop_getval("boot-ncpus"); 329 330 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 331 boot_ncpus = NCPU; 332 333 max_ncpus = boot_max_ncpus = boot_ncpus; 334 335 /* 336 * Initialize the lgrp framework 337 */ 338 lgrp_init(); 339 340 if (boothowto & RB_HALT) { 341 prom_printf("unix: kernel halted by -h flag\n"); 342 prom_enter_mon(); 343 } 344 345 ASSERT_STACK_ALIGNED(); 346 347 /* 348 * Fill out cpu_ucode_info. Update microcode if necessary. 349 */ 350 ucode_check(CPU); 351 352 if (workaround_errata(CPU) != 0) 353 panic("critical workaround(s) missing for boot cpu"); 354 } 355 356 357 void 358 mach_modpath(char *path, const char *filename) 359 { 360 /* 361 * Construct the directory path from the filename. 362 */ 363 364 int len; 365 char *p; 366 const char isastr[] = "/amd64"; 367 size_t isalen = strlen(isastr); 368 369 if ((p = strrchr(filename, '/')) == NULL) 370 return; 371 372 while (p > filename && *(p - 1) == '/') 373 p--; /* remove trailing '/' characters */ 374 if (p == filename) 375 p++; /* so "/" -is- the modpath in this case */ 376 377 /* 378 * Remove optional isa-dependent directory name - the module 379 * subsystem will put this back again (!) 380 */ 381 len = p - filename; 382 if (len > isalen && 383 strncmp(&filename[len - isalen], isastr, isalen) == 0) 384 p -= isalen; 385 386 /* 387 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 388 */ 389 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 390 (void) strncpy(path, filename, p - filename); 391 } 392