1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_IMPL_H 27 #define _SYS_NXGE_NXGE_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * NIU HV API version definitions. 37 */ 38 #define NIU_MAJOR_VER 1 39 #define NIU_MINOR_VER 1 40 41 /* 42 * NIU HV API v1.0 definitions 43 */ 44 #define N2NIU_RX_LP_CONF 0x142 45 #define N2NIU_RX_LP_INFO 0x143 46 #define N2NIU_TX_LP_CONF 0x144 47 #define N2NIU_TX_LP_INFO 0x145 48 49 #ifndef _ASM 50 51 #include <sys/types.h> 52 #include <sys/byteorder.h> 53 #include <sys/debug.h> 54 #include <sys/stropts.h> 55 #include <sys/stream.h> 56 #include <sys/strlog.h> 57 #ifndef COSIM 58 #include <sys/strsubr.h> 59 #endif 60 #include <sys/cmn_err.h> 61 #include <sys/vtrace.h> 62 #include <sys/kmem.h> 63 #include <sys/ddi.h> 64 #include <sys/sunddi.h> 65 #include <sys/strsun.h> 66 #include <sys/stat.h> 67 #include <sys/cpu.h> 68 #include <sys/kstat.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <sys/dlpi.h> 72 #include <inet/nd.h> 73 #include <netinet/in.h> 74 #include <sys/ethernet.h> 75 #include <sys/vlan.h> 76 #include <sys/pci.h> 77 #include <sys/taskq.h> 78 #include <sys/atomic.h> 79 80 #include <sys/nxge/nxge_defs.h> 81 #include <sys/nxge/nxge_hw.h> 82 #include <sys/nxge/nxge_mac.h> 83 #include <sys/nxge/nxge_mii.h> 84 #include <sys/nxge/nxge_fm.h> 85 #if !defined(IODIAG) 86 #include <sys/netlb.h> 87 #endif 88 89 #include <sys/ddi_intr.h> 90 91 #if defined(_KERNEL) 92 #include <sys/mac.h> 93 #include <sys/mac_impl.h> 94 #include <sys/mac_ether.h> 95 #endif 96 97 #if defined(sun4v) 98 #include <sys/hypervisor_api.h> 99 #include <sys/machsystm.h> 100 #include <sys/hsvc.h> 101 #endif 102 103 /* 104 * Handy macros (taken from bge driver) 105 */ 106 #define RBR_SIZE 4 107 #define DMA_COMMON_CHANNEL(area) ((area.dma_channel)) 108 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 109 #define DMA_COMMON_VPTR_INDEX(area, index) \ 110 (((char *)(area.kaddrp)) + \ 111 (index * RBR_SIZE)) 112 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 113 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 114 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 115 #define DMA_COMMON_IOADDR_INDEX(area, index) \ 116 ((area.dma_cookie.dmac_laddress) + \ 117 (index * RBR_SIZE)) 118 119 #define DMA_NPI_HANDLE(area) ((area.npi_handle) 120 121 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 122 (area).offset, (area).alength, \ 123 (flag))) 124 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 125 ((void) ddi_dma_sync((area).dma_handle,\ 126 (area.offset + bufoffset), len, \ 127 (flag))) 128 129 #define DMA_COMMON_SYNC_RBR_DESC(area, index, flag) \ 130 ((void) ddi_dma_sync((area).dma_handle,\ 131 (index * RBR_SIZE), RBR_SIZE, \ 132 (flag))) 133 134 #define DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag) \ 135 ((void) ddi_dma_sync((area).dma_handle,\ 136 (index * RBR_SIZE), count * RBR_SIZE, \ 137 (flag))) 138 #define DMA_COMMON_SYNC_ENTRY(area, index, flag) \ 139 ((void) ddi_dma_sync((area).dma_handle,\ 140 (index * (area).block_size), \ 141 (area).block_size, \ 142 (flag))) 143 144 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 145 #define NEXT_ENTRY_PTR(ptr, first, last) \ 146 ((ptr == last) ? first : (ptr + 1)) 147 148 /* 149 * NPI related macros 150 */ 151 #define NXGE_DEV_NPI_HANDLE(nxgep) (nxgep->npi_handle) 152 153 #define NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah) 154 #define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap) 155 156 #define NPI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_handle.regh = ah) 157 #define NPI_ADD_HANDLE_SET(nxgep, ap) \ 158 nxgep->npi_handle.is_vraddr = B_FALSE; \ 159 nxgep->npi_handle.function.instance = nxgep->instance; \ 160 nxgep->npi_handle.function.function = nxgep->function_num; \ 161 nxgep->npi_handle.nxgep = (void *) nxgep; \ 162 nxgep->npi_handle.regp = ap; 163 164 #define NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah) 165 #define NPI_REG_ADD_HANDLE_SET(nxgep, ap) \ 166 nxgep->npi_reg_handle.is_vraddr = B_FALSE; \ 167 nxgep->npi_handle.function.instance = nxgep->instance; \ 168 nxgep->npi_handle.function.function = nxgep->function_num; \ 169 nxgep->npi_reg_handle.nxgep = (void *) nxgep; \ 170 nxgep->npi_reg_handle.regp = ap; 171 172 #define NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah) 173 #define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap) 174 175 #define NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah) 176 #define NPI_VREG_ADD_HANDLE_SET(nxgep, ap) \ 177 nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \ 178 nxgep->npi_handle.function.instance = nxgep->instance; \ 179 nxgep->npi_handle.function.function = nxgep->function_num; \ 180 nxgep->npi_vreg_handle.nxgep = (void *) nxgep; \ 181 nxgep->npi_vreg_handle.regp = ap; 182 183 #define NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah) 184 #define NPI_V2REG_ADD_HANDLE_SET(nxgep, ap) \ 185 nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \ 186 nxgep->npi_handle.function.instance = nxgep->instance; \ 187 nxgep->npi_handle.function.function = nxgep->function_num; \ 188 nxgep->npi_v2reg_handle.nxgep = (void *) nxgep; \ 189 nxgep->npi_v2reg_handle.regp = ap; 190 191 #define NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh) 192 #define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp) 193 #define NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh) 194 #define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp) 195 #define NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh) 196 #define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp) 197 #define NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh) 198 #define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp) 199 #define NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh) 200 #define NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp) 201 #define NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh) 202 #define NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp) 203 204 #define NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah) 205 #define NPI_DMA_ACC_HANDLE_GET(dmap) (dmap->npi_handle.regh) 206 207 /* 208 * DMA handles. 209 */ 210 #define NXGE_DESC_D_HANDLE_GET(desc) (desc.dma_handle) 211 #define NXGE_DESC_D_IOADD_GET(desc) (desc.dma_cookie.dmac_laddress) 212 #define NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress) 213 #define NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress) 214 215 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 216 #define LDV2_ON_1(ldv, vector) ((vector >> (ldv - 64)) & 0x1) 217 #define LDV2_ON_2(ldv, vector) (((vector >> 5) >> (ldv - 64)) & 0x1) 218 219 typedef uint32_t nxge_status_t; 220 221 typedef enum { 222 IDLE, 223 PROGRESS, 224 CONFIGURED 225 } dev_func_shared_t; 226 227 typedef enum { 228 DVMA, 229 DMA, 230 SDMA 231 } dma_method_t; 232 233 typedef enum { 234 BKSIZE_4K, 235 BKSIZE_8K, 236 BKSIZE_16K, 237 BKSIZE_32K 238 } nxge_rx_block_size_t; 239 240 #ifdef TX_ONE_BUF 241 #define TX_BCOPY_MAX 1514 242 #else 243 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 244 #define TX_BCOPY_MAX 4096 245 #define TX_BCOPY_SIZE 4096 246 #else 247 #define TX_BCOPY_MAX 2048 248 #define TX_BCOPY_SIZE 2048 249 #endif 250 #endif 251 252 #define TX_STREAM_MIN 512 253 #define TX_FASTDVMA_MIN 1024 254 255 #define NXGE_ERROR_SHOW_MAX 0 256 257 /* 258 * Defaults 259 */ 260 #define NXGE_RDC_RCR_THRESHOLD 8 261 #define NXGE_RDC_RCR_TIMEOUT 16 262 263 #define NXGE_RDC_RCR_THRESHOLD_MAX 1024 264 #define NXGE_RDC_RCR_TIMEOUT_MAX 64 265 #define NXGE_RDC_RCR_THRESHOLD_MIN 1 266 #define NXGE_RDC_RCR_TIMEOUT_MIN 1 267 #define NXGE_RCR_FULL_HEADER 1 268 269 #define NXGE_IS_VLAN_PACKET(ptr) \ 270 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 271 htons(VLAN_ETHERTYPE)) 272 273 typedef enum { 274 NONE, 275 SMALL, 276 MEDIUM, 277 LARGE 278 } dma_size_t; 279 280 typedef enum { 281 USE_NONE, 282 USE_BCOPY, 283 USE_DVMA, 284 USE_DMA, 285 USE_SDMA 286 } dma_type_t; 287 288 typedef enum { 289 NOT_IN_USE, 290 HDR_BUF, 291 MTU_BUF, 292 RE_ASSEMBLY_BUF, 293 FREE_BUF 294 } rx_page_state_t; 295 296 struct _nxge_block_mv_t { 297 uint32_t msg_type; 298 dma_type_t dma_type; 299 }; 300 301 typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t; 302 303 typedef enum { 304 NIU_TYPE_NONE = 0, 305 306 NEPTUNE_4_1GC = 307 (NXGE_PORT_1G_COPPER | 308 (NXGE_PORT_1G_COPPER << 4) | 309 (NXGE_PORT_1G_COPPER << 8) | 310 (NXGE_PORT_1G_COPPER << 12)), 311 312 NEPTUNE_2_10GF = 313 (NXGE_PORT_10G_FIBRE | 314 (NXGE_PORT_10G_FIBRE << 4) | 315 (NXGE_PORT_NONE << 8) | 316 (NXGE_PORT_NONE << 12)), 317 318 NEPTUNE_2_10GF_2_1GC = 319 (NXGE_PORT_10G_FIBRE | 320 (NXGE_PORT_10G_FIBRE << 4) | 321 (NXGE_PORT_1G_COPPER << 8) | 322 (NXGE_PORT_1G_COPPER << 12)), 323 324 NEPTUNE_1_10GF_3_1GC = 325 (NXGE_PORT_10G_FIBRE | 326 (NXGE_PORT_1G_COPPER << 4) | 327 (NXGE_PORT_1G_COPPER << 8) | 328 (NXGE_PORT_1G_COPPER << 12)), 329 330 NEPTUNE_1_1GC_1_10GF_2_1GC = 331 (NXGE_PORT_1G_COPPER | 332 (NXGE_PORT_10G_FIBRE << 4) | 333 (NXGE_PORT_1G_COPPER << 8) | 334 (NXGE_PORT_1G_COPPER << 12)), 335 336 N2_NIU = 337 (NXGE_PORT_RSVD | 338 (NXGE_PORT_RSVD << 4) | 339 (NXGE_PORT_RSVD << 8) | 340 (NXGE_PORT_RSVD << 12)) 341 342 } niu_type_t; 343 344 typedef enum { 345 P_NEPTUNE_NONE, 346 P_NEPTUNE_ATLAS, 347 P_NEPTUNE_MARAMBA_P0, 348 P_NEPTUNE_MARAMBA_P1, 349 P_NEPTUNE_NIU 350 } platform_type_t; 351 352 #define NXGE_IS_VALID_NEPTUNE_TYPE(niu_type) \ 353 ((niu_type) == NEPTUNE_4_1GC || (niu_type) == NEPTUNE_2_10GF || \ 354 (niu_type) == NEPTUNE_2_10GF_2_1GC || \ 355 (niu_type) == NEPTUNE_1_10GF_3_1GC || \ 356 (niu_type) == NEPTUNE_1_1GC_1_10GF_2_1GC) 357 358 typedef enum { 359 CFG_DEFAULT = 0, /* default cfg */ 360 CFG_EQUAL, /* Equal */ 361 CFG_FAIR, /* Equal */ 362 CFG_CLASSIFY, 363 CFG_L2_CLASSIFY, 364 CFG_L3_CLASSIFY, 365 CFG_L3_DISTRIBUTE, 366 CFG_L3_WEB, 367 CFG_L3_TCAM, 368 CFG_NOT_SPECIFIED, 369 CFG_CUSTOM /* Custom */ 370 } cfg_type_t; 371 372 typedef enum { 373 NO_MSG = 0x0, /* No message output or storage. */ 374 CONSOLE = 0x1, /* Messages are go to the console. */ 375 BUFFER = 0x2, /* Messages are go to the system buffer. */ 376 CON_BUF = 0x3, /* Messages are go to the console and */ 377 /* system buffer. */ 378 VERBOSE = 0x4 /* Messages are go out only in VERBOSE node. */ 379 } out_msg_t, *p_out_msg_t; 380 381 typedef enum { 382 DBG_NO_MSG = 0x0, /* No message output or storage. */ 383 DBG_CONSOLE = 0x1, /* Messages are go to the console. */ 384 DBG_BUFFER = 0x2, /* Messages are go to the system buffer. */ 385 DBG_CON_BUF = 0x3, /* Messages are go to the console and */ 386 /* system buffer. */ 387 STR_LOG = 4 /* Sessage sent to streams logging driver. */ 388 } out_dbgmsg_t, *p_out_dbgmsg_t; 389 390 391 392 #if defined(_KERNEL) || defined(COSIM) 393 394 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 395 typedef struct ether_header ether_header_t, *p_ether_header_t; 396 typedef queue_t *p_queue_t; 397 398 #if !defined(IODIAG) 399 typedef mblk_t *p_mblk_t; 400 #endif 401 402 /* 403 * Generic phy table to support different phy types. 404 */ 405 typedef struct _nxge_xcvr_table { 406 nxge_status_t (*serdes_init) (); /* Serdes init routine */ 407 nxge_status_t (*xcvr_init) (); /* xcvr init routine */ 408 nxge_status_t (*link_intr_stop) (); /* Link intr disable routine */ 409 nxge_status_t (*link_intr_start) (); /* Link intr enable routine */ 410 nxge_status_t (*check_link) (); /* Link check routine */ 411 412 uint32_t device_id; 413 uint32_t xcvr_inuse; 414 uint32_t xcvr_addr; 415 } nxge_xcvr_table_t, *p_nxge_xcvr_table_t; 416 417 /* 418 * Common DMA data elements. 419 */ 420 struct _nxge_dma_common_t { 421 uint16_t dma_channel; 422 void *kaddrp; 423 void *first_kaddrp; 424 void *last_kaddrp; 425 void *ioaddr_pp; 426 void *first_ioaddr_pp; 427 void *last_ioaddr_pp; 428 ddi_dma_cookie_t dma_cookie; 429 uint32_t ncookies; 430 431 nxge_block_mv_t msg_dma_flags; 432 ddi_dma_handle_t dma_handle; 433 nxge_os_acc_handle_t acc_handle; 434 npi_handle_t npi_handle; 435 436 size_t block_size; 437 uint32_t nblocks; 438 size_t alength; 439 uint_t offset; 440 uint_t dma_chunk_index; 441 void *orig_ioaddr_pp; 442 uint64_t orig_vatopa; 443 void *orig_kaddrp; 444 size_t orig_alength; 445 boolean_t contig_alloc_type; 446 }; 447 448 typedef struct _nxge_t nxge_t, *p_nxge_t; 449 typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t; 450 451 typedef struct _nxge_dma_pool_t { 452 p_nxge_dma_common_t *dma_buf_pool_p; 453 uint32_t ndmas; 454 uint32_t *num_chunks; 455 boolean_t buf_allocated; 456 } nxge_dma_pool_t, *p_nxge_dma_pool_t; 457 458 /* 459 * Each logical device (69): 460 * - LDG # 461 * - flag bits 462 * - masks. 463 * - interrupt handler function. 464 * 465 * Generic system interrupt handler with two arguments: 466 * (nxge_sys_intr_t) 467 * Per device instance data structure 468 * Logical group data structure. 469 * 470 * Logical device interrupt handler with two arguments: 471 * (nxge_ldv_intr_t) 472 * Per device instance data structure 473 * Logical device number 474 */ 475 typedef struct _nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t; 476 typedef struct _nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t; 477 typedef uint_t (*nxge_sys_intr_t)(void *arg1, void *arg2); 478 typedef uint_t (*nxge_ldv_intr_t)(void *arg1, void *arg2); 479 480 /* 481 * Each logical device Group (64) needs to have the following 482 * configurations: 483 * - timer counter (6 bits) 484 * - timer resolution (20 bits, number of system clocks) 485 * - system data (7 bits) 486 */ 487 struct _nxge_ldg_t { 488 uint8_t ldg; /* logical group number */ 489 uint8_t vldg_index; 490 boolean_t arm; 491 boolean_t interrupted; 492 uint16_t ldg_timer; /* counter */ 493 uint8_t func; 494 uint8_t vector; 495 uint8_t intdata; 496 uint8_t nldvs; 497 p_nxge_ldv_t ldvp; 498 nxge_sys_intr_t sys_intr_handler; 499 uint_t (*ih_cb_func)(caddr_t, caddr_t); 500 p_nxge_t nxgep; 501 }; 502 503 struct _nxge_ldv_t { 504 uint8_t ldg_assigned; 505 uint8_t ldv; 506 boolean_t is_rxdma; 507 boolean_t is_txdma; 508 boolean_t is_mif; 509 boolean_t is_mac; 510 boolean_t is_syserr; 511 boolean_t use_timer; 512 uint8_t channel; 513 uint8_t vdma_index; 514 uint8_t func; 515 p_nxge_ldg_t ldgp; 516 uint8_t ldv_flags; 517 boolean_t is_leve; 518 boolean_t is_edge; 519 uint8_t ldv_ldf_masks; 520 nxge_ldv_intr_t ldv_intr_handler; 521 uint_t (*ih_cb_func)(caddr_t, caddr_t); 522 p_nxge_t nxgep; 523 }; 524 #endif 525 526 typedef struct _nxge_logical_page_t { 527 uint16_t dma; 528 uint16_t page; 529 boolean_t valid; 530 uint64_t mask; 531 uint64_t value; 532 uint64_t reloc; 533 uint32_t handle; 534 } nxge_logical_page_t, *p_nxge_logical_page_t; 535 536 /* 537 * (Internal) return values from ioctl subroutines. 538 */ 539 enum nxge_ioc_reply { 540 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 541 IOC_DONE, /* OK, reply sent */ 542 IOC_ACK, /* OK, just send ACK */ 543 IOC_REPLY, /* OK, just send reply */ 544 IOC_RESTART_ACK, /* OK, restart & ACK */ 545 IOC_RESTART_REPLY /* OK, restart & reply */ 546 }; 547 548 typedef struct _pci_cfg_t { 549 uint16_t vendorid; 550 uint16_t devid; 551 uint16_t command; 552 uint16_t status; 553 uint8_t revid; 554 uint8_t res0; 555 uint16_t junk1; 556 uint8_t cache_line; 557 uint8_t latency; 558 uint8_t header; 559 uint8_t bist; 560 uint32_t base; 561 uint32_t base14; 562 uint32_t base18; 563 uint32_t base1c; 564 uint32_t base20; 565 uint32_t base24; 566 uint32_t base28; 567 uint32_t base2c; 568 uint32_t base30; 569 uint32_t res1[2]; 570 uint8_t int_line; 571 uint8_t int_pin; 572 uint8_t min_gnt; 573 uint8_t max_lat; 574 } pci_cfg_t, *p_pci_cfg_t; 575 576 #if defined(_KERNEL) || defined(COSIM) 577 578 typedef struct _dev_regs_t { 579 nxge_os_acc_handle_t nxge_pciregh; /* PCI config DDI IO handle */ 580 p_pci_cfg_t nxge_pciregp; /* mapped PCI registers */ 581 582 nxge_os_acc_handle_t nxge_regh; /* device DDI IO (BAR 0) */ 583 void *nxge_regp; /* mapped device registers */ 584 585 nxge_os_acc_handle_t nxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 586 void *nxge_msix_regp; /* MSI/X register */ 587 588 nxge_os_acc_handle_t nxge_vir_regh; /* virtualization (BAR 4) */ 589 unsigned char *nxge_vir_regp; /* virtualization register */ 590 591 nxge_os_acc_handle_t nxge_vir2_regh; /* second virtualization */ 592 unsigned char *nxge_vir2_regp; /* second virtualization */ 593 594 nxge_os_acc_handle_t nxge_romh; /* fcode rom handle */ 595 unsigned char *nxge_romp; /* fcode pointer */ 596 } dev_regs_t, *p_dev_regs_t; 597 598 599 typedef struct _nxge_mac_addr_t { 600 ether_addr_t addr; 601 uint_t flags; 602 } nxge_mac_addr_t; 603 604 /* 605 * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac) 606 * for each XMAC port and supports 1 unique MAC and 7 alternate MACs 607 * for each BMAC port. The number of MACs assigned by the factory is 608 * different and is as follows, 609 * BMAC port: num_factory_mmac = num_mmac = 7 610 * XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15 611 * XMAC port on a 4-port NIC: num_factory_mmac = 7 612 * So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses 613 * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac. 614 * 615 * total_factory_macs is the total number of factory MACs, including 616 * the unique MAC, assigned to a Neptune based NIC card, it is 32. 617 */ 618 typedef struct _nxge_mmac_t { 619 uint8_t total_factory_macs; 620 uint8_t num_mmac; 621 uint8_t num_factory_mmac; 622 nxge_mac_addr_t mac_pool[XMAC_MAX_ADDR_ENTRY]; 623 ether_addr_t factory_mac_pool[XMAC_MAX_ADDR_ENTRY]; 624 uint8_t naddrfree; /* number of alt mac addr available */ 625 } nxge_mmac_t; 626 627 /* 628 * mmac stats structure 629 */ 630 typedef struct _nxge_mmac_stats_t { 631 uint8_t mmac_max_cnt; 632 uint8_t mmac_avail_cnt; 633 struct ether_addr mmac_avail_pool[16]; 634 } nxge_mmac_stats_t, *p_nxge_mmac_stats_t; 635 636 #define NXGE_MAX_MMAC_ADDRS 32 637 #define NXGE_NUM_MMAC_ADDRS 8 638 #define NXGE_NUM_OF_PORTS_QUAD 4 639 #define NXGE_NUM_OF_PORTS_DUAL 2 640 641 #define NXGE_EROM_LEN 1048576 642 643 #endif 644 645 #include <sys/nxge/nxge_common_impl.h> 646 #include <sys/nxge/nxge_common.h> 647 #include <sys/nxge/nxge_txc.h> 648 #include <sys/nxge/nxge_rxdma.h> 649 #include <sys/nxge/nxge_txdma.h> 650 #include <sys/nxge/nxge_fflp.h> 651 #include <sys/nxge/nxge_ipp.h> 652 #include <sys/nxge/nxge_zcp.h> 653 #include <sys/nxge/nxge_fzc.h> 654 #include <sys/nxge/nxge_flow.h> 655 #include <sys/nxge/nxge_virtual.h> 656 657 #include <npi_espc.h> 658 #include <npi_vir.h> 659 660 #include <sys/nxge/nxge.h> 661 662 #include <sys/modctl.h> 663 #include <sys/pattr.h> 664 665 extern int secpolicy_net_config(const cred_t *, boolean_t); 666 extern void nxge_fm_report_error(p_nxge_t, uint8_t, 667 uint8_t, nxge_fm_ereport_id_t); 668 extern int fm_check_acc_handle(ddi_acc_handle_t); 669 extern int fm_check_dma_handle(ddi_dma_handle_t); 670 671 /* nxge_classify.c */ 672 nxge_status_t nxge_classify_init(p_nxge_t); 673 nxge_status_t nxge_classify_uninit(p_nxge_t); 674 nxge_status_t nxge_set_hw_classify_config(p_nxge_t); 675 nxge_status_t nxge_classify_exit_sw(p_nxge_t); 676 677 /* nxge_fflp.c */ 678 void nxge_put_tcam(p_nxge_t, p_mblk_t); 679 void nxge_get_tcam(p_nxge_t, p_mblk_t); 680 nxge_status_t nxge_classify_init_hw(p_nxge_t); 681 nxge_status_t nxge_classify_init_sw(p_nxge_t); 682 nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t); 683 nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t, 684 uint32_t); 685 686 nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t, 687 tcam_class_t, 688 uint32_t *); 689 690 nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t, 691 uint32_t); 692 693 nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t, 694 uint32_t); 695 696 uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t); 697 nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *); 698 nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t); 699 nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t); 700 701 nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t); 702 nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t); 703 704 nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t); 705 nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t); 706 707 nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t); 708 nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t); 709 710 nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t); 711 712 nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t); 713 714 nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t); 715 716 void nxge_handle_tcam_fragment_bug(p_nxge_t); 717 nxge_status_t nxge_fflp_hw_reset(p_nxge_t); 718 nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t); 719 nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t); 720 721 /* nxge_kstats.c */ 722 void nxge_init_statsp(p_nxge_t); 723 void nxge_setup_kstats(p_nxge_t); 724 void nxge_destroy_kstats(p_nxge_t); 725 int nxge_port_kstat_update(kstat_t *, int); 726 void nxge_save_cntrs(p_nxge_t); 727 728 int nxge_m_stat(void *arg, uint_t, uint64_t *); 729 730 /* nxge_hw.c */ 731 void 732 nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 733 void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 734 void nxge_global_reset(p_nxge_t); 735 uint_t nxge_intr(void *, void *); 736 void nxge_intr_enable(p_nxge_t); 737 void nxge_intr_disable(p_nxge_t); 738 void nxge_hw_blank(void *arg, time_t, uint_t); 739 void nxge_hw_id_init(p_nxge_t); 740 void nxge_hw_init_niu_common(p_nxge_t); 741 void nxge_intr_hw_enable(p_nxge_t); 742 void nxge_intr_hw_disable(p_nxge_t); 743 void nxge_hw_stop(p_nxge_t); 744 void nxge_global_reset(p_nxge_t); 745 void nxge_check_hw_state(p_nxge_t); 746 747 void nxge_rxdma_channel_put64(nxge_os_acc_handle_t, 748 void *, uint32_t, uint16_t, 749 uint64_t); 750 uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *, 751 uint32_t, uint16_t); 752 753 754 void nxge_get32(p_nxge_t, p_mblk_t); 755 void nxge_put32(p_nxge_t, p_mblk_t); 756 757 void nxge_hw_set_mac_modes(p_nxge_t); 758 759 /* nxge_send.c. */ 760 uint_t nxge_reschedule(caddr_t); 761 762 /* nxge_rxdma.c */ 763 nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t, 764 uint8_t, uint8_t); 765 766 nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t, 767 uint8_t, uint8_t); 768 nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t, 769 uint16_t); 770 nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t, 771 uint16_t, uint8_t); 772 773 /* nxge_ndd.c */ 774 void nxge_get_param_soft_properties(p_nxge_t); 775 void nxge_copy_hw_default_to_param(p_nxge_t); 776 void nxge_copy_param_hw_to_config(p_nxge_t); 777 void nxge_setup_param(p_nxge_t); 778 void nxge_init_param(p_nxge_t); 779 void nxge_destroy_param(p_nxge_t); 780 boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t); 781 boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t); 782 boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t); 783 784 boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t); 785 786 int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t); 787 int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 788 int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 789 int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t); 790 int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 791 int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t); 792 long nxge_strtol(char *, char **, int); 793 boolean_t nxge_param_get_instance(queue_t *, mblk_t *); 794 void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 795 boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 796 void nxge_nd_free(caddr_t *); 797 int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t); 798 799 void nxge_set_lb_normal(p_nxge_t); 800 boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t); 801 802 /* nxge_virtual.c */ 803 nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *); 804 void nxge_common_lock_get(p_nxge_t); 805 void nxge_common_lock_free(p_nxge_t); 806 807 nxge_status_t nxge_get_config_properties(p_nxge_t); 808 void nxge_get_xcvr_properties(p_nxge_t); 809 void nxge_init_vlan_config(p_nxge_t); 810 void nxge_init_mac_config(p_nxge_t); 811 812 813 void nxge_init_logical_devs(p_nxge_t); 814 int nxge_init_ldg_intrs(p_nxge_t); 815 816 void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t, 817 uint32_t); 818 819 void nxge_init_fzc_txdma_channels(p_nxge_t); 820 821 nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t, 822 p_tx_ring_t, p_tx_mbox_t); 823 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 824 825 nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t, 826 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 827 828 nxge_status_t nxge_init_fzc_rdc_tbl(p_nxge_t); 829 nxge_status_t nxge_init_fzc_rx_common(p_nxge_t); 830 nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t); 831 832 nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t, 833 uint16_t, p_rx_rbr_ring_t); 834 nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t, 835 uint16_t, p_rx_rcr_ring_t); 836 837 nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t, 838 uint16_t, p_rx_rbr_ring_t); 839 840 841 nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t, 842 uint16_t, p_tx_ring_t); 843 844 nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t, 845 p_tx_ring_t); 846 847 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 848 849 void nxge_init_fzc_ldg_num(p_nxge_t); 850 void nxge_init_fzc_sys_int_data(p_nxge_t); 851 void nxge_init_fzc_ldg_int_timer(p_nxge_t); 852 nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on); 853 854 /* MAC functions */ 855 nxge_status_t nxge_mac_init(p_nxge_t); 856 nxge_status_t nxge_link_init(p_nxge_t); 857 nxge_status_t nxge_xif_init(p_nxge_t); 858 nxge_status_t nxge_pcs_init(p_nxge_t); 859 nxge_status_t nxge_serdes_init(p_nxge_t); 860 nxge_status_t nxge_setup_xcvr_table(p_nxge_t); 861 nxge_status_t nxge_xcvr_init(p_nxge_t); 862 nxge_status_t nxge_tx_mac_init(p_nxge_t); 863 nxge_status_t nxge_rx_mac_init(p_nxge_t); 864 nxge_status_t nxge_tx_mac_enable(p_nxge_t); 865 nxge_status_t nxge_tx_mac_disable(p_nxge_t); 866 nxge_status_t nxge_rx_mac_enable(p_nxge_t); 867 nxge_status_t nxge_rx_mac_disable(p_nxge_t); 868 nxge_status_t nxge_tx_mac_reset(p_nxge_t); 869 nxge_status_t nxge_rx_mac_reset(p_nxge_t); 870 nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t); 871 nxge_status_t nxge_mii_xcvr_init(p_nxge_t); 872 nxge_status_t nxge_mii_read(p_nxge_t, uint8_t, 873 uint8_t, uint16_t *); 874 nxge_status_t nxge_mii_write(p_nxge_t, uint8_t, 875 uint8_t, uint16_t); 876 nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t, 877 uint16_t, uint16_t *); 878 nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t, 879 uint8_t, uint16_t, uint16_t); 880 nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t, 881 mii_bmsr_t, nxge_link_state_t *); 882 nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *); 883 nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *); 884 nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *); 885 nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *); 886 void nxge_link_is_down(p_nxge_t); 887 void nxge_link_is_up(p_nxge_t); 888 nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t); 889 uint32_t crc32_mchash(p_ether_addr_t); 890 nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t); 891 nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t); 892 nxge_status_t nxge_10g_link_led_on(p_nxge_t); 893 nxge_status_t nxge_10g_link_led_off(p_nxge_t); 894 nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t); 895 boolean_t nxge_is_valid_local_mac(ether_addr_st); 896 897 /* espc (sprom) prototypes */ 898 nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t); 899 nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *); 900 nxge_status_t nxge_espc_num_ports_get(p_nxge_t); 901 nxge_status_t nxge_espc_phy_type_get(p_nxge_t); 902 nxge_status_t nxge_espc_verify_chksum(p_nxge_t); 903 void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *); 904 nxge_status_t nxge_vpd_info_get(p_nxge_t); 905 906 907 void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...); 908 int nxge_nports_from_niu_type(niu_type_t); 909 910 uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t, 911 uint64_t, uint64_t); 912 #pragma weak hv_niu_rx_logical_page_conf 913 914 uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t, 915 uint64_t *, uint64_t *); 916 #pragma weak hv_niu_rx_logical_page_info 917 918 uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t, 919 uint64_t, uint64_t); 920 #pragma weak hv_niu_tx_logical_page_conf 921 922 uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t, 923 uint64_t *, uint64_t *); 924 #pragma weak hv_niu_tx_logical_page_info 925 926 #ifdef NXGE_DEBUG 927 char *nxge_dump_packet(char *, int); 928 #endif 929 930 #endif /* !_ASM */ 931 932 #ifdef __cplusplus 933 } 934 #endif 935 936 #endif /* _SYS_NXGE_NXGE_IMPL_H */ 937