1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NXGE_NXGE_HIO_H 28 #define _SYS_NXGE_NXGE_HIO_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <nxge_mac.h> 35 #include <nxge_ipp.h> 36 #include <nxge_fflp.h> 37 #include <sys/mac_provider.h> 38 39 #define isLDOMservice(nxge) \ 40 (nxge->environs == SOLARIS_SERVICE_DOMAIN) 41 #define isLDOMguest(nxge) \ 42 (nxge->environs == SOLARIS_GUEST_DOMAIN) 43 #define isLDOMs(nxge) \ 44 (isLDOMservice(nxge) || isLDOMguest(nxge)) 45 46 #define NXGE_HIO_SHARE_MIN_CHANNELS 2 47 #define NXGE_HIO_SHARE_MAX_CHANNELS 2 48 49 /* ------------------------------------------------------------------ */ 50 typedef uint8_t nx_rdc_t; 51 typedef uint8_t nx_tdc_t; 52 53 typedef uint64_t res_map_t; 54 55 typedef uint64_t hv_rv_t; 56 57 typedef hv_rv_t (*vr_assign)(uint64_t, uint64_t, uint32_t *); 58 typedef hv_rv_t (*vr_unassign)(uint32_t); 59 typedef hv_rv_t (*vr_getinfo)(uint32_t, uint64_t *, uint64_t *); 60 61 62 typedef struct { 63 vr_assign assign; 64 vr_unassign unassign; 65 vr_getinfo getinfo; 66 67 } nxhv_vr_fp_t; 68 69 typedef hv_rv_t (*vrlp_conf)(uint64_t, uint64_t, uint64_t, uint64_t); 70 typedef hv_rv_t (*vrlp_info)(uint64_t, uint64_t, uint64_t *, uint64_t *); 71 72 typedef hv_rv_t (*dc_assign)(uint32_t, uint64_t, uint64_t *); 73 typedef hv_rv_t (*dc_unassign)(uint32_t, uint64_t); 74 typedef hv_rv_t (*dc_getstate)(uint32_t, uint64_t, uint64_t *); 75 typedef hv_rv_t (*dc_get_map)(uint32_t, uint64_t *); 76 77 typedef hv_rv_t (*dc_getinfo)(uint32_t, uint64_t, uint64_t *, uint64_t *); 78 79 typedef struct { 80 dc_assign assign; 81 dc_unassign unassign; 82 dc_getstate getstate; 83 dc_get_map get_map; 84 85 vrlp_conf lp_conf; 86 vrlp_info lp_info; 87 88 dc_getinfo getinfo; 89 } nxhv_dc_fp_t; 90 91 typedef struct { 92 boolean_t ldoms; 93 nxhv_vr_fp_t vr; 94 nxhv_dc_fp_t tx; 95 nxhv_dc_fp_t rx; 96 } nxhv_fp_t; 97 98 /* ------------------------------------------------------------------ */ 99 #define NXGE_VR_SR_MAX 8 /* There are 8 subregions (SR). */ 100 101 typedef enum { 102 NXGE_HIO_TYPE_SERVICE, /* We are a service domain driver. */ 103 NXGE_HIO_TYPE_GUEST /* We are a guest domain driver. */ 104 } nxge_hio_type_t; 105 106 typedef enum { 107 FUNC0_MNT, 108 FUNC0_VIR = 0x1000000, 109 FUNC1_MNT = 0x2000000, 110 FUNC1_VIR = 0x3000000, 111 FUNC2_MNT = 0x4000000, 112 FUNC2_VIR = 0x5000000, 113 FUNC3_MNT = 0x6000000, 114 FUNC3_VIR = 0x7000000 115 } vr_base_address_t; 116 117 #define VR_STEP 0x2000000 118 #define VR_VC_STEP 0x0004000 119 120 typedef enum { /* 0-8 */ 121 FUNC0_VIR0, 122 FUNC0_VIR1, 123 FUNC1_VIR0, 124 FUNC1_VIR1, 125 FUNC2_VIR0, 126 FUNC2_VIR1, 127 FUNC3_VIR0, 128 FUNC3_VIR1, 129 FUNC_VIR_MAX 130 } vr_region_t; 131 132 typedef enum { 133 VP_CHANNEL_0, 134 VP_CHANNEL_1, 135 VP_CHANNEL_2, 136 VP_CHANNEL_3, 137 VP_CHANNEL_4, 138 VP_CHANNEL_5, 139 VP_CHANNEL_6, 140 VP_CHANNEL_7, 141 VP_CHANNEL_MAX 142 } vp_channel_t; 143 144 typedef enum { 145 VP_BOUND_TX = 1, 146 VP_BOUND_RX 147 } vpc_type_t; 148 149 #define VP_VC_OFFSET(channel) (channel << 10) 150 #define VP_RDC_OFFSET (1 << 9) 151 152 typedef enum { 153 RXDMA_CFIG1 = 0, 154 RXDMA_CFIG2 = 8, 155 RBR_CFIG_A = 0x10, 156 RBR_CFIG_B = 0x18, 157 RBR_KICK = 0x20, 158 RBR_STAT = 0x28, 159 RBR_HDH = 0x30, 160 RBR_HDL = 0x38, 161 RCRCFIG_A = 0x40, 162 RCRCFIG_B = 0x48, 163 RCRSTAT_A = 0x50, 164 RCRSTAT_B = 0x58, 165 RCRSTAT_C = 0x60, 166 RX_DMA_ENT_MSK = 0x68, 167 RX_DMA_CTL_STAT = 0x70, 168 RCR_FLSH = 0x78, 169 RXMISC = 0x90, 170 RX_DMA_CTL_STAT_DBG = 0x98 171 172 } rdc_csr_offset_t; 173 174 typedef enum { 175 Tx_RNG_CFIG = 0, 176 Tx_RNG_HDL = 0x10, 177 Tx_RNG_KICK = 0x18, 178 Tx_ENT_MASK = 0x20, 179 Tx_CS = 0x28, 180 TxDMA_MBH = 0x30, 181 TxDMA_MBL = 0x38, 182 TxDMA_PRE_ST = 0x40, 183 Tx_RNG_ERR_LOGH = 0x48, 184 Tx_RNG_ERR_LOGL = 0x50, 185 TDMC_INTR_DBG = 0x60, 186 Tx_CS_DBG = 0x68 187 188 } tdc_csr_offset_t; 189 190 /* 191 * ------------------------------------------------------------- 192 * These definitions are used to handle the virtual PIO_LDSV 193 * space of a VR. 194 * ------------------------------------------------------------- 195 */ 196 #define VLDG_OFFSET 0x2000 197 #define VLDG_SLL 5 198 199 typedef enum { 200 PIO_LDSV0, /* ldf_0, 0-63 */ 201 PIO_LDSV1, /* ldf_1, 0-63 */ 202 PIO_LDSV2, /* ldf_0 & ldf_1, 64-69 */ 203 PIO_LDGIMGN /* arm/timer */ 204 205 } pio_ld_op_t; 206 207 #define VR_INTR_BLOCK_SIZE 8 208 #define HIO_INTR_BLOCK_SIZE 4 209 210 /* ------------------------------------------------------------------ */ 211 typedef struct { 212 const char *name; 213 int offset; 214 } dmc_reg_name_t; 215 216 typedef struct { 217 uintptr_t nxge; 218 dc_map_t map; 219 220 } nx_rdc_tbl_t; 221 222 typedef struct nxge_hio_vr { 223 uintptr_t nxge; 224 225 uint32_t cookie; /* The HV cookie. */ 226 uintptr_t address; 227 size_t size; 228 vr_region_t region; /* 1 of 8 regions. */ 229 230 int rdc_tbl; /* 1 of 8 RDC tables. */ 231 int tdc_tbl; /* 1 of 8 TDC tables. */ 232 ether_addr_t altmac; /* The alternate MAC address. */ 233 int slot; /* According to nxge_m_mmac_add(). */ 234 235 nxge_grp_t rx_group; 236 nxge_grp_t tx_group; 237 238 } nxge_hio_vr_t; 239 240 typedef nxge_status_t (*dc_init_t)(nxge_t *, int); 241 typedef void (*dc_uninit_t)(nxge_t *, int); 242 243 typedef struct { 244 uint32_t number; /* The LDG number assigned to this DC. */ 245 uint64_t index; /* Bits 7:5 of the (virtual) PIO_LDSV. */ 246 247 uint64_t ldsv; /* The logical device number */ 248 uint64_t map; /* Currently unused */ 249 250 int vector; /* The DDI vector number (index) */ 251 } hio_ldg_t; 252 253 /* 254 * ------------------------------------------------------------- 255 * The service domain driver makes use of both <index>, the index 256 * into a VR's virtual page, and <channel>, the absolute channel 257 * number, what we will call here the physical channel number. 258 * 259 * The guest domain will set both fields to the same value, since 260 * it doesn't know any better. And if a service domain owns a 261 * DMA channel, it will also set both fields to the same value, 262 * since it is not using a VR per se. 263 * ------------------------------------------------------------- 264 */ 265 typedef struct nx_dc { 266 267 struct nx_dc *next; 268 269 nxge_hio_vr_t *vr; /* The VR belonged to. */ 270 271 vp_channel_t page; /* VP_CHANNEL_0 - VP_CHANNEL_7 */ 272 nxge_channel_t channel; /* 1 of 16/24 channels */ 273 /* 274 * <channel> has its normal meaning. <page> refers to the 275 * virtual page of the VR that <channel> has been bound to. 276 * Therefore, in the service domain, <page> & <channel> 277 * are almost always different. While in a guest domain, 278 * they are always the same. 279 */ 280 vpc_type_t type; /* VP_BOUND_XX */ 281 dc_init_t init; /* nxge_init_xxdma_channel() */ 282 dc_uninit_t uninit; /* nxge_uninit_xxdma_channel() */ 283 284 nxge_grp_t *group; /* The group belonged to. */ 285 uint32_t cookie; /* The HV cookie. */ 286 287 hio_ldg_t ldg; 288 boolean_t interrupting; /* Interrupt enabled? */ 289 290 } nxge_hio_dc_t; 291 292 typedef struct { 293 nxge_hio_type_t type; 294 295 kmutex_t lock; 296 int vrs; 297 unsigned sequence; 298 299 nxhv_fp_t hio; 300 301 /* vr[0] is reserved for the service domain. */ 302 nxge_hio_vr_t vr[NXGE_VR_SR_MAX]; /* subregion map */ 303 nxge_hio_dc_t rdc[NXGE_MAX_RDCS]; 304 nxge_hio_dc_t tdc[NXGE_MAX_TDCS]; 305 306 nx_rdc_tbl_t rdc_tbl[NXGE_MAX_RDC_GROUPS]; 307 308 } nxge_hio_data_t; 309 310 /* 311 * ------------------------------------------------------------- 312 * prototypes 313 * ------------------------------------------------------------- 314 */ 315 extern void nxge_get_environs(nxge_t *); 316 extern int nxge_hio_init(nxge_t *); 317 extern void nxge_hio_uninit(nxge_t *); 318 319 extern int nxge_dci_map(nxge_t *, vpc_type_t, int); 320 321 /* 322 * --------------------------------------------------------------------- 323 * These are the general-purpose DMA channel group functions. That is, 324 * these functions are used to manage groups of TDCs or RDCs in an HIO 325 * environment. 326 * 327 * But is also expected that in the future they will be able to manage 328 * Crossbow groups. 329 * --------------------------------------------------------------------- 330 */ 331 extern nxge_grp_t *nxge_grp_add(nxge_t *, nxge_grp_type_t); 332 extern void nxge_grp_remove(nxge_t *, nxge_grp_t *); 333 extern int nxge_grp_dc_add(nxge_t *, nxge_grp_t *, vpc_type_t, int); 334 extern void nxge_grp_dc_remove(nxge_t *, vpc_type_t, int); 335 extern nxge_hio_dc_t *nxge_grp_dc_find(nxge_t *, vpc_type_t, int); 336 337 extern void nxge_delay(int); 338 extern const char *nxge_ddi_perror(int); 339 340 /* 341 * --------------------------------------------------------------------- 342 * These are the Sun4v HIO function prototypes. 343 * --------------------------------------------------------------------- 344 */ 345 extern void nxge_hio_group_get(void *arg, mac_ring_type_t type, int group, 346 mac_group_info_t *infop, mac_group_handle_t ghdl); 347 extern int nxge_hio_share_alloc(void *arg, mac_share_handle_t *shandle); 348 extern void nxge_hio_share_free(mac_share_handle_t shandle); 349 extern void nxge_hio_share_query(mac_share_handle_t shandle, 350 mac_ring_type_t type, mac_ring_handle_t *rings, uint_t *n_rings); 351 extern int nxge_hio_share_add_group(mac_share_handle_t, 352 mac_group_driver_t); 353 extern int nxge_hio_share_rem_group(mac_share_handle_t, 354 mac_group_driver_t); 355 extern int nxge_hio_share_bind(mac_share_handle_t, uint64_t cookie, 356 uint64_t *rcookie); 357 extern void nxge_hio_share_unbind(mac_share_handle_t); 358 extern int nxge_hio_rxdma_bind_intr(nxge_t *, rx_rcr_ring_t *, int); 359 360 /* nxge_hio_guest.c */ 361 extern void nxge_hio_unregister(nxge_t *); 362 363 extern int nxge_guest_regs_map(nxge_t *); 364 extern void nxge_guest_regs_map_free(nxge_t *); 365 366 extern int nxge_hio_vr_add(nxge_t *nxge); 367 extern int nxge_hio_vr_release(nxge_t *nxge); 368 369 extern nxge_status_t nxge_tdc_lp_conf(p_nxge_t, int); 370 extern nxge_status_t nxge_rdc_lp_conf(p_nxge_t, int); 371 372 extern void nxge_hio_start_timer(nxge_t *); 373 374 /* nxge_intr.c */ 375 extern nxge_status_t nxge_hio_intr_init(nxge_t *); 376 extern void nxge_hio_intr_uninit(nxge_t *); 377 378 extern nxge_status_t nxge_intr_add(nxge_t *, vpc_type_t, int); 379 extern nxge_status_t nxge_intr_remove(nxge_t *, vpc_type_t, int); 380 381 extern nxge_status_t nxge_hio_intr_add(nxge_t *, vpc_type_t, int); 382 extern nxge_status_t nxge_hio_intr_remove(nxge_t *, vpc_type_t, int); 383 384 extern nxge_status_t nxge_hio_intr_add(nxge_t *, vpc_type_t, int); 385 extern nxge_status_t nxge_hio_intr_rem(nxge_t *, int); 386 387 extern hv_rv_t nxge_hio_ldsv_add(nxge_t *, nxge_hio_dc_t *); 388 389 extern void nxge_hio_ldsv_im(nxge_t *, nxge_ldg_t *, pio_ld_op_t, uint64_t *); 390 extern void nxge_hio_ldgimgn(nxge_t *, nxge_ldg_t *); 391 392 /* nxge_hv.c */ 393 extern void nxge_hio_hv_init(nxge_t *); 394 395 /* nxge_mac.c */ 396 extern int nxge_hio_hostinfo_get_rdc_table(p_nxge_t); 397 extern int nxge_hio_hostinfo_init(nxge_t *, nxge_hio_vr_t *, ether_addr_t *); 398 extern void nxge_hio_hostinfo_uninit(nxge_t *, nxge_hio_vr_t *); 399 400 #ifdef __cplusplus 401 } 402 #endif 403 404 #endif /* _SYS_NXGE_NXGE_HIO_H */ 405